83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
1
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
GENERAL DESCRIPTION
The ICS83840 is a DDR SDRAM MUX and is a
member of the HiPerClockS family of High Perfor-
mance Clock Solutions from ICS. The device has 10
Host Lines and each host line can be passed to 4
Data Ports. The 10 channels are allocated as follows
in the DDR SDRAM application: 8 data lines, 1 strobe line and 1
DQm line. The Host/Data Ports are compatible with single-ended
SSTL-2 and the device operates from a 2.5V supply .
Guaranteed low output skew makes the ICS83840 ideal for
demanding applications which require well defined performance
and repeatability .
LOGIC DIAGRAM
FEATURES
•40 low skew single-ended DIMM ports
•4 SSTL-2 compatible enable inputs
•Maximum Switching Speed: 3ns
•Output skew: 120ps (maximum)
•Bank skew: 45ps (maximum)
•ron = 8Ω (typical)
•Full 2.5V supply modes
•0°C to 70°C ambient operating temperature
•Pin compatible with the CBTV4010
HiPerClockS™
,&6
SIMPLIFIED SCHEMATIC
HPx
nSn
nDPx
SW
400Ω
HP0 0DP0
1DP0
2DP0
3DP0
HP9
Sw
Sw
Sw
Sw
0DP9
1DP9
2DP9
3DP9
Sw
Sw
Sw
Sw
nS0
nS1
nS2
nS3
R
ON
R
ON
ICS83840
64-Ball TFBGA
7mm x 7mm x 0.7mm
package body
H Package
Top View
PIN ASSIGNMENT
V
DD
1Sncn0PD10PD20PD31PD21PD32PD0
2SnV
DD
0SnDNG0PD00PH1PD01PD11PHDNG2PD1
cn3Sn 2PH2PD2
DNG 2PD3
9PD29PD3 3PD03PD1
9PD19PH 3PH3PD2
9PD08PD3 DNG3PD3
8PD2 4PD0
8PD18PH 4PH4PD1
8PD0DNG7PH7PD06PD36PHDNG5PD35PH4PD34PD2
7PD37PD27PD16PD26PD16PD05PD25PD15PD0
1234567891011
A
B
C
D
E
F
G
H
J
K
L
83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
2
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
2B,1AV
DD
rewoP.snipylppusevitisoP
7K,2K,01G,2D,01B,4BDNGrewoP.dnuorgylppusrewoP
1C,3AcndesunU.tcennocoN
3B,2C,1B,2A0Sn,3Sn,2Sn,1SntroP.sniptceleS
,01F,2F,01C,9B,6B 9K,6K,3K,01J,2J ,3PH,9PH,2PH,1PH,0PH 5PH,6PH,7PH,4PH,8PH troP.stroptsoH
5B,7A,6A,5A0PD0,0PD3,0PD2,0PD1troP.stropMMID
8B,7B,01A,9A1PD1,1PD0,1PD3,1PD2troP.stropMMID
01D,11C,11B,11A2PD3,2PD2,2PD1,2PD0troP.stropMMID
11G,11F,11E,01E3PD3,3PD2,3PD1,3PDOtroP.stropMMID
11K,01K,11J,01H4PD2,4PD3,4PD1,4PD0troP.stropMMID
11L,01L,9L,8K5PD0,5PD1,5PD2,5PD3troP.stropMMID
7L,6L,5L,5K6PD0,6PD1,6PD2,6PD3troP.stropMMID
3L,2L,1L,4K7PD1,7PD2,7PD3,7PD0troP.stropMMID
1K,1J,2H,2G8PD0,8PD1,8PD2,8PD3troP.stropMMID
1G,1F,2E,1E9PD0,9PD1,9PD3,9PD2troP.stropMMID
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FUNCTION TABLE
tupnIlortnoC noitcnuF
xSnLtroPMMID=troPtsoH
HdetcennocsiD=troPtsoH 004=troPMMID ΩDNGot
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnIxSnV
I
VroV0=
DD
5Fp
C
NO
ecnaticapaCnolennahCxPHV
NI
V5.1=21Fp
.detsetnoitcudorptonsiecnaticapaC.V3egatlovsaibadnazHM01taderusaemeraseulavecnaticapaC:ETON
83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
3
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 3.25.27.2V
I
DD
tnerruCylppuSrewoP 05Aµ
TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnIxSn6.1V
V
LI
egatloVwoLtupnIxSn 9.0V
V
KI
egatloVpmalCtupnIV
DD
;V3.2=I
I
Am81-=2.1-V
I
L
egakaeLtupnI tnerruC
xSn V
DD
;V5.2=V
I
V=
DD
;DNGro
V=Sn
DD
001±Aµ
troPtsoH 001±Aµ
troPMMIDIrofDNG=Sn
)tset(LI
001±Aµ
r
NO
1ETON;ecnatsiseRnO V
DD
V;V5.2=
A
V;V8.0=
B
V0.1=5831Ω
V
DD
V;V5.2=
A
V;V7.1=
B
V5.1=5831Ω
edishcaenosegatlovdetacidniehttaslanimretMMIDehtdnatsoHehtneewtebtnerrucehtybderusaeM:1ETON .hctiwsehtfo
ABSOLUTE MAXIMUM RATINGS
Supply V oltage, VDD -0.5V to +3.3V
Inputs, V I-0.3V to VDD + 0.3 V
Ports
DC Input Clamp Current, IIK -50mA
Package Thermal Impedance, θJA 50.04°C/W (0 mfps)
Storage T emperature, TSTG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only . Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability .
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
t
DP
;yaleDnoitagaporP 4,1ETON otxPDxroxPHmorF xPHroxPDx 58051022sp
t
NE
tuptuO emiTelbanE otxSnmorF xPDnroxPH 7.1sn
t
SID
tuptuO emiTelbasiD otxSnmorF xPDnroxPH 6.1sn
t
KSO
;wekStuptuO 4,2ETON troPynaottroPynA 021sp
t
KSB
;wekSknaB 4,3ETON troPynaottroPynA knabemasehtnihtiw 54sp
VmorfderusaeM:1ETON
DD
ottupniehtfo2/V
DD
.tuptuoehtfo2/ VtaderusaeM.snoitidnocdaollauqehtiwdnaegatlovylppusemasehttastuptuoneewtebwekssadenifeD:2ETON
ODD
.2/
.snoitidnocdaollauqehtiwknabanihtiwwekssadenifeD:3ETON .noitaziretcarahcybdeetnaraug,detsetnoitcudorptoN:4ETON
83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
4
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
t
PD
V
DD
2
V
DD
2
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD = 1.25V ± 0.1V
-1.25V ± 0.1V
PROPAGATION DELAY
tsk(o)
V
DD
2
V
DD
2
nDPx
nDPy
D or H
H or D
tsk(o)
V
DD
2
V
DD
2
1.25V 1.25V
1.25V V
OH
- 0.15V
V
OL
V
OH
0V
2.5V
t
PHZ →
t
PZH →
Output nDPx
(See Note)
Sn
(Low-level
enabling)
NOTE: The output is high except when disabled by the Sn control.
←
3-STATE OUTPUT ENABLE/DISABLE TIMESBANK SKEW (where X denotes outputs in the same bank)
XDP0:XDP9
XDP0:XDP9
SCOPE
Qx
LVCMOS
VDD
GND
This circuit is used for test purposes only,
not intended for application use.
83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
5
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS83840 is: 320
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by V elocity (Millimeter Feet per Second)
012
T wo-Layer PCB, JEDEC Standard Test Boards 50.04°C/W 43.18°C/W 41.17°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
6
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
PACKAGE OUTLINE - H SUFFIX
TABLE 7. PACKAGE DIMENSIONS
REFERENCE DOCUMENT: JEDEC PUBLICATION 95
NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA
LOBMYS
AGB
MUMINIMLANIMONMUMIXAM
sllaB46
A0.11.12.1
1A 561.02.0532.0
2A 61.02.042.0
3A 576.07.0527.0
b52.03.053.0
D08.60.72.7
1D CSB00.5
E08.60.72.7
1E CSB00.5
eCSB5.0
83840AH www.icst.com/products/hiperclocks.html REV. A AUGUST 8, 2003
7
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
TABLE 8. ORDERING INFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
rebmuNredrO/traPgnikraMegakcaPtnuoCerutarepmeT
HA04838SCIHA04838SCIAGBFTllaB-46yartrep614C°07otC°0
THA04838SCIHA04838SCIleeRdnaepaTnoAGBFTllaB-460001C°07otC°0
