KMSC8122TVT6400 - Freescale Semiconductor

Freescale Semiconductor

Technical Data

MSC8122

Rev. 12, 4/2006

MSC8122

Quad Core 16-Bit Digital Signal Processor

The MSC8122 is a highly integrated system-on-a-chip that combines four SC140 extended cores with an RS-232

serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a

flexible system interface unit (SIU), an Ethernet interface, and a multi-channel DMA engine. The four extended

cores can deliver a total 4800/6400/8000 DSP MMACS performance at 300/400/500 MHz.

Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers.

The MSC8122 targets high-bandwidth highly computational DSP applications and is optimized for wireless

transcoding and packet telephony as well as high-bandwidth base station applications. The MSC8122 delivers

enhanced performance while maintaining low power dissipation and greatly reducing system cost.

Figure 1. MSC8122 Block Diagram

MQBus

SQBus

Local Bus

128

Boot

ROM 64

PLL

JTAG

RS-232

Internal Local Bus

Internal System Bus

IPBus

IP Master

UART

Memory

Controller

RAM

GPIO Pins

Interrupts

Memory

Controller

System Bus

32/64

DSI Port

32/64

PLL/Clock

JTAG Port

SC140

Extended Core

SC140

Extended Core

SC140

Extended Core

System

Interface

32 Timers

4 TDMs

SC140

Extended Core

DMA Bridge SIU

Registers

Direct

Slave

Interface

(DSI)

8 Hardware

Semaphores

GIC

GPIO

MII/RMII/SMII

Ethernet

The raw processing power of

this highly integrated system-

on- a-chip device will enable

developers to create next-

generation networking

products that offer

tremendous channel

densities, while maintaining

system flexibility, scalability,

and upgradeability. The

MSC8122 is offered in three

core speed levels: 300, 400,

and 500 MHz.

What’s New?

Rev. 12 includes the following:

•Chapter 2 updates Figure 2-11

for reset timing.

MSC8122 Technical Data, Rev. 12

ii Freescale Semiconductor

Table of Contents

Features...............................................................................................................................................................iv

Product Documentation ......................................................................................................................................ix

Chapter 1 Signals/Connections

1.1 Power Signals ...................................................................................................................................................1-3

1.2 Clock Signals ....................................................................................................................................................1-3

1.3 Reset and Configuration Signals.......................................................................................................................1-3

1.4 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals ...............................................................1-4

1.5 Memory Controller Signals ............................................................................................................................1-14

1.6 GPIO, TDM, UART, and Timer Signals.........................................................................................................1-16

1.7 Dedicated Ethernet Signals.............................................................................................................................1-23

1.8 EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-24

1.9 Reserved Signals.............................................................................................................................................1-24

Chapter 2 Specifications

2.1 Maximum Ratings.............................................................................................................................................2-1

2.2 Recommended Operating Conditions...............................................................................................................2-2

2.3 Thermal Characteristics ....................................................................................................................................2-3

2.4 DC Electrical Characteristics............................................................................................................................2-3

2.5 AC Timings.......................................................................................................................................................2-4

Chapter 3 Packaging

3.1 Package Description .........................................................................................................................................3-1

3.2 MSC8122 Package Mechanical Drawing .......................................................................................................3-20

Chapter 4 Design Considerations

4.1 Start-up Sequencing Recommendations ...........................................................................................................4-1

4.2 Power Supply Design Considerations...............................................................................................................4-1

4.3 Connectivity Guidelines ...................................................................................................................................4-3

4.4 External SDRAM Selection..............................................................................................................................4-4

4.5 Thermal Considerations....................................................................................................................................4-5

Data Sheet Conventions

OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples: Signal/Symbol Logic State Signal State Voltage

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

Data Sheet Conventions

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor iii

Figure 2. SC140 Extended Core Block Diagram

SC140

Power

Management

Core

Program

Sequencer

Address

File

Data ALU

File

Address

ALU

Data

ALU

EOnCEJTAG

QBus

IRQs

MQBus

SQBus

Local Bus

128

LIC

PIC

128

SC140 Core

QBus

Interface

Instruction

Cache

RAM

Notes: 1. The arrows show the data transfer direction.

QBus

Bank 1

QBus

Bank 3

2. The QBus interface includes a bus switch, write buffer, fetch unit, and a

control unit that defines four QBus banks. In addition, the QBC handles internal

QBC

memory contentions.

MSC8122 Technical Data, Rev. 12

iv Freescale Semiconductor

Features

Feature Description

SC140 Cores

Four SC140 cores:

• Up to 8000 MMACS using 16 ALUs running at up to 500 MHz.

• A total of 1436 KB of internal SRAM (224 KB per core + 16 KB ICache per core + the shared M2 memory).

Each SC140 core provides the following:

• Up to 2000 MMACS using an internal 500 MHz clock. A MAC operation includes a multiply-accumulate

command with the associated data move and pointer update.

• 4 ALUs per SC140 core.

• 16 data registers, 40 bits each.

• 27 address registers, 32 bits each.

• Hardware support for fractional and integer data types.

• Very rich 16-bit wide orthogonal instruction set.

• Up to six instructions executed in a single clock cycle.

• Variable-length execution set (VLES) that can be optimized for code density and performance.

•IEEE Std 1149.1™ JTAG port.

• Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.

Extended Core

Each SC140 core is embedded within an extended core that provides the following:

• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.

• Support for atomic accesses to the M1 memory.

• 16 KB instruction cache, 16 ways.

• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.

• External cache support by asserting the global signal (GBL) when predefined memory banks are accessed.

• Programmable interrupt controller (PIC).

• Local interrupt controller (LIC).

Multi-Core Shared

Memories

• 476 KB M2 memory (shared memory) working at the core frequency, accessible from the local bus, and

accessible from all four SC140 cores using the MQBus.

• 4 KB bootstrap ROM.

M2-Accessible Multi-

Core Bus (MQBus)

• A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory.

• Data bus access of up to 128-bit read and up to 64-bit write.

• Operation at the SC140 core frequency.

• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.

• Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.

Internal PLL

• Generates up to 500 MHz core clock and up to166 MHz bus clocks for the 60x-compatible local and system

buses and other modules.

• PLL values are determined at reset based on configuration signal values.

60x-Compatible

System Bus

• 64/32-bit data and 32-bit address 60x bus.

• Support for multiple-master designs.

• Four-beat burst transfers (eight-beat in 32-bit wide mode).

• Port size of 64, 32, 16, and 8 controlled by the internal memory controller.

• Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to

access internal resources.

• Slave support, direct access by an external host to internal resources including the M1 and M2 memories.

• On-device arbitration between up to four master devices.

Direct Slave

Interface (DSI)

A 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host

processor.

• 21–25 bit address, 32/64-bit data.

• Direct access by an external host to internal and external resources, including the M1 and the M2 memories as

well as external devices on the system bus.

• Synchronous and asynchronous accesses, with burst capability in the synchronous mode.

• Dual or Single strobe modes.

• Write and read buffers improve host bandwidth.

• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.

• Sliding window mode enables access with reduced number of address pins.

• Chip ID decoding enables using one CS signal for multiple DSPs.

• Broadcast CS signal enables parallel write to multiple DSPs.

• Big-endian, little-endian, and munged little-endian support.

3-Mode Signal

Multiplexing

• 64-bit DSI, 32-bit system bus.

• 32-bit DSI, 64-bit system bus.

• 32-bit DSI, 32-bit system bus.

Features

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor v

Memory Controller

Flexible eight-bank memory controller:

• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode

SDRAM machine.

• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable

peripherals.

• Byte enables for either 64-bit or 32-bit bus width mode.

• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus

peripherals and internal memories. Each bank has the following features:

— 32-bit address decoding with programmable mask.

— Variable block sizes (32 KB to 4 GB).

— Selectable memory controller machine.

— Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even

parity for single accesses.

— Write-protection capability.

— Control signal generation machine selection on a per-bank basis.

— Support for internal or external masters on the system bus.

— Data buffer controls activated on a per-bank basis.

— Atomic operation.

— RMW data parity check (on system bus only).

— Extensive external memory-controller/bus-slave support.

— Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus

only).

— Data pipeline to reduce data set-up time for synchronous devices.

Multi-Channel DMA

Controller

• 16 time-multiplexed unidirectional channels.

• Services up to four external peripherals.

• Supports DONE or DRACK protocol on two external peripherals.

• Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:

— A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.

— A hungry request to indicate that the FIFO can accept more data.

• Priority-based time-multiplexing between channels using 16 internal priority levels.

• Round-robin time-multiplexing between channels.

• A flexible channel configuration:

— All channels support all features.

— All channels connect to the system bus or local bus.

• Flyby transfers in which a single data access is transferred directly from the source to the destination without

using a DMA FIFO.

Time-Division

Multiplexing (TDM)

Up to four independent TDM modules, each with the following features:

• Optional operating configurations:

— Totally independent receive and transmit channels, each having one data line, one clock line, and one frame

sync line.

— Four data lines with one clock and one frame sync shared among the transmit and receive lines.

• Connects gluelessly to most T1/E1 framers as well as to common buses such as the ST-BUS.

• Hardware A-law/µ-law conversion.

• Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used,

15.63 MHz if four data lines are used).

• Up to 256 channels.

• Up to 16 MB per channel buffer (granularity 8 bytes), where A/µ law buffer size is double (granularity 16 byte).

• Receive buffers share one global write offset pointer that is written to the same offset relative to their start

address.

• Transmit buffers share one global read offset pointer that is read from the same offset relative to their start

address.

• All channels share the same word size.

• Two programmable receive and two programmable transmit threshold levels with interrupt generation that can

be used, for example, to implement double buffering.

• Each channel can be programmed to be active or inactive.

• 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.

• The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.

• Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge

of the clock.

• Frame sync can be programmed as active low or active high.

• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.

• MSB or LSB first support.

Feature Description

MSC8122 Technical Data, Rev. 12

vi Freescale Semiconductor

Features

Ethernet Controller

• Designed to comply with IEEE® Std 802® including Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™.

• Three Ethernet physical interfaces:

— 10/100 Mbps MII.

— 10/100 Mbps RMII.

— 10/100 Mbps SMII.

• Full and half-duplex support.

• Full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation

and recognition).

• Out-of-sequence transmit queue for initiating flow-control.

• Programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (VLAN)

tags and priority.

• Retransmission from transmit FIFO following a collision.

• CRC generation and verification of inbound/outbound packets.

• Address recognition:

— Each exact match can be programmed to be accepted or rejected.

— Broadcast address (accept/reject).

— Exact match 48-bit individual (unicast) address.

— Hash (256-bit hash) check of individual (unicast) addresses.

— Hash (256-bit hash) check of group (multicast) addresses.

— Promiscuous mode.

• Pattern matching:

— Up to 16 unique 4-byte patterns.

— Pattern match on bit-basis.

— Matching range up to 256 bytes deep into the frame.

— Offsets to a maximum of 252 bytes.

— Programmable pattern size in 4-byte increments up to 64 bytes.

— Accept or reject frames if a match is detected.

— Up to eight unicast addresses for exact matches.

— Pattern matching accepts/rejects IP addresses.

• Filing of receive frames based on pattern match; prioritization of frames.

• Insertion with expansion or replacement for transmit frames; VLAN tag insertion.

• RMON statistics.

• Master DMA on the local bus for fetching descriptors and accessing the buffers.

• Ethernet PHY can be exposed either on GPIO pins or on the high most significant bits of the DSI/system when

the DSI and the system bus are both 32 bits.

• MPC8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode.

• MII Bridge (MIIGSK):

— Programmable selection of the 50 MHz RMII reference clock source (external or internal).

— Independent 2 bit wide transmit and receive data paths.

— Six operating modes.

— Four general-purpose control signals.

— Programmable transmitted inter-frame bits to support inter-frame gap for frames in the SMII domain.

• SMII features:

— Multiplexed only with GPIO signals

— Convey complete MII information between the PHY and MAC.

— Allow direct MAC-to-MAC communication in SMII mode.

— Can generate an interrupt request line while receiving inter-frame segments.

Feature Description

Features

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor vii

UART

• Two signals for transmit data and receive data.

• No clock, asynchronous mode.

• Can be serviced either by the SC140 DSP cores or an external host on the system bus or the DSI.

• Full-duplex operation.

• Standard mark/space non-return-to-zero (NRZ) format.

• 13-bit baud rate selection.

• Programmable 8-bit or 9-bit data format.

• Separately enabled transmitter and receiver.

• Programmable transmitter output polarity.

• Two receiver wake-up methods:

— Idle line wake-up.

— Address mark wake-up.

• Separate receiver and transmitter interrupt requests.

• Nine flags, the first five can generate interrupt request:

— Transmitter empty.

— Transmission complete.

— Receiver full.

— Idle receiver input.

— Receiver overrun.

— Receiver active.

— Noise error.

— Framing error.

— Parity error.

• Receiver framing error detection.

• Hardware parity checking.

• 1/16 bit-time noise detection.

• Maximum bit rate 6.25 Mbps.

• Single-wire and loop operations.

General-Purpose I/O

(GPIO) Port

• 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.

• Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports

open-drain output mode.

I2C Software Module • Booting from a serial EEPROM.

• Uses GPIO timing.

Timers

Two modules of 16 timers each.

• Cyclic or one-shot.

• Input clock polarity control.

• Interrupt request when counting reaches a programmed threshold.

• Pulse or level interrupts.

• Dynamically updated programmed threshold.

• Read counter any time.

Watchdog mode for the timers that connect to the device.

Hardware

Semaphores

Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism.

Global Interrupt

Controller (GIC)

• Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT,

NMI_OUT, and to the cores.

• Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.

• Generation of virtual NMI (one to each SC140 core) by a simple write access.

Reduced Power

Dissipation

• Low power CMOS design.

• Separate power supply for internal logic (1.2 V or 1.1 V) and I/O (3.3 V).

• Low-power standby modes.

• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent).

Packaging

• 0.8 mm pitch flip-chip plastic ball-grid array (FC-PBGA) with lead-free or lead-bearing spheres.

• 431-connection (ball).

•20 mm × 20 mm.

Real-Time Operating

System (RTOS)

The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache,

timers, DMA controller, interrupts, peripherals), as follows:

• High-performance and deterministic, delivering predictive response time.

• Optimized to provide low interrupt latency with high data throughput.

• Preemptive and priority-based multitasking.

• Fully interrupt/event driven.

• Small memory footprint.

• Comprehensive set of APIs.

Feature Description

MSC8122 Technical Data, Rev. 12

viii Freescale Semiconductor

Features

Multi-Core Support • One instance of kernel code in all four SC140 cores.

• Dynamic and static memory allocation from local memory (M1) and shared memory (M2).

Distributed System

Support

Enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks

running in on-board devices or remote network devices:

• Messaging mechanism between tasks using mailboxes and semaphores.

• Networking support; data transfer between tasks running inside and outside the device using networking

protocols.

• Includes integrated device drivers for such peripherals as TDM, UART, and external buses.

Software Support

• Task debugging utilities integrated with compilers and vendors.

• Board support package (BSP) for the application development system (ADS).

• Integrated development environment (IDE):

— C/C++ compiler with in-line assembly so developers can generate highly optimized DSP code. Translates

C/C++ code into parallel fetch sets and maintains high code density.

— Librarian. User can create libraries for modularity.

— A collection of C/C++ functions for developer use.

— Highly efficient linker to produce executables from object code.

— Seamlessly integrated real-time, non-intrusive multi-mode debugger for debugging highly optimized DSP

algorithms. The developer can choose to debug in source code, assembly code, or mixed mode.

— Device simulation models enable design and simulation before hardware availability.

— Profiler using a patented binary code instrumentation (BCI) technique helps developers identify program

design inefficiencies.

— Version control. Metrowerks® CodeWarrior® includes plug-ins for ClearCase, Visual SourceSafe, and

CVS.

Boot Options

• External memory.

• External host.

•UART.

•TDM.

•I

MSC8122ADS

• Host debug through single JTAG connector supports both processors.

• MSC8103 as the MSC8122 host with both devices on the board. The MSC8103 system bus connects to the

MSC8122 DSI.

• Flash memory for stand-alone applications.

• Communications ports:

— 10/100Base-T.

— 155 Mbit ATM over Optical.

— T1/E1 TDM interface.

— H.110.

— Voice codec.

— RS-232.

— High-density (MICTOR) logic analyzer connectors to monitor MSC8122 signals

— 6U CompactPCI form factor.

• Emulates MSC8122 DSP farm by connecting to three other ADS boards.

Feature Description

Product Documentation

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor ix

Product Documentation

The documents listed in Table 1 are required for a complete description of the MSC8122 and are necessary to

design properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the

Freescale DSP website. See the contact information on the back of this document.

Table 1. MSC8122 Documentation

Name Description Order Number

MSC8122

Technical Data

MSC8122 features list and physical, electrical, timing, and package specifications MSC8122

MSC8122

User’s Guide

User information includes system functionality, getting started, and programming

topics

Availability TBD

MSC8122

Reference Manual

Detailed functional description of the MSC8122 memory and peripheral configuration,

operation, and register programming

MSC8122RM

StarCore™ SC140 DSP

Core Reference Manual

Detailed description of the SC140 family processor core and instruction set MNSC140CORE

Application Notes

Documents describing specific applications or optimized device operation including

code examples

Refer to the MSC8122

product page.

MSC8122 Technical Data, Rev. 12

xFreescale Semiconductor

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-1

Signals/Connections 1

The MSC8122 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.

Tabl e 1-1 lists the functional groups, the number of signal connections in each group, and references the table that

gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8122 external signals

organized by function.

Table 1-1. MSC8122 Functional Signal Groupings

Functional Group

Number of

Signal

Connections

Description

Power (VDD, VCC, and GND) 155 Table 1-2 on page 1-3

Clock 3Table 1-3 on page 1-3

Reset and configuration 4 Table 1-4 on page 1-3

DSI, system bus, Ethernet, and interrupts 210 Table 1-5 on page 1-4

Memory controller 16 Table 1-6 on page 1-14

General-purpose input/output (GPIO), time-division multiplexed (TDM) interface,

universal asynchronous receiver/ transmitter (UART), Ethernet, and timers

32 Table 1-7 on page 1-16

Dedicated Ethernet signals 3 Table 1-8 on page 1-23

EOnCE and JTAG test access port 7 Table 1-9 on page 1-24

Reserved (denotes connections that are always reserved) 1 Table 1-10 on page 1-24

MSC8122 Technical Data, Rev. 12

1-2 Freescale Semiconductor

Signals/Connections

HD0/SWTE ↔1

32 ↔A[0–31]

HD1/DSISYNC ↔1 1 ↔TT0/HA7

HD2/DSI64 ↔1 1 ↔TT1

HD3/MODCK1 ↔1 3 ↔TT[2–4]/CS[5–7]

HD4/MODCK2 ↔1 5 →CS[0–4]

HD5/CNFGS ↔1 4 ↔TSZ[0–3]

HD[6–31] ↔26 1↔TBST

HD[32-39]/D[32-39]/reserved ↔8 1 ↔IRQ1/GBL

HD40/D40/ETHRXD0 ↔1 1 ↔IRQ3/BADDR31

HD41/D41/ETHRXD1 ↔1 1 ↔IRQ2/BADDR30

HD42/D42/ETHRXD2/reserved ↔1 1 ↔IRQ5/BADDR29

HD43/D43/ETHRXD3/reserved ↔1 1 →BADDR28

HD[44-45]/D[44-45]/reserved ↔2 1 →BADDR27

HD46/D46/ETHTXD0 ↔1 1 ↔BR

HD47/D47/ETHTXD1 ↔1 1 ↔BG

HD48/D48/ETHTXD2/reserved ↔1 1 ↔DBG

HD49/D49/ETHTXD3/reserved ↔1 1 ↔ABB/IRQ4

HD[50-53]/D[50-53]/reserved ↔4 1 ↔DBB/IRQ5

HD54/D54/ETHTX_EN ↔1 1 ↔TS

HD55/D55/ETHTX_ER/reserved ↔1 1 ↔AACK

HD56/D56/ETHRX_DV/ETHCRS_DV ↔1 1 ↔ARTRY

HD57/D57/ETHRX_ER ↔132 ↔D[0–31]

HD58/D58/ETHMDC ↔1 1 ↔reserved/DP0/DREQ1/EXT_BR2

HD59/D59/ETHMDIO ↔1 1 ↔IRQ1/DP1/DACK1/EXT_BG2

HD60/D60/ETHCOL/reserved ↔1 1 ↔IRQ2/DP2/DACK2/EXT_DBG2

HD[61–63]/D[61-63]/reserved ↔3 1 ↔IRQ3/DP3/DREQ2/EXT_BR3

HCID[0–2] →3

1↔IRQ4/DP4/DACK3/EXT_DBG3

HCID3/HA8 →1 1 ↔IRQ5/DP5/DACK4/EXT_BG3

HA[11–29] →19 1↔IRQ6/DP6/DREQ3

HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3] →4 1 ↔IRQ7/DP7/DREQ4

HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/

PWE[4–7]/PSDDQM[4–7]/PBS[4–7]

↔4 1 ↔TA

HRDS/HRW/HRDE →1 1 ↔TEA

HBRST →1 1 ←NMI

HDST[0–1]/HA[9–10] →2 1 →NMI_OUT

HCS →1 1 ↔PSDVAL

HBCS →1 1 ↔IRQ7/INT_OUT

HTA ←1

1→BCTL0

HCLKIN →1 1 →BCTL1/CS5

GPIO0/CHIP_ID0/IRQ4/ETHTXD0 ↔1

3↔BM[0–2]/TC[0–2]/BNKSEL[0–2]

GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1 ↔1 1 →ALE

GPIO2/TIMER1/CHIP_ID2/IRQ6 ↔1 4 →PWE[0–3]/PSDDQM[0–3]/PBS[0–3]

GPIO3/TDM3TSYN/IRQ1/ETHTXD2 ↔1 1 →PSDA10/PGPL0

GPIO4/TDM3TCLK/IRQ2/ETHTX_ER ↔1 1 →PSDWE/PGPL1

GPIO5/TDM3TDAT/IRQ3/ETHRXD3 ↔1 1 →POE/PSDRAS/PGPL2

GPIO6/TDM3RSYN/IRQ4/ETHRXD2 ↔1 1 →PSDCAS/PGPL3

GPIO7/TDM3RCLK/IRQ5/ETHTXD3 ↔1 1 ↔PGTA/PUPMWAIT/PGPL4/PPBS

GPIO8/TDM3RDAT/IRQ6/ETHCOL ↔1 1 →PSDAMUX/PGPL5

GPIO9/TDM2TSYN/IRQ7/ETHMDIO ↔1

GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC ↔1De

bug

1←EE0

GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD ↔1 1 →EE1

GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC ↔1 C

1→CLKOUT

GPIO13/TDM2RCLK/IRQ11/ETHMDC ↔1 1 ←Reserved

GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC ↔1 1 ←CLKIN

GPIO15/TDM1TSYN/DREQ1 ↔1R

1←PORESET

GPIO16/TDM1TCLK/DONE1/DRACK1 ↔1 1 ↔HRESET

GPIO17/TDM1TDAT/DACK1 ↔1 1 ↔SRESET

GPIO18/TDM1RSYN/DREQ2 ↔1 1 ←RSTCONF

GPIO19/TDM1RCLK/DACK2 ↔1J

1←TMS

GPIO20/TDM1RDAT ↔1 1 ←TDI

GPIO21/TDM0TSYN ↔1 1 ←TCK

GPIO22/TDM0TCLK/DONE2/DRACK2 ↔1 1 ←TRST

GPIO23/TDM0TDAT/IRQ13 ↔1 1 →TDO

GPIO24/TDM0RSYN/IRQ14 ↔1

GPIO25/TDM0RCLK/IRQ15 ↔1

GPIO26/TDM0RDAT ↔1

GPIO27/URXD/DREQ1 ↔1

GPIO28/UTXD/DREQ2 ↔1

GPIO29/CHIP_ID3/ETHTX_EN ↔1Ded.

Eth.

Net

1←ETHRX_CLK/ETHSYNC_IN

GPIO30/TIMER2/TMCLK/SDA ↔1 1 ←ETHTX_CLK/ETHREF_CLK/ETHCLOCK

GPIO31/TIMER3/SCL ↔1 1 ←ETHCRS/ETHRXD

Power signals are: VDD, VDDH, VCCSYN, GND, GNDH, and GNDSYN. Reserved signals can be left unconnected. NC signals must not be connected.

Figure 1-1. MSC8122 External Signals

Power Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-3

1.1 Power Signals

1.2 Clock Signals

1.3 Reset and Configuration Signals

Table 1-2. Power and Ground Signal Inputs

Signal Name Description

VDD Internal Logic Power

VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with

an extremely low impedance path to the VDD power rail.

VDDH Input/Output Power

This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

VCCSYN System PLL Power

VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input

should be provided with an extremely low impedance path to the VCC power rail.

GND System Ground

An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip

ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors.

GNDSYN System PLL Ground

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to

ground.

Table 1-3. Clock Signals

Signal Name Type Signal Description

CLKIN Input Clock In

Primary clock input to the MSC8122 PLL.

CLKOUT Output Clock Out

The bus clock.

Reserved Input Reserved. Pull down to ground.

Table 1-4. Reset and Configuration Signals

Signal Name Type Signal Description

PORESET Input Power-On Reset

When asserted, this line causes the MSC8122 to enter power-on reset state.

RSTCONF Input Reset Configuration

Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in

the

MSC8122 Reference Manual

. This signal is sampled upon deassertion of PORESET.

Note: When PORESET is deasserted, the MSC8122 also samples the following signals:

• BM[0–2]—Selects the boot mode.

• MODCK[1–2]—Selects the clock configuration.

• SWTE—Enables the software watchdog timer.

• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.

Refer to Table 1-5 for details on these signals.

HRESET Input/Output Hard Reset

When asserted as an input, this signal causes the MSC8122 to enter hard reset state. After the device

enters a hard reset state, it drives the signal as an open-drain output.

SRESET Input/Output Soft Reset

When asserted as an input, this signal causes the MSC8122 to enter soft reset state. After the device

enters a soft reset state, it drives the signal as an open-drain output.

MSC8122 Technical Data, Rev. 12

1-4 Freescale Semiconductor

Signals/Connections

1.4 Direct Slave Interface, System Bus, Ethernet, and

Interrupt Signals

The direct slave interface (DSI) is combined with the system bus because they share some common signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Tabl e 1-5

describes the signals in this group.

Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple

external lines that can connect to these internal signal lines. After reset, the default configuration enables

only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for

each required interrupt and reconfigure the other external signal line or lines for alternate functions.

Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals

Signal Name Type Description

HD0

SWTE

Input/ Output

Input

Host Data Bus 0

Bit 0 of the DSI data bus.

Software Watchdog Timer Disable.

It is sampled on the rising edge of PORESET signal.

HD1

DSISYNC

Input/ Output

Input

Host Data Bus 1

Bit 1 of the DSI data bus.

DSI Synchronous

Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising

edge of PORESET signal.

HD2

DSI64

Input/ Output

Input

Host Data Bus 2

Bit 2 of the DSI data bus.

DSI 64

Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET

signal.

HD3

MODCK1

Input/ Output

Input

Host Data Bus 3

Bit 3 of the DSI data bus.

Clock Mode 1

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD4

MODCK2

Input/ Output

Input

Host Data Bus 4

Bit 4 of the DSI data bus.

Clock Mode 2

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD5

CNFGS

Input/ Output

Input

Host Data Bus 5

Bit 5 of the DSI data bus.

Configuration Source

One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of

PORESET signal.

HD[6–31] Input/ Output Host Data Bus 6–31

Bits 6–31 of the DSI data bus.

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-5

HD[32–39]

D[32–39]

Reserved

Input/ Output

Input

Host Data Bus 32–39

Bits 32–39 of the DSI data bus.

System Bus Data 32–39

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD40

D40

ETHRXD0

Input/ Output

Input

Host Data Bus 40

Bit 40 of the DSI data bus.

System Bus Data 40

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 0

In MII and RMII modes, bit 0 of the Ethernet receive data.

HD41

D41

ETHRXD1

Input/ Output

Input

Host Data Bus 41

Bit 41 of the DSI data bus.

System Bus Data 41

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 1

In MII and RMII modes, bit 1 of the Ethernet receive data.

HD42

D42

ETHRXD2

Reserved

Input/ Output

Input

Host Data Bus 42

Bit 42 of the DSI data bus.

System Bus Data 42

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 2

In MII mode only, bit 2 of the Ethernet receive data.

In RMII mode, this pin is reserved and can be left unconnected.

HD43

D43

ETHRXD3

Reserved

Input/ Output

Input

Host Data Bus 43

Bit 43 of the DSI data bus.

System Bus Data 43

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data 3

In MII mode only, bit 3 of the Ethernet receive data.

In RMII mode, this pin is reserved and can be left unconnected.

HD[44–45]

D[44–56]

Reserved

Input/ Output

Input

Host Data Bus 44–45

Bits 44–45 of the DSI data bus.

System Bus Data 44–45

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-6 Freescale Semiconductor

Signals/Connections

HD46

D46

ETHTXD0

Input/ Output

Output

Host Data Bus 46

Bit 46 of the DSI data bus.

System Bus Data 46

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 0

In MII and RMII modes, bit 0 of the Ethernet transmit data.

HD47

D47

ETHTXD1

Input/ Output

Output

Host Data Bus 47

Bit 47 of the DSI data bus.

System Bus Data 47

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 1

In MII and RMII modes, bit 1 of the Ethernet transmit data.

HD48

D48

ETHTXD2

Reserved

Input/ Output

Output

Input

Host Data Bus 48

Bit 48 of the DSI data bus.

System Bus Data 48

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 2

In MII mode only, bit 2 of the Ethernet transmit data.

In RMII mode, this pin is reserved and can be left unconnected.

HD49

D49

ETHTXD3

Reserved

Input/ Output

Output

Input

Host Data Bus 49

Bit 49 of the DSI data bus.

System Bus Data 49

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 3

In MII mode only, bit 3 of the Ethernet transmit data.

In RMII mode, this pin is reserved and can be left unconnected.

HD[50–53]

D[50–53]

Reserved

Input/ Output

Input

Host Data Bus 50–53

Bits 50–53 of the DSI data bus.

System Bus Data 50–53

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD54

D54

ETHTX_EN

Input/ Output

Output

Host Data Bus 54

Bit 54 of the DSI data bus.

System Bus Data 54

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data Enable

In MII and RMII modes, indicates that the transmit data is valid.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-7

HD55

D55

ETHTX_ER

Reserved

Input/ Output

Output

Input

Host Data Bus 55

Bit 55 of the DSI data bus.

System Bus Data 55

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data Error

In MII mode only, indicates a transmit data error.

In RMII mode, this pin is reserved and can be left unconnected.

HD56

D56

ETHRX_DV

ETHCRS_DV

Input/ Output

Input

Host Data Bus 56

Bit 56 of the DSI data bus.

System Bus Data 56

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data Valid

Indicates that the receive data is valid.

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, indicates that a carrier is detected and after the connection is established that the receive

data is valid.

HD57

D57

ETHRX_ER

Input/ Output

Input

Host Data Bus 57

Bit 57 of the DSI data bus.

System Bus Data 57

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Receive Data Error

In MII and RMII modes, indicates a receive data error.

HD58

D58

ETHMDC

Input/ Output

Output

Host Data Bus 58

Bit 58 of the DSI data bus.

System Bus Data 58

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Management Clock

In MII and RMII modes, used for the MDIO reference clock.

HD59

D59

ETHMDIO

Input/ Output

Host Data Bus 59

Bit 59 of the DSI data bus.

System Bus Data 59

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Management Data

In MII and RMII modes, used for station management data input/output.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-8 Freescale Semiconductor

Signals/Connections

HD60

D60

ETHCOL

Reserved

Input/ Output

Input

Host Data Bus 60

Bit 60 of the DSI data bus.

System Bus Data 60

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Collision

In MII mode only, indicates that a collision was detected.

In RMII mode, this pin is reserved and can be left unconnected.

HD[61–63]

D[61–63]

Reserved

Input/ Output

Input

Host Data Bus 61–63

Bits 61–63 of the DSI data bus.

System Bus Data 61–63

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HCID[0–2] Input Host Chip ID 0–2

With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]

matches the Chip_ID, or if HBCS is asserted.

HCID3

HA8

Input

Host Chip ID 3

With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3]

matches the Chip_ID, or if HBCS is asserted.

Host Bus Address 8

Used by an external host to access the internal address space.

HA[11–29] Input Host Bus Address 11–29

Used by external host to access the internal address space.

HWBS[0–3]

HDBS[0–3]

HWBE[0–3]

HDBE[0–3]

Input

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host read or write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host write accesses

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-9

HWBS[4–7]

HDBS[4–7]

HWBE[4–7]

HDBE[4–7]

PWE[4–7]

PSDDQM[4–7]

PBS[4–7]

Input

Output

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host read or write accesses

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory

operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the

address and size of the transaction and the port size of the accessed device.

HRDS

HRW

HRDE

Input

Host Read Data Strobe (In Asynchronous dual mode)

Used as a strobe for host read accesses.

Host Read/Write Select (in Asynchronous/Synchronous single mode)

Host read/write select.

Host Read Data Enable (In Synchronous dual mode)

Indicates valid data for host read accesses.

HBRST Input Host Burst

The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous

mode only.

HDST[0–1]

HA[9–10]

Input Host Data Structure 0–1

Defines the data structure of the host access in DSI little-endian mode.

Host Bus Address 9–10

Used by an external host to access the internal address space.

HCS Input Host Chip Select

DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID.

HBCS Input Host Broadcast Chip Select

DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for

broadcast write accesses.

HTA Output Host Transfer Acknowledge

Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access,

indicates to the host that the data on the data bus was written to the DSI write buffer.

HCLKIN Input Host Clock Input

Host clock signal for DSI synchronous mode.

A[0–31] Input/ Output Address Bus

When the MSC8122 is in external master bus mode, these pins function as the system address bus. The

MSC8122 drives the address of its internal bus masters and responds to addresses generated by external

bus masters. When the MSC8122 is in internal master bus mode, these pins are used as address lines

connected to memory devices and are controlled by the MSC8122 memory controller.

TT0

HA7

Input/ Output Bus Transfer Type 0

The bus master drives this pins during the address tenure to specify the type of the transaction.

Host Bus Address 7

Used by an external host to access the internal address space.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-10 Freescale Semiconductor

Signals/Connections

TT1 Input/ Output Bus Transfer Type 1

The bus master drives this pins during the address tenure to specify the type of the transaction. Some

applications use only the TT1 signal, for example, from MSC8122 to MSC8122 or MSC8122 to MSC8101

and

vice

versa

. In these applications, TT1 functions as read/write signal.

TT[2–4]

CS[5–7]

Input/ Output

Output

Bus Transfer Type 2–4

The bus master drives these pins during the address tenure to specify the type of the transaction.

Chip Select 5–7

Enables specific memory devices or peripherals connected to the system bus.

CS[0–4] Output Chip Select 0–4

Enables specific memory devices or peripherals connected to the system bus.

TSZ[0–3] Input/ Output Transfer Size 0–3

The bus master drives these pins with a value indicating the number of bytes transferred in the current

transaction.

TBST Input/ Output Bus Transfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers

eight words).

IRQ1

GBL

Input

Output

Interrupt Request 11

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Global1

When a master within the MSC8122 initiates a bus transaction, it drives this pin. Assertion of this pin

indicates that the transfer is global and should be snooped by caches in the system.

IRQ3

BADDR31

Input

Output

Interrupt Request 31

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Burst Address 311

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

IRQ2

BADDR30

Input

Output

Interrupt Request 21

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Burst Address 301

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

IRQ5

BADDR29

Input

Output

Interrupt Request 51

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

Bus Burst Address 291

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR28 Output Burst Address 28

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

BADDR27 Output Burst Address 27

Five burst address output pins are outputs of the memory controller. These pins connect directly to

burstable memory devices without internal address incrementors controlled by the MSC8122 memory

controller.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

MSC8122 Technical Data, Rev. 12

Freescale Semiconductor 1-11

BR Input/ Output Bus Request2

When an external arbiter is used, the MSC8122 asserts this pin as an output to request ownership of the

bus. When the MSC8122 controller is used as an internal arbiter, an external master asserts this pin as an

input to request bus ownership.

BG Input/ Output Bus Grant2

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to

an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus

ownership to the MSC8122.

DBG Input/ Output Data Bus Grant2

When the MSC8122 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership

to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data

bus ownership to the MSC8122.

ABB

IRQ4

Input/ Output

Input

Address Bus Busy1

The MSC8122 asserts this pin as an output for the duration of the address bus tenure. Following an

AACK, which terminates the address bus tenure, the MSC8122 deasserts ABB for a fraction of a bus

cycle and then stops driving this pin. The MSC8122 does not assume bus ownership as long as it senses

this pin is asserted as an input by an external bus master.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

DBB

IRQ5

Input/ Output

Input

Data Bus Busy1

The MSC8122 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which

terminates the data bus tenure, the MSC8122 deasserts DBB for a fraction of a bus cycle and then stops

driving this pin. The MSC8122 does not assume data bus ownership as long as it senses that this pin is

asserted as an input by an external bus master.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

TS Input/ Output Bus Transfer Start

Assertion of this pin signals the beginning of a new address bus tenure. The MSC8122 asserts this signal

when one of its internal bus masters begins an address tenure. When the MSC8122 senses that this pin is

asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled,

access internal MSC8122 resources, memory controller support).

AACK Input/ Output Address Acknowledge

A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY Input/ Output Address Retry

Assertion of this signal indicates that the bus master should retry the bus transaction. An external master

asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.

D[0–31] Input/ Output Data Bus Bits 0–31

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave

drives the valid data on this bus.

Reserved

DP0

DREQ1

EXT_BR2

Input

Input/ Output

Input

The primary configuration selection (default after reset) is reserved.

System Bus Data Parity 0

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and

D[0–7].

DMA Request 1

Used by an external peripheral to request DMA service.

External Bus Request 2

An external master asserts this pin to request bus ownership from the internal arbiter.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

MSC8122 Technical Data, Rev. 12

1-12 Freescale Semiconductor

Signals/Connections

IRQ1

DP1

DACK1

EXT_BG2

Input

Input/ Output

Output

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 1

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and

D[8–15].

DMA Acknowledge 1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Bus Grant 22

The MSC8122 asserts this pin to grant bus ownership to an external bus master.

IRQ2

DP2

DACK2

EXT_DBG2

Input

Input/ Output

Output

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 2

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and

D[16–23].

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 22

The MSC8122 asserts this pin to grant data bus ownership to an external bus master.

IRQ3

DP3

DREQ2

EXT_BR3

Input

Input/ Output

Input

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 3

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and

D[24–31].

DMA Request 2

Used by an external peripheral to request DMA service.

External Bus Request 32

An external master should assert this pin to request bus ownership from the internal arbiter.

IRQ4

DP4

DACK3

EXT_DBG3

Input

Input/ Output

Output

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the

SC140 core.

System Bus Data Parity 4

The agent that drives the data bus also drives the data parity signals. The value driven on the data parity

4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and

D[32–39].

DMA Acknowledge 3

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 32

The MSC8122 asserts this pin to grant data bus ownership to an external bus master.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description