FE CM D/ SEMICONDUCTOR DIV LLE D Ml 4832640 0001503 2 MMCAL T-75-27-07 A G8870-1 cmp Microcircuits CMOS DTMF Integrated Receiver Features General Description * CMOS technology for low power consumption The CMD G8870-1 provides full DTMF receiver capability by . id ores ceiver integrating both the bandspiit filter and digital decoder functions * Provides DTMF high and low group filtering into a single 18-pin DIP or 20-pin PLCC pacage. The G8870-t * Adjustable acquisition and release times is manufactured using state-of-the-art CMOS process tech- * Dial tone suppression nology for low power consumption (35 mw max.) and precise * Integrated bandsplit filter and digital decoder functions data handling. The filter section uses a switched capacitor tech- * On-chip differential amplifier, clock oscillator, and latched nique for both high and low group filters and dial tone rejection. three-state bus. The G8870-1 decoder uses digital counting techniques for the * Uses inexpensive 3.58 MHz crystal detection and decoding of all 16 DTMF tone pairs into a 4-bit * Central office quality and performance code, The G8870-1 minimizes external component count by * Single +5 volt power supply providing an on-chip differential input amplifier, clock generator, 18-pin DIP or 20-pin PLCC package and a latched three-state interface bus. The on-chip clock gen- tant erator requires only a low cost TV crystal as an external Applications component. PABX Remote data entry * Central office Receiver system for Conference of Key systems European Postal and Telecommunica- Mobile radio tions (CEPT), and British Telecom Remote control Block Diagram Voo Vss VREF BIAS CIRCUIT CHIP REF CHIP CHIP POWER BIAS cacup a1 FILTER CODE Q2 ZERO DIGITAL IN+ PONE CROSSING DETECTION CONVERTER IN- FILTER 7 DETECTORS [ALGORITHM LATCH os Low Gs | GROUP _ Qa FILTER TO ALi Y y CHIP CLOCKS St STEERING Locic Osc 1 OSC 2 SGT Est StD TOE 4-45CM D/ SEMICONDUCTOR DIV ax cmMD LIE D MM 2834640 00 Absolute Maximum Ratings: (Note 1) Parameter Symbol Value Power Supply Voltage (Vpb-Vss) Voo 6.0V Max Voltage on any Pin Vde Vss-0.3, Voo+0.3 Current on any Pin Ibo 10 mA Max Operating Temperature TA " -40C to +85C Storage Temperature Ts -65C to +150C This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. Notes: 1. Exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied. DC Characteristics: All voltages referenced to Vss unless otherwise noted. Voo = 5.0V, Vss = OV, Ta = 26C. }OOLSO4 4 MMCAL G8870-1 Parameter Symbo! Min Typ Max Units Test Conditions Operating Supply Voltage Voo 4.75 5.25 Vv Operating Supply Current lop 3.0 7.0 mA Power Consumption Po 15 35 mw f = 3.579 MHz; Voo = 5.0V Low Level Input Voitage VIL 1.5 Vv High Level Input Voltage Vin 3.6 v Input Leakage Current LA/TL 0.1 uA Vin = Vss or Voo (Note 11) Pull Up (Source) Current on TOE {so 6.5 15.0 BA TOE =0V Input Impedance, Signal Inputs 1,2 RIN 8 10 Meg 2. @ iKHz Steering Threshold Voltage VTst 2.2 2.5 v Low Level Output Voltage VOL 0.03 Vv No Load High Level Output Voltage VOH 4.97 v No Load Output Low (Sink) Current fou 1.0 2.5 mA VouT =0.4V Output High (Source) Current IoH 0.4 0.8 mA Vout = 4.6V Output Voltage VREF VREF 2.4 2.7 Vv No Load Output Resistance i Ror 10 Ka Operating Characteristics: All voltages referenced to Vss unless otherwise noted. VoD = 5.0V, Vss = OV, TA = 26C. Gain Setting Amplitier Parameter Symbol! Min Typ Max Units Test Conditions Input Leakage Current NIN +100 nA Vss < VIN << VOD Input Resistance Rin 10 MQ Input Offset Voltage Vos 25 mV Power Supply Rejection PSRR 50 dB 1 KHz (Note 12) Common Mode Rejection CMRR 55 dB -3.0 V< VIN< 3.0V DC Open Loop Voltage Gain AVOL 60 dB Open Loop Unity Gain Bandwidth fc 1.2 1.5 MHz : Output Voltage Swing Vo 3.5 Vp-p Ri 2 100K) to Vss ' Tolerable Capacitive Laad (GS) CL - 400 pF Tolerable Resistive Load (GS) Ri 50 KO , Common Mode Range Vem 2.5 Vp-p No Load 4-46 "weetEx" Pf SEMICONDUCTOR DIV LUE D MM 2833640 0001505 & MMCAL T-75-27-07 G8870-1 AC Characteristics: All voltages referenced to Vss unless otherwise noted. VOD = 5.0V, Vss = OV, TA = 25C, fcLK = 3.579545 MHz using test circuit (Fig. 1). Parameter Symbol Min Typ Max Units Notes ] Valid Input Signal Levels 31 4 dBm 1.2.3.4.58 {each tone of composite signal) 21.8 869 mvams{ ; ; -37 dBm Input Signal Level Reject 1,2.3.4.5.8 10.9 mVaMs Positive Twist Accept 10 dB 2.3.4.8 Negative Twist Accept 10 dB Freq. Deviation Accept Limit 1.5% '2Hzt Nom 2.3,5,8, 10 Freq. Deviation Reject Limit "3.5% Nom. 2.3.5 Third Tone Tolerance ~18.5 -16 dB 2.3.4.5, 8. 9,13, 14 Noise Tolerance -12 dB 2.3.4,5.6.8.9 Dial Tone Tolerance +18 +22 dB 2.3.4,5,7,8.9 Tone Present Detection Time top 5 8 14 mS Refer to Tone Absent Detection Time tOA 0.5 3 85 ms Timing Diagram Min. Tone Duration Accept tREC 40 mS (User Adjustable) Max. Tone Duration Reject tREC 20 mS Times shown are Min. Interdigit Pause Accept tio 40 ms obtained with Max. Interdigit Pause Reject too 20 mS ctrcuitin Fig. 1 Propagation Delay (St to Q) tea 6 11 BS Propagation Delay (St to StO) testo 9 nS TOE = Vop Output Data Set Up (Q to StD) tasio 4.0 us Propagation Delay Enable tpTE 50 60 ns Ru = 10K (TOE to Q) Disable tpTo 300 ns CL = 50pF Crystal/Clock Frequency foLk 3.5759 |3.5795| 3.5831 MHz Clock Output Capacitive CLo 30 pF (OSC2) Load NOTES: 1. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load. amplitude. oD Apbon 440 Hz) +2%. . Digit sequence consists of al 16 DTMF tones. . Tone duration = 40 mS. Tone pause = 40 mS. . Nominal OTMF frequencies are used. . Both tones in the composite signal have an equal . Bandwidth limited (0 to 3 KHz) Gaussian Noise. . The precise dial tone frequencies are (350 Hz and 8. For an error rate of better than 1 in 10,000. 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. Input pins defined as IN+, IN-, and TOE. 12, External voltage source used to bias VREF. 13. This parameter also applies to a third tone injected onto the power supply. 14, Referenced to Figure 1. Input DTMF tone level at -28 dBm. 4-47CM D/ SEMICONDUCTOR DIV ax NN ee LUE D MM 1832640 0001506 8 MMCAL G8870-1 cmp T-75-27-07 Timing Diagram | | EVENTS | A | 8 | c | E | & | G eee] fe be tnec-e| LNTERO No -| too TONE DROPOUT vin TONE Wn TONE Nn TONE wr| ftor tate | toma i a Cc svGT 7 LN] _ IT et pa ours CODED TONE 1 K DECODED TONE # jee < DECODED TONE 1 OUTPUTS DECOD ant ane ai-a4 HIGH IMPEDANCE ] nes 1PS10 sto ouTPUT | | | | Livre TOE i | Explanation of Events Explanation of Symbols A) _ Tone bursts detected, tone duration invalid, outputs not VIN DTMF composite input signal. updated. Est Early Steering Output. indicates detection of valid tone B) Tone #n detected, tone duration valid, tone decoded and frequencies. latched in outputs. SVGT Steering input/guard time output. Drives external RC C) End of tone #n detected, tone absent duration valid, timing circuit. outputs remain latched until next valid tone. Q1-Q4 4-bit decoded tone output. D) Outputs switched to high impedance state. StD Delayed Steering Output. Indicates that valid fre- E) Tone #n+1 detected, tone duration valid, tone decoded quencies have been present/absent for the required and latched in outputs (currently high impedance). guard time, thus constituting a valid signal. F) Acceptable dropout of tone #n + 1, tone absent duration TOE Tone Output Enable (input). A low level shifts Q1-Q4 invalid, outputs remain latched. to its high impedance state. G) End of tone #n + 1 detected, tone absent duration valid, {REG == Maximum DTMF signal duration not detected as valid. outputs remain latched until next valid tone. tREC Minimum DTM signal duration required for valid recognition. tip Minimum time between valid OTMF signals. too Maximum allowable drop-out during valid DTMF signal. toP Time to detect the presence of valid DTMF signals. {0A Time to detect the absence of valid DTMF signals. tGTP Guard time, tone present. tGTA Guard time, tone absent. 4-48CM D/ SEMICONDUCTOR DIV bun oe CMD DE D MM 1832640 Functional Description The CMD G8870-1 DTMF Integrated Receiver provides the design engineer with not only low power consumption, but high performance in a small 18-pin DIP or 20-pin PLCC package configuration. The G8870-1's internal architecture consists of a band-split filter section which separates the high and low tones of the received pair, followed by a digital decode (count- ing) section which verifies both the frequency and duration of the received tones before passing the resultant 4-bit code to the output bus. Filter Section Separation of the low-group and high-group tones is achieved by applying the dual-tone signal to the inputs of two 9th-order switched capacitor bandpass filters. The bandwidths of these filters correspond to the bands enclosing the low-group and high-group tones (See Figure 3). The filter section also incorporates notches at 350 Hz and 440 Hz which provides excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor section which smooths the signals prior to limiting. Signal limiting is performed by high- gain comparators, These comparators are provided with a hysteresis to prevent detection of unwanted low-level signals and noise. The outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. Decoder Section The G8870-1 decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that these tones correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while Providing tolerance to small frequency variations. The averaging algorithm has been developed to ensure an opti- mum combination of immunity to talk-off" and tolerance to the presence of interfering signals (third tones) and noise. When the detector recognizes the simultaneous presence of two valid tones (known as signal condition), it raises the Early Steering flag (ESt). Any subsequent toss of signal condition will cause ESt to fall. Steering Circuit Before the registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character- recognition-condition"). This check is performed by an ex- ternal RC time constant driven by ESt. A logic high on ESt causes Vc (See Figure 4) to rise as the capacitor discharges. Providing signal condition is maintained (ESt remains high) for the validation period (tatF), Vc reaches the threshold (VTsv) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (See Figure 2) into the output latch, At this point, the GT output is activated and drives Vc to Voo. GT continues to drive high as [ong as ESt remains high. Finally, after a short delay to allow the output [latch to settle, the delayed steering output flag (StD) goes high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (TOE) toa logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal inter- tuptions (drop outs) too short to be considered a valid pause. This capability, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment In situations which do not require independent selection of receive and pause, the simple steering circuit of Figure 4 is applicable. Component values are chosen according to the following formula: tREC = top + taTP teTP = 0.67 RC The value of top is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 uF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R fora tREc of 40 milliseconds would be 300K. A typical circuit using this steering configuration is shown in Figure 1. The timing requirements for most telecommunication applications are satisfied with this circuit. Different steering arrangements may be used to select independently the guard- times for tone-present (taTP} and tone-absent (t@TA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters such as taik-off and noise immunity. Increasing tRec improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short trec with a long too would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be requirements. Design information for guard time adjustment is shown in Figure 5. Input Configuration The input arrangement of the G8870-1 provides a differential input operational amplifier as well as a bias source (VREF) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 1 with the op-amp connected for unity gain and Veer biasing the input at %Vop. Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor Rs. DTMF Clock Circuit The internal clock circuit is completed with the addition of a standard television color burst crystal having a resonant fre- quency of 3.579545 MHz. A number of G8880 devices can be connected as shown in Figure 8 such that only one crystal is required. osct OSsc2 osc1 osc2 osci osc2 rela! Ly) 1 3.68 MHz pF Figure 8. Common Crystal Connection GO0O150? T MMCAL G8870-1 4-49CM D/ SEMICONDUCTOR DIV cmp T-75-27-07 Pin Function Table Name Description IN* Non-inverting input Connections to the front-end differential amplifier IN- Inverting input Gs Gain Select. Gives access to output of front-end differential amplifier for connection of feedback resistor. VReEF Reference voltage output (nominally Vo0/2). May be used to bias the inputs at mid-rail. IC Internal connection. Must be tied to Vss. IC internal connection. Must be tied to Vss. Osc! Clock input 3.579545 MHz crystal connected between these pins completes internal oscillator. oOsc2 Clock output Vss Negative power supply (Normally connected to 0V). TOE Three-state output enable (input). Logic high enables the outputs Q1-Q4. internal pull-up. Qt Qe Three-state outputs. When enabled by TOE, provides the code corresponding to the last valid tone pair Q3 received. (See Fig. 2.) ~ Qs StD Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SY/GT falls below VTSt. Est Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return toa logic low. SVGT Steering input/guard time output (bidirectional). A voltage greater than VTst detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than Vrst frees the device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See Fig. 2.) Voo Positive power supply 5v fFlrow | FHIGH | KEY | TOE | 4 Q3 Q2 a Gas70-1 Ot uF 1 697 1209 1 H 0 0 0 1 0.1 nF Ne Voo- +e 697 | 1336 | 2 | H | Oo | O 1 0 Oo wat IN- SGT[} 100 kit as estt 300 Kit 697 1477 3 H 0 0 1 1 tookitL_ +] yee sto -4 O 770 1209 4 H 0 1 0 0 (J IG atc+-t+_O 770 1336 5 H 0 1 0 1 $J Ic Qaf7+4--O 770 1477 6 H 0 1 1 0 58 -C 1 OSC 1 att; MHz & osc2 a - 852 1209 7 H a 1 1 1 o___C vss TOE 852 1336 8 H 1 9 0 0 V1 g52 | 1477 | 9 H 1 0 0 1 All resistors ~1% tolerance, All capacitors =5% tolerance. 941 1336 9 H 1 9 1 9 941 1209 . H 1 0 1 1 Figure 1. Single Ended Input 941 | i477 | # H 1 1 o | 0 Configuration Test Circult 697 | 1633 | A H 1 1 9 1 770 1633 B H 1 1 1 0 852 1633 c H 1 1 1 i 941 1633 Do H 0 0 0 0 _ ANY L Zz Zz Zz Zz L = LOGIC LOW, H = LOGIC HIGH, Z = HIGH IMPEDANCE Figure 2. Functional Decode Table 4-50 DLE D MM 2830640 0001508 1 MMCAL | G8870-1CM D/ SEMICONDUCTOR DIV A. CMD VE D MM 2834640 0001509 3 MMCAL T-75-27-07 G8870-1 10 ATTENUATION dB s oth HEHE AED 4 xy ape o1K ge F g@ 4y FREQUENCY Hz PRECISE DIAL TONES DTMF TONES X= 350 Hz A = 697 Hz E = 1209 Hz Y= 440 Hz B=770Hz2 F = 1336 Hz C>852Hz G = 1477Hz D=941Hz2 H = 1633Hz Figure 3. Typical Filter Characteristic 0 c suet O Rt Ra RiR2 est i Re= a Aa a) Decreasing tata (taTP > taTa) OF vi c (faTR= (RpC) In (vas aya ) = Voo tate =(R1C} In (wove) : Yoo tata = (RPC) In ( var) sveTO q tava = (AIC) In (=) Ri Ra RiR2 Est O Ree Ries b) Decreasing tarp (iGTP < tata) Figure 5. Guard Time Adjustment suGT Ve Est SID Vist tGTaA=RC In ( Voo ) Voo =(BC os - tere =(RC) In (ee ) Figure 4. Basic Steering Circuit {f iN - ci Ri f IN - - { Hw 8870-1 C2 Ra Gs Rs Rs Rz Vrer >. O DIFFERENTIAL INPUT AMPLIFIER C1=C2=100F Al =RAa=As = 100 KN Az = 60K), A3 = 37.5 KO RaRs A2+Rs Aa= As VOLTAGE GAIN (Av diff) = Ar INPUT IMPEOANCE (ZiNoIFF) = 2 A+ (4 y wf Allresistors are 1% tolerance. All capacitors are 5 tolerance. Figure 6. Differentiat Input Configuration 4-51IN cmMpD CM DZ SEMICONDUCTOR DIV DLE D MM 1832640 OO01510 T MMCAL Application Receiver System for British Telecom Spec POR 1151 The circuit shown in Fig. 8 illustrates the use of the G8870-1 device in a typical receiver system. The British Telecom specifications define the input signals less than -34 dBm as the non-operate level. This condition can be attained by choosing suitable values for Ri and R2 to provide 3 dB attenu- ation, such that the -34 dBm input signal will correspond to -37 dBm at the gain setting pin GS of the G8870-1. As shown in the diagram, the component values of R3 and C2 are the guard time requirement when the total component tolerance is 6%. For better performance, it is recommended to use the non-symmetric guard time circuit in Fig. 7. er ct Ss IN Voo[ +4 DTMF O-| bo] IN- SUGT[7} Input At as est{ fa Lo Vagr sio 1S 477 ae _C ic ast +4 J 1c Qa 4 =T_] osci acs =C] osc2 Qa oo] vss TOE Voo oO) svGr 4 T-75-27-07 G8870-1 tote = (RPC1) In [Voo/(Voo-VTst)} ci {ava = (R1C1) In (VDO/VTST) Re = R1A2/(A1 + R2) Ri a2 Est O_* Ai = 368 Kit Allresistors are 1% tolerance. R2= 2.260 Allcapacitors are 5% tolerance. 1 = 100nF Figure 7, Non-Symmetric Guard Time Circult O G8870-1 | J ~ C2 AAA bass Ra All resistors are > 1% tolerance. All capacitors are +5% tolerance. R1 = 102 Kt A2= 74.5 Ko Ra =390 Ki} 1,C2 = 100 nF X1 = 3.579545 MHz -0.1% Figure 8. Single Ended Input Configuration for British Telecom or CEPT Specifications 4-521431640 OO01511 1 G8870-1 CM D/ SEMICONDUCTOR DIV LLE D cmMD - T-75-27-07 Pin Function Pin Description Pin Description IN+ Non-Inverting Input Q1-4 Three-State Data Outputs IN- Inverting Input Sto Delayed Steering Output Gs Gain Select ESt Early Steering Output Ic Internal Connection St/GT|Steering Input/Guard Time tnput OSC1 Clock Input VREF Reference Voltage Output oOsce Clock Output Vss Negative Power Supply TOE Three-State Output Enable Vop Positive Power Supply Pin Configuration _- tne C1 18 kL Voo In- C2 17) set os (3 16[) Est Vaer C4 Gss70-1 18) Sto ic* C5 14 [7 Oa Ic C6 13/9 Q3 osc1 (|? fa osc2 C8 neaa Vss J9 10 [7 TOE *CONNECT TO Vss Nc IN- IN+ Voo SUVGT 1011 12 Est sto Nc Qs Ordering information Description CSpecial GStandard Product Identification Number Package PPlastic ELeaded Chip Carrier CCeramic LLeadless Chip Carrier DCerdip XDice Temperature/ Processing None 0C ta+70C, + 5% PS. Tol, I~ -40C to +85C, 5% P.S. Tol. 4-53 2020 D-13