© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 1 1Publication Order Number:
NB3V8312C/D
NB3V8312C
Ultra-Low Jitter, Low Skew
1:12 LVCMOS/LVTTL Fanout
Buffer
The NB3V8312C is a high performance, low skew LVCMOS
fanout buffer which can distribute 12 ultra−low jitter clocks from an
LVCMOS/LVTTL input up to 250 MHz.
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
Separate VDD core and VDDO output supplies allow the output
buffers to operate at the same supply as the VDD (VDD = VDDO) or
from a lower supply voltage. Compared to single−supply operation,
dual supply operation enables lower power consumption and
output−level compatibility.
The VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V,
while the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or
1.8 V, with the constraint that VDD ≥ VDDO.
This buffer is ideally suited for various networking, telecom, server
and storage area networking, RRU LO reference distribution, medical
and test equipment applications.
Features
•Power Supply Modes:
VDD (Core) / VDDO (Outputs)
3.3 V / 3.3 V
3.3 V / 2.5 V
3.3 V / 1.8 V
2.5 V / 2.5 V
2.5 V / 1.8 V
1.8 V / 1.8 V
•250 MHz Maximum Clock Frequency
•Accepts LVCMOS, LVTTL Clock Inputs
•LVCMOS Compatible Control Inputs
•12 LVCMOS Clock Outputs
•Synchronous Clock Enable
•Output Enable to High Z State Control
•150 ps Max. Skew Between Outputs
•Temp. Range −40°C to +85°C
•32−pin LQFP and QFN Packages
•These are Pb−Free Devices
Applications
•Networking
•Telecom
•Storage Area Network
End Products
•Servers
•Routers
•Switches
LQFP−32
FA SUFFIX
CASE 873A
See detailed ordering and shipping information on page 9 o
f
this data sheet.
ORDERING AND MARKING INFORMATION
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Figure 1. Simplified Logic Diagram
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q
DCLK_EN
CLK
OE
GND
VDDO
VDD
QFN32
MN SUFFIX
CASE 488AM
32
1
RPU
RPU
RPD
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2
Figure 2. LQFP−32 Pinout Configuration
(Top View)
Q11
VDDO
Q10
GND
Q9
VDDO
Q8
GND
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
GND
GND
GND
GND
Q7
VDDO
Q6
GND
Q5
Q4
VDDO
VDD
CLK_EN
CLK
OE
VDD
Figure 3. QFN32 Pinout Configuration
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Exposed
NB3V8312C
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17 GND
GND
GND
VDD
CLK_EN
CLK
OE
VDD
GND
Q7
VDDO
Q6
GND
Q5
Q4
VDDO
32 31 252630 272829
910 161511 141312
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
Q11
VDDO
Q10
GND
Q9
VDDO
Q8
GND
NB3V8312C
Pad (EP)
Table 1. PIN DESCRIPTION
Pin Name I/O Open
Default Description
1, 5, 8, 12, 16, 17,
21, 25, 29 GND Power Ground, Negative Power Supply
2, 7 VDD Power Positive Supply for Core and Inputs
3 CLK_EN Input High Synchronous Clock Enable Input. When High, outputs
are enabled. When Low, outputs are disabled Low.
Internal Pullup Resistor.
4 CLK Input Low Single−ended Clock input; LVCMOS/LVTTL. Internal
Pull−down Resistor.
6 OE Input High Output Enable. Internal Pullup Resistor.
9, 11, 13, 15, 18,
20, 22, 24, 26, 28,
30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output Single−ended LVCMOS/LVTTL outputs
10, 14, 19, 23, 27,
31 VDDO Power Positive Supply for Outputs
− EP − − The Exposed Pad (EP) on the package bottom is ther-
mally connected to the die for improved heat transfer
out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is connected to the die
and must only be connected electrically to GND on the
PC board.
1. All VDD, VDDO and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with
0.01 mF to GND.
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Figure 4. CLK_EN Control Timing Diagram
CLK
CLK_EN
Q
Table 2. OE, CLK_EN FUNCTION TABLES
Inputs Outputs
OE CLK_EN (Note 2) CLK Q[0:11]
0 X X Hi−Z
1 0 X Low
1 1 0 Low
1 1 1 High
2. The CLK_EN control input synchronously enables or disables the outputs as shown in Figure 4.
This cont r o l l a t c h e s o n t h e f a l l i ng e d g e o f t he s e l e c t e d i n p u t C L K. W h e n C L K _E N i s L O W, the
outputs are disabled in a LOW state. When CLK_EN is HIGH, the outputs are enabled as
shown. CLK_EN to CLK Set up and Hold times must be satisfied.
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Table 3. ATTRIBUTES (Note 3)
Characteristics Value
Internal Input Pullup (RPU) and Pulldown (RPD) Resistor 50 kW
Input Capacitance, CIN 4 pF
Power Dissipation Capacitance, CPD (per Output) 20 pF
ROUT 8 W
ESD Protection Human Body Model
Machine Model > 1.5 kV
> 200 V
Moisture Sensitivity (Note 3) LQFP
QFN Level 2
Level 1
Flammability Rating
Oxygen Index UL−94 code V−0 A 1/8”
28 to 34
Transistor Count 464 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 4)
Symbol Parameter Condition Rating Unit
VDD /
VDDO Positive Power Supply GND = 0 V 4.6 V
VIInput Voltage −0.5 v VI v VDD + 0.5 V
Tstg Storage Temperature Range −65 to +150 °C
qJA Thermal Resistance (Junction−to−Ambient)
(Note 5) 0 lfpm
500 lfpm LQFP−32
LQFP−32 80
55 °C/W
°C/W
qJC Thermal Resistance (Junction−to−Case)
(Note 5) Standard Board LQFP−32
LQFP−32 12−17 °C/W
qJA Thermal Resistance (Junction−to−Ambient)
(Note 5) 0 lfpm
500 lfpm QFN*32
QFN*32 31
27 °C/W
qJC Thermal Resistance (Junction−to−Case)
(Note 5) Standard
Board QFN*32 12 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
4. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
5. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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Table 5. LVCMOS/LVTTL DC CHARACTERISTICS (TA = −40°C to +85°C)
Symbol Characteristics Conditions Min Typ Max Unit
VIH Input High Voltage
VDD = 3.465 V 2.0 VDD +
0.3 V
VDD = 2.625 V 1.7 VDD +
0.3 V
VDD = 2.0 V 0.65 x
VDD VDD +
0.3 V
VIL Input Low Voltage
VDD = 3.465 V −0.3 1.3 V
VDD = 2.625 V −0.3 0.7 V
VDD = 2.0 V −0.3 0.35 x
VDD V
IIH Input High
Current CLK VDD = VIN = 3.465 V or 2.625 V or 2.0 V 150 mA
OE, CLK_EN 5
IIL Input Low
Current CLK VDD = 3.465 V or 2.625 V or 2.0 V, VIN = 0 V −5 mA
OE, CLK_EN −150
VOH Output High Voltage (Note 6)
VDDO = 3.3 V ±5% 2.6
V
VDDO = 2.5 V ±5% 1.8
VDDO = 2.5 V ±5%; IOH = −1 mA 2.0
VDDO = 1.8 V ±0.2 V VDD –
0.4
VDDO = 1.8 V ±0.2 V; IOH = −100 mAVDD –
0.2
VOL Output Low Voltage (Note 6)
VDDO = 3. 3V ±5% 0.5
V
VDDO = 2.5 V ±5% 0.45
VDDO = 2.5 V ±5%; IOL = 1 mA 0.4
VDDO = 1.8 V ±0.2 V 0.35
VDDO = 1.8 V ±0.2 V; IOL = 100 mA0.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to VDDO/2 unless otherwise specified. See Figure 7.
Table 6. POWER SUPPLY DC CHARACTERISTICS, (TA = −40°C to +85°C)
VDD (Core) VDDO (Outputs) Min Typ Max Unit
3.3 V ±5% 3.3 V ±5% 10 mA
3.3 V ±5% 2.5 V ±5% 10 mA
3.3 V ±5% 1.8 V ± 0.2V 10 mA
2.5 V ±5% 2.5 V ±5% 10 mA
2.5 V ±5% 1.8 V ± 0.2V 10 mA
1.8 V ± 0.2 V 1.8 V ± 0.2V 10 mA
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Table 7. AC CHARACTERISTICS (TA = −40°C to +85°C) (Note 7)
Symbol Characteristic Min Typ Max Unit
fMAX Maximum Operating Frequency VDD / VDDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
250
250
200
250
200
200
MHz
tpLH Propagation Delay, Low to High; (Note 8) VDD / VDDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
0.9
1.0
1.0
1.3
1.3
2.4
2.2
2.3
3.0
3.1
3.5
4.2
ns
tjit Additive Phase Jitter, RMS; VDD / VDDO
fC = 100 MHz 3.3 V ±5% / 3.3 V ±5%
Integration Range: 12 kHz − 20 MHz 3.3 V ±5% / 2.5 V ±5%
See Figure 5 3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
30
40
50
20
100
130
fs
tsk(o) Output−to−output skew; (Note 9); Figure 6 VDD / VDDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
125
135
145
150
150
140
ps
tsk(pp) Part−to−Part Skew; (Note 10) VDD / VDDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
250
250
250
250
250
250
ps
tr/tfOutput rise and fall times VDD / VDDO
3.3 V ±5% / 3.3 V ±5%
3.3 V ±5% / 2.5 V ±5%
3.3 V ±5% / 1.8 V ± 0.2 V
2.5 V ±5% / 2.5 V ±5%
2.5 V ±5% / 1.8 V ± 0.2 V
1.8 V ± 0.2 V / 1.8 V ± 0.2 V
200
200
200
200
200
200
700
700
700
700
700
800
ps
ODC Output Duty Cycle (Note 11) VDD / VDDO
f ≤ 200 MHz, 3.3 V ±5% / 3.3 V ±5%
f ≤ 150 MHz, 3.3 V ±5% / 2.5 V ±5%
f ≤ 100 MHz, 3.3 V ±5% / 1.8 V ± 0.2 V
f ≤ 150 MHz, 2.5 V ±5% / 2.5 V ±5%
f ≤ 100 MHz, 2.5 V ±5% / 1.8 V ± 0.2 V
f ≤ 100 MHz, 1.8 V ± 0.2 V / 1.8 V ± 0.2 V
45
45
45
45
45
45
55
55
55
55
55
55
%
All parameters measured at fMAX unless noted otherwise.
7. Outputs loaded with 50 W to VDDO/2; see Figure 7. CLOCK input with 50% duty cycle; minimum input amplitude = 1.2 V at VDD = 3.3 V,
1.0 V at VDD = 2.5 V, VDD/2 at VDD = 1.8 V.
8. Measured from the VDD/2 of the input to VDDO/2 of the output.
9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
10.Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
11.Clock input with 50% duty cycles, rail−to−rail amplitude and tr/tf = 500 ps.
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Figure 5. Typical Phase Noise Plot at fcarrier = 100 MHz at an Operating Voltage of 3.3 V, Room Temperature
NB3V8312C
Additive Phase Jitter @ 100 MHz
VDD = VDDO = 3.3 V
12 kHz to 20 MHz = 29.8 fs (typical)
Filter = 12 kHz − 20 MHz
Source RMS Jitter = 200.53 fs
Output RMS Jitter = 202.73 fs
RMS addititive jitter +RMS phase jitter of output2*RMS phase jitter of input2
Ǹ
29.8 +202.73 fs2*200.53 fs2
Ǹ
Output (DUT + Source)
Input Source
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The RMS Phase Jitter
contributed by the device (integrated between 12 kHz and
20 MHz) is 29.8 fs.
The additive phase jitter performance of the fanout buffer
is highly dependent on the phase noise of the input source.
To obtain the most accurate additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source i s greater than the device under test output, the source
noise will dominate the additive phase jitter calculation and
lead to an artificially low result for the additive phase noise
measurement within the integration range. The Figure above
is a good example of the NB3V8312C source generator
phase noise having a significantly higher floor such that the
DUT output results in an additive phase jitter of 29.8 fs.
RMS addititive jitter +RMS phase jitter of output2*RMS phase jitter of input2
Ǹ
29.8 +202.73 fs2*200.53 fs2
Ǹ
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Figure 6. AC Reference Measurement
VIHCMR
GND
tPHL
tLH
CLK
CLK
Qx
Qx
tPW
tP
VDD
2
tSKEWDC %+ǒtPWńtPǓ 100
VDD
2
VDD
2
VDD
2
VDDO
2
VDDO
2
VDDO
2
VDDO
2
VDDO
2
LVCMOS_CLK
VPP = VIH − VIL
IN
ZO = 50 W
NB3V8312C Scope
50 W
VDD VDDO
GND
Figure 7. Typical Device Evaluation and Termination Setup − See Table 8
VDDO ÷ 2 = 0 V = Ground
Qx
Table 8. TEST SUPPLY SETUP. VDDO SUPPLY MAY BE CENTERED ON 0.0 V (SCOPE GND) TO PERMIT DIRECT
CONNECTION INTO “50 W TO GND” SCOPE MODULE. VDD SUPPLY TRACKS DUT GND PIN
Spec Condition: VDD Test Setup VDDO Test Setup GND Pin Test Setup
VDD = 3.3 V ±5%, VDDO = 3.3 V ±5% +1.65 ±5% +1.65 V ±5% −1.65 V ±5%
VDD = 3.3 V ±5%, VDDO = 2.5 V ±5% +2.05 V ±5% +1.25 V ±5% −1.25 V ±5%
VDD = 3.3 V ±5%, VDDO = 1.8 V ±5% +2.4 V ±5% +0.9 V ±0.1 V −0.9 V ±0.1 V
VDD = 2.5 V ±5%, VDDOO = 2.5 V ±5% +1.25 V ±5% +1.25 V ±5% −1.25 V ±5%
VDD = 2.5 V ±5%, VDDO = 1.8 V ±0.2 V +1.6 V ±5% +0.9 V ±0.1 V −0.9 V ±0.1 V
VDD = 1.8 V ±0.2 V, VDDO = 1.8 V ±0.2 V +0.9 V ±0.1 V +0.9 V ±0.1 V −0.9 V ±0.1 V
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MARKING DIAGRAMS*
*For additional marking information, refer to
Application Note AND8002/D.
(*Note: Microdot may be in either location)
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
NB3V
8312C
AWLYYWWG NB3V
8312C
AWLYYWWG
132
LQFP−32 QFN32
ORDERING INFORMATION
Device Package Shipping†
NB3V8312CFAG LQFP−32
(Pb−Free) 250 Units / Tray
NB3V8312CFAR2G LQFP−32
(Pb−Free) 2000 / Tape & Reel
NB3V8312CMNG QFN32
(Pb−Free) 74 Units / Rail
NB3V8312CMNR4G QFN32
(Pb−Free) 1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE C
ÉÉ
ÉÉ
ÉÉ
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE−AE
G
SEATING
PLANE
R
Q_
WK
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1 V1
4X
S
4X
9
−T−
−Z−
−U−
T-U0.20 (0.008) Z
AC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
−AC−
−AB−
M_
8X
−T−, −U−, −Z−
T-U
M
0.20 (0.008) ZAC
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DA TUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B7.000 BSC 0.276 BSC
C1.400 1.600 0.055 0.063
D0.300 0.450 0.012 0.018
E1.350 1.450 0.053 0.057
F0.300 0.400 0.012 0.016
G0.800 BSC 0.031 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.450 0.750 0.018 0.030
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.400 BSC 0.016 BSC
Q1 5 1 5
R0.150 0.250 0.006 0.010
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
___ _
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
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PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
SEATING
NOTE 4
K
0.15 C
(A3)
A
A1
D2
b
1
9
17
32
E2
32X
8
L
32X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA
B
E
0.15 C
ÉÉ
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C C
25
e
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
3.35
0.30
3.35
32X
0.63
32X
5.30
5.30
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
ÉÉ
ÉÉ
ÇÇ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL B
DET AIL A
DIM
AMIN
MILLIMETERS
0.80
A1 −−−
A3 0.20 REF
b0.18
D5.00 BSC
D2 2.95
E5.00 BSC
2.95
E2
e0.50 BSC
0.30
L
K0.20
1.00
0.05
0.30
3.25
3.25
0.50
−−−
MAX
−−−
L1 0.15
e/2 NOTE 3
PITCH DIMENSION: MILLIMETERS
RECOMMENDED
A
M
0.10 BC
M
0.05 C
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reserves the r ight t o m ake c hanges wit hout f urt her n ot ice t o a ny p roduct s h erein. SCILLC makes no warrant y, r epresent ation o r guarantee regarding t he s uitability o f i ts p roducts f or a ny
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation s pecial, c onsequential o r i ncidental d amages. “T ypical” p arameters w hich m ay b e p rovided in SCILLC d ata s heets a nd/ or s pecif ications c an a nd d o v ary i n d if ferent a pplicat ions
and actual performance may vary over time. All operating parameters, including “Typical s” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under i ts p at ent rights nor the right s o f o thers. SCILLC products are n ot d esigned, intended, or authorized f or use as components in systems intended for
surgical implant i nto t he b ody, o r other applications i ntended t o s upport or sustain l ife, o r f or a ny o ther a pplication i n w hich t he f ailure o f t he S CILLC p roduct c ould c reate a s ituation w here
personal injury or death may occur. Should Buyer purchase o r u se S CI LLC p roduct s for any such unintended or unauthorized application, B uyer shall indemnify and hold SCILLC and
its o f ficers, e mployees, s ubsidiaries, a ff iliates, and d istributors h armless against a ll c laims, c ost s, damages, a nd e xpenses, a nd r easonable a ttorney f ees a rising o ut o f, d irectly o r indirectly ,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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