© 2009 Microchip Technology Inc. DS21668D-page 1
MCP6141/2/3/4
Features:
• Low Quiescent Current: 600 nA/amplifier (typical)
• Gain Bandwidth Product: 100 kHz (typical)
• Stable for gains of 10 V/V or higher
• Rail-to-Rail Input/Output
• Wide Supply Voltage Range: 1.4V to 6.0V
• Available in Single, Dual, and Quad
• Chip Select (CS) with MCP6143
• Available in 5-lead and 6-lead SOT-23 Packages
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Applications:
• Toll Booth Tags
• Wearable Products
• Temperature Measurement
•Battery Powered
Design Aids:
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Simulation Tool
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Related Devices:
• MCP6041/2/3/4: Unity Gain Stable Op Amps
Typical Application
Description:
The MCP6141/2/3/4 family of non-unity gain stable
operational amplifiers (op amps) from Microchip
Technology Inc. operate with a single supply voltage as
low as 1.4V, while drawing less than 1 µA (maximum)
of quiescent current per amplifier. These devices are
also designed to support rail-to-rail input and output
operation. This combination of features supports
battery-powered and portable applications.
The MCP6141/2/3/4 amplifiers have a gain bandwidth
product of 100 kHz (typical) and are stable for gains of
10 V/V or higher. These specifications make these op
amps appropriate for battery powered applications
where a higher frequency response from the amplifier
is required.
The MCP6141/2/3/4 family operational amplifiers are
offered in single (MCP6141), single with Chip Select
(CS) (MCP6143), dual (MCP6142) and quad
(MCP6144) configurations. The MCP6141 device is
available in the 5-lead SOT-23 package, and the
MCP6143 device is available in the 6-lead SOT-23
package.
Package Types
MCP614X
VOUT
RF
R3
V3
R2
V2
R1
V1
VREF
Inverting, Summing Amplifier
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NC
NC
MCP6141
PDIP, SOIC, MSOP
MCP6142
PDIP, SOIC, MSOP
MCP6143
PDIP, SOIC, MSOP
MCP6144
PDIP, SOIC, TSSOP
VINA+
VINA–
VSS
VOUTB
VINB–
1
2
3
4
8
7
6
5VINB+
VDD
VOUTA
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
VINA+
VINA–
VDD
VIND–
VIND+
1
2
3
4
14
13
12
11 VSS
VOUTD
VOUTA
VINB–
VINB+
VOUTB
VINC+
VINC–
5
6
7
10
9
8VOUTC
VIN+
VSS
VIN–
1
2
3
5
4
VDD
VOUT
MCP6141
SOT-23-5
VIN+
VSS
VIN–
1
2
3
6
4
VDD
VOUT
MCP6143
SOT-23-6
5CS
600 nA, Non-Unity Gain Rail-to-Rail Input/Output Op Amps
MCP6141/2/3/4
DS21668D-page 2 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 3
MCP6141/2/3/4
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Analog Input Pins.........................................±2 mA
Analog Inputs (VIN+, VIN–) †† ........ VSS –1.0VtoV
DD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ................................... –65°C to +150°C
Maximum Junction Temperature (TJ)......................... .+150°C
ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC ELECTRICAL CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS =GND, T
A=+25°C, V
CM =V
DD/2,
VOUT ≈VDD/2, VL=V
DD/2, RL = 1 MΩ to VL and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3 — +3 mV VCM = VSS
Drift with Temperature ΔVOS/ΔTA—±1.8 —µV/°CV
CM = VSS, TA= -40°C to +85°C
ΔVOS/ΔTA—±10 —µV/°CV
CM = VSS,
TA = +85°C to +125°C
Power Supply Rejection PSRR 70 85 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB—1 —pA
Industrial Temperature IB— 20 100 pA TA = +85°
Extended Temperature IB— 1200 5000 pA TA = +125°
Input Offset Current IOS —1 —pA
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||6 — Ω||pF
Common Mode
Common-Mode Input Range VCMR VSS−0.3 — VDD+0.3 V
Common-Mode Rejection Ratio CMRR 62 80 — dB VDD = 5V, VCM = -0.3V to 5.3V
CMRR 60 75 — dB VDD = 5V, VCM = 2.5V to 5.3V
CMRR 60 80 — dB VDD = 5V, VCM = -0.3V to 2.5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 95 115 — dB RL = 50 kΩ to VL,
VOUT = 0.1V to VDD−0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS +10 — V
DD −10 mV RL = 50 kΩ to VL,
0.5V input overdrive
Linear Region Output Voltage Swing VOVR VSS + 100 — VDD −100 mV RL = 50 kΩ to VL,
AOL ≥ 95 dB
Output Short Circuit Current ISC —2 —mAV
DD = 1.4V
ISC —20 —mAV
DD = 5.5V
Power Supply
Supply Voltage VDD 1.4 — 6.0 V Note 1
Quiescent Current per Amplifier IQ0.3 0.6 1.0 µA IO = 0
Note 1: All parts with date codes February 2008 and later have been screened to ensure operation at VDD = 6.0V. However, the
other minimum and maximum specifications are measured at 1.8V and 5.5V
MCP6141/2/3/4
DS21668D-page 4 © 2009 Microchip Technology Inc.
AC ELECTRICAL CHARACTERISTICS
MCP6143 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS
FIGURE 1-1: Chip Select (CS) Timing
Diagram (MCP6143 only).
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS =GND, T
A=+25°C, V
CM =V
DD/2,
VOUT ≈VDD/2, VL=V
DD/2, RL = 1 MΩ to VL, CL= 60 pF and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 100 — kHz
Slew Rate SR — 24 — V/ms
Phase Margin PM — 60 — ° G = +10 V/V
Noise
Input Voltage Noise Eni —5.0—µV
P-P f = 0.1 Hz to 10 Hz
Input Voltage Noise Density eni —170—nV/√Hz f = 1 kHz
Input Current Noise Density ini —0.6—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS =GND, T
A=+25°C, V
CM =V
DD/2,
VOUT ≈VDD/2, VL=V
DD/2, RL = 1 MΩ to VL, and CL= 60 pF (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —V
SS+0.3 V
CS Input Current, Low ICSL —5—pACS = VSS
CS High Specifications
CS Logic Threshold, High VIH VDD–0.3 — VDD V
CS Input Current, High ICSH —5—pACS = VDD
CS Input High, GND Current ISS —-20—pACS = VDD
Amplifier Output Leakage, CS High IOLEAK —20—pACS = VDD
Dynamic Specifications
CS Low to Amplifier Output Turn-on Time tON — 2 50 ms G = +1 V/V, CS = 0.3V to
VOUT = 0.9VDD/2
CS High to Amplifier Output High-Z tOFF — 10 — µs G = +1 V/V, CS = VDD–0.3V to
VOUT = 0.1VDD/2
Hysteresis VHYST —0.6— VV
DD = 5.0V
VIL
High-Z
tON
VIH
CS
tOFF
VOUT
-20 pA
High-Z
ISS
ICS 5 pA (typical) 5 pA (typical)
-20 pA
-0.6 µA
(typical)(typical)
(typical)
© 2009 Microchip Technology Inc. DS21668D-page 5
MCP6141/2/3/4
TEMPERATURE CHARACTERISTICS
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
Electrical Characteristics: Unless otherwise indicated, VDD = +1.4V to +5.5V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C Industrial Temperature parts
TA-40 — +125 °C Extended Temperature parts
Operating Temperature Range TA-40 — +125 °C (Note 1)
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA —256—°C/W
Thermal Resistance, 6L-SOT-23 θJA —230—°C/W
Thermal Resistance, 8L-MSOP θJA —206—°C/W
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA —163—°C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA —120—°C/W
Thermal Resistance, 14L-TSSOP θJA —100—°C/W
Note 1: The MCP6141/2/3/4 family of Industrial Temperature op amps operates over this extended range, but with
reduced performance. In any case, the internal Junction Temperature (TJ) must not exceed the Absolute
Maximum specification of +150°C.
VDD
MCP614X
RGRF
RNVOUT
VIN
VDD/2
1µF
CLRL
VL
0.1 µF
VDD
MCP614X
RGRF
RNVOUT
VDD/2
VIN
1µF
CLRL
VL
0.1 µF
MCP6141/2/3/4
DS21668D-page 6 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 7
MCP6141/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.4V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL=V
DD/2, RL=1MΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift
with TA= -40°C to +85°C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage with VDD =1.4V.
FIGURE 2-4: Input Offset Voltage Drift
with TA= +85°C to +125°C and VDD =1.4V.
FIGURE 2-5: Input Offset Voltage Drift
with TA= +85°C to +125°C and VDD =5.5V.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD =5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
-3 -2 -1 0 1 2 3
Input Offset Voltage (mV)
Percentage of Occurrences
2396 Samples
VCM = VSS
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-10-8-6-4-20246810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
2267 Samples
TA = -40°C to +85°C
VCM = VSS
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 1.4V
TA
= +25°C
TA
= -40°C
TA
= +125°C
TA
= +85°C
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-10-8-6-4-2 0 2 4 6 810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
234 Samples
Representative Lot
VDD = 1.4V
VCM = VSS
TA = +85°C to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
-10-8-6-4-2 0 2 4 6 810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
234 Samples
Representative Lot
VDD = 5.5V
VCM = VSS
TA = +85°C to +125°C
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA
= +25°C
TA
= -40°C
TA = +125°C
TA = +85°C
MCP6141/2/3/4
DS21668D-page 8 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.4V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL=V
DD/2, RL=1MΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-7: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-8: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-9: CMRR, PSRR vs.
Frequency.
FIGURE 2-10: The MCP6141/2/3/4 Family
Shows No Phase Reversal.
FIGURE 2-11: Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-12: CMRR, PSRR vs. Ambient
Temperature.
250
300
350
400
450
500
0.00.51.01.52.02.53.03.54.04.55.05.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
VDD = 1.4V
100
1,000
0.1 1 10 100 1000
Frequency (Hz)
Input Noise Voltage Density
(nV/√Hz)
20
30
40
50
60
70
80
90
100
1 10 100 1,000 10,000
Frequency (Hz)
CMRR, PSRR (dB)
PSRR–
PSRR+
CMRR
Referred to Input
1 10 100 1k 10k
-1
0
1
2
3
4
5
6
0 5 10 15 20 25Time (5 ms/div)
Input, Output Voltages (V)
VIN
VDD = 5.0V
G = +11 V/V
VOUT
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/√Hz)
f = 1 kHz
VDD = 5.0V
70
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR (VCM = VSS)
CMRR (VDD = 5.0V,
VCM = -0.3V to +5.3V)
© 2009 Microchip Technology Inc. DS21668D-page 9
MCP6141/2/3/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.4V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL=V
DD/2, RL=1MΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-13: Input Bias, Offset Currents
vs. Ambient Temperature.
FIGURE 2-14: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-15: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-16: Input Bias, Offset Currents
vs. Common Mode Input Voltage.
FIGURE 2-17: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-18: DC Open-Loop Gain vs.
Output Voltage Headroom.
0.1
1
10
100
1000
10000
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias and Offset Currents
(pA)
| IOS |
IB
VDD = 5.5V
VCM = VDD
0.1
1
10
100
1k
10k
-40
-20
0
20
40
60
80
100
120
1.E-
02
1.E-
01
1.E+
00
1.E+
01
1.E+
02
1.E+
03
1.E+
04
1.E+
05Frequency (Hz)
Open-Loop Gain (dB)
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
0.01 0.1 1 10 100 1k 10k 100k
Gain
Phase
80
90
100
110
120
130
140
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
DC Open-Loop Gain (dB)
RL = 50 kΩ
VOUT = 0.1V to VDD – 0.1V
0.1
1
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
VDD = 5.5V
IB
| IOS |
TA = +125°C
0.1
1
10
100
1k
10k
60
70
80
90
100
110
120
130
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
DC Open-Loop Gain (dB)
VDD = 1.4V
100 1k 10k 100k
VOUT = 0.1V to VDD – 0.1V
VDD = 5.5V
70
80
90
100
110
120
130
140
0.00 0.05 0.10 0.15 0.20 0.25
Output Voltage Headroom;
VDD – VOH or VOL – VSS (V)
DC Open-Loop Gain (dB)
RL = 50 kΩ
VDD = 5.5V
VDD = 1.4V
MCP6141/2/3/4
DS21668D-page 10 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.4V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL=V
DD/2, RL=1MΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-19: Channel to Channel
Separation vs. Frequency (MCP6142 and
MCP6144 only) .
FIGURE 2-20: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD =1.4V.
FIGURE 2-21: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-22: Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature with
VDD =5.5V.
FIGURE 2-24: Output Short Circuit Current
vs. Power Supply Voltage.
80
90
100
110
120
130
140
1.E+03 1.E+04
Frequency (Hz)
Channel-to-Channel
Separation (dB)
1k 10k
Input Referred
0
10
20
30
40
50
60
70
80
90
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
Phase Margin (°)
PM
(G = +10)
GBWP
VDD = 1.4V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Quiescent Current
(µA/Amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
10
20
30
40
50
60
70
80
90
100
110
120
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Common Mode Input Voltage
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
100
110
120
Phase Margin (°)
PM
(G = +10)
GBWP
VDD = 5.0V
0
10
20
30
40
50
60
70
80
90
-50-250 255075100125
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
Phase Margin (°)
PM
(G = +10)
GBWP
VDD = 5.5V
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Ambient Temperature (°C)
Output Short Circuit Current
Magnitude (mA)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
© 2009 Microchip Technology Inc. DS21668D-page 11
MCP6141/2/3/4
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.4V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL=V
DD/2, RL=1MΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-25: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-26: Slew Rate vs. Ambient
Temperature.
FIGURE 2-27: Small Signal Non-inverting
Pulse Response.
FIGURE 2-28: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-29: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-30: Small Signal Inverting Pulse
Response.
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom;
VDD – VOH or VOL – VSS (mV)
VDD – V
OH
VOL – VSS
0
5
10
15
20
25
30
35
40
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/ms)
High-to-Low
Low-to-High
VDD = 1.4V
VDD = 5.5V
-80
-60
-40
-20
0
20
40
60
80
0.00.10.20.30.40.50.60.70.80.91.0Time (100 µs/div)
Output Voltage (20 mV/div)
G = +11 V/V
RL = 50 kΩ
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom,
VDD – VOH or VOL – VSS (mV)
VOL – VSS
VDD – VOH
VDD = 5.5V
RL = 50 kΩ
0.1
1
10
1.E+02 1.E+03 1.E+04
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
100 1k 10k
VDD = 5.5V
VDD = 1.4V
-80
-60
-40
-20
0
20
40
60
80
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Time (100 µs/div)
Voltage (20 mV/div)
G = -10 V/V
RL = 50 kΩ
MCP6141/2/3/4
DS21668D-page 12 © 2009 Microchip Technology Inc.
Note: Unless otherwise indicated, TA= +25°C, VDD = +1.4V to +5.5V, VSS =GND, V
CM =V
DD/2, VOUT ≈VDD/2,
VL=V
DD/2, RL=1MΩ to VL, CL= 60 pF, and CS is tied low.
FIGURE 2-31: Large Signal Non-inverting
Pulse Response.
FIGURE 2-32: Chip Select (CS) to
Amplifier Output Response Time (MCP6143
only).
FIGURE 2-33: Input Current vs. Input
Voltage (Below VSS).
FIGURE 2-34: Large Signal Inverting Pulse
Response.
FIGURE 2-35: Internal Chip Select (CS)
Hysteresis (MCP6143 only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
00011111222Time (200 µs/div)
Output Voltage (V)
VDD = 5.0V
G = +11 V/V
RL = 50 kΩ
0.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
012345678910Time (1 ms/div)
CS Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Output Voltage (V)
VDD = 5.0V
G = +11 V/V
VIN = +3.0V
VOUT
High-Z
On
CS
On
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
00011111222Time (200 µs/div)
Output Voltage (V)
VDD
= 5.0
V
G = -10 V/V
RL = 50 kΩ
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Voltage (V)
Internal CS Switch Output (V)
VOUT On
VOUT High-Z
VDD = 5.0V
G = +11 V/V
VIN = 3.0V
Hysteresis
CS
High-to-Low
CS
Low-to-High
© 2009 Microchip Technology Inc. DS21668D-page 13
MCP6141/2/3/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3 CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.4 Power Supply Pins
The positive power supply pin (VDD) is 1.4V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP6141 MCP6142 MCP6143 MCP6144
Symbol Description
MSOP,
PDIP,
SOIC
SOT-23-5
MSOP,
PDIP,
SOIC
MSOP,
PDIP,
SOIC
SOT-23-6
MSOP,
PDIP,
SOIC
61 161 1V
OUT
,V
OUTA Analog Output (op amp A)
24 224 2V
IN–, VINA– Inverting Input (op amp A)
33 333 3V
IN+, VINA+ Non-inverting Input (op amp A)
75 876 4V
DD Positive Power Supply
—— 5—— 5 V
INB+ Non-inverting Input (op amp B)
—— 6—— 6 V
INB– Inverting Input (op amp B)
—— 7—— 7V
OUTB Analog Output (op amp B)
—— ——— 8V
OUTC Analog Output (op amp C)
—— ——— 9 V
INC– Inverting Input (op amp C)
—— ——— 10V
INC+ Non-inverting Input (op amp C)
42 442 11V
SS Negative Power Supply
—— ——— 12V
IND+ Non-inverting Input (op amp D)
—— ——— 13V
IND– Inverting Input (op amp D)
—— ——— 14V
OUTD Analog Output (op amp D)
—— —8 5 — CSChip Select
1, 5, 8 — — 1, 5 — — NC No Internal Connection
MCP6141/2/3/4
DS21668D-page 14 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 15
MCP6141/2/3/4
4.0 APPLICATIONS INFORMATION
The MCP6141/2/3/4 family of op amps is manufactured
using Microchip’s state of the art CMOS process These
op amps are stable for gains of 10 V/V and higher. They
are suitable for a wide range of general purpose, low
power applications.
See Microchip’s related MCP6041/2/3/4 family of op
amps for applications needing unity gain stability.
4.1 Rail-to-Rail Input
4.1.1 PHASE REVERSAL
The MCP6141/2/3/4 op amps are designed to not
exhibit phase inversion when the input pins exceed the
supply voltages. Figure 2-10 shows an input voltage
exceeding both supplies with no phase inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Absolute
Maximum Ratings † at the beginning of Section 1.0
“Electrical Characteristics”). Figure 4-2 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-33. Applications that are high impedance may
need to limit the usable voltage range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6141/2/3/4 op amps uses
two differential input stages in parallel. One operates at
a low common mode input voltage (VCM), while the
other operates at a high VCM. With this topology, the
device operates with a VCM up to 300 mV above VDD
and 300 mV below VSS. The input offset voltage is
measured at VCM =V
SS – 0.3V and VDD + 0.3V to
ensure proper operation.
There are two transitions in input behavior as VCM is
changed. The first occurs, when VCM is near
VSS + 0.4V, and the second occurs when VCM is near
VDD – 0.5V (see Figure 2-3 and Figure 2-6). For the
best distortion performance with non-inverting gains,
avoid these regions of operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad VIN–
V1
MCP604X
R1
VDD
D1
R1>VSS –(minimum expected V1)
2mA
VOUT
R2>VSS –(minimum expected V2)
2mA
V2
R2
D2
MCP6141/2/3/4
DS21668D-page 16 © 2009 Microchip Technology Inc.
4.2 Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP6141/2/3/4 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load condition. Thus,
the output voltage swings to within 10 mV of either
supply rail with a 50 kΩ load to VDD/2. Figure 2-10
shows how the output voltage is limited when the input
goes beyond the linear region of operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
Voltage Range. This specification defines the
maximum output swing that can be achieved while the
amplifier still operates in its linear region. To verify
linear operation in this range, the large signal DC
Open-Loop Gain (AOL) is measured at points inside the
supply rails. The measurement must meet the specified
AOL condition in the specification table.
4.3 Output Loads and Battery Life
The MCP6141/2/3/4 op amp family has outstanding
quiescent current, which supports battery-powered
applications. There is minimal quiescent current
glitching when Chip Select (CS) is raised or lowered.
This prevents excessive current draw, and reduced
battery life, when the part is turned off or on.
Heavy resistive loads at the output can cause
excessive battery drain. Driving a DC voltage of 2.5V
across a 100 kΩ load resistor will cause the supply
current to increase by 25 µA, depleting the battery 43
times as fast as IQ (0.6 µA, typical) alone.
High frequency signals (fast edge rate) across
capacitive loads will also significantly increase supply
current. For instance, a 0.1 µF capacitor at the output
presents an AC impedance of 15.9 kΩ (1/2πfC) to a
100 Hz sinewave. It can be shown that the average
power drawn from the battery by a 5.0 VP-P sinewave
(1.77 Vrms), under these conditions, is:
EQUATION 4-1:
This will drain the battery 18 times as fast as IQ alone.
4.4 Stability
4.4.1 NOISE GAIN
The MCP6141/2/3/4 op amp family is designed to give
high bandwidth and slew rate for circuits with high noise
gain (GN) or signal gain. Low gain applications should
be realized using the MCP6041/2/3/4 op amp family;
this simplifies design and implementation issues.
Noise gain is defined to be the gain from a voltage
source at the non-inverting input to the output when all
other voltage sources are zeroed (shorted out). Noise
gain is independent of signal gain and depends only on
components in the feedback loop. The amplifier circuits
in Figure 4-3 and Figure 4-4 have their noise gain
calculated as follows:
EQUATION 4-2:
In order for the amplifiers to be stable, the noise gain
should meet the specified minimum noise gain. Note
that a noise gain of GN= +10 V/V corresponds to a
non-inverting signal gain of G = +10 V/V, or to an
inverting signal gain of G = -9 V/V.
FIGURE 4-3: Noise Gain for Non-inverting
Gain Configuration.
FIGURE 4-4: Noise Gain for Inverting
Gain Configuration.
PSupply = (VDD - VSS) (IQ + VL(p-p) f CL )
= (5V)(0.6 µA + 5.0Vp-p · 100Hz · 0.1µF)
= 3.0 µW + 50 µW
GN1RF
RG
-------10 V/V
≥
+=
VIN
MCP614X
RIN
VOUT
RF
RG
MCP614X
RIN
VOUT
RF
RG
VIN
© 2009 Microchip Technology Inc. DS21668D-page 17
MCP6141/2/3/4
Figure 4-5 shows three example circuits that are
unstable when used with the MCP6141/2/3/4 family.
The unity gain buffer and low gain amplifier
(non-inverting or inverting) are at gains that are too low
for stability (see Equation 4-2).The Miller integrator’s
capacitor makes it reach unity gain at high frequencies,
causing instability.
FIGURE 4-5: Examples of Unstable
Circuits for the MCP6141/2/3/4 Family.
4.4.2 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +10), a small series
resistor at the output (RISO in Figure 4-6) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-6: Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-7 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -9 V/V gives GN= +10 V/V).
FIGURE 4-7: Recommended RISO V alues
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6141/2/3/4 SPICE macro
model are helpful.
4.5 MCP6143 Chip Select
The MCP6143 is a single op amp with Chip Select
(CS). When CS is pulled high, the supply current drops
to 50 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high impedance state. By pulling CS low, the amplifier
is enabled. If the CS pin is left floating, the amplifier will
not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
Note: The three circuits shown in Figure 4-5 are
not to be used with the MCP6141/2/3/4 op
amps. They are included for illustrative
purposes only.
Low Gain Amplifier
MCP614X
VOUT
RG
V1
RF
RN
1RF
RG
-------10<+
V2
MCP614X VOUT
VIN
MCP614X
VOUT
CR
VIN
Unity Gain Buffer
Miller Integrator
VB
MCP614X
RISO
VOUT
CL
RF
RG
VA
1,000
10,000
100,000
1.E+00 1.E+01 1.E+02 1.E+03
Normalized Load Capacitance; CL/GN (F)
Recommended R ISO (Ω)
1p
1k
100k
10p
GN = +10
GN = +20
GN ≥ +50
10k
1n100p
MCP6141/2/3/4
DS21668D-page 18 © 2009 Microchip Technology Inc.
4.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor is not required
for most applications and can be shared with other
nearby analog parts.
4.7 Unused Op Amps
An unused op amp in a quad package (MCP6144)
should be configured as shown in Figure 4-8. These
circuits prevent the output from toggling and causing
crosstalk.
Circuits A sets the op amp near its minimum noise gain.
The resistor divider produces any desired reference
voltage within the output voltage range of the op amp;
the op amp buffers that reference voltage. Circuit B
uses the minimum number of components and
operates as a comparator, but it may draw more
current.
FIGURE 4-8: Unused Op Amps.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6141/2/3/4 family’s bias current at +25°C (1 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
FIGURE 4-9: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
VDD
VDD
¼ MCP6144 (A) ¼ MCP6144 (B)
R1
R2
10RR
VDD
VREF VDD
R2
R1R2
+
--------------------
⋅
=
VREF
Guard Ring VIN–V
IN+
© 2009 Microchip Technology Inc. DS21668D-page 19
MCP6141/2/3/4
4.9 Application Circuits
4.9.1 BATTERY CURRENT SENSING
The MCP6141/2/3/4 op amps’ Common Mode Input
Range, which goes 0.3V beyond both supply rails,
supports their use in high side and low side battery
current sensing applications. The very low quiescent
current (0.6 µA, typical) help prolong battery life, and
the rail-to-rail output supports detection low currents.
Figure 4-10 shows a high side battery current sensor
circuit. The 1 kΩ resistor is sized to minimize power
losses. The battery current (IDD) through the 1 kΩ
resistor causes its top terminal to be more negative
than the bottom terminal. This keeps the common
mode input voltage of the op amp below VDD, which is
within its allowed range. When no current is flowing, the
output will be at its Maximum Output Voltage Swing
(VOH), which is virtually at VDD.
.
FIGURE 4-10: High Side Battery Current
Sensor.
4.9.2 INVERTING SUMMING AMPLIFIER
The MCP6141/2/3/4 op amp is well suited for the
inverting summing amplifier shown in Figure 4-11 when
the resistors at the input (R1, R2, and R3) make the
noise gain at least 10 V/V. The output voltage (VOUT) is
a weighted sum of the inputs (V1, V2, and V3), and is
shifted by the VREF input. The necessary calculations
follow in Equation 4-3.
.
FIGURE 4-11: Summing Amplifier.
EQUATION 4-3:
VDD
IDD
MCP6141
100 kΩ1MΩ
1.4V
VOUT
1kΩ
to
6.0V
VOUT VDD 1 kΩ()11 V/V()IDD
–=
MCP614X
VOUT
RF
R3
V3
R2
V2
R1
V1
VREF
GN1R
F1
R1
------1
R2
------1
R3
------++
⎝⎠
⎛⎞
10 V/V
≥
+=
Noise Gain:
Output Signal:
VOUT V1G1V2G2V3G3VREFGN
+++=
G1RFR1
⁄
–=
Signal Gains:
G2RFR2
⁄
–=
G3RFR3
⁄
–=
MCP6141/2/3/4
DS21668D-page 20 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 21
MCP6141/2/3/4
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6141/2/3/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6141/2/3/4
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Simulation Tool
Microchip’s Mindi™ simulation tool aids in the design of
various circuits useful for active filter, amplifier and
power-management applications. It is a free online
simulation tool available from the Microchip web site at
www.microchip.com/mindi. This interactive simulator
enables designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
simulation tool can be downloaded to a personal
computer or workstation.
5.4 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
•8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
•14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.6 Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip.com/appnotes and are
recommended as supplemental reference resources.
•ADN003: “Select the Right Operational Amp lifier
for your Filtering Circuits”, DS21821
•AN722: “Operational Amplifier T opologies and DC
Specifications”, DS00722
•AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
•AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
•AN990: “Analog Se nsor Conditioning Circuits –
An Overview”, DS00990
These application notes and others are listed in the
design guide:
•“Signal Chain Design Guide”, DS21825
MCP6141/2/3/4
DS21668D-page 22 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 23
MCP6141/2/3/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead MSOP Example:
XXXXXX
YWWNNN
6143I
918256
5-Lead SOT-23 (MCP6141)Example:
XXNN AS25
Device E-Temp Code
MCP6141 ASNN
Note: Applies to 5-Lead SOT-23
6-Lead SOT-23 (MCP6143) Example:
XXNN AW25
Device E-Temp Code
MCP6143 AWNN
Note: Applies to 6-Lead SOT-23
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6141
I/P256
0918
MCP6142
I/SN0918
256
MCP6141
E/P 256
0918
MCP6142E
SN 0918
256
3
e
OR
OR
3
e
MCP6141/2/3/4
DS21668D-page 24 © 2009 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6144)Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP6144-I/P
0918256
MCP6144
0918256
I/P
3
e
OR
14-Lead TSSOP (MCP6144)Example:
14-Lead SOIC (150 mil) (MCP6144)Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXX
YYWW
NNN
6144ST
0918
256
XXXXXXXXXX
MCP6144ISL
0918256
MCP6144
0918256
I/SL^^
OR
3
e
6144EST
0918
256
OR
© 2009 Microchip Technology Inc. DS21668D-page 25
MCP6141/2/3/4
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MCP6141/2/3/4
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© 2009 Microchip Technology Inc. DS21668D-page 33
MCP6141/2/3/4
APPENDIX A: REVISION HISTORY
Revision D (May 2009)
The following is the list of modifications:
1. DC Electrical Charactistics table: Corrected
formatting issue in Output section.
2. AC Electrical Characteristics table: Slew Rate
- changed typical value from 3.0 to 24. Changed
Phase Margin from 65 to 60. Changed Phase
Margin Condition from G=+1 to G=+10 V/V.
3. Updated Package Outline Drawings
4. Updated Revision History.
Revision C (December 2007)
• Updated Figures 2.4 and 2.5
• Expanded Analog Input Absolute Max Voltage
Range (applies retroactively)
• Expanded maximum operating VDD (going
forward)
•Section 1.0 “Electrical Characteristics”
updated
•Section 2.0 “Typical Performance Curves”
updated
•Section 4.0 “Applications Information”
- Updated input stage explanation
•Section 5.0 “Design Aids” updated
Revision B (November 2005)
The following is the list of modifications:
1. Added the following:
a) SOT-23-5 package for the MCP6141 single
op amps.
b) SOT-23-6 package for the MCP6143 single
op amps with Chip Select.
c) Extended Temperature (-40°C to +125°C)
op amps.
2. Updated specifications in Section 1.0
“Electrical Characteristics” for E-temp parts.
3. Corrected and updated plots in Section 2.0
“Typical Performance Curves”.
4. Added Section 3.0 “Pin Descriptions”.
5. Updated Section 4.0 “Applications
Information” and added section on unused op
amps.
6. Updated Section 5.0 “Design Aids” to include
FilterLab.
7. Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information in
Section 6.0 “Packaging Information”.
8. Added Appendix A: “Revision History”.
Revision A (September 2002)
• Original Release of this Document.
MCP6141/2/3/4
DS21668D-page 34 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 35
MCP6141/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6141: Single Op Amp
MCP6141T: Single Op Amp
(Tape and Reel for SOT-23, SOIC, MSOP)
MCP6142: Dual Op Amp
MCP6142T: Dual Op Amp
(Tape and Reel for SOIC and MSOP)
MCP6143: Single Op Amp w/ CS
MCP6143T: Single Op Amp w/ CS
(Tape and Reel for SOT-23, SOIC, MSOP)
MCP6144: Quad Op Amp
MCP6144T: Quad Op Amp
(Tape and Reel for SOIC and TSSOP)
Temperature Range: I = -40°C to +85°C (industrial)
E= -40°C to +125°C (extended)
Package: CH = Plastic Small Outline Transistor (SOT-23),
6-lead (Tape and Reel - MCP6143 only)
MS = Plastic Micro Small Outline (MSOP), 8-lead
OT = Plastic Small Outline Transistor (SOT-23),
5-lead (Tape and Reel - MCP6141 only)
P = Plastic DIP (300 mil body), 8-lead, 14-lead
SL = Plastic SOIC (3.9 mm body), 14-lead
SN = Plastic SOIC (3.9 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm body), 14-lead
Examples:
a) MCP6141-I/P: Industrial Temperature
8 lead PDIP package.
b) MCP6141T-E/OT: Tape and Reel,
Extended Temperature
5 lead SOT-23 package.
a) MCP6142-I/SN: Industrial Temperature
8 lead SOIC package.
b) MCP6142T-E/MS: Tape and Reel,
Extended Temperature
8 lead MSOP package.
a) MCP6143-I/P: Industrial Temperature,
8 lead PDIP package.
b) MCP6143T-E/CH: Tape and Reel,
Extended Temperature
6 lead SOT-23 package.
a) MCP6144-I/SL: Industrial Temperature
14 lead PDIP package.
b) MCP6144T-E/ST: Tape and Reel,
Extended Temperature
14 lead TSSOP package.
PART NO.
Device
- X
Temperature
/ XX
Package
Range
MCP6141/2/3/4
DS21668D-page 36 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21668D-page 37
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Hampshire, Linear Active Thermistor, MXDEV,
MXLAB, SEEVAL, SmartSensor and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Total Endurance, TSHARC, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21668D-page 38 © 2009 Microchip Technology Inc.
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