1
®
FN4607.3
HS-565BRH
Radiation Hardened High Speed,
Monolithic Digital-to-Analog Converter
The HS-565BRH is a fast, radiation hardened 12-bit current
output, digital-to-analog converter. This part replaces the
HS-565ARH, which is no longer available. The monolithic
chip includes a precision voltage reference, thin-film R-2R
ladder, reference control amplifier and twelve high-speed
bipolar current swi tch es .
The Inters il Corpora tion Dielec tric Isolatio n process provides
latch-up free operation while minimizing stray capacitance
and leakage currents, to produce an excellent combination
of speed and acc uracy. Als o, ground curr ents are min imized
to produce a low and constant current through the ground
termina l, which reduc es error due to c ode-dependent g round
currents.
HS-565BRH die are laser trimmed for a maximum integral
nonlinearity error of ±0.25 LSB at 25oC. In addition, the low
noise buried zener reference is trimmed both for absolute
value and minimum temperature coefficient.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbu s (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96755. A “hot-link” is provided
on our website for downloading.
Features
• Electrically Screened to SMD # 5962-96755
• QML Qualifi ed per MIL-PRF-38 535 Require me nts
• Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max)
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
• Low Gain Drift
(Max., DAC Plus Reference) . . . . . . . . . . . . . . .50ppm/oC
•±0.75 LSB Accuracy Guaranteed Over Temperature
(±0.125 LSB Typical at 25oC)
Applications
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
Functional Diagram
Ordering Information
ORDERING NUMBER INTERNAL
MKT. NUMBER TEMP. RANGE
(oC)
5962R9675502V9A HS0-565BRH-Q 25
5962R9675502VJC HS1-565BRH-Q -55 to 125
5962R9675502VXC HS9-565B RH-Q -55 to 125
HS9-565BRH/PRO T O HS9-565BRH/ PROT O -55 to 125
REF OUT VCC
43
+
-
19.95K
REF
10V
6
5
REF
+
-
3.5K
3K
IREF
0.5mA
-VEE PWR
GND
712
24 . . . 13
MSB LSB
(4X I REF
X CODE)
GND
IN
20V
SPAN
10V
SPAN
OUT
IO
DAC 9.95K
BIP.
OFF.
8
5K
5K
2.5K
11
10
9
Data Sheet January 2003
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Pinouts HS1-565BRH
MIL-STD-1835 CDIP2-T 24
(SBDIP)
TOP VIEW
HS9-565BRH
MIL-STD-1835 CDFP4-F 24
(CERAMIC FLATPACK)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
NC
NC
VCC
REF OUT
REF GND
REF IN
-VEE
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR G N D
BIT 1 IN (MSB)
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 8 IN
BIT 10 IN
BIT 11 IN
BIT 12 IN (LSB)
BIT 2 IN
BIT 7 IN
BIT 9 IN
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
10
11
12
1
NC
NC
VCC
REF OUT
REF GND
REF IN
-VEE
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
BIT 1 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 8 IN
BIT 10 IN
BIT 11 IN
BIT 12 IN
BIT 2 IN
BIT 7 IN
BIT 9 IN
(LSB)
(MSB)
HS-565BRH
3
Burn-In Bias Circuit
NOTES:
D1 = D2 = D3 = IN4002 or Equivalent
F0 to F11: VIH = 5.0V ±0.5V
VIL = 0.0V ±0.5V
F0 = 100kHz ±10% (50% Duty Cycle)
F1 = F0/2 F7 = F0/128
F2 = F0/4 F8 = F0/256
F3 = F0/8 F9 = F0/512
F4 = F0/16 F10 = F0/1024
F5 = F0/32 F11 = F0/2048
F6 = F0/64
Radiation Bias Circuit
NOTE: Power Supply Levels are ±0.5V
Definitions of Specifications
Digital Inputs
The HS-5 65BRH accep ts di gital i nput c odes in bin ary fo rmat
and may be user connected for any one of three binary
codes. Straight binary, Two’s Complement (see note below),
or Offset Binary, (See Operating Instructions).
Accuracy
Nonlinearity - Nonlinearity of a D/A converter is an
importan t meas ure of its accura cy. It de scrib es the de viati on
from an ideal st raight line transfer cu rve drawn between zero
(all bits OFF) and full scale (all bits ON).
Differential Nonlinearity - For a D/A converter, it is the
differenc e betwe en the ac tual output voltage c hange and the
ideal (1 LSB) vo ltage c hange fo r a one bit cha nge in co de. A
Differential Nonlinearity of ±1 LSB or less guarantees
monoton ic ity ; i.e., the outp ut alw a ys incre ase s and never
decreases for an increasing input.
Settling Time
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usua lly spe cified for a fu ll sca le or maj or carry tra nsition,
settling to within 0.50 LSB of final value.
Drift
Gain Drift - The change in full sca le analog outp ut over the
specified temperature range expres sed in parts per million of
full scale range per oC (ppm of FSR/oC). Gain error is
measured with respect to 25oC at high (TH) and low (TL)
temperatures. Gain drift is calc ulated for both high (TH -
25oC) and low ranges (25oC - TL) by dividing the gain error by
the respective change in temperature. The specification is the
larger of the two representing worst case drift.
Offset Drift - The change in analog output with all bits OFF
over the s pec if ied tem pera ture range ex pre ssed i n pa rts per
million of full scale range per oC (ppm of FSR/oC). Offset
error is measured with respect to 25oC at hig h (TH) and l ow
(TL) temperatures. Offset drift is calculated for both high (TH
- 25oC) and low (25oC - TL) ranges by dividing the offset
error by the respective change in temperature. The
specification given is the larger of the two, representing
worst case drift.
C3
D3
+10V
1
4
5
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
2
3
6
7
NC
C1
D1
+15V
C2
D2
-15V
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
NC
VCC
REF GND
REF OUT
REF IN
-VEE
BIP OFF
OUT
10V SPAN
20V SPAN
PWR GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
+15V
1
4
5
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
2
3
6
7
NC
NC
VCC
REF GND
REF OUT
REF IN
-VEE
BIP OFF
OUT
10V SPAN
20V SPAN
PWR GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
-15V
+10V
+5V
DIGITAL
INPUT ANALOG OUTPUT
STRAIGHT
BINARY OFFSET
BINARY
(NOTE)
TWO’S
COMPLEMENTMSB...LSB
000....000 Zero -FS (Full Scale) Zero
100....000 0.50 FS Zero -FS
111....111 +FS - 1LSB +FS - 1LSB Zero - 1LSB
011....111 0.50 FS - 1LSB Zero - 1LSB +FS - 1LSB
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding
HS-565BRH
4
Power Supply Sensitivity
Power Supp ly Sensiti vi ty i s a m eas ure of the cha nge in ga in
and offset of the D/A converter resulting from a change in -
15V or +15V sup plies. It is specified u nder DC co nditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
Compliance
Compliance Voltage is the maximum output voltage range
that can be tole rated and still m aintain its spec ified accurac y.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
Applying the HS-565BRH
OP AMP Selection
The HS-565BRH’s current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination is
where tD, tA are settling times for the DAC and amplifier.
No Trim Operation
The HS-565BRH will perform as specified without calibration
adjustments. To operate without calibration, substitute 50Ω
resistors for the 100Ω trimming potentiometers: In Figure 1
replace R2 with 50Ω; also remove the network on pin 8 and
connect 50Ω to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50Ω resistors.
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical
unipolar zero will be ±0.50 LSB plus the op amp offset.
The feedback capacitor C must be selected to minimize
settling time.
Calibration
Calibration provides the maximum accuracy from a
converter by adjusting its gain and offset errors to zero, For
the HS-565BRH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 1 or 2.
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translat es the outpu t cha racteris tic, i.e . affects ea ch co de by
the same amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the neg ative FS value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
tD
()
2tA
()
2
+
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
1120V SPAN
10V SPAN
2.5K
5K
5K
C
9.95K
IO
24 13
MSB LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEEPWR
GND
7
x CODE)
IREF
0.5mA
HS-565BRH
3K
3.5K
19.95
K
+
-10V
34VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R2
100Ω
8
BIP.
OFF.
+15V
-15V
R1
50kΩ
100kΩ
100Ω
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
VO
-
+
R (SEE
TABLE 7)
DAC
OUT
9
10
11 20V SPAN
10V SPAN
2.5K
5K
5K
C
9.95K
IO
24 13
MSB LSB
. . . . .
CODE
INPUT
DAC
(4 x IREF
-VEEPWR
GND
7
x CODE)
IREF
0.5mA
HS-565BRH
3K
3.5K
19.95K
+
-10V
34VCC
+
-
6
5
REF
GND
REF
IN
REF OUT
R4
100Ω
8
BIP.
OFF.
R3
100Ω
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
HS-565BRH
5
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by conv erter manu facturers c an lead to consisten tly diff erent
results. An engineer should understand the advantage and
limitat ions of a given test methods before using the spec ified
settling time as a basis for design.
The approach used for several years at Intersil calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB a reasonable
magnitude (814mV for the HS-565BRH, which provides the
comparator with enough overdrive to establish an accurate
±0.50 LSB window about the final settled value. Also, the
required test conditions simulate the DACs environment for
a common application - use in a successive approximation
A/D converter. Considerable experience has shown this to
be a reliable and repeatable way to measure settling time.
The usua l spec ifica tion is based on a 10V st ep, prod uced b y
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of ±0.50 LSB about the settled value.
Four measurements characterize a given type of DAC:
(Cases (b) and (c) may be eliminated unless the overshoot
exceed s 0.50 LSB) . For example, re fer to Figures 3A and 3B
for the measurement of case (d ).
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the del ay on gen erator nu mber 2 for a tX of se veral
microseconds. This assures that the DAC output has
settled to its fin al wave .
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of equal
brightness on the oscilloscope display as shown in Figure
3B. Note DVM reading.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by 5
LSBs (DVM reads 10X, so this sets the comparator to
sense th e final settled va lue minus 0.50 LSB). Com parator
output disappears.
• Reduc e generator num ber 2 delay unt il compara tor output
reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e. tX + 15ns.
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
TABLE 1. OPERATING MODES AND CALIBRATION
MODE
CIRCUIT CONNECTIONS CALIBRATION
OUTPUT
RANGE PIN 10
TO PIN 11
TO RESISTOR
(R) APPLY
INPUT CODE ADJUST TO SET VO
Unipolar (See Figure 1) 0 to +10V VO Pin 10 1.43K All 0’s
All 1’s R1
R2 0V
+9.99756V
0 to +5V VO Pin 9 1.1K All 0’s
All 1’s R1
R2 0V
+4.99878V
Bipolar (See Figure 2) ±10V NC VO 1.69K All 0’s
All 1’s R3
R4 -10V
+9.99512V
±5V VO Pin 10 1.43K All 0’s
All 1’s R3
R4 -5V
+4.99756V
±2.5V VO Pin 9 1.1K All 0’s
All 1’s R3
R4 -2.5V
+2.49878V
HS-565BRH
6
Other Considerations
Grounds
The HS-565BRH has two ground terminals, pin 5 (REF GN D)
and pin 12 (PWR GND). These sh ould not be tied toge ther
near the package u nless tha t point is als o the s ystem signal
ground to which all returns are con nected. (If such a p oint
exists, then separate paths are required to pins 5 and 12).
The cur rent thro ugh pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the
analog/signal and digital/power grounds.
NOTE: Current cancellation is a two step process within the
HS-565BRH in which code dependent variations are eliminated, the
resulting DC current is supplied internally. First an auxiliary 9-bit
R-2R ladder is driven by the complement of the DACs input code.
Together, the main and auxiliary ladders draw a continuous 2.25mA
from t he int er nal gr ound no de, r egar dless of input code. Pa rt of t he
DC current is supplied by the zener voltage reference, and the
remainder is sourced from the positive supply via a current mirror
which is laser trimmed for zero current through the external terminal
(pin 5).
Layout
Connections to pin 9 (IOUT) on the HS-56 5BRH are most
critical for high speed perfo rmance. Output capacitance of the
DAC is only 20pF, so a smal l change of additional
capacitance may alter the op amp’s stability and affect settling
time. Connections to pi n 9 should be short and few.
Component leads s hould be s hort on the side co nnecting to
pin 9 (as for feedback capacitor C ). See the Settling Time
section.
Bypass Capacitors
Power supply bypass capacitors on the op amp will serve
the HS-565BRH also. If no op amp is used, a 0.01µF
ceramic capacitor from each supply terminal to pin 12 is
sufficient, since supply current variations are small.
FIGURE 3A. . FIGURE 3B.
VLSB
SUPPLY
0.1µF
DVM
COMPARATOR
OUT
B
C
10
90 200K
+
-
5
9
10 NC
11
8
2.5K
5K
5K
20V ± 20%
BIAS
TURN ON
TURN OFF
9.95K
2mA
12
HS-565BRH
D
PULSE
GENERATOR
NO. 2
OUT
14
13
23
24
.
.
.
.
.
.
.
.
.
.
.
.
.
5V
P
PULSE
GENERATOR
NO. 1
SYNC
IN
TRIG
OUT
OUT
A
~100
kHz
STROBE IN
LSB
50% DIGITAL
INPUT
DAC
OUTPUT
COMP.
STROBE
COMP.
OUT
“EQUAL BRIGHTNESS”
+3V
0V
0V
-400mV
2V
0.8V
4V
0V
(TURN OFF)
A
B
C
D
50%
tX tD = COMPARATOR DELAY
SETTLING TIME
-0.50LSB
HS-565BRH
7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicati on or otherwise under any patent or patent rights of Intersil or i ts subsi diaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Die Characteristics
DIE DIMENSIONS:
179 mils x 107 mils x 19 mils
INTERFACE MATERIALS:
Glassivation:
Type: AlCu
Thickness: 8kÅ ±1kÅ
Top Metallization:
Type: Al/Copper
Thickness: 16kÅ ±2kÅ
Substrate:
Bipolar DI,
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential:
Tie Substrate to VREF GND
ADDITIONAL INFORMATION:
Worst Case Current Density:
2.0 x 105 A/cm2
Transistor Count:
200
Metalliza ti on Mask Layout HS-565BRH
VCC (MSB)
BIT 1 BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11BIT 12
(LSB)
POWER
GND
20V
SPAN
10V
SPAN
IDAC
OUT
BIPOLAR
12
-VS
VREF IN
VREF
GND
VREF OUT
3NC
3NC
1A
HS-565BRH
