STF16N60M6 - STMICROELECTRONICS

March 2017

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This is information on a product in full production.

www.st.com

STF16N60M6

N-channel 600 V, 0.26 Ω typ., 12 A MDmesh™ M6

Power MOSFET in a TO-220FP package

Datasheet - production data

Figure 1: Internal schematic diagram

Features

Order code

VDS

RDS(on) max.

STF16N60M6

600 V

0.32 Ω

12 A

 Reduced switching losses

 Lower RDS(on) x area vs previous generation

 Low gate input resistance

 100% avalanche tested

 Zener-protected

Applications

 Switching applications

 LLC converters

 Boost PFC converters

Description

The new MDmesh™ M6 technology incorporates

the most recent advancements to the well-known

and consolidated MDmesh family of SJ

MOSFETs. STMicroelectronics builds on the

previous generation of MDmesh devices through

its new M6 technology, which combines excellent

RDS(on) * area improvement with one of the most

effective switching behaviors available, as well as

a user-friendly experience for maximum end-

application efficiency.

Table 1: Device summary

Order code

Marking

Package

Packing

STF16N60M6

16N60M6

TO-220FP

Tube

TO-220FP

AM15572v1_no_tab

D(2)

G(1)

S(3)

Contents

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Contents

1 Electrical ratings ............................................................................. 3

2 Electrical characteristics ................................................................ 4

2.1 Electrical characteristics (curves) ...................................................... 6

3 Test circuits ..................................................................................... 8

4 Package information ....................................................................... 9

4.1 TO-220FP package information ...................................................... 10

5 Revision history ............................................................................ 12

STF16N60M6

Electrical ratings

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1 Electrical ratings

Table 2: Absolute maximum ratings

Symbol

Parameter

Value

Unit

VGS

Gate-source voltage

±25

Drain current (continuous) at Tc = 25 °C

12(1)

Drain current (continuous) at Tc = 100 °C

7.6(1)

IDM

Drain current (pulsed)

32(1)(2)

PTOT

Total dissipation at Tc = 25 °C

dv/dt(3)

Peak diode recovery voltage slope

V/ns

dv/dt (4)

MOSFET dv/dt ruggedness

VISO

Insulation withstand voltage (RMS) from all three leads to external

heat sink (t = 1 s; TC = 25 °C)

2.5

Tstg

Storage temperature range

-55 to 150

°C

Operating junction temperature range

Notes:

(1) Limited by maximum junction temperature.

(2)Pulse width limited by safe operating area.

(3)ISD ≤ 12 A, di/dt ≤ 400 A/μs; VDS(peak) < V(BR)DSS, VDD = 400 V

(4) VDS ≤ 480 V

Table 3: Thermal data

Symbol

Parameter

Value

Unit

Rthj-case

Thermal resistance junction-case

°C/W

Rthj-amb

Thermal resistance junction-ambient

62.5

Table 4: Avalanche characteristics

Symbol

Parameter

Value

Unit

IAR

Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax)

2.5

EAS

Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V)

110

Electrical characteristics

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2 Electrical characteristics

(TC = 25 °C unless otherwise specified)

Table 5: On /off states

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

V(BR)DSS

Drain-source breakdown

voltage

VGS = 0 V, ID = 1 mA

600

IDSS

Zero gate voltage drain

current

VGS = 0 V, VDS = 600 V

µA

VGS = 0 V, VDS = 600 V,

TC = 125 °C (1)

100

IGSS

Gate-body leakage current

VDS = 0 V, VGS = ± 25 V

±5

µA

VGS(th)

Gate threshold voltage

VDS = VGS, ID = 250 µA

3.25

4.75

RDS(on)

Static drain-source on-

resistance

VGS = 10 V, ID = 6 A

0.26

0.32

Notes:

(1)Defined by design, not subject to production test.

Table 6: Dynamic

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

Ciss

Input capacitance

VGS = 100 V, f = 1 MHz,

VGS = 0 V

575

Coss

Output capacitance

Crss

Reverse transfer

capacitance

Coss eq.(1)

Equivalent output

capacitance

VDS = 0 to 480 V, VGS = 0 V

104

Intrinsic gate resistance

f = 1 MHz open drain

5.2

Total gate charge

VDD = 480 V, ID = 12 A, VGS = 0

to 10 V (see Figure 15: "Test

circuit for gate charge

behavior")

16.7

Qgs

Gate-source charge

3.5

Qgd

Gate-drain charge

9.4

Notes:

(1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS

increases from 0 to 80% VDSS.

Table 7: Switching times

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

td(on)

Turn-on delay time

VDD = 300 V, ID = 6 A

RG = 4.7 Ω, VGS = 10 V (see

Figure 14: "Test circuit for

resistive load switching times"

and Figure 19: "Switching time

waveform")

Rise time

7.6

td(off)

Turn-off delay time

19.8

Fall time

6.8

STF16N60M6

Electrical characteristics

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Table 8: Source drain diode

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

ISD

Source-drain current

ISDM(1)

Source-drain current

(pulsed)

VSD(2)

Forward on voltage

VGS = 0 V, ISD = 12 A

1.6

trr

Reverse recovery time

ISD = 12 A, di/dt = 100 A/µs,

VDD = 60 V (see Figure 16:

"Test circuit for inductive load

switching and diode recovery

times")

210

Qrr

Reverse recovery charge

1.7

µC

IRRM

Reverse recovery current

13.8

trr

Reverse recovery time

ISD = 12 A, di/dt = 100 A/µs,

VDD = 60 V, Tj = 150 °C (see

Figure 16: "Test circuit for

inductive load switching and

diode recovery times")

310

Qrr

Reverse recovery charge

3.2

µC

IRRM

Reverse recovery current

15.4

Notes:

(1) Pulse width is limited by safe operating area.

(2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%.

Electrical characteristics

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2.1 Electrical characteristics (curves)

Figure 2: Safe operating area

Figure 3: Thermal impedance

Figure 4: Output characteristics

Figure 5: Transfer characteristics

Figure 6: Gate charge vs gate-source voltage

Figure 7: Static drain-source on-resistance

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Electrical characteristics

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Figure 8: Capacitance variations

Figure 9: Normalized gate threshold voltage vs

temperature

Figure 10: Normalized on-resistance vs temperature

Figure 11: Normalized V(BR)DSS vs temperature

Figure 12: Output capacitance stored energy

Figure 13: Source-drain diode forward

characteristics

Test circuits

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3 Test circuits

Figure 14: Test circuit for resistive load

switching times

Figure 15: Test circuit for gate charge

behavior

Figure 16: Test circuit for inductive load

switching and diode recovery times

Figure 17: Unclamped inductive load test

circuit

Figure 18: Unclamped inductive waveform

Figure 19: Switching time waveform

STF16N60M6

Package information

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4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Package information

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4.1 TO-220FP package information

Figure 20: TO-220FP package outline

STF16N60M6

Package information

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Table 9: TO-220FP package mechanical data

Dim.

Min.

Typ.

Max.

4.4

4.6

2.5

2.7

2.5

2.75

0.45

0.7

0.75

1.15

1.70

1.15

1.70

4.95

5.2

2.4

2.7

10.4

28.6

30.6

9.8

10.6

2.9

3.6

15.9

16.4

9.3

Dia

3.2

Revision history

STF16N60M6

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5 Revision history

Table 10: Document revision history

Date

Revision

Changes

23-Mar-2017

First release.

STF16N60M6

DocID030461 Rev 1

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