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This literature is subject to all applicable copyright laws and is not for resale in any manner. 74AUP1G56 TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) Features Description 0.8 V to 3.6 V VCC Supply Operation Extremely High Speed tPD - 3.2 ns: Typical at 3.3 V Power-Off High-Impedance Inputs and Outputs The 74AUP1G56 is a universal, configurable, two-input logic gate with an open drain that provides a highperformance and low-power solution for batterypowered portable applications. This product is designed for a wide low-voltage operating range (0.8 V to 3.6 V) and guarantees very low static and dynamic power consumption across the entire voltage range. All inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. Low Dynamic Power Consumption - CPD=3.0 pF Typical at 3.3 V Ultra-Small MicroPakTM Packages 3.6 V Over-Voltage Tolerant I/Os at VCC from 0.8V to 3.6 V Low Static Power Consumption - ICC=0.9 A Maximum The 74AUP1G56 provides for multiple functions, as determined by various configurations of the three inputs. The potential logic functions provided are AND, NAND, OR, NOR, XNOR, inverter, and buffer (see Figure 2 through Figure 8). Ordering Information Part Number Top Mark 74AUP1G56L6X AK 6-Lead, MicroPakTM, 1.0 mm Wide 5000 Units on Tape & Reel 74AUP1G56FHX AK 6-Lead, MicroPak2TM, 1x1 mm Body, .35 mm Pitch 5000 Units on Tape & Reel (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 Package Packing Method www.fairchildsemi.com 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) September 2012 B 1 6 C GND 2 5 VCC A 3 4 Y Figure 1. MicroPakTM (Top Through View) Pin Definitions Pin # Name Description 1 B 2 GND 3 A Data Input 4 Y Output (Open Drain) 5 VCC 6 C Data Input Ground Supply Voltage Data Input Function Table Inputs Y=Output C B A L L L H(1) L L H L L H L H(1) L H H L H L L L H L H L H H L H(1) H H H = HIGH Logic Level L = LOW Logic Level H H(1) Note: 1. High impedance output state, open drain. Function Selection Table 2-Input Logic Function Connection Configuration 2-Input AND Figure 2 2-Input AND with Both Inputs Inverted Figure 5 2-Input NAND with Inverted Input Figure 3, Figure 4 2-Input OR with Inverted Input Figure 3, Figure 4 2-Input NOR Figure 5 2-Input NOR with Both Inputs Inverted Figure 2 2-Input XNOR Figure 6 Inverter Figure 7 Buffer Figure 8 (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) Pin Configuration www.fairchildsemi.com 2 implementation is next to the board-level physical implementation of how the pins should be connected. Figure 2 through Figure 8 show the logical functions that can be implemented using the 74AUP1G56. The diagrams show the DeMorgan's equivalent logic duals for a given two-input function. The logical VCC B B Y C B B Y C Figure 2. VCC 1 6 2 5 3 4 C Y B C Y B Y 1 6 2 5 3 4 C Y C 2-Input AND Gate or 2-Input NOR with Both Inputs Inverted Figure 3. 2-Input NAND with Inverted B Input or 2-Input OR Gate with Inverted C Input VCC VCC A A Y C A A Y 1 6 2 5 3 4 A Y A Y 1 6 2 5 3 4 C Y C C Figure 4. Y C C 2-Input NAND with Inverted C Input or 2-Input OR Gate with Inverted A Input Figure 5. 2-Input NOR Gate or 2-Input AND Gate with Both Inputs Inverted VCC VCC B B Y C 1 6 2 5 3 4 C A Y A Y 1 6 2 5 3 4 Figure 7. Inverter Figure 6. 2-Input XNOR Gate VCC B Y Figure 8. (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 B 1 6 2 5 3 4 Y Y 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) Logic Configurations Non-Inverter Buffer www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VOUT (2) DC Output Voltage Min. Max. Unit -0.5 4.6 V -0.5 4.6 V -0.5 4.6 V IIK DC Input Diode Current VIN < 0V -50 mA IOK DC Output Diode Current VOUT < 0V -50 mA IOL DC Output Sink Current +50 mA DC VCC or Ground Current per Supply Pin 50 mA ICC or IGND TSTG +150 C TJ Junction Temperature Under Bias +150 C TL Junction Lead Temperature, Soldering 10s +260 C PD Power Dissipation at +85C ESD Storage Temperature Range -65 MicroPakTM-6 130 MicroPak2TM-6 120 Human Body Model, JEDEC:JESD22-A114 4000 Charged Device Model, JEDEC:JESD22-C101 2000 mW V Note: 2. IO absolute maximum rating must be observed. Recommended Operating Conditions(3) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT IOL Output Voltage Output Current TA Operating Temperature, Free Air JA Thermal Resistance Condition VCC=0 V Min. Max. Unit 0.8 3.6 V 0 3.6 V 0 3.6 V VCC=3.0 V to 3.6 V 4.0 VCC=2.3 V to 2.7 V 3.1 VCC=1.65 V to 1.95 V 1.9 VCC=1.4 V to 1.6 V 1.7 VCC=1.1 V to 1.3 V 1.1 VCC=0.8 V 20.0 A +85 C -40 MicroPakTM-6 500 MicroPak2TM-6 560 mA 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) Absolute Maximum Ratings C/W Note: 3. Unused inputs must be held HIGH or LOW. They may not float. (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 www.fairchildsemi.com 4 Symbol VP VN VH VOL IIN Parameter VCC Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage Condition TA=25C TA=-40 to 85C Min. Max. Min. Max. 0.80 0.30 0.60 0.30 0.60 1.10 0.53 0.90 0.53 0.90 1.40 0.74 1.11 0.74 1.11 1.65 0.91 1.29 0.91 1.29 2.30 1.37 1.77 1.37 1.77 3.00 1.88 2.29 1.88 2.29 0.80 0.10 0.60 0.10 0.60 1.10 0.26 0.65 0.26 0.65 1.40 0.39 0.75 0.39 0.75 1.65 0.47 0.84 0.47 0.84 2.30 0.69 1.04 0.69 1.04 3.00 0.88 1.24 0.88 1.24 0.80 0.07 0.50 0.07 0.50 1.10 0.08 0.46 0.08 0.46 1.40 0.18 0.56 0.18 0.56 1.65 0.27 0.66 0.27 0.66 2.30 0.53 0.92 0.53 0.92 3.00 0.79 1.31 0.79 1.31 Unit V V V 0.80 VCC 3.60 IOL=20 A 0.10 0.10 1.10 VCC 1.30 IOL=1.1 mA 0.30 x VCC 0.30 x VCC 1.40 VCC 1.60 IOL=1.7 mA LOW Level 1.65 VCC 1.95 IOL=1.9 mA Output Voltage 0.31 0.37 0.31 0.35 2.30 VCC 2.70 IOL=3.1 mA 0.44 0.45 2.70 VCC 3.60 IOL=4.0 mA 0.44 0.45 0 VIN 3.6 V 0.1 0.5 A Input Leakage Current 0 V to 3.6 V V IOFF Power Off Leakage Current 0V 0 (VIN,VO) 3.6 V 0.2 0.6 A IOFF Additional Power Off Leakage Current 0V to 0.2 V VIN or VO = 0 V to 3.6 V 0.2 0.6 A VIN - VCC or GND 0.5 0.9 ICC Quiescent Supply Current 0.8V to 3.6 V ICC Increase in ICC per Input 3.3 V (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 VCC VIN 3.6 V VIN=VCC -0.6 V 0.9 40.0 50.0 A 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) DC Electrical Characteristics A www.fairchildsemi.com 5 Symbol Parameter VCC Condition TA=25C Min. 1.10 VCC 1.30 Propagation Delay Max. Min. Max. Unit 30 0.80 tPZL, tPLZ Typ. TA=-40 to 85C CL=15 pF, 1.40 VCC 1.60 RU=RD=5 K 1.65 VCC 1.95 VI = 2 x (VCC) (see Figure 9) 2.30 VCC 2.70 3.00 VCC 3.60 1.0 10.1 18.9 1.0 19.9 1.0 6.6 11.4 1.0 12.2 1.0 6.3 8.7 1.0 9.7 1.0 4.7 6.9 1.0 7.5 1.0 4.6 6.8 1.0 7.4 ns CIN Input Capacitance 0 0.8 pF COUT Output Capacitance 0 1.7 pF 0.80 3.0 1.10 VCC 1.30 3.1 1.40 VCC 1.60 VIN=0 V or VCC, 1.65 VCC 1.95 f=10 MHz 3.2 2.30 VCC 2.70 3.8 3.00 VCC 3.60 4.4 CPD Power Dissipation Capacitance (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 3.4 pF 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) AC Electrical Characteristics www.fairchildsemi.com 6 Notes: 4. CL includes load and stray capacitance. 5. Input PRR = 1.0 MHz, tW = 500 ns. Symbol Figure 9. AC Test Circuit Figure 10. AC Waveforms VCC 3.3 V 0.3 V 2.5 V 0.2 V Vmi VCC/2 VCC/2 VCC/2 Vx VOL + 0.3 V VOL + 0.15 V VOL + 0.15 V (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 1.8 V 0.15 V 1.5 V 0.10 V 1.2 V 0.10 V 0.8 V VCC/2 VCC/2 VCC/2 VOL + 0.1 V VOL + 0.1 V VOL + 0.1 V 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) AC Loadings and Waveforms www.fairchildsemi.com 7 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X BOTTOM VIEW DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 11. 6-Lead, MicroPakTM, 1.0 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor's online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 Tape Section Cavity Number Leader (Start End) 125 (Typical) 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) Physical Dimensions Cavity Status Cover Type Status Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 8 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 5 6 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 Figure 12. 0.075X45 CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2TM, 1x1 mm Body, .35 mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor's online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 Tape Section Cavity Number Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) Physical Dimensions Cavity Status Cover Type Status www.fairchildsemi.com 9 74AUP1G56 -- TinyLogic(R) Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output) 10 www.fairchildsemi.com (c) 2008 Fairchild Semiconductor Corporation 74AUP1G56 * Rev. 1.0.2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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