74AUP1G56L6X - FAIRCHILD SEMICONDUCTOR

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers

will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor

product management systems do not have the ability to manage part nomenclature that utilizes an underscore

(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain

device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated

device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please

email any questions regarding the system integration to Fairchild_questions@onsemi.com.

Is Now Part of

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right

to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON

Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

Class 3 medical devices or medical devices with a same or similar classiﬁcation in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its ofﬁcers, employees, subsidiaries, afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out

of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor

is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

September 2012

74AUP1G56 • Rev. 1.0.2

74AUP1G56 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

74AUP1G56

TinyLogic® Low Power Universal Configurable

Two-Input Logic Gate (Open Drain Output)

Features

 0.8 V to 3.6 V VCC Supply Operation

 3.6 V Over-Voltage Tolerant I/Os at VCC

from 0.8V to 3.6 V

 Extremely High Speed tPD

- 3.2 ns: Typical at 3.3 V

 Power-Off High-Impedance Inputs and Outputs

 Low Static Power Consumption

- ICC=0.9 µA Maximum

 Low Dynamic Power Consumption

- CPD=3.0 pF Typical at 3.3 V

 Ultra-Small MicroPak™ Packages

Description

The 74AUP1G56 is a universal, configurable, two-input

logic gate with an open drain that provides a high-

performance and low-power solution for battery-

powered portable applications. This product is

designed for a wide low-voltage operating range (0.8 V

to 3.6 V) and guarantees very low static and dynamic

power consumption across the entire voltage range. All

inputs are implemented with hysteresis to allow for

slower transition input signals and better switching

noise immunity.

The 74AUP1G56 provides for multiple functions, as

determined by various configurations of the three inputs.

The potential logic functions provided are AND, NAND,

OR, NOR, XNOR, inverter, and buffer (see Figure 2

through Figure 8).

Ordering Information

Part Number Top Mark Package Packing Method

74AUP1G56L6X AK 6-Lead, MicroPak™, 1.0 mm Wide 5000 Units on Tape & Reel

74AUP1G56FHX AK 6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch 5000 Units on Tape & Reel

74AUP1G56 • Rev. 1.0.2 2

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

Pin Configuration

GND

VCC

Figure 1. MicroPak™ (Top Through View)

Pin Definitions

Pin # Name Description

1 B Data Input

2 GND Ground

3 A Data Input

4 Y Output (Open Drain)

5 VCC Supply Voltage

6 C Data Input

Function Table

Inputs Y=Output

C B A

L L L H(1)

L L H L

L H L H(1)

L H H L

H L L L

H L H L

H H L H(1)

H H H H(1)

H = HIGH Logic Level

L = LOW Logic Level

Note:

1. High impedance output state, open drain.

Function Selection Table

2-Input Logic Function Connection Configuration

2-Input AND Figure 2

2-Input AND with Both Inputs Inverted Figure 5

2-Input NAND with Inverted Input Figure 3, Figure 4

2-Input OR with Inverted Input Figure 3, Figure 4

2-Input NOR Figure 5

2-Input NOR with Both Inputs Inverted Figure 2

2-Input XNOR Figure 6

Inverter Figure 7

Buffer Figure 8

74AUP1G56 • Rev. 1.0.2 3

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

Logic Configurations

Figure 2 through Figure 8 show the logical functions that

can be implemented using the 74AUP1G56. The

diagrams show the DeMorgan’s equivalent logic duals

for a given two-input function. The logical

implementation is next to the board-level physical

implementation of how the pins should be connected.

VCC

Figure 2. 2-Input AND Gate or 2-Input NOR

wi th Both Inputs Inverted Figure 3. 2-Input NAND with Inverted B Input or

2-Input OR Gate with Inverted C Input

VCC

Figure 4. 2-Input NAND with Inverted C Input or

2-Input OR Gate with Inverted A Input Figure 5. 2-Input NOR Gate or 2-Input AND Gate with

Both Inputs Inverted

Figure 6. 2-Input XNOR Gate Figure 7. Inverter

YB B

Figure 8. Non-Inverter Buffer

74AUP1G56 • Rev. 1.0.2 4

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 4.6 V

VIN DC Input Voltage -0.5 4.6 V

VOUT DC Output Voltage(2) -0.5 4.6 V

IIK DC Input Diode Current VIN < 0V -50 mA

IOK DC Output Diode Current VOUT < 0V -50 mA

IOL DC Output Sink Current +50 mA

ICC or IGND DC VCC or Ground Current per Supply Pin ±50 mA

TSTG Storage Temperature Range -65 +150 °C

TJ Junction Temperature Under Bias +150 °C

TL Junction Lead Temperature, Soldering 10s +260 °C

PD Power Dissipation at + 85°C MicroPak™-6 130

MicroPak2™-6 120

ESD Human Body Model, JEDEC:JESD22-A114 4000 V

Charged Device Model, JEDEC:JESD22-C101 2000

Note:

2. IO absolute maximum rating must be observed.

Recommended Operating Conditions(3)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Condition Min. Max. Unit

VCC Supply Voltage 0.8 3.6 V

VIN Input Voltage 0 3.6 V

VOUT Output Voltage VCC=0 V 0 3.6 V

IOL Output Current

VCC=3.0 V to 3.6 V 4.0

VCC=2.3 V to 2.7 V 3.1

VCC=1.65 V to 1.95 V 1.9

VCC=1.4 V to 1.6 V 1.7

VCC=1.1 V to 1.3 V 1.1

VCC=0.8 V 20.0 µA

TA Operating Temperature, Free Air -40 +85 °C

θJA Thermal Resistance MicroPak™-6 500

°C/W

MicroPak2™-6 560

Note:

3. Unused inputs must be held HIGH or LOW. They may not float.

74AUP1G56 • Rev. 1.0.2 5

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

DC Electrical Characteristics

Symbol Parameter VCC Condition

TA=25°C TA=-40 to 85°C Unit

Min. Max. Min. Max.

VP Positive

Threshold

Voltage

0.80

0.30 0.60 0.30 0.60

1.10 0.53 0.90 0.53 0.90

1.40 0.74 1.11 0.74 1.11

1.65 0.91 1.29 0.91 1.29

2.30 1.37 1.77 1.37 1.77

3.00 1.88 2.29 1.88 2.29

VN Negative

Threshold

Voltage

0.80

0.10 0.60 0.10 0.60

1.10 0.26 0.65 0.26 0.65

1.40 0.39 0.75 0.39 0.75

1.65 0.47 0.84 0.47 0.84

2.30 0.69 1.04 0.69 1.04

3.00 0.88 1.24 0.88 1.24

VH Hysteresis

Voltage

0.80

0.07 0.50 0.07 0.50

1.10 0.08 0.46 0.08 0.46

1.40 0.18 0.56 0.18 0.56

1.65 0.27 0.66 0.27 0.66

2.30 0.53 0.92 0.53 0.92

3.00 0.79 1.31 0.79 1.31

VOL LOW Level

Output Voltage

0.80 ≤ VCC ≤ 3.60 IOL=20 µA 0.10 0.10

1.10 ≤ VCC ≤ 1.30 IOL=1.1 mA

0.30 x

VCC 0.30 x

VCC

1.40 ≤ VCC ≤ 1.60 IOL=1.7 mA 0.31 0.37

1.65 ≤ VCC ≤ 1.95 IOL=1.9 mA 0.31 0.35

2.30 ≤ VCC ≤ 2.70 IOL=3.1 mA 0.44 0.45

2.70 ≤ VCC ≤ 3.60 IOL=4.0 mA 0.44 0.45

IIN Input Leakage

Current 0 V to 3.6 V 0 ≤ VIN ≤ 3.6 V ±0.1 ±0.5 µA

IOFF Power Off

Leakage

Current 0 V 0 ≤ (VIN,VO)≤ 3.6 V 0.2 0.6 µA

ΔIOFF

Additional

Power Off

Leakage

Current

0V to 0.2 V VIN or VO = 0 V to

3.6 V 0.2 0.6 µA

ICC Quiescent

Supply Current 0.8V to 3.6 V VIN - VCC or GND 0.5 0.9 µA

VCC ≤ VIN ≤ 3.6 V ±0.9

ΔICC Increase in ICC

per Input 3.3 V VIN=VCC -0.6 V 40.0 50.0 µA

74AUP1G56 • Rev. 1.0.2 6

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

AC Electrical Characteristics

Symbol Parameter VCC Condition

TA=25°C TA=-40 to 85°C Unit

Min. Typ. Max. Min. Max.

tPZL, tPLZ Propagation

Delay

0.80

CL=15 pF,

RU=RD=5 KΩ

VI = 2 x (VCC)

(see Figure 9)

1.10 ≤ VCC ≤ 1.30 1.0 10.1 18.9 1.0 19.9

1.40 ≤ VCC ≤ 1.60 1.0 6.6 11.4 1.0 12.2

1.65 ≤ VCC ≤ 1.95 1.0 6.3 8.7 1.0 9.7

2.30 ≤ VCC ≤ 2.70 1.0 4.7 6.9 1.0 7.5

3.00 ≤ VCC ≤ 3.60 1.0 4.6 6.8 1.0 7.4

CIN Input

Capacitance 0 0.8 pF

COUT Output

Capacitance 0 1.7 pF

CPD Power

Dissipation

Capacitance

0.80

VIN=0 V or VCC,

f=10 MHz

3.0

1.10 ≤ VCC ≤ 1.30 3.1

1.40 ≤ VCC ≤ 1.60 3.2

1.65 ≤ VCC ≤ 1.95 3.4

2.30 ≤ VCC ≤ 2.70 3.8

3.00 ≤ VCC ≤ 3.60 4.4

74AUP1G56 • Rev. 1.0.2 7

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

AC Loadings and Waveforms

Notes:

4. CL includes load and stray capacitance.

5. Input PRR = 1.0 MHz, tW = 500 ns. Figure 9. AC Test Circuit

Figure 10. AC Waveforms

Symbol VCC

3.3 V ± 0.3 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 1.5 V ± 0.10 V 1.2 V ± 0.10 V 0.8 V

Vmi V

CC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2

Vx V

OL + 0.3 V VOL + 0.15 V VOL + 0.15 V VOL + 0.1 V VOL + 0.1 V VOL + 0.1 V

74AUP1G56 • Rev. 1.0.2 8

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

Physical Dimensions

2. DIMENSIONS ARE IN MILLIMETERS

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

4. FILENAME AND REVISION: MAC06AREV4

Notes:

3. DRAWING CONFORMS TO ASME Y14.5M-1994

TOP VIEW

RECOMMENED

LAND PATTERN

BOTTOM VIEW

1.45

1.00

0.05 C

0.55MAX

0.05 C

(0.49)

(1)

(0.75)

(0.52)

(0.30)

PIN 1

DETAIL A

0.075 X 45

CHAMFER

0.25

0.15

0.35

0.25

0.40

0.30

0.5

(0.05)

1.0

DETAIL A

PIN 1 TERMINAL

0.40

0.30

0.45

0.35

0.10

0.00

0.10 CBA

0.05 C

C0.05 C

0.05

0.00

6X (0.13)

PIN 1 IDENTI FIER

(0.254)

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY

OTHER LINE IN THE MARK CODE LAYOUT.

Figure 11. 6-Lead, MicroPak™, 1.0 mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the m ost recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator Tape Section Cavi ty Number Cavity Status Cover Type Status

L6X Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (T ypical) Empty Sealed

74AUP1G56 • Rev. 1.0.2 9

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

Physical Dimensions

1.00

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

0.05 C A

0.55MAX

0.05 C

0.35

0.09

0.19

123

0.35

0.25

DETAIL A

0.60

(0.08)

(0.05) 6X

0.40

0.30

0.075X45°

CHAMFER

5X 0.40

0.35

1X 0.45

6X 0.19

TOP VIEW

BOTTOM VIEW

0.66

0.10 CBA

.05 C

0.89

PIN 1

0.05 C

2X 1.00

D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

E. DRAWING FILENAME AND REVISION: MGF06AREV3

0.52

0.73

0.57

0.20 6X

RECOMMENDED LAND PATTERN

FOR SPACE CONSTRAINED PCB

DETAIL A

PIN 1 LEAD SCALE: 2X

ALTERNATIVE LAND PATTERN

FOR UNIVERSAL APPL ICATIO N

DESIGN.

0.90

MIN 250uM

654

0.35

(0.08) 4X

SIDE VIEW

Figure 12. 6-Lead, MicroPak2™, 1x1 mm Body, .35 mm Pitch

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the m ost recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator Tape Section Cavi ty Number Cavity Status Cover Type Status

FHX Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (T ypical) Empty Sealed

74AUP1G56 • Rev. 1.0.2 10

74AUP1G56 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

www.onsemi.com

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative