MT9V034 1/3Inch WideVGA CMOS Digital Image Sensor General Description The MT9V034 is a 1/3-inch wide-VGA format CMOS active-pixel digital image sensor with global shutter and high dynamic range (HDR) operation. The sensor has specifically been designed to support the demanding interior and exterior surveillance imaging needs, which makes this part ideal for a wide variety of imaging applications in real-world environments. This wide-VGA CMOS image sensor features ON Semiconductor's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The active imaging pixel array is 752 H x 480 V. It incorporates sophisticated camera functions on-chip-such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions-as well as windowing, column and row mirroring. It is programmable through a simple two-wire serial interface. The MT9V034 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-size image at 60 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolution companded for 10 bits for small signals can be alternatively enabled, allowing more accurate digitization for darker areas in the image. In addition to a traditional, parallel logic output the MT9V034 also features a serial low-voltage differential signaling (LVDS) output. The sensor can be operated in a stereo-camera, and the sensor, designated as a stereo-master, is able to merge the data from itself and the stereo-slave sensor into one serial LVDS stream. The sensor is designed to operate in a wide temperature range (-30C to +70C). Features www.onsemi.com CLCC48 11.43 x 11.43 CASE 848AN ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. * ADC: On-chip, 10-bit Column-parallel * * * * Array format: Wide-VGA, Active 752 H x 480 V (360,960 Pixels) * Global Shutter Photodiode Pixels; Simultaneous Integration and * * * * * * * * Readout RGB Bayer or Monochrome: NIR Enhanced Performance for Use with Non-visible NIR Illumination Readout Modes: Progressive or Interlaced Shutter Efficiency: >99% Simple Two-wire Serial Interface Real-Time Exposure Context Switching - Dual Register Set Register Lock Capability Window Size: User Programmable to any Smaller Format (QVGA, CIF, QCIF). Data Rate can be Maintained Independent of Window Size Binning: 2 x 2 and 4 x 4 of the Full Resolution (c) Semiconductor Components Industries, LLC, 2008 January, 2017 - Rev. 7 1 * (Option to Operate in 12-bit to 10-bit Companding Mode) Automatic Controls: Auto Exposure Control (AEC) and Auto Gain Control (AGC); Variable Regional and Variable Weight AEC/AGC Support for Four Unique Serial Control Register IDs to Control Multiple Imagers on the Same Bus Data Output Formats: * Single Sensor Mode: 10-bit Parallel/stand-alone 8-bit or 10-bit Serial LVDS * Stereo Sensor Mode: Interspersed 8-bit Serial LVDS High Dynamic Range (HDR) Mode Applications * * * * * * * Security High Dynamic Range Imaging Unattended Surveillance Stereo Vision Video as Input Machine Vision Automation Publication Order Number: MT9V034/D MT9V034 Table 1. KEY PERFORMANCE PARAMETERS Parameter Value Optical Format 1/3-inch Active Imager Size 4.51 mm (H) x 2.88 mm (V) 5.35 mm diagonal Active Pixels 752 H x 480 V Pixel Size 6.0 x 6.0 m Color Filter Array Monochrome or color RGB Bayer Shutter Type Global Shutter Maximum Data Rate Master Clock 27 Mp/s 27 MHz Full Resolution 752 x 480 Frame Rate 60 fps (at full resolution) ADC Resolution 10-bit column-parallel Responsivity 4.8 V/lux-sec (550 nm) Dynamic Range >55 dB linear; >100 dB in HDR mode Supply Voltage 3.3 V 0.3 V (all supplies) Power Consumption <160 mW at maximum data rate (LVDS disabled); 120 W standby power at 3.3 V Operating Temperature -30C to + 70C ambient Packaging 48-pin CLCC ORDERING INFORMATION Table 2. AVAILABLE PART NUMBERS Part Number Product Description MT9V034C12STC-DP VGA 1/3" GS CIS Dry Pack with Protective Film MT9V034C12STC-DR VGA 1/3" GS CIS Dry Pack without Protective Film Orderable Product Attribute Description MT9V034C12STM-DP VGA 1/3" GS CIS Dry Pack with Protective Film MT9V034C12STM-DR VGA 1/3" GS CIS Dry Pack without Protective Film MT9V034C12STM-DR1 VGA 1/3" GS CIS Dry Pack Single Tray without Protective Film MT9V034C12STM-TP VGA 1/3" GS CIS Tape & Reel with Protective Film MT9V034C12STM-TR VGA 1/3" GS CIS Tape & Reel without Protective Film MT9V034D00STMC13CC1-200 VGA 1/3" GS CIS Die Sales, 200 mm Thickness MT9V034W00STMC13CC1-750 VGA 1/3" GS CIS Wafer Sales, 750 mm Thickness www.onsemi.com 2 MT9V034 Serial Register I/O Control Register Active-Pixel Sensor (APS) Array 752H x 480V Timing and Control Analog Processing ADCs Parallel Video Data Out Digital Processing Serial Video LVDS Out Slave Video LVDS In (for stereo applications only) DOUT2 1 DOUT1 2 DOUT0 SHFT_CLKOUT_ N 3 PIXCLK SHFT_CLKOUT_P 4 SYSCLK SER_DATAOUT_N 5 DGND SER_DATAOUT_P 6 VDD VDDLVDS Figure 1. Block Diagram 48 47 46 45 44 43 VAAPIX SER_DATAIN_N 10 39 VAA SER_DATAIN_P 11 38 A GND LVDSGND 12 37 D GND 13 36 NC VDD 14 35 VAA D OUT 5 15 34 AGND D OUT 6 16 33 STANDBY DOUT 7 17 32 RESET_BAR D OUT 8 18 31 S_CTRL_ADR1 D OUT 9 19 20 21 22 23 24 25 26 27 28 29 30 S_CTRL_ADR0 40 RSVD 9 OE BYPASS_CLKIN_P LED_OUT DOUT 4 STFRM_OUT 41 SCLK 8 SDATA BYPASS_CLKIN_N EXPOSURE DOUT 3 STLN_OUT 42 FRAME_VALID 7 LINE_VALID LVDSGND Figure 2. 48-Pin CLCC Package Pinout Diagram www.onsemi.com 3 NC MT9V034 BALL DESCRIPTIONS Table 3. BALL DESCRIPTIONS Symbol Type 29 RSVD Input Connect to DGND. 10 SER_DATAIN_N Input Serial data in for stereoscopy (differential negative). Tie to 1K pull-up (to 3.3 V) in non-stereoscopy mode. 11 SER_DATAIN_P Input Serial data in for stereoscopy (differential positive). Tie to DGND in non-stereoscopy mode. 8 BYPASS_CLKIN_N Input Input bypass shift-CLK (differential negative). Tie to 1K pull-up (to 3.3 V) in non-stereoscopy mode. 9 BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to DGND in non-stereoscopy mode. 23 EXPOSURE Input Rising edge starts exposure in snapshot and slave modes. 25 SCLK Input Two-wire serial interface clock. Connect to VDD with 1.5 K resistor even when no other two-wire serial interface peripheral is attached. 28 OE Input DOUT enable pad, active HIGH. 30 S_CTRL_ADR0 Input Two-wire serial interface slave address select (see Table 6). 31 S_CTRL_ADR1 Input Two-wire serial interface slave address select (see Table 6). 32 RESET_BAR Input Asynchronous reset. All registers assume defaults. 33 STANDBY Input Shut down sensor operation for power saving. 47 SYSCLK Input Master clock (26.6 MHz; 13 MHz - 27 MHz). 24 SDATA I/O Two-wire serial interface data. Connect to VDD with 1.5 K resistor even when no other two-wire serial interface peripheral is attached. 22 STLN_OUT I/O Output in master mode-start line sync to drive slave chip in-phase; input in slave mode. 26 STFRM_OUT I/O Output in master mode-start frame sync to drive a slave chip in-phase; input in slave mode. 20 LINE_VALID Output Asserted when DOUT data is valid. 21 FRAME_VALID Output Asserted when DOUT data is valid. 15 DOUT5 Output Parallel pixel data output 5. 16 DOUT6 Output Parallel pixel data output 6. 17 DOUT7 Output Parallel pixel data output 7. 18 DOUT8 Output Parallel pixel data output 8. 19 DOUT9 Output Parallel pixel data output 9. 27 LED_OUT Output LED strobe output. 41 DOUT4 Output Parallel pixel data output 4. 42 DOUT3 Output Parallel pixel data output 3. 43 DOUT2 Output Parallel pixel data output 2. 44 DOUT1 Output Parallel pixel data output 1. 45 DOUT0 Output Parallel pixel data output 0. 46 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. 2 SHFT_CLKOUT_N Output Output shift CLK (differential negative). 52-Ball IBA Numbers Description www.onsemi.com 4 Note 1 2 MT9V034 Table 3. BALL DESCRIPTIONS (continued) 52-Ball IBA Numbers Symbol Type Description Note 3 SHFT_CLKOUT_P Output Output shift CLK (differential positive). 4 SER_DATAOUT_N Output Serial data out (differential negative). 5 SER_DATAOUT_P Output Serial data out (differential positive). 1, 14 VDD Supply Digital power 3.3 V. 35, 39 VAA Supply Analog power 3.3 V. 40 VAAPIX Supply Pixel power 3.3 V. 6 VDDLVDS Supply Dedicated power for LVDS pads. 7, 12 LVDSGND Ground Dedicated GND for LVDS pads. 13, 48 DGND Ground Digital GND. 34, 38 AGND Ground Analog GND. 36, 37 NC NC No connect. 3 1. Pin 29, (RSVD) must be tied to GND. 2. Output enable (OE) tri-states signals DOUT0-DOUT9, LINE_VALID, FRAME_VALID, and PIXCLK. 3. No connect. These pins must be left floating for proper operation. 10K 1.5K Master Clock VDDLVDS VAA VAAPIX VDD VAA VAAPIX DOUT(9:0) LINE_VALID FRAME_VALID PIXCLK SYSCLK OE RESET_BAR EXPOSURE STANDBY S_CTRL_ADR0 S_CTRL_ADR1 SCLK SDATA STANDBY from Controller or Digital GND Two-Wire Serial Interface RSVD LED_OUT ERROR DGND LVDSGND 0.1 F Note: VDD To Controller To LED output AGND LVDS signals are to be left floating. Figure 3. Typical Configuration (Connection) - Parallel Output Mode www.onsemi.com 5 MT9V034 PIXEL DATA FORMAT Pixel Array Structure 753 columns by 481 rows of optically active pixels. While the sensor's format is 752 x 480, one additional active column and active row are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. This one pixel adjustment is always performed, for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Neither dummy pixels nor barrier pixels can be read out. The MT9V034 pixel array is configured as 809 columns by 499 rows, shown in Figure 4. The dark pixels are optically black and are used internally to monitor black level. Of the left 52 columns, 36 are dark pixels used for row noise correction. Of the top 14 rows of pixels, two of the dark rows are used for black level correction. Also, three black rows from the top black rows can be read out by setting the show dark rows bit in the Read Mode register; setting show dark columns will display the 36 dark columns. There are (0, 0) active pixel 2 barrier + 8 (2 + 4 addressed + 2) dark + 2 barrier + 2 light dummy 4.92 x 3.05mm 2 Pixel Array 809 x 499 (753 x 481 active) 6.0 m pixel light dummy pixel dark pixel 3 barrier + 38 (1 + 36 addressed + 1) dark + 9 barrier + 2 light dummy 2 barrier + 2 light dummy barrier pixel 2 barrier + 2 light dummy Figure 4. Pixel Array Description Column Readout Direction Row Readout Direction Active Pixel (0,0) Array Pixel (4,14) G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G Figure 5. Pixel Color Pattern Detail RGB Bayer (Top Right Corner) www.onsemi.com 6 MT9V034 COLOR (RGB BAYER) DEVICE LIMITATIONS The color version of the MT9V034 does not support or offers reduced performance for the following functionalities. on all dark pixels' offset values, the color bit should be cleared. Defective Pixel Correction For defective pixel correction to calculate replacement pixel values correctly, for color sensors the color bit must be set (R0x0F[1] = 1). However, the color bit also applies unequal offset to the color planes, and the results might not be acceptable for some applications. Pixel Binning Pixel binning is done on immediate neighbor pixels only, no facility is provided to skip pixels according to a Bayer pattern. Therefore, the result of binning combines pixels of different colors. See "Pixel Binning" for additional information. Other Limiting Factors Black level correction and row-wise noise correction are applied uniformly to each color. The row-wise noise correction algorithm does not work well in color sensors. Automatic exposure and gain control calculations are made based on all three colors, not just the green channel. High dynamic range does operate in color; however, ON Semiconductor strongly recommends limiting use to linear operation where good color fidelity is required. Interlaced Readout Interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. This is due to the Bayer pattern of the CFA. Automatic Black Level Calibration When the color bit is set (R0x0F[1]=1), the sensor uses black level correction values from one green plane, which are applied to all colors. To use the calibration value based www.onsemi.com 7 MT9V034 OUTPUT DATA FORMAT The MT9V034 image data can be read out in a progressive scan or interlaced scan mode. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 6. The amount of horizontal and vertical blanking is programmable through R0x05 and R0x06, respectively (R0xCD and R0xCE for context B). LV is HIGH during the shaded region of the figure. See "Output Data Timing" for the description of FV timing. P0,0 P0,1 P0,2 .....................................P0,n-1 P0,n P1,0 P1,1 P1,2 .....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE HORIZONTAL BLANKING Pm-1,0 Pm-1,1 .....................................Pm-1,n-1Pm-1,n Pm,0 Pm,1 .....................................Pm,n-1 Pm,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 Figure 6. Spatial Illustration of Image Readout www.onsemi.com 8 MT9V034 OUTPUT DATA TIMING The data output of the MT9V034 is synchronized with the PIXCLK output. When LINE_VALID (LV) is HIGH, one 10-bit pixel datum is output every PIXCLK period. ... LINE_VALID ... PIXCLK Blanking P0 (9:0) DOUT(9:0) ... Valid Image Data P1 (9:0) P2 (9:0) P3 (9:0) P4 (9:0) Blanking ... Pn-1 (9:0) Pn (9:0) Figure 7. Timing Example of Pixel Data The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled, the PIXCLK is HIGH for one complete master clock master period and then LOW for one complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for two complete master clock periods and then LOW for two complete master clock periods. It is continuously enabled, even during the blanking period. Setting R0x72 bit[4] = 1 causes the MT9V034 to invert the polarity of the PIXCLK. The parameters P1, A, Q, and P2 in Figure 8 are defined in Table 4. ... FRAME_VALID ... LINE_VALID ... Number of master clocks P1 A Q A Q A P2 Figure 8. Row Timing and FRAME_VALID/LINE_VALID Signals Table 4. FRAME TIME Parameters Name A Active data time P1 Equation Default Timing at 26.66 MHz Context A: R0x04 Context B: R0xCC 752 pixel clocks = 752 master = 28.2 s Frame start blanking Context A: R0x05 - 23 Context B: R0xCD - 23 71 pixel clocks = 71 master = 2.66 s P2 Frame end blanking 23 (fixed) 23 pixel clocks = 23 master = 0.86 s Q Horizontal blanking Context A: R0x05 Context B: R0xCD 94 pixel clocks = 94 master = 3.52 s A+Q Row time Context A: R0x04 + R0x05 Context B: R0xCC + R0xCD 846 pixel clocks = 846 master = 31.72 s V Vertical blanking Context A: (R0x06) x (A + Q) + 4 Context B: (R0xCE) x (A + Q) + 4 38,074 pixel clocks = 38,074 master = 1.43 ms www.onsemi.com 9 MT9V034 Table 4. FRAME TIME (continued) Default Timing at 26.66 MHz Parameters Name Nrows x (A + Q) Frame valid time Context A: (R0x03) x (A + Q) Context B: (R0xCB) x (A + Q) 406,080 pixel clocks = 406,080 master = 15.23 ms F Total frame time V + (Nrows x (A + Q)) 444,154 pixel clocks = 444,154 master = 16.66 ms Equation Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to Figure 7). The recommended master clock frequency is 26.66 MHz. The vertical blanking and the total frame time equations assume that the integration time (Coarse Shutter Width plus Fine Shutter Width) is less than the number of active rows plus the blanking rows minus the overhead rows: Window Height ) Vertical Blanking * 2 Table 5. In this example it is assumed that the Coarse Shutter Width Control is programmed with 523 rows, and the Fine Shutter Width Total is zero. For Simultaneous mode, if the exposure time registers (Coarse Shutter Width Total plus Fine Shutter Width Total) exceed the total readout time, then the vertical blanking time is internally extended automatically to adjust for the additional integration time required. This extended value is not written back to the vertical blanking registers. The Vertical Blank register can be used to adjust frame-to-frame readout time. This register does not affect the exposure time but it may extend the readout time. (eq.1) If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 5. FRAME TIME-LONG INTEGRATION TIME Parameter Name Equation (Number of Master Clock Cycles) Default Timing at 26.66 MHz V' Vertical blanking (long integration time) Context A: (R0x0B + 2 - R0x03) y (A + Q) + R0xD5 + 4 Context B: (R0xD2 + 2 - R0xCB) x (A + Q) + R0xD8 + 4 38,074 pixel clocks = 38,074 master = 1.43 ms F' Total frame time (long integration time) Context A: (R0x0B + 2) y (A + Q) + R0xD5 +4 Context B: (R0xD2 + 2) x (A + Q) + R0xD8 +4 444,154 pixel clocks = 444,154 master = 16.66 ms 1. The MT9V034 uses column parallel analog-digital converters; thus short row timing is not possible. The minimum total row time is 704 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 61 for normal mode, 71 for column bin 2 mode, and 91 for column bin 4 mode. When the window width is set below 643, horizontal blanking must be increased. In binning mode, the minimum row time is R0x04+R0x05 = 704. www.onsemi.com 10 MT9V034 SERIAL BUS DESCRIPTION Registers are written to and read from the MT9V034 through the two-wire serial interface bus. The MT9V034 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0 and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is transferred into the MT9V034 and out through the serial data (SDATA) line. The SDATA line is pulled up to VDD off-chip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down-the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16-bit wide, and can be accessed through 16- or 8-bit two-wire serial interface sequences. clock pulse. A no-acknowledge bit is used to terminate a read sequence. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Sequence A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request is a read or a write, where a "0" indicates a WRITE and a "1" indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a WRITE, the master then transfers the 8-bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9V034 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical READ sequence is executed as follows. First the master sends the write mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is automatically incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V034 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to Byte-Wise Address register (0x0F0). Protocol The two-wire serial interface defines several different transmission codes, as shown in the following sequence: 1. a start bit 2. the slave device 8-bit address 3. a(n) (no) acknowledge bit 4. an 8-bit message 5. a stop bit Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A "0" in the LSB of the address indicates write mode, and a "1" indicates read mode. As indicated above, the MT9V034 allows four possible slave addresses determined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge Table 6. SLAVE ADDRESS MODES {S_CTRL_ADR1, S_CTRL_ADR0} Slave Address Write/Read Mode 00 0x90 Write 0x91 Read 01 0x98 Write 0x99 Read 10 0xB0 Write 0xB1 Read 11 0xB8 Write 0xB9 Read www.onsemi.com 11 MT9V034 Data Bit Transfer the serial clock-it can only change when the two-wire serial interface clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit. One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of TWO-WIRE SERIAL INTERFACE SAMPLE READ AND WRITE SEQUENCES 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master, followed by the write address, starts the sequence. The image sensor then gives an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit the image sensor gives an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. SCLK SDATA START 0000 0010 Reg0x09 0xBA ADDR ACK 1000 0100 ACK ACK STOP ACK Figure 9. Timing Diagram Showing a WRITE to Reg0x09 with the Value 0x0284 16-Bit Read Sequence clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. A typical read sequence is shown in Figure 10. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then SCLK SDATA 0xBA ADDR START 0xB9 ADDR Reg0x09 ACK ACK 0000 0010 ACK 1000 0100 ACK STOP NACK Figure 10. Timing Diagram Showing a READ from Reg0x09, Returned Value 0x0284 8-Bit Write Sequence (R0xF0). The register is not updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 11, a typical sequence for 8-bit writing is shown. The second byte is written to the Bytewise register (R0xF0). To be able to write 1 byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the Bytewise Address register SCLK DATA 0000 0010 R0x09 0xB8 ADDR 0xB8 ADDR 1000 0100 R0xF0 STOP START START ACK ACK ACK ACK ACK Figure 11. Timing Diagram Showing a Bytewise Write to R0x09 with the Value 0x0284 www.onsemi.com 12 ACK MT9V034 8-Bit Read Sequence Bytewise Address register (R0xF0) the lower 8 bits are accessed (Figure 12). The master sets the no-acknowledge bits shown. To read one byte at a time the same special register address is used for the lower byte. The upper 8 bits are read from the desired register. By following this with a read from the SCLK SDATA 0xB8 ADDR 0000 0010 0xB9 ADDR R0x09 START START ACK ACK NACK ACK SCLK SDATA 0xB8 ADDR 1000 0100 0xB9 ADDR R0xF0 STOP START START ACK ACK ACK NACK Figure 12. Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284 Register Lock Lock Only Read Mode Registers (R0x0D and R0x0E) If a unique pattern (0xDEAF) to R0xFE is programmed, any subsequent two-wire serial interface writes to R0x0D or R0x0E are NOT committed. Alternatively, if the user writes a 0xBEEF to register lock register, registers R0x0D and R0x0E are unlocked and any subsequent two-wire serial interface writes to these registers are committed. Included in the MT9V034 is a register lock (R0xFE) feature that can be used as a solution to reduce the probability of an inadvertent noise-triggered two-wire serial interface write to the sensor. All registers, or only the Read Mode registers- R0x0D and R0x0E, can be locked. It is important to prevent an inadvertent two-wire serial interface write to the Read Mode registers in automotive applications since this register controls the image orientation and any unintended flip to an image can cause serious results. At power-up, the register lock defaults to a value of 0xBEEF, which implies that all registers are unlocked and any two-wire serial interface writes to the register gets committed. Lock All Registers If a unique pattern (0xDEAD) to R0xFE is programmed, any subsequent two-wire serial interface writes to registers (except R0xFE) are NOT committed. Alternatively, if the user writes a 0xBEEF to the register lock register, all registers are unlocked and any subsequent two-wire serial interface writes to the register are committed. www.onsemi.com 13 MT9V034 Real-Time Context Switching the new values apply to the immediate next exposure and readout time (frame n+1), except for shutter width and V1-V4 control, which will take effect for next exposure but will show up in the n+2 image. In the MT9V034, the user may switch between two full register sets (listed in Table 7) by writing to a context switch change bit in register 0x07. This context switch will change all registers (no shadowing) at the frame start time and have Table 7. REAL-TIME CONTEXT-SWITCHABLE REGISTERS Register Name Register Number (Hex) For Context A Register Number (Hex) for Context B Column Start 0x01 0xC9 Row Start 0x02 0xCA Window Height 0x03 0xCB Window Width 0x04 0xCC Horizontal Blanking 0x05 0xCD Vertical Blanking 0x06 0xCE Coarse Shutter Width 1 0x08 0xCF Coarse Shutter Width 2 0x09 0xD0 Coarse Shutter Width Control 0x0A 0xD1 Coarse Shutter Width Total 0x0B 0xD2 Fine Shutter Width 1 0xD3 0xD6 Fine Shutter Width 2 0xD4 0xD7 Fine Shutter Width Total 0xD5 0xD8 0x0D [5:0] 0x0E [5:0] 0x0F [0] 0x0F [8] ADC Resolution Control 0x1C [1:0] 0x1C [9:8] V1 Control - V4 Control 0x31 - 0x34 0x39 - 0x3C 0x35 0x36 Read Mode High Dynamic Range enable Analog Gain Control Row Noise Correction Control 1 0x70 [1:0] 0x70 [9:8] Tiled Digital Gain 0x80 [3:0] - 0x98 [3:0] 0x80 [11:8] - 0x98 [11:8] AEC/AGC Enable 0xAF [1:0] 0xAF [9:8] Recommended Register Settings Table 8 describes new suggested register settings, and descriptions of performance improvements and conditions: Table 8. RECOMMENDED REGISTER SETTINGS AND PERFORMANCE IMPACT (RESERVED REGISTERS) Register Current Default New Setting Performance Impact R0x20 0x01C1 0x03C7 Recommended by design to improve performance in HDR mode and when frame rate is low. We also recommended using R0x13 = 0x2D2E with this setting for better column FPN. NOTE: When coarse integration time set to 0 and fine integration time less than 456, R0x20 should be set to 0x01C7 R0x24 0x0010 0x001B Corrects pixel negative dark offset when global reset in R0x20[9] is enabled. R0x2B 0x0004 0x0003 Improves column FPN. R0x2F 0x0004 0x0003 Improves FPN at near-saturation. www.onsemi.com 14 MT9V034 FEATURE DESCRIPTION Operational Modes The MT9V034 works in master, snapshot, or slave mode. In master mode the sensor generates the readout timing. In snapshot mode it accepts an external trigger to start integration, then generates the readout timing. In slave mode the sensor accepts both external integration and readout controls. The integration time is programmed through the two-wire serial interface during master or snapshot modes, or controlled through an externally generated control signal during slave mode. Simultaneous Master Mode In simultaneous master mode, the exposure period occurs during readout. The frame synchronization waveforms are shown in Figure 13 and Figure 14. The exposure and readout happen in parallel rather than sequential, making this the fastest mode of operation. Master Mode There are two possible operation methods for master mode: simultaneous and sequential. One of these operation modes must be selected through the two-wire serial interface. EXPOSURE TIME LED_OUT t LED2FV-SIM t LED2FV-SIM FRAME_VALID tVBLANK LINE_VALID FRAME TIME Figure 13. Simultaneous Master Mode Synchronization Waveforms #1 EXPOSURE TIME LED_OUT tLEDOFF tLED2FV-SIM FRAME_VALID t VBLANK LINE_VALID FRAME TIME Figure 14. Simultaneous Master Mode Synchronization Waveforms #2 When exposure time is greater than the sum of vertical blank and window height, the number of vertical blank rows is increased automatically to accommodate the exposure time. www.onsemi.com 15 MT9V034 sequential master mode are shown in Figure 15. The frame rate changes as the integration time changes. Sequential Master Mode In sequential master mode the exposure period is followed by readout. The frame synchronization waveforms for EXPOSURE TIME LED_OUT tLED2FV-SEQ tFV2LED-SEQ FRAME_VALID tVBLANK LINE_VALID FRAME TIME Figure 15. Sequential Master Mode Synchronization Waveforms through the two-wire serial interface. After the frame's integration period is complete the readout process commences and the syncs and data are output. Sensor in snapshot mode can capture a single image or a sequence of images. The frame rate may only be controlled by changing the period of the user supplied EXPOSURE pulse train. The frame synchronization waveforms for snapshot mode are shown in Figure 17. Snapshot Mode In snapshot mode the sensor accepts an input trigger signal which initiates exposure, and is immediately followed by readout. Figure 16 shows the interface signals used in snapshot mode. In snapshot mode, the start of the integration period is determined by the externally applied EXPOSURE pulse that is input to the MT9V034. The integration time is preprogrammed at R0x0B or R0xD2 EXPOSURE SYSCLK PIXCLK LINE_VALID CONTROLLER FRAME_VALID MT9V034 DOUT(9:0) Figure 16. Snapshot Mode Interface Signals TE2E EXPOSURE TEW EXPOSURE TIME LED_OUT TE2LED TLED2FV TFV2E FRAME_VALID TVBLANK LINE_VALID FRAME TIME Figure 17. Snapshot Mode Frame Synchronization Waveforms www.onsemi.com 16 MT9V034 provide enough time between successive STLN_OUT pulses to allow the complete readout of one row. It is also important to provide additional STLN_OUT pulses to allow the sensors to read the vertical blanking rows. It is recommended that the user program the vertical blank register (R0x06) with a value of 4, and achieve additional vertical blanking between frames by delaying the application of the STFRM_OUT pulse. The elapsed time between the rising edge of STLN_OUT and the first valid pixel data is calculated for context A by [horizontal blanking register (R0x05) + 4] clock cycles. For context B, the time is (R0xCD + 4) clock cycles. Slave Mode In slave mode, the exposure and readout are controlled using the EXPOSURE, STFRM_OUT, and STLN_OUT pins. When the slave mode is enabled, STFRM_OUT and STLN_OUT become input pins. The start and end of integration are controlled by EXPOSURE and STFRM_OUT pulses, respectively. While a STFRM_OUT pulse is used to stop integration, it is also used to enable the readout process. After integration is stopped, the user provides STLN_OUT pulses to trigger row readout. A full row of data is read out with each STLN_OUT pulse. The user must EXPOSURE t EW t SF2SF t E2SF t SFW STFRM_OUT STLN_OUT t FV2SF t SF2FV FRAME_VALID LINE_VALID EXPOSURE TIME t SF2LED t E2LED LED_OUT Note: 1. Not drawn to scale. 2. Frame readout shortened for clarity. 3. Simultaneous progressive scan readout mode shown. Figure 18. Exposure and Readout Timing (Simultaneous Mode) EXPOSURE tEW tE2SF tSF2SF tSFW STFRM_OUT STLN_OUT tFV2E tSF2FV FRAME_VALID LINE_VALID tE2LED EXPOSURE TIME tSF2LED LED_OUT Note: 1. 2. 3. 4. Not drawn to scale. Frame readout shortened for clarity. STLN_OUT pulses are optional during exposure time. Sequential progressive scan readout mode shown. Figure 19. Exposure and Readout Timing (Sequential Mode) www.onsemi.com 17 MT9V034 Signal Path "Black Level Calibration" for the programmable offset operation description. The MT9V034 signal path consists of a programmable gain, a programmable analog offset, and a 10-bit ADC. See Gain Selection (R0x35 or R0x36 or result of AGC) Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) VREF (R0x2C) 10 (12) bit ADC S ADC Data (9:0) C1 C2 Figure 20. Signal Path On-Chip Biases Blanking Control Horizontal Blank and Vertical Blank registers R0x05 and R0x06 (B: 0xCD and R0xCE), respectively, control the blanking time in a row (horizontal blanking) and between frames (vertical blanking). * Horizontal blanking is specified in terms of pixel clocks. * Vertical blanking is specified in terms of numbers of rows. ADC Voltage Reference The ADC voltage reference is programmed through R0x2C, bits 2:0. The ADC reference ranges from 1.0 V to 2.1 V. The default value is 1.4 V. The increment size of the voltage reference is 0.1 V from 1.0 V to 1.6 V (R0x2C[2:0] values 0 to 6). At R0x2C[2:0] = 7, the reference voltage jumps to 2.1 V. It is very important to preserve the correct values of the other bits in R0x2C. The default register setting is 0x0004. This corresponds to 1.4 V - at this setting 1 mV input to the ADC equals approximately 1 LSB. The actual imager timing can be calculated using Table 4 and Table 5 which describe "Row Timing and FV/LV signals".The minimum number of vertical blank rows is 4. V_Step Voltage Reference This voltage is used for pixel high dynamic range operations, programmable from R0x31 through R0x34 for Context A, or R0x39 through R0x3B for context B. Pixel Integration Control Total Integration Total integration time is the result of coarse shutter width and fine shutter width registers, and depends also on whether manual or automatic exposure is selected. The actual total integration time, tINT is defined as: Chip Version Chip version register R0x00 is read-only. t INT * t INTCoarse ) t INTFint Window Control Registers Column Start A/B, Row Start A/B, Window Height A/B (row size), and Window Width (column size) A/B control the size and starting coordinates of the window. The values programmed in the window height and width registers are the exact window height and width out of the sensor. The window start value should never be set below four. To read out the dark rows set bit 6 of R0x0D. In addition, bit 7 of R0x0D can be used to display the dark columns in the image. Note that there are Show Dark settings only for Context A. (eq. 2) = (number of rows of integration x row time) + (number of pixels of integration x pixel time) where: Number of Rows of Integration (Auto Exposure Control: Enabled) When automatic exposure control (AEC) is enabled, the number of rows of integration may vary from frame to frame, with the limits controlled by R0xAC (minimum coarse shutter width) and R0xAD (maximum coarse shutter width). www.onsemi.com 18 MT9V034 Number of Rows of Integration (Auto Exposure Control: Disabled) If AEC is disabled, the number of rows of integration equals the value in R0x0B or If context B is enabled, the number of rows of integration equals the value in R0xD2. this means the frame time must be a multiple of 1/120 of a second. Under 50 Hz flicker, the frame time must be a multiple of 1/100 of a second. Changes to Integration Time With automatic exposure control disabled (R0xAF[0] for context A, or R0xAF[8] for context B) and if the total integration time (R0x0B or R0xD2) is changed through the two-wire serial interface while FV is asserted for frame n, the first frame output using the new integration time is frame (n + 2). Similarly, when automatic exposure control is enabled, any change to the integration time for frame n first appears in frame (n + 2) output. The sequence is as follows: 1. During frame n, the new integration time is held in the R0x0B or R0D2 live register. 2. Prior to the start of frame (n + 1) readout, the new integration time is transferred to the exposure control module. Integration for each row of frame (n + 1) has been completed using the old integration time. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent on the new value of the integration time. 3. When frame (n + 2) is read out, it is integrated using the new integration time. If the integration time is changed (R0x0B or R0xD2 written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. Number of Pixels of Integration The number of fine shutter width pixels is independent of AEC mode (enabled or disabled): * Context A: the number of pixels of integration equals the value in R0xD5. * Context B: the number of pixels of integration equals the value in R0xD8. Row Timing Context A : Row time + (R0x04 ) R0x05) master clock periods (eq. 3) Context B : Row time + (R0xCC ) R0xCD) master clock periods (eq. 4) Typically, the value of the Coarse Shutter Width Total registers is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If the Coarse Shutter Width Total is increased beyond the total number of rows per frame, the user must add additional blanking rows using the Vertical Blanking registers as needed. See descriptions of the Vertical Blanking registers, R0x06 and R0xCE in Table 1 and Table 2 of the MT9V034 register reference. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60 Hz flicker, www.onsemi.com 19 20 www.onsemi.com AEC-sample point FRAME_VALID (Output) LED_OUT (Output) Two-wire serial Interface (Input) frame-start Exp "A" idle AEC-sample writes new exposure value (Exp "B") Readout Exp "A" Exp "A" frame n frame-start activates new exposure value (Exp "B") Readout Exp "A" Exp "B" frame n+1 new image available at output Exp "B" frame n+2 Readout Exp "B" write new exposure value (Exp "B") Exp "B" Readout Exp "B" idle Readout Exp "B" MT9V034 Figure 21. Latency of Exposure Register in Master Mode MT9V034 Exposure Indicator The exposure indicator is controlled by: * R0x1B LED_OUT Control is clear, LED_OUT is HIGH during exposure. By using R0x1B, bit 1, the polarity of the LED_OUT pin can be inverted. The MT9V034 provides an output pin, LED_OUT, to indicate when the exposure takes place. When R0x1B bit 0 High Dynamic Range High dynamic range is controlled by: Table 9. HIGH DYNAMIC RANGE Context A Context B R0x0F[0] R0x0F[8] Shutter Width 1 R0x08 R0xCF Shutter Width 2 R0x09 R0xD0 Shutter Width Control R0x0A R0xD1 R0x31-R0x34 R0x39-R0x3C High Dynamic Enable V_Step Voltages In the MT9V034, high dynamic range (by setting R0x0F, bit 0 or 8 to 1) is achieved by controlling the saturation level of the pixel (HDR or high dynamic range gate) during the exposure period. The sequence of the control voltages at the HDR gate is shown in Figure 22. After the pixels are reset, the step voltage, V_Step, which is applied to HDR gate, is set up at V1 for integration time t1, then to V2 for time t2, then V3 for time t3, and finally it is parked at V4, which also serves as an antiblooming voltage for the photodetector. This sequence of voltages leads to a piecewise linear pixel response, illustrated (approximately) in Figure 22 and Figure 23. Exposure VAA (3.3V) V1~1.4V V2~1.2V t1 HDR Voltage V3~1.0V V4~0.8V t2 t3 Figure 22. Sequence of Control Voltages at the HDR Gate dV3 Output dV2 dV1 Light Intensity 1/t 1 1/t 2 1/t 3 Figure 23. Sequence of Voltages in a Piecewise Linear Pixel Response www.onsemi.com 21 MT9V034 The parameters of the step voltage V_Step which take values V1, V2, and V3 directly affect the position of the knee points in Figure 23. Light intensities work approximately as a reciprocal of the partial exposure time. Typically, t1 is the longest exposure, t2 shorter, and so on. Thus the range of light intensities is shortest for the first slope, providing the highest sensitivity. The register settings for V_Step and partial exposures are: * V1 = R0x31, bits 5:0 (Context B: R0x39, bits 5:0) * V2 = R0x32, bits 5:0 (Context B: R0x3A, bits 5:0) * V3 = R0x33, bits 5:0 (Context B: R0x3B, bits 5:0) * V4 = R0x34, bits 5:0 (Context B: R0x3C, bits 5:0) * tINT = t1 + t2 + t3 For context A these become: (eq. 5) t 2 + tINT x (12) R0x0A[3:0] or R0xD1[3:0] (eq. 6) t 2 +t INT x (12) R0x0A[7:4] or R0xD1[7:4] (eq. 7) (eq. 11) t 2 + R0x09 * ROx08 ) R0xD4 * R0xD3 (eq. 12) t 3 + R0x0B ) R0xD4 *t 1 *t 2 (eq. 13) For context B these are: t 1 + R0xCF ) R0xD6 (eq. 14) t 2 + R0xD0 * ROxCF ) R0xD7 * R0xD6 (eq. 15) t 3 + R0xD2 ) R0xD8 * t1 *t2 (eq. 16) In all cases above, the coarse component of total integration time may be based on the result of AEC or values in Reg0x0B and Reg0xD2, depending on the settings. Similar to Fine Shutter Width Total registers, the user must not set the Fine Shutter Width 1 or Fine Shutter Width 2 register to exceed the row time (Horizontal Blanking + Window Width). The absolute maximum value for the Fine Shutter Width registers is 1774 master clocks. There are two ways to specify the knee points timing, the first by manual setting and the second by automatic knee point adjustment. Knee point auto adjust is controlled for context A by R0x0A[8] (where default is ON), and for context B by R0xD1[8] (where default is OFF). When the knee point auto adjust enabler is enabled (set HIGH), the MT9V034 calculates the knee points automatically using the following equations: t 1 +t INT * t2 * t 3 t 1 + R0x08 ) R0xD3 ADC Companding Mode By default, ADC resolution of the sensor is 10-bit. Additionally, a companding scheme of 12-bit into 10-bit is enabled by the ADC Companding Mode register. This mode allows higher ADC resolution, which means less quantization noise at low-light, and lower resolution at high light, where good ADC quantization is not so critical because of the high level of the photon's shot noise. As a default for auto exposure, t2 is 1/16 of tINT, t3 is 1/64 of tINT. When the auto adjust enabler is disabled (set LOW), t1, t2, and t3 may be programmed through the two-wire serial interface: t 1 + Coarse SW1 (row * times) ) Fine SW1 (pixel * times) (eq. 8) t 2 + Coarse SW2 * Coarse SW1 ) Fine SW2 * Fine SW1 (eq. 9) t 3 + Total Integration *t 1 *t 2 + Coarse Total Shutter Width ) Fine Shutter Width Total *t 1 *t 2 (eq. 10) 10-bit Codes 1,024 768 8 to 1 Companding (2,048- 4095 4 to 1 Companding (512 - 2047 512 2 to 1 Companding (256- 511 256 No companding (0 -255 256 512 1,024 256- 383) 12-bit Codes 0 -255) 2,048 4,096 Figure 24. 12- to 10-Bit Companding Chart www.onsemi.com 22 384 - 767) 768- 1023) MT9V034 Gain Settings effect the next frame. The frame boundary is slightly after the falling edge of Frame_Valid. In Figure 25 this is shown by the dashed vertical line labeled Frame Start. Both analog and digital gain change regardless of whether the integration time is also changed simultaneously. Digital gain will change as soon as the register is written. new image available AGC-sample at output activates new gain value (Gain "B") frame-start writes new gain value (Gain "B") frame-start Readout Gain "A" FRAME_VALID (Output) Readout Gain "A" LED_OUT (Output) idle Two-wire serial Interface (Input) AGC-sample point Readout Gain "B" Readout Gain "B" frame n+2 frame n+1 frame n write new gain value (Gain "B") idle Readout Gain "B" Readout Gain "B" Changes to Gain Settings When the analog gain (R0x35 for context A or R0x36 for context B) or the digital gain settings (R0x80-R0x98) are changed, the gain is updated on the next frame start. The gain setting must be written before the frame boundary to take Figure 25. Latency of Gain Register(s) in Master Mode www.onsemi.com 23 MT9V034 In the MT9V034, the gain logic divides the image into 25 tiles, as shown in Figure 25. The size and gain of each tile can be adjusted using the above digital gain control registers. Separate tile gains can be assigned for context A and context B. Registers 0x99-0x9E and 0x9F-0xA4 represent the coordinates X0/5-X5/5 and Y0/5-Y5/5 in Figure 25, respectively. Digital gains of registers 0x80-0x98 apply to their corresponding tiles. The MT9V034 supports a digital gain of 0.25-3.75X. When binning is enabled, the tile offsets maintain their absolute values; that is, tile coordinates do not scale with row or column bin setting. Digital gain is applied as soon as register is written. NOTE: There is one exception, for the condition when Column Bin 4 is enabled (R0x0D[3:2] or R0x0E[3:2] = 2). For this case, the value for Digital Tile Coordinate X-direction must be doubled. Analog Gain Analog gain is controlled by: * R0x35 Global Gain context A * R0x36 Global Gain context B The formula for gain setting is: Gain + Bits[6 : 0] 0.0625 (eq. 17) The analog gain range supported in the MT9V034 is 1X-4X with a step size of 6.25 percent. To control gain manually with this register, the sensor must NOT be in AGC mode. When adjusting the luminosity of an image, it is recommended to alter exposure first and yield to gain increases only when the exposure value has reached a maximum limit. * Analog gain = bits (6:0) x 0.0625 for values 16-31 * Analog gain = bits (6:0)/2 x 0.125 for values 32-64 For values 16-31: each LSB increases analog gain 0.0625 v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X. For values 32-64: each 2 LSB increases analog gain 0.125 v/v (that is, double the gain increase for 2 LSB). Range: 2X to 4X. Odd values do not result in gain increases; the gain increases by 0.125 for values 32, 34, 36, and so on. The formula for digital gain setting is: Digital Gain + Bits[3 : 0] Digital Gain Digital gain is controlled by: * R0x99-R0xA4 Tile Coordinates * R0x80-R0x98 Tiled Digital Gain and Weight X0/5 X1/5 X2/5 X3/5 X4/5 X5/5 x0_y0 x1_y0 x4_y0 x0_y1 x1_y1 x4_y1 x0_y2 x1_y2 x4_y2 x0_y3 x1_y3 x4_y3 x0_y4 x1_y4 x4_y4 Y0/5 Y1/5 Y2/5 Y3/5 Y4/5 Y5/5 Figure 26. Tiled Sample www.onsemi.com 24 0.25 (eq. 18) MT9V034 * Black Level Calibration Value: R0x48 * Black Level Calibration Value Step Size: R0x4C Black Level Calibration * * * Black level calibration is controlled by: Frame Dark Average: R0x42 Dark Average Thresholds: R0x46 Black Level Calibration Control: R0x47 The MT9V034 has automatic black level calibration on-chip, and if enabled, its result may be used in the offset correction shown in Figure 27. Gain Selection (R0x35 or R0x36 or result of AGC) Pixel Output (reset minus signal) Offset Correction Voltage (R0x48 or result of BLC) VREF (R0x2C) 10 (12) bit ADC S ADC Data (9:0) C1 C2 Figure 27. Black Level Calibration Flow Chart To avoid oscillation of the black level from below to above, the region the thresholds should be programmed so the difference is at least two times the offset DAC step size. In normal operation, the black level calibration value/offset correction value is calculated at the beginning of each frame and can be read through the two-wire serial interface from R0x48. This register is an 8-bit signed two's complement value. However, if R0x47, bit 0 is set to "1," the calibration value in R0x48 is used rather than the automatic black level calculation result. This feature can be used in conjunction with the "show dark rows" feature (R0x0D[6]) if using an external black level calibration circuit. The offset correction voltage is generated according to the following formulas: The automatic black level calibration measures the average value of pixels from 2 dark rows (1 dark row if row bin 4 is enabled) of the chip. (The pixels are averaged as if they were light-sensitive and passed through the appropriate gain.) This row average is then digitally low-pass filtered over many frames (R0x47, bits 7:5) to remove temporal noise and random instabilities associated with this measurement. Then, the new filtered average is compared to a minimum acceptable level, low threshold, and a maximum acceptable level, high threshold. If the average is lower than the minimum acceptable level, the offset correction voltage is increased by a programmable offset LSB in R0x4C. (Default step size is 2 LSB Offset = 1 ADC LSB at analog gain = 1X.) If it is above the maximum level, the offset correction voltage is decreased by 2 LSB (default). Offset Correction Voltage + (8 * bit signed twos complement calibration value, -127 to 127) ADC input voltage + (Pixel Output Voltage) Analog Gain ) Offset Correction Voltage Defective Pixel Correction 0.25 mV (eq. 19) (Analog Gain ) 1) (eq. 20) Defective Pixel Correction is enabled by R0x07[9]. By default, correction is enabled, and pixels mapped in internal ROM are replaced with corrected values. This might be unacceptable to some applications, in which case pixel correction should be disabled (R0x07[9] = 0). Defective pixel correction is intended to compensate for defective pixels by replacing their value with a value based on the surrounding pixels, making the defect less noticeable to the human eye. The locations of defective pixels are stored in a ROM on chip during the manufacturing process; the maximum number of defects stored is 32. There is no provision for later augmenting the table of programmed defects. In the defect correction block, bad pixels will be substituted by either the average of its neighboring pixels, or its nearest-neighbor pixel, depending on pixel location. Row-wise Noise Correction Row-wise noise correction is controlled by the following registers: * R0x70 Row Noise Control * R0x72 Row Noise Constant www.onsemi.com 25 MT9V034 values from dark columns; it is meant to prevent clipping from negative noise fluctuations. Row-wise noise cancellation is performed by calculating a row average from a set of optically black pixels at the start of each row and then applying each average to all the active pixels of the row. Read Dark Columns register bit and Row Noise Correction Enable register bit must both be set to enable row-wise noise cancellation to be performed. The behavior when Read Dark Columns register bit = 0 and Row Noise Correction Enable register bit = 1 is undefined. The algorithm works as follows: Logical columns 755-790 in the pixel array provide 36 optically black pixel values. Of the 36 values, two smallest value and two largest values are discarded. The remaining 32 values are averaged by summing them and discarding the 5 LSB of the result. The 10-bit result is subtracted from each pixel value on the row in turn. In addition, a positive constant will be added (Reg0x71, bits 7:0). This constant should be set to the dark level targeted by the black level algorithm plus the noise expected on the measurements of the averaged Pixel value + ADC value - dark column average ) R0x71[9 : 0] (eq. 21) Note that this algorithm does not work in color sensor. Automatic Gain Control and Automatic Exposure Control The integrated AEC/AGC unit is responsible for ensuring that optimal auto settings of exposure and (analog) gain are computed and updated every frame. AEC and AGC can be individually enabled or disabled by R0xAF. When AEC is disabled (R0xAF[0] = 0), the sensor uses the manual exposure value in coarse and fine shutter width registers. When AGC is disabled (R0xAF[1] = 0), the sensor uses the manual gain value in R0x35 or R0x36. See "Pixel Integration Control" and the MT9V034 Developer Guide, for more information. EXP. LPF EXP. SKIP Coarse Shutter (R0xA6) Width Total (R0xA8) MAX. EXPOSURE (R0xBD) AEC UNIT CURRENT BIN (current luminance) (R0xBC) MIN EXPOSURE (R0xAC) DESIRED BIN (desired luminance) (R0xA5) 16 AEC OUTPUT 0 To exposure timing control 1 R0xBB HISTOGRAM GENERATOR UNIT AGC OUTPUT AGC UNIT MIN GAIN AEC ENABLE (R0xAF[0 or 8]) 1 To analog gain control 0 MAX. GAIN (R0xAB) R0xBA GAIN LPF (R0xAB) GAIN SKIP (R0xA9) MANUAL GAIN AGC ENABLE A or B (R0xAF[1 or 9]) Figure 28. Controllable and Observable AEC/AGC Registers The exposure is measured in row-time by reading R0xBB. The exposure range is 1 to 2047. The gain is measured in gain-units by reading R0xBA. The gain range is 16 to 63 (unity gain = 16 gain-units; multiply by 1/16 to get the true gain). When AEC is enabled (R0xAF), the maximum auto exposure value is limited by R0xBD; minimum auto exposure is limited by AEC Minimum Exposure, R0xAC. NOTE: AEC does not support sub-row timing; calculated exposure values are rounded down to the nearest row-time. For smoother response, manual control is recommended for short exposure times. When AGC is enabled (R0xAF), the maximum auto gain value is limited by R0xAB; minimum auto gain is fixed to 16 gain-units. The exposure control measures current scene luminosity and desired output luminosity by accumulating a histogram of pixel values while reading out a frame. All pixels are used, whether in color or mono mode. The desired exposure and gain are then calculated from this for subsequent frame. When binning is enabled, tuning of the AEC may be required. The histogram pixel count register, R0xB0, may be adjusted to reflect reduced pixel count. Desired bin register, R0xA5, may be adjusted as required. www.onsemi.com 26 MT9V034 Pixel Clock Speed The sensor goes into monitor mode when R0xD9[0] is set to HIGH. In this mode, the sensor first captures a programmable number of frames (R0xC0), then goes into a sleep period for five minutes. The cycle of sleeping for five minutes and waking up to capture a number of frames continues until R0xD9[0] is cleared to return to normal operation. In some applications when monitor mode is enabled, the purpose of capturing frames is to calibrate the gain and exposure of the scene using automatic gain and exposure control feature. This feature typically takes less than 10 frames to settle. In case a larger number of frames is needed, the value of R0xC0 may be increased to capture more frames. During the sleep period, none of the analog circuitry and a very small fraction of digital logic (including a five-minute timer) is powered. The master clock (SYSCLK) is therefore always required. The pixel clock speed is same as the master clock (SYSCLK) at 26.66 MHz by default. However, when column binning 2 or 4 (R0x0D or R0x0E, bit 2 or 3) is enabled, the pixel clock speed is reduced by half and one-fourth of the master clock speed respectively. See "Read Mode Options" and "Column Binning" for additional information. Hard Reset of Logic The RC circuit for the MT9V034 uses a 10 k resistor and a 0.1 F capacitor. The rise time for the RC circuit is 1s maximum. Soft Reset of Logic * Soft reset of logic is controlled by: R0x0C Reset Bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. Bit 1 is a shadowed reset control register bit to explicitly reset the automatic gain and exposure control feature. These two bits are self-resetting bits and also return to "0" during two-wire serial interface reads. Read Mode Options (Also see "Output Data Format" and "Output Data Timing"). Column Flip By setting bit 5 of R0x0D or R0x0E the readout order of the columns is reversed, as shown in Figure 29. Row Flip By setting bit 4 of R0x0D or R0x0E the readout order of the rows is reversed, as shown in Figure 30. STANDBY Control The sensor goes into standby mode by setting STANDBY to HIGH. Once the sensor detects that STANDBY is asserted, it completes the current frame before disabling the digital logic, internal clocks, and analog power enable signal. To release the sensor out from the standby mode, reset STANDBY back to LOW. The LVDS must be powered to ensure that the device is in standby mode. See "Appendix A - Power-On Reset and Standby Timing" for more information on standby. Monitor Mode Control Monitor mode is controlled by: * R0xD9 Monitor Mode Enable * R0xC0 Monitor Mode Image Capture Control LINE_VALID Normal readout DOUT(9:0) Reverse readout D OUT (9:0) P4,1 (9:0) P4,n (9:0) P4,2 (9:0) P4,3 (9:0) P4,4 (9:0) P4,5 (9:0) P4,n-1 P4,n-2 P4,n-3 P4,n-4 (9:0) (9:0) (9:0) (9:0) P4,6 (9:0) P4,n-5 (9:0) Figure 29. Readout of Six Pixels in Normal and Column Flip Output Mode www.onsemi.com 27 MT9V034 FRAME_VALID Normal readout DOUT(9:0) Reverse readout DOUT(9:0) Row4 (9:0) Row5 (9:0) Row6 (9:0) Row7 (9:0) Row8 7(9:0) Row9 (9:0) Row9 (9:0) Row8 (9:0) Row7 (9:0) Row6 (9:0) Row5 7(9:0) Row4 (9:0) Figure 30. Readout of Six Rows in Normal and Row Flip Output Mode rate by 2x and 4x respectively. Column binning does not increase the frame rate. Pixel Binning In addition to windowing mode in which smaller resolutions (CIF, QCIF) are obtained by selecting a smaller window from the sensor array, the MT9V034 also provides the ability to down-sample the entire image captured by the pixel array using pixel binning. There are two resolution options: binning 2 and binning 4, which reduce resolution by two or by four, respectively. Row and column binning are separately selected. Image mirroring options will work in conjunction with binning. For column binning, either two or four columns are combined by averaging to create the resulting column. For row binning, the binning result value depends on the difference in pixel values: for pixel signal differences of less than 200 LSBs, the result is the average of the pixel values. For pixel differences of greater than 200 LSBs, the result is the value of the darker pixel value. Binning operation increases SNR but decreases resolution. Enabling row bin2 and row bin4 improves frame Row Binning By setting bit 0 or 1 of R0x0D or R0x0E, only half or one-fourth of the row set is read out, as shown in Figure 30. The number of rows read out is half or one-fourth of the value set in R0x03. The row binning result depends on the difference in pixel values: for pixel signal differences less than 200 LSB's, the result is the average of the pixel values. For pixel differences of 200 LSB's or more, the result is the value of the darker pixel value. Column Binning For column binning, either two or four columns are combined by averaging to create the result. In setting bit 2 or 3 of R0x0D or R0x0E, the pixel data rate is slowed down by a factor of either two or four, respectively. This is due to the overhead time in the digital pixel data processing chain. As a result, the pixel clock speed is also reduced accordingly. LINE_VALID Normal readout DOUT(9:0) Row4 (9:0) Row5 (9:0) Row6 (9:0) Row7 (9:0) Row4 (9:0) Row6 (9:0) Row8 (9:0) Row10 (9:0) Row4 (9:0) Row8 (9:0) Row8 (9:0) Row9 (9:0) Row10 (9:0) Row11 (9:0) LINE_VALID Row Bin 2 readout DOUT(9:0) LINE_VALID Row Bin 4 readout DOUT(9:0) Figure 31. Readout of 8 Pixels in Normal and Row Bin Output Mode www.onsemi.com 28 MT9V034 LINE_VALID Normal readout DOUT(9:0) D1 (9:0) D2 (9:0) D3 (9:0) D4 (9:0) D5 (9:0) D6 (9:0) D7 (9:0) D8 (9:0) PIXCLK LINE_VALID Column Bin 2 readout DOUT(9:0) D3 (9:0) D1 (9:0) D5 (9:0) D7 (9:0) PIXCLK LINE_VALID Column Bin 4 readout DOUT(9:0) D1 (9:0) D5 (9:0) PIXCLK Figure 32. Readout of 8 Pixels in Normal and Column Bin Output Mode Consequently, the number of rows read out is half what is set in the window height register. The row start register determines which field gets read out; if the row start register is even, then the even field is read out; if row start address is odd, then the odd field is read out. Interlaced Readout The MT9V034 has two interlaced readout options. By setting R0x07[2:0] = 1, all the even-numbered rows are read out first, followed by a number of programmable field blanking rows (set by R0xBF[7:0]), then the odd-numbered rows, and finally the vertical blanking rows. By setting R0x07[2:0] = 2 only one field row is read out. P4,1 P4,2 P4,3 .....................................P4,n-1 P4,n P6,0 P6,1 P6,2 .....................................P6,n-1 P6,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE - Even Field HORIZONTAL BLANKING Pm-2,0Pm-2,2 .....................................Pm-2,n-2Pm-2,n Pm,2 Pm,2 .....................................Pm,n-1 P m,n 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 P5,1 P5,2 P5,3 .....................................P5,n-1 P5,n P7,0 P7,1 P7,2 .....................................P7,n-1 P7,n FIELD BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE - Odd Field Pm-3,1Pm-3,2 .....................................Pm-3,n-1Pm-3,n Pm,1 Pm,1 .....................................Pm,n-1 Pm,n VERTICAL BLANKING 00 00 00 ............................................................................................. 00 00 00 00 00 00 ............................................................................................. 00 00 00 Figure 33. Spatial Illustration of Interlaced Image Readout When interlaced mode is enabled, the total number of blanking rows are determined by both Field Blanking register (R0xBF) and Vertical Blanking register (R0x06 or R0xCE). The followings are their equations. www.onsemi.com 29 MT9V034 Field Blanking + R0xBF[7 : 0] (eq. 22) Vertical Blanking + R0x06[8 : 0] - R0xBF[7 : 0] (contextA) or R0xCE[8 : 0] - R0xBF[7 : 0] (contextB) (eq. 23) with minimum vertical blanking requirement + 4 (absolute minimum operate; see Vertical Blanking Registers description for VBlank minimums for valid image output) (eq. 24) Similar to progressive scan, FV is logic LOW during the valid image row only. Binning should not be used in conjunction with interlaced mode. LINE_VALID rows and two vertical blanking rows are shown in Figure 34. In the last format, the LV signal is the XOR between the continuous LV signal and the FV signal. By setting bit 2 and 3 of R0x72, the LV signal can get three different output formats. The formats for reading out four Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID Figure 34. Different LINE_VALID Formats LVDS Serial (Stand-Alone/Stereo) Output data. Irrespective of the mode (stereoscopy/stand-alone), LV and FV are always embedded in the pixel data. In stereoscopic mode, the two sensors run in lock-step, implying all state machines are in the same state at any given time. This is ensured by the sensor-pair getting their sys-clks and sys-resets in the same instance. Configuration writes through the two-wire serial interface are done in such a way that both sensors can get their configuration updates at once. The inter-sensor serial link is designed in such a way that once the slave PLL locks and the data-dly, shft-clk-dly and stream-latency-sel are configured, the master sensor streams valid stereo content irrespective of any variation voltage and/or temperature as long as it is within specification. The configuration values of data-dly, shft-clk-dly and stream-latency-sel are either predetermined from the board-layout or can be empirically determined by reading back the stereo-error flag. This flag is asserted when the two sensor streams are not in sync when merged. The combo_reg is used for out-of-sync diagnosis. The LVDS interface allows for the streaming of sensor data serially to a standard off-the-shelf deserializer up to eight meters away from the sensor. The pixels (and controls) are packeted-12-bit packets for stand-alone mode and 18-bit packets for stereoscopy mode. All serial signalling (CLK and data) is LVDS. The LVDS serial output could either be data from a single sensor (stand-alone) or stream-merged data from two sensors (self and its stereoscopic slave pair). The appendices describe in detail the topologies for both stand-alone and stereoscopic modes. There are two standard deserializers that can be used. One for a stand-alone sensor stream and the other from a stereoscopic stream. The deserializer attached to a stand-alone sensor is able to reproduce the standard parallel output (8-bit pixel data, LV, FV, and PIXCLK). The deserializer attached to a stereoscopic sensor is able to reproduce 8-bit pixel data from each sensor (with embedded LV and FV) and pixel-clk. An additional (simple) piece of logic is required to extract LV and FV from the 8-bit pixel www.onsemi.com 30 MT9V034 Internal PIXCLK Internal Parallel Data Internal Line_Valid P41 P42 Internal Frame_Valid External Serial Data Out P51 P52 P53 P43 P44 P45 P46 1023 0 1023 1 P41 P42 P43 P44 P45 P46 P54 P55 P56 2 1 P51 P52 P53 P54 P55 P56 2 3 Figure 35. Serial Output Format for a 6x2 Frame 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information). Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4. 2. The external pixel sequence 1023, 0, 1023 is a reserved sequence (conveys control information for legacy support of MT9V021 applications). Any raw pixel sequence of 1023, 0, 1023 will be substituted with an output serial stream of 1023, 4, 1023. LVDS Output Format consists of a start bit, 8-bit pixel data (with sync codes), the line valid bit, the frame valid bit and the stop bit. For 10-bit pixel mode (R0xB6[0] = 1), the packet consists of a start bit, 10-bit pixel data, and the stop bit. In stand-alone mode, the packet size is 12 bits (2 frame bits and 10 payload bits); 10-bit pixels or 8-bit pixels can be selected. In 8-bit pixel mode (R0xB6[0] = 0), the packet Table 10. LVDS PACKET FORMAT IN STAND-ALONE MODE (Stereoscopy Mode Bit De-Asserted) 12-Bit Packet use_10-bit_pixels Bit De-Asserted (8-Bit Mode) use_10-bit_pixels Bit Asserted (10-Bit Mode) Bit[0] 1'b1 (Start bit) 1'b1 (Start bit) Bit[1] PixelData[2] PixelData[0] Bit2] PixelData[3] PixelData[1] Bit[3] PixelData[4] PixelData[2] Bit4] PixelData[5] PixelData[3] Bit[5] PixelData[6] PixelData[4] Bit[6] PixelData[7] PixelData[5] Bit[7] PixelData[8] PixelData[6] Bit[8] PixelData[9] PixelData[7] Bit[9] Line_Valid PixelData[8] Bit[10] Frame_Valid PixelData[9] Bit[11] 1'b0 (Stop bit) 1'b0 (Stop bit) In stereoscopic mode, the packet size is 18 bits (2 frame bits and 16 payload bits). The packet consists of a start bit, the master pixel byte (with sync codes), the slave byte (with sync codes), and the stop bit.) www.onsemi.com 31 MT9V034 Table 11. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted) 18-bit Packet Function Bit[0] 1'b1 (Start bit) Bit[1] MasterSensorPixelData[2] Bit[2] MasterSensorPixelData[3] Bit[3] MasterSensorPixelData[4] Bit[4] MasterSensorPixelData[5] Bit[5] MasterSensorPixelData[6] Bit[6] MasterSensorPixelData[7] Bit[7] MasterSensorPixelData[8] Bit[8] MasterSensorPixelData[9] Bit[9] SlaveSensorPixelData[2] Bit[10] SlaveSensorPixelData[3] Bit[11] SlaveSensorPixelData[4] Bit[12] SlaveSensorPixelData[5] Bit[13] SlaveSensorPixelData[6] Bit[14] SlaveSensorPixelData[7] Bit[15] SlaveSensorPixelData[8] Bit[16] SlaveSensorPixelData[9] Bit[17] 1'b0 (Stop bit) Control signals LV and FV can be reconstructed from their respective preceding and succeeding flags that are always embedded within the pixel data in the form of reserved words. Table 12. RESERVED WORDS IN THE PIXEL DATA STREAM Pixel Data Reserved Word Flag 0 Precedes frame valid assertion 1 Precedes line valid assertion 2 Succeeds line valid de-assertion 3 Succeeds frame valid de-assertion LVDS Enable and Disable When LVDS mode is enabled along with column binning (bin 2 or bin 4, R0x0D[3:2], the packet size remains the same but the serial pixel data stream repeats itself depending on whether 2X or 4X binning is set: * For bin 2, LVDS outputs double the expected data (post-binning pixel 0,0 is output twice in sequence, followed by pixel 0,1 twice, ...). * For bin 4, LVDS outputs 4 times the expected data (pixel 0,0 is output 4 times in sequence followed by pixel 0,1 times 4, ...). The Table 13 and Table 14 further explain the state of the LVDS output pins depending on LVDS control settings. When the LVDS block is not used, it may be left powered down to reduce power consumption. Table 13. SER_DATAOUT_* STATE R0xB1[1] LVDS power down R0xB3[4] LVDS data power down SER_DATAOUT_* 0 0 Active 0 1 Active 1 0 Z 1 1 Z The receiving hardware will need to undersample the output stream, getting data either every 2 clocks (bin 2) or every 4 (bin 4) clocks. If the sensor provides a pixel whose value is 0,1, 2, or 3 (that is, the same as a reserved word) then the outgoing serial pixel value is switched to 4. www.onsemi.com 32 MT9V034 Table 14. SHFT_CLK_* STATE R0xB1[1] LVDS power down R0xB2[4] LVDS shift-clk power down SHFT_CLKOUT_* 0 0 Active 0 1 Z 1 0 Z 1 1 Z 1. ERROR pin: When the sensor is not in stereo mode, the ERROR pin is at LOW. LVDS Data Bus Timing The LVDS bus timing waveforms and timing specifications are shown in Table 15 and Figure 36. Data Rise/Fall Time (10% - 90%) Data Setup Time Data Hold Time LVDS Data Output (SER_DATAOUT_N/P) LVDS Clock Output (Shft_CLKOUT_N/P) Clock Jitter Clock Rise/Fall Time (10% - 90%) Figure 36. LVDS Timing Table 15. LVDS AC TIMING SPECIFICATIONS (VPWR = 3.3 V 0.3 V; TJ = - 30C to +70C; output load = 100 ; frequency 27 MHz) Minimum Typical Maximum Unit LVDS clock rise time Parameter - 0.22 0.30 ns LVDS clock fall time - 0.22 0.30 ns LVDS data rise time - 0.28 0.30 ns LVDS data fall time - 0.28 0.30 ns LVDS data setup time 0.3 0.67 - ns LVDS data hold time 0.1 1.34 - ns 92 ps LVDS clock jitter - www.onsemi.com 33 MT9V034 ELECTRICAL SPECIFICATIONS Table 16. DC ELECTRICAL CHARACTERISTICS OVER TEMPERATURE (VPWR = 3.3 V 0.3 V; TJ = - 30C to +70C; Output Load = 10 pF; Frequency 13 MHz to 27 MHz; LVDS off) Symbol Definition VIH Input HIGH voltage Condition VIL Input LOW voltage IIN Input leakage current No pull-up resistor; VIN = VPWR or VGND VOH Output HIGH voltage VOL Min. Typ. VPWR - 1.4 - Max. Unit V - 1.3 V -5 - 5 mA IOH = -4.0 mA VPWR - 0.3 - - V Output LOW voltage IOL = 4.0 mA - - 0.3 V IOH Output HIGH current VOH = VDD - 0.7 -11 - - mA IOL Output LOW current VOL = 0.7 - - 11 mA IPWRA Analog supply current Default settings - 12 20 mA IPIX Pixel supply current Default settings - 1.1 3 mA IPWRD Digital supply current Default settings, CLOAD = 10 pF - 42 60 mA ILVDS LVDS supply current Default settings with LVDS on - 13 16 mA IPWRA Standby Analog standby supply current STDBY = VDD - 0.2 3 mA IPWRD Standby Clock Off Digital standby supply current with clock off STDBY = VDD, CLKIN = 0 MHz - 0.1 10 mA IPWRD Standby Clock On Digital standby supply current with clock on STDBY= VDD, CLKIN = 27 MHz - 1 2 mA Table 17. DC ELECTRICAL CHARACTERISTICS (VPWR = 3.3 V 0.3 V; TA = Ambient = 25C) Symbol Definition Condition Min. Typ. Max. Unit 250 - 400 mV - - 50 mV 1.0 1.2 1.4 V - - 35 mV LVDS Driver DC Specifications |VOD| Output differential voltage RLOAD = 100 |DVOD| Change in VOD between complementary output states VOS Output offset voltage DVOS Pixel array current IOS Digital supply current 10 mA Output current when driver is tri-state 1 mA IOZ W + 1% LVDS Receiver DC Specifications VIDTH+ Input differential Iin Input current |VGPD| < 925mV www.onsemi.com 34 -100 - 100 mV - - 20 mA MT9V034 Table 18. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min. Max. Unit -0.3 4.5 V Total power supply current - 200 mA IGND Total ground current - 200 mA VIN DC input voltage -0.3 VDD + 0.3 V VOUT DC output voltage -0.3 VDD + 0.3 V TSTG1 Storage temperature -50 +150 C VSUPPLY Power supply voltage (all supplies) ISUPPLY Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 19. AE ELECTRICAL CHARACTERISTICS (VPWR = 3.3 V 0.3 V; TJ= -30C to +70C; Output Load = 10 pF) Symbol SYSCLK Definition Input clock frequency Condition Min. Typ. Max. Unit Note 1 13.0 26.6 27.0 MHz 45.0 50.0 55.0 % Clock duty cycle tR Input clock rise time - 3 5 ns tF Input clock fall time - 3 5 ns tPLHP SYSCLK to PIXCLK propagation delay CLOAD = 10 pF 4 6 8 ns tPD PIXCLK to valid DOUT(9:0) propagation delay CLOAD = 10 pF -3 0.6 3 ns tSD Data setup time 14 16 - ns tHD Data hold time 14 16 - tPFLR PIXCLK to LV propagation delay CLOAD = 10 pF 5 7 9 ns tPFLF PIXCLK to FV propagation delay CLOAD = 10 pF 5 7 9 ns Propagation Delays for PIXCLK and Data Out Signals falling edge and the data output transition is typically 7ns. Note that the falling edge of the pixel clock occurs at approximately the same time as the data output transitions. See Table 19 for data setup and hold times. The pixel clock is inverted and delayed relative to the master clock. The relative delay from the master clock (SYSCLK) rising edge to both the pixel clock (PIXCLK) tF tR SYSCLK t PLHP PIXCLK t PD t HD t SD DOUT(9:0) Figure 37. Propagation Delays for PIXCLK and Data Out Signals www.onsemi.com 35 MT9V034 Propagation Delays for FRAME_VALID and LINE_VALID Signals rising edge as the end of the output of the last valid pixel's data. As shown in the "Output Data Timing", FV goes HIGH 143 pixel clocks before the first LV goes HIGH. It returns LOW 23 pixel clocks after the last LV goes LOW. The LV and FV signals change on the same rising master clock edge as the data output. The LV goes HIGH on the same rising master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock t PFLR t PIXCLK PFLF PIXCLK FRAME_VALID LINE_VALID FRAME_VALID LINE_VALID Figure 38. Propagation Delays for FRAME_VALID and LINE_VALID Signals Two-Wire Serial Bus Timing Detailed timing waveforms and parameters for the two-wire serial interface bus are shown in Figure 39 and Table 20. SDATA t LOW tf tSU;DAT tr tf t HD;STA tr t BUF SCLK S tHD;STA t HD;DAT t HIGH tSU;STA Sr Figure 39. Two-Wire Serial Bus Timing Parameters www.onsemi.com 36 tSU;STO P S MT9V034 Table 20. TWO-WIRE SERIAL BUS CHARACTERISTICS (fEXTCLK = 27 MHz; VPWR = 3.3 V +0.3 V; TA = 25C) Standard-Mode Fast-Mode Symbol Min Max Min Max Unit fSCL 0 100 0 400 KHz tHD;STA 4.0 - 0.6 - s LOW period of the SCLK clock tLOW 4.7 - 1.3 - s HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - s tSU;STA 4.7 - 0.6 - s tHD;DAT 04 3.455 06 0.95 s - ns Parameter SCLK Clock Frequency After this period, the first clock pulse is generated Set-up time for a repeated START condition Data hold time: tSU;DAT 250 - 1006 Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7 300 ns Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7 300 ns tSU;STO 4.0 - 0.6 - s tBUF 4.7 - 1.3 - s Cb - 400 - 400 pF CIN_SI - 3.3 - 3.3 pF CLOAD_SD - 30 - 30 pF RSD 1.5 4.7 1.5 4.7 K Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Serial interface input pin capacitance SDATA max load capacitance SDATA pull-up resistor 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 2. Two-wire control is I2C-compatible. 3. 4. 5. 6. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. www.onsemi.com 37 MT9V034 certain minimum master clock cycles between transitions. These are specified in Figures 40 through 45, in units of master clock cycles. Minimum Master Clock Cycles In addition to the AC timing requirements described in Table 20, the two-wire serial bus operation also requires 4 4 SCLK SDATA Figure 40. Serial Host Interface Start Condition Timing 4 4 SCLK SDATA Note: All timing are in units of master clock cycle. Figure 41. Serial Host Interface Stop Condition Timing 4 4 SCLK SDATA Note: SDATA is driven by an off-chip transmitter. Figure 42. Serial Host Interface Data Timing for WRITE 5 SCLK SDATA Note: SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip. Figure 43. Serial Host Interface Data Timing for Read www.onsemi.com 38 MT9V034 3 6 SCLK Sensor pulls down SDATA pin SDATA Figure 44. Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor 7 6 SCLK SDATA Note: Sensor tri-states S DATA pin (turns off pull down) After a READ, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a "No Acknowledge" by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used. Figure 45. Acknowledge Signal Timing After an 8-Bit READ from the Sensor Figure 46. Typical Quantum Efficiency - RGB Bayer www.onsemi.com 39 MT9V034 Figure 47. Typical Quantum Efficiency - Monochrome www.onsemi.com 40 MT9V034 APPENDIX A - POWER-ON RESET AND STANDBY TIMING There are no constraints concerning the order in which the requires reset to operate properly at power-up. Refer to various power supplies are applied; however, the MT9V034 Figure 48 for the power-up, reset, and standby sequences. Power up VDD, VDDLVDS, VAA, VAAPIX Active non-Low-Power Low-Power non-Low-Power Pre-Standby Standby Wake up Active Power down MIN 20 SYSCLK cycles RESET_BAR Note 3 STANDBY MIN 10 SYSCLK cycles SYSCLK MIN 10 SYSCLK cycles MIN 10 SYSCLK cycles SCLK, SDATA Does not respond to serial interface when STANDBY = 1 Two-Wire Serial I/F DOUT[9:0] DATA OUTPUT Notes: DOUT[9:0] Driven = 0 1. All output signals are defined during initial power-up with RESET_BAR held LOW without SYSCLK being active. To properly reset the rest of the sensor, during initial power-up, assert RESET_BAR (set to LOW state) for at least 750 ns after all power supplies have stabilized and SYSCLK is active (being clocked). Driving RESET_BAR to LOW state does not put the part in a low power state. 2. Before using two-wire serial interface, wait for 10 SYSCLK rising edges after RESET_BAR is de-asserted. 3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering standby mode. The user must supply enough SYSCLKs to allow a complete frame readout. See Table 4, "Frame Time," for more information. 4. In standby, all video data and synchronization output signals are driven to a low state. 5. In standby, the two-wire serial interface is not active. Figure 48. Power-up, Reset, Clock and Standby Sequence APPENDIX B: ELECTRICAL IDENTIFICATION OF CFA TYPE In order to identify the CFA type (RGB Bayer, Monochrome) that a specific MT9V034 has been, the following table may be used. Table 21. ELECTRICAL IDENTIFICATION OF CFA CFA R0x6B[11:9] R0x6B[8:0] RGB 6 4 Mono 0 4 www.onsemi.com 41 MT9V034 CLCC48 11.43 x 11.43 CASE 848AN D 2.3 0.2 1.7 Seating plane A 8.8 48X R 0.15 1.75 0.8 TYP 4.4 47X 1.0 0.2 48 1 48X 0.40 0.05 5.215 4.84 11.43 8.8 4.4 5.715 0.8 TYP 4X 0.2 5.215 5.715 B 11.43 C Lead finish: Au plating, 0.50 microns minimum thickness over Ni plating, 1.27 microns minimum thickness Substrate material: alumina ceramic 0.7 thickness Wall material: alumina ceramic Lid material: borosilicate glass 0.55 thickness H CTR First clear pixel 0.20 A B C V CTR 10.9 0.1 CTR 0.20 A B C A 0.05 1.400 0.125 0.90 for reference only 0.35 for reference only Image sensor die: 0.675 thickness 0.10 A Optical area 10.9 0.1 CTR Optical center1 Optical area: Maximum rotation of optical area relative to package edges: 1 Maximum tilt of optical area relative to seating plane A : 50 microns Maximum tilt of optical area relative to top of cover glass D : 100 microns Note: 1. Optical center = package center. www.onsemi.com 42 MT9V034 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 43 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MT9V034/D