UL634H256
1
August 15, 2006 STK Control #ML0058 Rev 1.1
Low Voltage PowerStore 32K x 8 nvSRAM
Pin Configuration Pin Description
Signal Name Signal Description
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Out
EChip Enable
GOutput Enable
WWrite Enable
VCCX Power Supply Voltage
VSS Ground
VCAP Capacitor
HSB Hardware Controlled Store/Busy
The UL634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The UL634H256 is a fast static
RAM (35 and 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion) take place automatically upon
power down using charge stored in
an external 68 μF capacitor. Trans-
fers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The UL634H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Top View
SOP
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VCAP
A14
A12
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Features Description
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
35 and 45 ns Access Times
15 and 20 ns Output Enable
Access Times
ICC = 8 mA typ. at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Software initiated STORE
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
Operating temperature range:
0 to 70 °C
-40 to 85 °C
-40 to 125 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Package:SOP32 (300 mil)
Not Recommended For New Designs
UL634H256
2 August 15, 2006
STK Control #ML0058 Rev 1.1
Block Diagram
Operating Mode E HSB W G DQ0 - DQ7
Standby/not selected H H ** High-Z
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L *Data Inputs High-Z
Truth Table for SRAM Operations
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum RatingsaSymbol Min. Max. Unit
Power Supply Voltage VCC -0.5 4.6 V
Input Voltage VI-0.3 VCC+0.5 V
Output Voltage VO-0.3 VCC+0.5 V
Power Dissipation PD1W
Operating Temperature C-Type
K-Type
A-Type
Ta0
-40
-40
70
85
125
°C
°C
°C
Storage Temperature Tstg -65 150 °C
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
*H or L
EEPROM Array
512 x (64 x 8)
RECALL
A0 - A13
Store/
Recall
Control
HSB
Row Decoder
VCCX
VSS
VCAP
G
E
W
Software
Detect
Power
Control
VCCX
VCAP
A5
A6
A7
A8
A9
A11
A12
A13
A14
STORE
SRAM
Array
512 Rows x
64 x 8 Columns
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Column I/O
Column Decoder
A0 A1 A2 A3 A4A10
Input Buffers
UL634H256
3
August 15, 2006 STK Control #ML0058 Rev 1.1
b: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is con-
nected to ground.
c: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
ICC2 is the average current required for the duration of the STORE cycle (STORE Cycle Time).
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
DC Characteristics Symbol Conditions C-Type K-Type A-Type Unit
Min. Max. Min. Max. Min. Max.
Operating Supply CurrentcICC1 VCC
VIL
VIH
tc
tc
= 3.6 V
= 0.8 V
= 2.2 V
= 35 ns
= 45 ns
45
35
47
37
-
40
mA
mA
Average Supply Current during
STOREc
ICC2 VCC
E
W
VIL
VIH
= 3.6 V
≤ 0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
344mA
Average Supply Current during
PowerStore Cycle
ICC4 VCC
VIL
VIH
= 2.7 V
= 0.2 V
≥ VCC-0.2 V
223mA
Standby Supply Currentd
(Cycling TTL Input Levels)
ICC(SB)1 VCC
E
tc
tc
= 3.6 V
= VIH
= 35 ns
= 45 ns
11
9
12
10
-
12
mA
mA
Operating Supply Current
at tcR = 200 nsc
(Cycling CMOS Input Levels)
ICC3 VCC
W
VIL
VIH
= 3.6 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
10 11 12 mA
Standby Supply Curentd
(Stable CMOS Input Levels)
ICC(SB) VCC
E
VIL
VIH
= 3.6 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
111mA
Recommended
Operating Conditions Symbol Conditions Min. Max. Unit
Power Supply VoltagebVCC tc = 35 ns
tc = 45 ns
3.0
2.7
3.6
3.6
V
V
Input Low Voltage VIL
-2 V at Pulse Width
10 ns permitted -0.3 0.8 V
Input High Voltage VIH 2.2 VCC+0.3 V
UL634H256
4 August 15, 2006
STK Control #ML0058 Rev 1.1
DC Characteristics Symbol Conditions Min. Max. Unit
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
IOL
= VCCmin
=-2 mA
= 2 mA
2.4
0.4
V
V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VOL
= VCCmin
= 2.4 V
= 0.4 V 2
-2 mA
mA
Input Leakage Current
High
Low
IIH
IIL
VCC
VIH
VIL
= 3.6 V
= 3.6 V
= 0 V -1
1μA
μA
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
IOHZ
IOLZ
VCC
VOH
VOL
= 3.6 V
= 3.6 V
= 0 V -1
1μA
μA
SRAM Memory Operations
No. Switching Characteristics
Read Cycle
Symbol 35 45 Unit
Alt. IEC Min.Max.Min.Max.
1 Read Cycle TimeftAVAV tcR 35 45 ns
2 Address Access Time to Data ValidgtAVQV ta(A) 35 45 ns
3 Chip Enable Access Time to Data Valid tELQV ta(E) 35 45 ns
4 Output Enable Access Time to Data
Valid tGLQV
ta(G) 15 20 ns
5E
HIGH to Output in High-ZhtEHQZ tdis(E) 13 15 ns
6G
HIGH to Output in High-ZhtGHQZ tdis(G) 13 15 ns
7E LOW to Output in Low-Z tELQX ten(E) 55ns
8G
LOW to Output in Low-Z tGLQX ten(G) 00ns
9 Output Hold Time after Address Change tAXQX tv(A) 33ns
10 Chip Enable to Power ActiveetELICCH tPU 00ns
11 Chip Disable to Power Standbyd, e tEHICCL tPD 35 45 ns
e: Parameter guaranteed but not tested.
f: Device is continuously selected with E and G both LOW.
g: Address valid prior to or coincident with E transition LOW.
h: Measured ± 200 mV from steady state output voltage.
UL634H256
5
August 15, 2006 STK Control #ML0058 Rev 1.1
High Impedance
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
No. Switching Characteristics
Write Cycle
Symbol 35 45 Unit
Alt. #1 Alt. #2 IEC Min. Max. Min. Max.
12 Write Cycle Time tAVAV tAVAV tcW 35 45 ns
13 Write Pulse Width tWLWH tw(W) 25 30 ns
14 Write Pulse Width Setup Time tWLEH tsu(W) 25 30 ns
15 Address Setup Time tAVWL tAVEL tsu(A) 00ns
16 Address Valid to End of Write tAVWH tAVEH tsu(A-WH) 25 30 ns
17 Chip Enable Setup Time tELWH tsu(E) 25 30 ns
18 Chip Enable to End of Write tELEH tw(E) 25 30 ns
19 Data Setup Time to End of Write tDVWH tDVEH tsu(D) 12 15 ns
20 Data Hold Time after End of Write tWHDX tEHDX th(D) 00ns
21 Address Hold after End of Write tWHAX tEHAX th(A) 00ns
22 W LOW to Output in High-Zh, i tWLQZ tdis(W) 13 15 ns
23 W HIGH to Output in Low-Z tWHQX ten(W) 55ns
ta(A)
Previous Data Valid Output Data Valid
tcR
Address Valid
tv(A)
Ai
DQi
Output
(1)
(2)
(9)
Ai
E
G
DQi
Output
tdis(E)
tcR
ta(E)
ten(E)
ten(G)
ta(G) tdis(G)
Output Data Valid
ICC
ACTIVE
STANDBY
tPD
tPU
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(10)
(11)
ta(A) (2)
Address Valid
UL634H256
6 August 15, 2006
STK Control #ML0058 Rev 1.1
L- to H-level
undefined H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
Write Cycle #1: W-controlledj
th(D)
tcW
tsu(E) th(A)
tw(W)
tsu(D)
tdis(W) ten(W)
Address Valid
Input Data Valid
High Impedance
tsu(A-WH)
(12)
(16)
(13)
(19) (20)
(23)
(21)
tsu(A)
th(D)
tcW
tw(E) th(A)
tsu(D)
Input Data Valid
tsu(W)
(12)
(18) (21)
(20)
(19)
Previous Data
High Impedance
tsu(A)
Address Valid
Write Cycle #2: E-controlledj
Ai
E
W
DQi
Input
DQi
Output
Ai
E
W
DQi
Input
DQi
Output
(17)
(15)
(22)
(15) (14)
UL634H256
7
August 15, 2006 STK Control #ML0058 Rev 1.1
Nonvolatile Memory Operations
Mode Selection
EWHSB A13 - A0
(hex) Mode I/O Power Notes
H X H X Not Selected Output High Z Standby
L H H X Read SRAM Output Data Active l
L L H X Write SRAM Input Data Active
LHH 0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active k, l
k, l
k, l
k, l
k, l
k
LHH 0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active k, l
k, l
k, l
k, l
k, l
k
X X L X STORE/Inhibit Output High Z ICC2/Standby m
k: The six consecutive addresses must be in order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a Store cycle or (0E38, 31C7, 03E0, 3C1F,
303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and dia-
grams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
No. PowerStore Power Up RECALL/
Hardware Controlled STORE
Symbol Conditions Min. Max. Unit
Alt. IEC
24 Power Up RECALL Durationn, e tRESTORE 650 μs
25 STORE Cycle Duration tHLQX td(H)S VCC > 2.7 V 10 ms
26 HSB Low to Inhibit OnetHLQZ tdis(H)S 500 ns
27 HSB High to Inhibit OffetHHQX ten(H)S 700 ns
28 External STORE Pulse WidthetHLHX tw(H)S 20 ns
HSB Output Low Currente,o IHSBOL HSB = VOL 1.8 mA
HSB Output High Currente, o IHSBOH HSB = VIL 560μA
Low Voltage Trigger Level VSWITCH 2.4 2.7 V
n: tRESTORE starts from the time VCC rises above VSWITCH.
o: HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 UL634H256 to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other UL634H256 HSB pins.
UL634H256
8 August 15, 2006
STK Control #ML0058 Rev 1.1
PowerStore and Automatic Power Up RECALL
Hardware Controlled STORE
DQi
Output
Previous Data Valid
HSB ten(H)S
td(H)S
Data Valid
tdis(H)S
p: tPDSTORE approximate td(E)S or td(H)S; tDELAY approximate tdis(H)S.
q: After tw(H)S HSB is hold down internal by STORE operation.
r: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
s: Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
t: Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
No. Software Controlled STORE/
RECALL Cycle
Symbol 35 45 Unit
Alt. IEC Min. Max. Min. Max.
29 STORE/RECALL Initiation Time tAVAV tcR 35 45 ns
30 Chip Enable to Output InactivestELQZ tdis(E)SR 600 600 ns
31 STORE Cycle Time tELQXS td(E)S 10 10 ms
32 RECALL Cycle TimertELQXR td(E)R 20 20 μs
33 Address Setup to Chip EnablettAVELN tsu(A)SR 00ns
34 Chip Enable Pulse Widths, t tELEHN tw(E)SR 25 30 ns
35 Chip Disable to Address ChangettEHAXN th(A)SR 00ns
tw(H)Sq(28)
(26)
(27)
(25)
High Impedance
VCAP
3.0 V
t
PowerStore
Power Up
VSWITCH
W
DQi
POWER UP
RECALL
BROWN OUT
tRESTOREtRESTORE
BROWN OUT
PowerStore
(NO SRAM WRITES)
RECALL (24) (24)
NO STORE
tPDSTOREp
tDELAYp
UL634H256
9
August 15, 2006 STK Control #ML0058 Rev 1.1
u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the UL634H256 performs a
STORE or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles
tcR
tw(E)SR
ADDRESS 1
VALID
Software Controlle d STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)
ADDRESS 6
(29) (29)
th(A)SR
(35)
(34)
tsu(A)SR (33)
tcR
tw(E)SR
ADDRESS 1
VALID VALID
ADDRESS 6
td(E)S (31) (32)
(29)
th(A)SR
(35)
(34)
tsu(A)SR (33)
tdis(E)SR (30)
th(A)SR (35)
tsu(A)SR
(33)
tw(E)SR
th(A)SR (35)
(34)
tsu(A)SR
(33) (5)
tdis(E)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tdis(E)SR (30)
VALID
High Impedance
High Impedance
Ai
E
DQi
Output
Ai
E
DQi
Output
td(E)S
(31) (32)
td(E)R
td(E)R
tcR
UL634H256
10 August 15, 2006
STK Control #ML0058 Rev 1.1
Test Configuration for Functional Check
x: In measurement of tdis-times and ten-times the capacitance is 5 pF.
y: Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
CapacitanceeConditions Symbol Min. Max. Unit
Input Capacitance VCC
VI
f
Ta
= 3.0 V
= VSS
= 1 MHz
= 25 °C
CI8pF
Output Capacitance CO7pF
All Pins not under test must be connected with ground by capacitors.
VCCXY V
CAP
VIH
VIL
VSS
1.1 k
950
30 pF x
VO
Simultaneous measure-
ment of all 8 output pins
Input level according to the
relevant test measurement
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
HSB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
HSB
E
W
G
3 V
A13
A14
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
A = -40 to 125 °C
G1S45CUL634H256
Type
Package
S = SOP32 (300mil)
Ordering Code
Leadfree Option
G1 = Leadfree Green Package
Access Time
35 = 35 ns (VCC = 3.0 ... 3.6 V)
45 = 45 ns (VCC = 2.7 ... 3.6 V)
Example
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
Product specification
Internal Code
Device Marking (example)
ZMD
UL634H256SC
45 Z 0425
G1
UL634H256
11
August 15, 2006 STK Control #ML0058 Rev 1.1
Device Operation
The UL634H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory ope-
rates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence or HSB assertion and are also auto-
matically initiated when the power supply voltage level
of the chip falls below VSWITCH. RECALL operations are
automatically initiated upon power up and may also
occur when the VCCX rises above VSWITCH, after a low
power condition. RECALL cycles may also be initiated
by a software sequence.
SRAM READ
The UL634H256 performs a READ cycle whenever E
and G are LOW and HSB and W are HIGH. The
address specified on pins A0 - A14 determines which of
the 32768 data bytes will be accessed. When the
READ is initiated by an address transition, the outputs
will be valid after a delay of tcR. If the READ is initiated
by E or G, the outputs will be valid at ta(E) or at ta(G),
whichever is later. The data outputs will repeatedly
respond to address changes within the tcR access time
without the need for transition on any control input pins,
and will remain valid until another address change or
until E or G is brought HIGH or W or HSB is brought
LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW and HSB is HIGH. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes HIGH at the end
of the cycle. The data on pins DQ0 - 7 will be written
into the memory if it is valid tsu(D) before the end of a W
controlled WRITE or tsu(D) before the end of an E con-
trolled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
Automatic STORE
During normal operation, the UL634H256 will draw cur-
rent from VCCX to charge up a capacitor connected to
the VCAP pin. This stored charge will be used by the
chip to perform a single STORE operation. If the
voltage on the VCCX pin drops below VSWITCH, the part
will automatically disconnect the VCAP pin from VCCX
and initiate a STORE operation.
Figure 1 shows the proper connection of capacitors for
automatic STORE operation. The charge storage capa-
citor should have a capacity of 68 μF (± 20 %) at 6 V.
Each UL634H256 must have its own 68 μF capacitor.
Each UL634H256 must have a high quality, high fre-
quency bypass capacitor of 0.1 μF connected between
VCAP and VSS, using leads and traces that are short as
possible. This capacitor does not replace the normal
expected high frequency bypass capacitor between the
power supply voltage and VSS.
In order to prevent unneeded STORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE cycle. Note that if HSB is driven LOW
via external circuitry and no WRITES have taken place,
the part will still be disabled until HSB is allowed to
return HIGH. Software initiated STORE cycles are per-
formed regardless of whether or not a WRITE opera-
tion has taken place.
Automatic RECALL
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
VSWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the UL634H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
Software Nonvolatile STORE
The UL634H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the UL634H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the pre-
vious nonvolatile data is performed first, followed by a
parallel programming of all nonvolatile elements. Once
a STORE cycle is initiated, further inputs and outputs
are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
UL634H256
12 August 15, 2006
STK Control #ML0058 Rev 1.1
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles are used in the sequence, although it
is not necessary that G is LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
Software Nonvolatile RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
HSB Nonvolatile STORE
The hardware controlled STORE Busy pin (HSB) is
connected to an open drain circuit acting as both input
and output to perform two different functions. When
driven LOW by the internal chip circuitry it indicates that
a STORE operation (initiated via any means) is in pro-
gress within the chip. When driven LOW by external cir-
cuitry for longer than tw(H)S, the chip will conditionally
initiate a STORE operation after tdis(H)S.
READ and WRITE operations that are in progress
when HSB is driven LOW (either by internal or external
circuitry) will be allowed to complete before the STORE
operation is performed, in the following manner.
After HSB goes LOW, the part will continue normal
SRAM operation for tdis(H)S. During tdis(H)S, a transition
on any address or control signal will terminate SRAM
operation and cause the STORE to commence.
Note that if an SRAM WRITE is attempted after HSB
has been forced LOW, the WRITE will not occur and
the STORE operation will begin immediately.
HARDWARE-STORE-BUSY (HSB) is a high speed,
low drive capability bidirectional control line.
In order to allow a bank of UL634H256s to perform syn-
chronized STORE functions, the HSB pin from a num-
ber of chips may be connected together. Each chip
contains a small internal current source to pull HSB
HIGH when it is not being driven LOW. To decrease the
sensitivity of this signal to noise generated on the PC
board, it may optionally be pulled to power supply via
an external resistor with a value such that the combi-
ned load of the resistor and all parallel chip connections
does not exceed IHSBOL at VOL (see Figure 1 and 2).
Only if HSB is to be connected to external circuits, an
external pull-up resistor should be used.
During any STORE operation, regardless of how it was
initiated, the UL634H256 will continue to drive the HSB
pin LOW, releasing it only when the STORE is com-
plete.
Upon completion of a STORE operation, the part will be
disabled until HSB actually goes HIGH.
Hardware Pr otection
The UL634H256 offers hardware protection against
inadvertent STORE operation during low voltage condi-
tions. When VCAP < VSWITCH, all software or HSB initia-
ted STORE operations will be inhibited.
Preventing Automatic STORES
The PowerStore function can be disabled on the fly by
holding HSB HIGH with a driver capable of sourcing
15 mA at VOH of at least 2.2 V as it will have to overpo-
wer the internal pull-down device that drives HSB LOW
for 50 ns at the onset of a PowerStore.
When the UL634H256 is connected for PowerStore
operation (see Figure 1) and VCCX crosses VSWITCH on
the way down, the UL634H256 will attempt to pull HSB
LOW; if HSB doesn′t actually get below VIL, the part will
stop trying to pull HSB LOW and abort the PowerStore
attempt.
Disabling Automatic STORES
If the PowerStore function is not required, then VCAP
should be tied directly to the power supply and VCCX
should by tied to ground. In this mode, STORE opera-
tion may be triggered through software control or the
HSB pin. In either event, VCAP (Pin 1) must always
have a proper bypass capacitor connected to it
(Figure 2).
UL634H256
13
August 15, 2006 STK Control #ML0058 Rev 1.1
Low A verage Active Power
The UL634H256 has been designed to draw signifi-
cantly less power when E is LOW (chip enabled) but
the access cycle time is longer than 45 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the power supply voltage level
+
0.1 μF
Bypass
68 μF
± 20 %
VCAP
VSS
Power
Supply
VCCX
HSB 10 kΩ
(optional,
Figure 1: Automatic STORE Operation
Schematic Diagram
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
32
231
429
528
330
627
726
825
12 21
924
10 23
11 22
13 20
14 19
15 18
16 17
VCAP
3.0 V
STORE inhibit
Power Up
VSWITCH
tRESTORE
RECALL
(24)
t
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
1
see description HSB
nonvolatile store)
0.1 μF
Bypass
VCAP
VSS
Power
Supply
VCCX
HSB
10 kΩ
(optional,
Figure 2: Disabling Automatic STORES
Schematic Diagram
32
231
429
528
330
627
726
825
12 21
924
10 23
11 22
13 20
14 19
15 18
16 17
1
see description HSB
nonvolatile store)
Simtek Corporation
4250 Buckingham Drive suite 100 • Colorado Springs, CO 80907 • USA
Phone: +(800)637-1667 • Fax: +(719)531-9481 • Email: information@simtek.com • http://www.simtek.com
UL634H256
August 15, 2006
LIFE SUPPORT POLICY
SIMTEK products are not designed, intended, or authorized for use as components in systems intended for surgi-
cal implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SIMTEK product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by SIMTEK for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However SIMTEK Cor-
poration (SIMTEK) makes no guarantee or warranty concerning the accuracy of said information and shall not be
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The informa-
tion in this document describes the type of component and shall not be considered as assured characteristics.
SIMTEK does not guarantee that the use of any information contained herein will not infringe upon the patent,
trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby.
This document does not in any way extent SIMTEK’s warranty on any product beyond that set forth in its standard
terms and conditions of sale.
SIMTEK reserves terms of delivery and reserves the right to make changes in the products or specifications, or
both, presented in this publication at any time and without notice.
Change record
Date/Rev Name Change
01.11.2001 Ivonne Steffens format revision and release for “Memory CD 2002”
22.04.2002 Thomas Wolf
Matthias Schniebel
removing “at least” for the 100 μF capacitor on page 11 (Automatic
STORE)
03.07.2002 Matthias Schniebel adding 35 ns type with VCC = 3.0 ... 3.6 V
changing capacitor value to 68 μF
09.01.2003 Matthias Schniebel Removing 55 ns type
26.05.2003 Thomas Wolf
Matthias Schniebel
adding A-Type with ICC1 = 40mA; ICC2 = 4mA; ICC3 = 10mA;
ICC4 = 3mA; ICC(SB) = 1mA; ICC(SB)1 = 12 mA
20.10.2003 Matthias Schniebel Low Voltage Trigger Level VSWITCH = 2.4 ... 2.7 V (old: 2.5 ... 2.7 V)
05.12.2003 Matthias Schniebel ICC = 8 mA typ. at 200 ns Cycle Time
adding K-Type with 35 ns: ICC1 = 47 mA, ICC(SB)1 = 12mA
changing ICC3 = 10mA (C-Type), 11mA (K-Type), 12mA (A-Type)
21.04.2004 Matthias Schniebel adding “Leadfree Green Package” to ordering information
adding “Device Marking”
7.4.2005 Stefan Günther page1: adding RoHS compliance and Pb- free, 106 endurance cycles
and 100a dataretention
12.10.2005 Stefan Günther add A- type on page 1 and in ordering instructions
31.03.2006 Simtek Assigned Simtek Document Control Number
15.08.2006 Simtek Move Product to End of Life Status
