Rev. 0.1 / Nov. 2009 1
240pin DDR3L SDRAM Registered DIMM
DDR3L SDRAM Registered DIMM
Based on 1Gb B-die
HMT112R7BFR8A
HMT125R7BFR8A
HMT125R7BFR4A
HMT151R7BFR8A
HMT151R7BFR4A
*Hynix Semiconductor reserves the right to change products or sp ecifications without notice
Rev. 0.1 / Nov. 2009 2
Revision History
Revision No. History Draft Date Remark
0.1 Initial Release Nov. 2009 Preliminary
Rev. 0.1 / Nov. 2009 3
Description
Hynix Registered DDR3L SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3L SDRAM
devices. These R egister ed SDRAM DIMMs are intended f or use as main memory when installed in systems
such as servers and workstations.
Features
• Power Supply: VDD=1.35V (1.283V to 1.45V)
• VDDQ = 1.35V (1.283V to 1.45V)
• Backward Compatible with 1.5V DDR3 Memory Module
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the DDR3L SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3L-10600, PC3L-8500
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
* This product is in compliance with the RoHS directive.
Ordering Information
* In order to uninstall FDHS, please contact sales administrator
Part Number Density Organization Component Composition # of
ranks FDHS
HMT112R7BFR8A-G7/H9 1GB 128Mx72 128Mx8(H5TC1G83BFR)*9 1 X
HMT125R7BFR8A-G7/H9 2GB 256Mx72 128Mx8(H5TC1G83BFR)*18 2 X
HMT125R7BFR4A-G7/H9 2GB 256Mx72 256Mx4(H5TC1G43BFR)*18 2 X
HMT151R7BFR4A-G7/H9 4GB 512Mx72 256Mx4(H5TC1G43BFR)*36 2 O
HMT151R7BFR8A-G7 4GB 512Mx72 128Mx8(H5TC1G83BFR)*36 4 O
Rev. 0.1 / Nov. 2009 4
Key Parameters
Speed Grade
Address Table
MT/s Grade tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns) tRP
(ns) tRAS
(ns) tRC
(ns) CL-tRCD-tRP
DDR3-1066 -G7 1.875 713.125 13.125 37.5 50.625 7-7-7
DDR3-1333 -H9 1.5 9 13.5 13.5 36 49.5 9-9-9
Grade Frequency [MHz] Remark
CL6 CL7 CL8 CL9 CL10
-G7 800 1066 1066
-H9 800 1066 1066 1333 1333
1GB(1Rx8) 2GB(2Rx8) 2GB(1Rx4) 4GB(2Rx4) 4GB(4Rx8)
Refresh
Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms
Row Address A0-A13 A0-A13 A0-A13 A0-A13 A0-A13
Column
Address A0-A9 A0-A9 A0-A9, A11 A0-A9,A11 A0-A9
Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2
Page Size 1KB 1KB 1KB 1KB 1KB
Rev. 0.1 / Nov. 2009 5
Pin Descriptions
Pin Name Description Num
ber Pin Name Description Num
ber
CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2
CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64
CK1 Clock Input, positive line 1 CB[7:0] Data check bits Input/Output 8
CK1 Clock Input, negative line 1 DQS[8:0] Data strobes 9
CKE[1:0] Clock Enables 2 DQS[8:0] Data strobes, negative line 9
RAS Row Address Strobe 1 DM[8:0]/
DQS[17:9],
TDQS[17:9]
Data Masks / Data strobes,
Termination data strobes 9
CAS Column Address Strobe 1 DQS[17:9],
TDQS[17:9] Data strobes, negative line,
Termination data strobes 9
WE Write Enable 1 EVENT Reserved for optional hardware
temperature sensing 1
S[3:0] Chip Selects 4 TEST Memory bus test tool (Not Con-
nected and Not Usable on DIMMs) 1
A[9:0],A11,
A[15:13] Address Inputs 14 RESET Register and SDRAM control pin 1
A10/AP Address Input/Autoprecharge 1 VDD Power Supply 22
A12/BC Address Input/Burst chop 1 VSS Ground 59
BA[2:0] SDRAM Bank Addresses 3 VREFDQ Reference Voltage for DQ 1
SCL Serial Presence Detect (SPD)
Clock Input 1VREFCA Reference Voltage for CA 1
SDA SPD Data Input/Output 1 VTT Termination Voltage 4
SA[2:0] SPD Address Inputs 3 VDDSPD SPD Power 1
Par_In Parity bit for the Address and
Control bus 1
Err_Out Parity error found on the
Address and Control bus 1
Rev. 0.1 / Nov. 2009 6
Input/Output Functional Descriptions
Symbol Type Polarity Function
CK0 IN Positive
Line Positive line of the differential pair of system clock inputs that drives input to the on-
DIMM Clock Driver.
CK0 IN Negative
Line Negative line of the differential pair of system clock inputs that drives the input to the
on-DIMM Clock Driver.
CK1 IN Positive
Line Terminated but not used on RDIMMs.
CK1 IN Negative
Line Terminated but not used on RDIMMs.
CKE[1:0] IN Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle ), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
S[3:0] IN Active
Low
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
and previous operations continue. Other combinations of these input signals perform
unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or acc e ssing internal control words in the register device(s). For modules
with two registers, S[3:2] operat e similarl y to S[1:0] for the second set of register out-
puts or register control words.
ODT[1:0] IN Active
High On-Die Terminat io n co ntrol signals
RAS, CAS, WE IN Active
Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
VREFDQ Supply Reference voltage for DQ0-DQ63 and CB0-CB7.
VREFCA Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
BA[2:0] IN —
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines mode register is to be accessed during an MRS
cycle.
A[15:13,
12/BC,11,
10/AP,[9:0] IN —
Provided the row addre ss for Ac tive commands and the column address
and Auto Precharge bit for Read/W rite commands to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a Precharge command to deter-
mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be prec harged , the ban k is sel ected by BA. A12 is also util ized f or B L
4/8 identification of “’BL on the fly’’ during CAS command. The address inputs also pro-
vide the op-code during Mode Register Set commands.
DQ[63:0],
CB[7:0] I/O — Data and C heck Bit Input/Output pins
DM[8:0] IN Active
High Masks write data when high, issued concurrently with input data.
VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
VTT Supply Termination Voltage for Address/Command/Control/Clock nets.
Rev. 0.1 / Nov. 2009 7
DQS[17:0] I/O Positive
Edge Positive line of the differential data strobe for input and output data.
DQS[17:0] I/O Negative
Edge Negative line of the differential data strobe for input and output data.
TDQS[17:9]
TDQS[17:9] OUT
TDQS/TDQS is applicabl e for X8 DRAMs only. When enabled via Mo de Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4 /X16 DRAM s must disable the
TDQS function via mode register A11=0 in MR1
SA[2:0] IN — These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
SDA I/O — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SD A bus li ne to VDDSPD on the system planar to act as a
pullup.
SCL IN — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
EVENT OUT
(open
drain) Active Low
This signal ind icates that a thermal event has been detected i n the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
No pull-up resister is provided on DIMM.
VDDSPD Supply Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
RESET IN The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
Par_In IN Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Err_Out OUT
(open
drain)
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to VDD on the system planar to act as a pull up.
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs )
Symbol Type Polarity Function
Rev. 0.1 / Nov. 2009 8
Pin Assignments
Pin # Front Side
(left 1–60) Pin # Back Side
(right 121–180) Pin # Front Side
(left 61–120) Pin # Back Side
(right 181–240)
1VREFDQ 121
V
SS
61 A2 181 A1
2
V
SS
122 DQ4 62 VDD 182 VDD
3 DQ0 123 DQ5 63 NC, CK1 183 VDD
4 DQ1 124
V
SS
64 NC, CK1 184 CK0
5
V
SS
125 DM0,DQS9,
TDQS9 65 VDD 185 CK0
6DQS0126 NC,DQS9,
TDQS9 66 VDD 186 VDD
7 DQS0 127
V
SS
67 VREFCA 187 EVENT, NC
8
V
SS
128 DQ6 68 Par_In, NC 188 A0
9 DQ2 129 DQ7 69 VDD 189 VDD
10 DQ3 130
V
SS
70 A10 / AP 190 BA1
11
V
SS
131 DQ12 71 BA0 191 VDD
12 DQ8 132 DQ13 72 VDD 192 RAS
13 DQ9 133
V
SS
73 WE 193 S0
14
V
SS
134 DM1,DQS10,
TDQS10 74 CAS 194 VDD
15 DQS1 135 NC,DQS10,
TDQS10 75 VDD 195 ODT0
16 DQS1 136
V
SS
76 S1, NC 196 A 13
17
V
SS
137 DQ14 77 ODT1, NC 197 VDD
18 DQ10 138 DQ15 78 VDD 198 S3, NC
19 DQ11 139
V
SS
79 S2, NC 199
V
SS
20
V
SS
140 DQ20 80
V
SS
200 DQ36
21 DQ16 141 DQ21 81 DQ32 201 DQ37
22 DQ17 142
V
SS
82 DQ33 202
V
SS
23
V
SS
143 DM2,DQS11,
TDQS11 83
V
SS
203 DM4,DQS13,
TDQS13
24 DQS2 144 NC,DQS11,
TDQS11 84 DQS4 204 NC,DQS13,
TDQS13
25 DQS2 145
V
SS
85 DQS4 205
V
SS
26
V
SS
146 DQ22 86
V
SS
206 DQ38
27 DQ18 147 DQ23 87 DQ34 207 DQ39
28 DQ19 148
V
SS
88 DQ35 208
V
SS
29
V
SS
149 DQ28 89
V
SS
209 DQ44
30 DQ24 150 DQ29 90 DQ40 210 DQ45
31 DQ25 151
V
SS
91 DQ41 211
V
SS
NC = No Connect; RFU = Reserved Future Use
Rev. 0.1 / Nov. 2009 9
32
V
SS
152 DM3,DQS12,
TDQS12 92
V
SS
212 DM5,DQS14,
TDQS14
33 DQS3 153 NC,DQS12,
TDQS12 93 DQS5 213 NC,DQS14,
TDQS14
34 DQS3 154
V
SS
94 DQS5 214
V
SS
35
V
SS
155 DQ30 95
V
SS
215 DQ46
36 DQ26 156 DQ31 96 DQ42 216 DQ47
37 DQ27 157
V
SS
97 DQ43 217
V
SS
38
V
SS
158 CB4, NC 98
V
SS
218 DQ52
39 CB0, NC 159 CB5, NC 99 DQ48 219 DQ53
40 CB1, NC 160
V
SS
100 DQ49 220
V
SS
41
V
SS
161 NC,DM8,DQS17,
TDQS17 101
V
SS
221 DM6,DQS15,
TDQS15
42 DQS8 162 NC,DQS17,
TDQS17 102 DQS6 222 NC,DQS15,
TDQS15
43 DQS8 163
V
SS
103 DQS6 223
V
SS
44
V
SS
164 CB6, NC 104
V
SS
224 DQ54
45 CB2, NC 165 CB7, NC 105 DQ50 225 DQ55
46 CB3, NC 166
V
SS
106 DQ51 226
V
SS
47
V
SS
167 NC(TEST) 107
V
SS
227 DQ60
48 VTT, NC 168 RESET 108 DQ56 228 DQ61
KEY KEY 109 DQ57 229
V
SS
49 VTT, NC 169 CKE1, NC 110
V
SS
230 DM7,DQS16,
TDQS16
50 CKE0 170 VDD 111 DQS7 231 NC,DQS16,
TDQS16
51 VDD 171 A15 112 DQS7 232
V
SS
52 BA2 172 A14 113
V
SS
233 DQ62
53 Err_Out, NC 173 VDD 114 DQ58 234 DQ63
54 VDD 174 A12 / BC 115 DQ59 235
V
SS
55 A11 175 A9 116
V
SS
236 VDDSPD
56 A7 176 VDD 117 SA0 237 SA1
57 VDD 177 A8 118 SCL 238 SDA
58 A5 178 A6 119
SA2
239
V
SS
59 A4 179 VDD 120 VTT 240 VTT
60 VDD 180 A3
Pin # Front Side
(left 1–60) Pin # Back Side
(right 121–180) Pin # Front Side
(left 61–120) Pin # Back Side
(right 181–240)
NC = No Connect; RFU = Reserved Future Use
Rev. 0.1 / Nov. 2009 10
Registering Clock Driver Specifications
Capacitance Values
Input & Output Timing Requirements
Symbol Parameter Conditions Min Typ Max Unit
CI
Input capacitance, Data inputs 1.5 -2.5 pF
Input capacitance, CK, CK, FBIN, FBIN 2 - 3 pF
Input capacitance, CK, CK, FBIN, FBIN
(DDR3-1600) 1.5 -2.5 pF
CIR Input capacitance, RESET, MIRROR,
QCSEN VI = VDD or GND; VDD = 1.5v --3pF
Symbol Parameter Conditions
DDR3-800
1066/1333 Unit
Min Max
fclock Input clock frequency Application frequency 300 670 Mhz
fTEST Input clock frequency Test frequency 70 300 Mhz
tSU Setup time Input valid before CK/CK 100 - ps
tHHold time Input to remain valid after CK/CK 175 - ps
tPDM Propagation delay, single-
bit switching CK/CK to output 0.65 1.0 ns
tDIS Output disable time (1/2-
Clock prelaunch) Yn/Yn to output float 0.5 tCK +
tQSK1(min) -ps
tEN Output enable time (1/2-
Clock prelaunch) Output driving to Yn/Yn 0.5 tCK -
tQSK1(max) -ps
Rev. 0.1 / Nov. 2009 11
On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal
sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.
Connection of Thermal Sensor
Temperature-to-Digital Conversion Performance
Parameter Condition Min Typ Max Unit
Temperature Sensor Accuracy (Grade B)
Active Range,
75°C < TA < 95°C -± 0.5 ± 1.0 °C
Monitor Range,
40°C < TA < 125°C -± 1.0 ± 2.0 °C
-20°C < TA < 125°C -± 2.0 ± 3.0 °C
Resolution 0.25 °C
EVENT
SCL
SDA
SA0
SA1
SA2
EVENT
SCL
SDA
SA0
SA1
SA2
SPD with
Integrated
TS
Rev. 0.1 / Nov. 2009 12
Functional Block Diagram
1GB, 128Mx72 Module(1Rank of x8)
CB[7:0]
DQS8
DQS8
DM8/DQS17
DQS17
RRASA
RCASA
RS0A
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[N:O]A
Vtt
DQ[31:24]
DQS3
DQS3
DM3/DQS12
DQS12
DQ[23:16]
DQS2
DQS2
DM2/DQS11
DQS11
DQ[15:8]
DQS1
DQS1
DM1/DQS10
DQS10
DQ[7:0]
DQS0
DQS0
DM0/DQS9
DQS9
DQS
DQS
TDQS
TDQS
D8
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D3
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D2
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D1
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D0
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A
[N
:O]/BA[N:O]
DQ[39:32]
DQS4
DQS4
DM4/DQS13
DQS13
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
Vtt
DQ[47:40]
DQS5
DQS5
DM5/DQS14
DQS14
DQ[55:48]
DQS6
DQS6
DM6/DQS15
DQS15
DQ[63:56]
DQS7
DQS7
DM7/DQS16
DQS16
DQS
DQS
TDQS
TDQS
D4
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
TDQS
TDQS
D5
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D6
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D7
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
/BA[N:O]A
/BA[N:O]B
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→
CS0: SDRAMs D[3:0], D8
RS0B
→
CS0: SDRAMs D[7:4]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[3:0], D8
RRASA
→
RAS: SDRAMs D[7:4]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[7:4]
RA[N:0]A
→
A[N:0]: SDRAMs D[7:4]
RA[N:0]A
→
A[N:0]: SDRAMs D[3:0], D8
RRASA
→
RAS: SDRAMs D[3:0], D8
RCASA
→
CAS: SDRAMs D[7:4]
RCASA
→
CAS: SDRAMs D[3:0], D8
RWEA
→
WE: SDRAMs D[7:4]
RWEA
→
WE: SDRAMs D[3:0], D8
RCKE0B
→
CKE0: SDRAMs D[7:4]
RCKE0A
→
CKE0: SDRAMs D[3:0], D8
RODT0B
→
ODT0: SDRAMs D[7:4]
RODT0A
→
ODT0: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
Err_Out
OERR
RESET
RST
RST: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330
Ω
resistor to ground
1:
2
R
E
G
I
S
T
E
R
/
P
D0–D8
V
DD
V
TT
V
DDSPD
D0–D8
VREFDQ
SPD
VREFCA
V
SS
D0–D8
D0–D8
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are 240Ω±1%.For all other resistor values refer to the
appropriate wiring diagram.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
120
Ω
±
1%
CK0
CK0
120
Ω
±
1%
L
L
Rev. 0.1 / Nov. 2009 13
2GB, 256Mx72 Module(2Rank of x8) - page1
DQS
DQS
TDQS
TDQS
D17
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
RRASA
RCASA
RS0A
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[N:O]A
Vtt
/BA[N:O]
A
RS1A
PCK1A
PCK1A
RCKE1A
RODT1A
DQ[31:24]
DQS3
DQS3
DM3/DQS12
DQS12
DQS
DQS
TDQS
TDQS
D3
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D12
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQ[23:16]
DQS2
DQS2
DM2/DQS11
DQS11
DQS
DQS
TDQS
TDQS
D2
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D11
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQ[15:8]
DQS1
DQS1
DM1/DQS10
DQS10
DQS
DQS
TDQS
TDQS
D1
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D10
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQ[7:0]
DQS0
DQS0
DM0/DQS9
DQS9
DQS
DQS
TDQS
TDQS
D0
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D9
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
CB[7:0]
DQS8
DQS8
DM8/DQS17
DQS17
DQS
DQS
TDQS
TDQS
D8
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D13
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
Vtt
/BA[N:O]
B
RS1B
PCK1B
PCK1B
RCKE1B
RODT1B
DQ[47:40]
DQS5
DQS5
DM5/DQS14
DQS14
DQS
DQS
TDQS
TDQS
D5
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D14
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQ55:48]
DQS6
DQS6
DM6/DQS15
DQS15
DQS
DQS
TDQS
TDQS
D6
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D15
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQ[63:56]
DQS7
DQS7
DM7/DQS16
DQS16
DQS
DQS
TDQS
TDQS
D7
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D16
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQ[39:32]
DQS4
DQS4
DM4/DQS13
DQS13
DQS
DQS
TDQS
TDQS
D4
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
D0–D17
V
DD
D0–D17
V
TT
V
DDSPD
D0–D17
VREFDQ
Serial PD
VREFCA
V
SS
D0–D17
D0–D17
Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 15Ω±5%.
3. ZQ resistors are 240Ω±1%. For all other resistor values
refer to the appropriate wiring diagram.
4. See the wiring diagrams for all resistors associated with the
command, address and control bus.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s r equests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Rev. 0.1 / Nov. 2009 14
2GB, 256Mx72 Module(2Rank of x8) - page2
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→
CS0: SDRAMs D[3:0], D8
RS0B
→
CS0: SDRAMs D[7:4]
RS1A
→
CS1: SDRAMs D[12:9], D17
RRASB
→
RAS: SDRAMs D[7:4], D[16 :1 3]
RS1B
→
CS1: SDRAMs D[16:13]
RBA[N:0]B
→
BA[N:0]: SDRAMs D[7:4], D[16:13]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[3:0], D[ 12:8], D17
RRASA
→
RAS: SDRAMs D[3:0], D[12 :8], D17
RCASB
→
CAS: SDRAMs D[7:4], D[16:13]
RCASA
→
CAS: SDRAMs D[3:0], D[12:8], D17
RWEB
→
WE: SDRAMs D[7:4], D[16:13]
RWEA
→
WE: SDRAMs D[3:0], D[12:8], D17
RCKE0B
→
CKE0: SDRAMs D[7:4]
RCKE0A
→
CKE0: SDRAMs D[3: 0], D8
RODT0B
→
ODT0: SDRAMs D[7:4]
ROD T 0A
→
ODT0: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7 :4]
PCK0A
→
CK: SDRAMs D[3:0], D8
Err_Out
OERR
RESET RST RST: SDRAMs D[1 7 :0]
1:2
R
E
G
I
S
T
E
R
/
P
RCKE1B
→
CKE1: SDRAMs D[16:13]
RCKE1A
→
CKE1: SDRAMs D[12:9], D17
ODT1 ROD T1A
→
ODT1: SDRAMs D[16:13]
ROD T 1A
→
ODT1: SDRAMs D[12:9], D17
CKE1
RA[N:0 ]B
→
A[N:0]: SDRAMs D[7:4], D[16:1 3]
RA[N:0 ]A
→
A[N:0]: SDRAMs D[3:0], D[12:8], D17
PCK1B
→
CK: SDRAMs D[16:13]
PCK1A
→
CK: SDRAMs D[12:9], D17
PCK1B
→
CK: SDRAMs D[16:13
]
PCK1A
→
CK: SDRAMs D[12:9], D17
L
L
* S[3:2], CK1 and CK1 are NC
S[3:2] NC
120
Ω
±5%
CK1
CK1
120
Ω
±5%
Rev. 0.1 / Nov. 2009 15
2GB, 256Mx72 Module(1Rank of x4) - page1
RRASA
RCASA
RS0A
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[O:N]A
Vtt
/BA[O:N]A
CB[3:0]
DQS8
DQS8 DQS
DQS
DM
D8
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
CB[7:4]
DQS17
DQS17
VSS
DQS
DQS
DM
D17
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[27:24]
DQS3
DQS3 DQS
DQS
DM
D3
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[31:28]
DQS12
DQS12
VSS
DQS
DQS
DM
D12
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[19:16]
DQS2
DQS2 DQS
DQS
DM
D2
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ23:20]
DQS11
DQS11
VSS
DQS
DQS
DM
D11
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[11;8]
DQS1
DQS1 DQS
DQS
DM
D1
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[15:12]
DQS10
DQS10
VSS
DQS
DQS
DM
D10
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[3:0]
DQS0
DQS0 DQS
DQS
DM
D0
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[7:4]
DQS9
DQS9
VSS
DQS
DQS
DM
D9
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[O:N]B
Vtt
/BA[O:N]B
DQ[35:32]
DQS4
DQS4 DQS
DQS
DM
D4
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[39:36]
DQS13
DQS13
VSS
DQS
DQS
DM
D13
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[43:40]
DQS5
DQS5 DQS
DQS
DM
D5
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[47:44]
DQS14
DQS14
VSS
DQS
DQS
DM
D14
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[51:48]
DQS6
DQS6 DQS
DQS
DM
D6
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[55;52]
DQS15
DQS15
VSS
DQS
DQS
DM
D15
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
DQ[59:56]
DQS7
DQS7 DQS
DQS
DM
D7
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQ[63:60]
DQS16
DQS16
VSS
DQS
DQS
DM
D16
DQ [3:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
VSS
VSS
VSS
D0–D17
V
DD
D0–D17
V
TT
V
DDSPD
D0–D17
VREFDQ
SPD
VREFCA
V
SS
D0–D17
D0–D17
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15%.
3. See the wiring diagrams for all resistors associated with the com-
mand, address and control bus.
4. ZQ resistors are 240%. For all other resistor values refe r to the appro-
priate wiring diagram. Ω1±
Ω5±
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Rev. 0.1 / Nov. 2009 16
2GB, 256Mx72 Module(1Rank of x4) - page2
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→
CS0: SDRAMs D[3:0], D[12 :8 ], D17
RS0B
→
CS0: SDRAMs D[7:4], D[16:13]
RRASB
→
RAS: SDRAMs D[7:4], D[16:13]
RBA[N:0]B
→
BA[N:0]: SDRAMs D[7:4], D[16:13]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[3:0], D[12:8], D17
RRASA
→
RAS: SDRAMs D[3:0], D[12:8], D17
RCASB
→
CAS: SDRAMs D[7:4], D[16:13]
RCASA
→
CAS: SDRAMs D[3:0], D[12:8], D17
RWEB
→
WE: SDRAMs D[7:4], D[16:13]
RWEA
→
WE: SDRAMs D[3:0], D[12:8], D17
RCKE0B
→
CKE0: SDRAMs D[7:4], D[16:13]
RCKE0A
→
CKE0: SDRAMs D[3:0], D[12:8], D17
RODT0B
→
ODT0: SDRAMs D[7:4], D[16:13]
RODT0A
→
ODT0: SDRAMs D[3:0], D[12:8]. D17
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
Err_Out
OERR
RESET RST RST: SDRAMs D[17:0]
1:2
R
E
G
I
S
T
E
R
/
P
RA[N:0]B
→
A[N:0]: SDRAMs D[7:4], D[16:13]
RA[N:0]A
→
A[N:0]: SDRAMs D[3:0], D[12:8], D17
L
L
* S[3:2], CKE1, ODT1, CK1 and CK1 are NC (Unused regist er in pu ts ODT1 and C KE1 have a 330 resistor to grou n d.)
Ω
RS1A
→
CS1: SDRAMs D[12:9], D17
RS1B
→
CS1: SDRAMs D[16:13]
Rev. 0.1 / Nov. 2009 17
4GB, 512Mx72 Module(2Rank of x4) - page1
RRASA
RCASA
RS0A
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[O:N]A
/BA[O:N]A
CB[7:4]
DQS17
DQS17 DQS
DQS
DM
D17
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D35
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[31:28]
DQS12
DQS12 DQS
DQS
DM
D12
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
D30
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[23:20]
DQS11
DQS11 DQS
DQS
DM
D11
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D29
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[15:12]
DQS10
DQS10 DQS
DQS
DM
D10
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D28
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[3:0]
DQS0
DQS0 DQS
DQS
DM
D0
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D18
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
Vtt
CB[3:0]
DQS8
DQS8 DQS
DQS
DM
D8
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D26
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[27:24]
DQS3
DQS3 DQS
DQS
DM
D3
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
D21
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[19:16]
DQS2
DQS2 DQS
DQS
DM
D2
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D20
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[11:8]
DQS1
DQS1 DQS
DQS
DM
D1
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D19
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[7:4]
DQS9
DQS9 DQS
DQS
DM
D9
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D27
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
RS1A
RCKE1A
R0DT1A
DM DM
Vtt
RRASA
RCASA
RS0A
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[O:N]A
/BA[O:N]A
RS1A
RCKE1A
R0DT1A
PCK1A
PCK1A
PCK1A
PCK1A
Rev. 0.1 / Nov. 2009 18
4GB, 512Mx72 Module(2Rank of x4) - page2
D0–D35
V
DD
D0–D35
V
TT
V
DDSPD
D0–D35
VREFDQ
SPD
VREFCA
V
SS
D0–D35
D0–D35
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for all resistors values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
/BA[N:O]B
DQ[47:44]
DQS14
DQS14 DQS
DQS
DM
D14
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D32
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQS4
DQS4 DQS
DQS
DM
D4
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
D22
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQS16
DQS16 DQS
DQS
DM
D16
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D34
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQS7
DQS7 DQS
DQS
DM
D7
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D25
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
Vtt
DQ[39:36]
DQS13
DQS13 DQS
DQS
DM
D13
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D31
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[43:40]
DQS5
DQS5 DQS
DQS
DM
D5
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
D23
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[55:52]
DQS15
DQS15 DQS
DQS
DM
D15
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D33
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
DQ[51:48]
DQS6
DQS6 DQS
DQS
DM
D6
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
DM
D24
DQ [3:0]
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
VSS
RS1B
RCKE1B
R0DT1B
DM DM
Vtt
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
/BA[N:O]B
RS1B
RCKE1B
R0DT1B
PCK1B
PCK1B
PCK1B
PCK1B
DQ[35:32]
DQ[63:60]
DQ[59:56]
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’ s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
Rev. 0.1 / Nov. 2009 19
4GB, 512Mx72 Module(2Rank of x4) - page3
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→
CS0: SDRAMs D[3:0], D[12:8], D17
RS0B
→
CS0: SDRAMs D[7:4] , D[1 6 :13 ]
RS1A
→
CS1: SDRAMs D[21:18], D[30:26], D35
RRASB
→
RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RS1B
→
CS1: SDRAMs D[25:22], D[34:31]
RBA[N:0]B
→
BA[N:0]: SDRAMs D[7:4 ] , D[ 16 :1 3] , D[25 :2 2] , D[34:31]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASA
→
RAS: SDRAMs D[3:0], D[12 :8], D[21:17], D[30:2 6] , D35
RCASB
→
CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA
→
CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB
→
WE: SDRAMs D[7:4], D[16:13] , D[25:22], D[34:31]
RWEA
→
WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCKE0B
→
CKE0: SDRAMs D[7:4], D[16:13]
RCKE0A
→
CKE0: SDRAMs D[3:0], D[12:8], D17
RODT0B
→
ODT0: SDRAMs D[7:4], D[16:13]
ROD T 0A
→
ODT0: SDRAMs D[3:0], D[12:8], D17
PCK0B
→
CK: SDRAMs D[7:4], D[16:13]
PCK0A
→
CK: SDRAMs D[3:0], D[12:8], D17
PCK0B
→
CK: SDRAMs D[7:4], D[ 16 :1 3]
PCK0A
→
CK: SDRAMs D[3:0], D[12:8], D17
Err_Out
RESET RST RST: SDRAMs D[3 5 :0]
1:2
R
E
G
I
S
T
E
R
/
P
RCKE1B
→
CKE1: SDRAMs D[25:22], D[34:31]
RCKE1A
→
CKE1: SDRAMs D[21:18], D[30:26], D35
ODT1 ROD T1A
→
ODT1: SDRAMs D[25:22], D[34:3 1]
ROD T 1A
→
ODT1: SDRAMs D[21:18], D[30:26], D35
CKE1
RA[N:0 ]B
→
A[N:0]: SDRAMs D[7:4], D[16:13], D[ 25 :2 2 ], D[34:3 1 ]
RA[N:0 ]A
→
A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
PCK1B
→
CK: SDRAMs D[25:22], D[ 34 :3 1]
PCK1A
→
CK: SDRAMs D[21:18] , D[ 30 :2 6] , D3 5
PCK1B
→
CK: SDRAMs D[25:22], D[34:31]
PCK1A
→
CK: SDRAMs D[21:1 8] , D[ 30 :2 6 ], D35
L
L
* S[3:2], CK1 and CK1 are NC
CK1
CK1
120
Ω
±5%
Rev. 0.1 / Nov. 2009 20
4GB, 512Mx72 Module(4Rank of x8) - page1
WRAS
WCAS
CS0
WWE
PCK0
PCK0
WCKE0
WODT0
WA[N:0]
Vtt
WBA[N:0]
DQ[7:0]
DQS0
DQS0
DM0/TDQS9
TDQS9
DQS
DQS
TDQS
TDQS
U2
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CS1
PCK0
PCK0
WCKE01
VDD
DQS
DQS
TDQS
TDQS
U11
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CS2
PCK2
PCK2
WCKE0
WODT1
DQS
DQS
TDQS
TDQS
U20
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CS3
PCK2
PCK2
WCKE1
VDD
DQS
DQS
TDQS
TDQS
U29
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQ[15:8]
DQS1
DQS1
DM1/TDQS10
TDQS10
DQS
DQS
TDQS
TDQS
U3
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U12
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U21
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U30
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQ[32:16]
DQS2
DQS2
DM2/TDQS11
TDQS11
DQS
DQS
TDQS
TDQS
U4
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U13
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U22
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U31
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQ[31:24]
DQS3
DQS3
DM3/TDQS12
TDQS12
DQS
DQS
TDQS
TDQS
U5
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U14
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U23
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U32
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CB[7:0]
DQS8
DQS8
DM8/TDQS17
TDQS17
DQS
DQS
TDQS
TDQS
U6
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U15
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U24
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U33
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
Rev. 0.1 / Nov. 2009 21
4GB, 512Mx72 Module(4Rank of x8) - page2
WRAS
WCAS
CS0
WWE
PCK0
PCK0
WCKE0
WODT0
WA[N:0]
WBA[N:0]
DQ[39:32]
DQS4
DQS4
DM4/TDQS13
TDQS13
DQS
DQS
TDQS
TDQS
U7
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CS1
PCK0
PCK0
WCKE01
VDD
DQS
DQS
TDQS
TDQS
U16
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CS2
PCK2
PCK2
WCKE0
WODT1
DQS
DQS
TDQS
TDQS
U25
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
CS3
PCK2
PCK2
WCKE1
VDD
DQS
DQS
TDQS
TDQS
U34
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQ[47:40]
DQS5
DQS5
DM5/TDQS14
TDQS14
DQS
DQS
TDQS
TDQS
U8
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U17
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U26
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U35
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQ[55:48]
DQS6
DQS6
DM6/TDQS15
TDQS15
DQS
DQS
TDQS
TDQS
U9
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U18
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U27
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U36
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQ[31:24]
DQS3
DQS3
DM3/TDQS12
TDQS12
DQS
DQS
TDQS
TDQS
U10
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U19
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U28
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
DQS
DQS
TDQS
TDQS
U37
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]
BA[N:O]
Vtt
U1-U37
V
DD
V
TT
V
DDSPD
U1-U37
V
REFDQ
Serial PD
V
REFCA
V
SS
U1–U37
U1-U37
Notes:
1. DQ-to-I/O wiring may be changed within a byte.
2. See wiring diagrams for resistor values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Ther mal sensor, please contact
local Hynix sales representative
Rev. 0.1 / Nov. 2009 22
4GB, 512Mx72 Module(4Rank of x8) - page3
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
CS0
→
CS0: SDRAMs U[10:2]
CS1
→
CS1: SDRAMs U[19:11]
CS2
→
CS2: SDRAMs U[28:20]
ERAS
→
RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34 ]
CS3
→
CS3: SDRAMs U[37:29]
EBA[N:0]
→
BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WBA[N:0]
→
BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
WRAS
→
RAS: SDRAMs U[6:2], U[15:11], U[24 :2 0 ], U[33:2 9]
ECAS
→
CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37 :3 4 ]
WCAS
→
CAS: SDRAMs U[6:2], U[15:11] , U[24:20], U[33:29]
EWE
→
WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WWE
→
WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29 ]
ECKE0
→
CKE0: SDRAMs U[10:7], U[28:25]
WCKE0
→
CKE0: SDRAMs U[6:2], U[24:20]
EODT0
→
ODT0: SDRAMs U[10:7]
WODT0
→
ODT0: SDRAMs U[6:2]
PCK1
→
CK: SDRAMs U[10:7], U[28:25]
PCK0
→
CK: SDRAMs U[6:2], U[15:11]
PCK1
→
CK: SDRAMs U[10:7], U[28:25]
PCK0
→
CK: SDRAMs U[6: 2] , U[15:11]
Err_Out
RESET RST RST: SDRA M s U[37:2]
1:2
R
E
G
I
S
T
E
R
/
P
ECKE1
→
CKE1: SDRAMs U[19:16] , U[ 37 :3 4]
WCKE1
→
CKE1: SDRAMs U[15:11], U[33:29]
ODT1 EODT0
→
ODT1: SDRAMs U[28:25]
WODT0
→
ODT1: SDRAMs U[24:20]
CKE1
EA[N:0]
→
A[N:0]: SDRAMs U[10:7], U[19:16 ] , U[ 28 :2 5] , U[ 37 :3 4]
WA [N:0]
→
A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
PCK3
→
CK: SDRAMs U[19:16], U[37:34 ]
PCK2
→
CK: SDRAMs U[24:20], U[33:29 ]
PCK3
→
CK: SDRAMs U[19:16], U[37:34]
PCK2
→
CK: SDRAMs U[24:20], U[33:29]
L
L
CK1
CK1
120
Ω
±5%
S2
S3
Rev. 0.1 / Nov. 2009 23
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reli ability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temper ature R ange.
Please refer to the DIMM SPD for option availability
b. Hynix DDR3L SDRAMs support Auto Self -R efr esh and Extended Temper ature R ange and please ref er to Hynix
component datasheet and/or the DIMM SPD for tREFI requirement in the Extended Temperature Range.
Absolute Maximum DC Ratings
Symbol Parameter Rating Units Notes
VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1,
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1,
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V 1
TSTG Storage Temperature -55 to +100 oC1, 2
Temperature Range
Symbol Parameter Rating Units Notes
TOPER Normal Operating Temperature Range 0 to 85 oC 1,2
Extended Temperature Range 85 to 95 oC1,3
Rev. 0.1 / Nov. 2009 24
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.283 1.35 1.45 V 1,2,3,4
VDDQ Supply Voltage for Output 1.283 1.35 1.45 V 1,2,3,4
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3L specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
Symbol Parameter Rating Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2,3
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2,3
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 0.1 / Nov. 2009 25
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
Ta
CK,CK#
RESET#
Tb Tc Td Te Tf Tg Th Ti Tj Tk
MRS1) 1)MRS MRS
CKE
DON’T CARE
READ MRS
T = 500us
COMMAND
ODT
BA
RTT
MR3 MR1 MR0READ MR2
READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
ZQCL VALID
VALID
VALID
VALID
Tmin = 200us
Tmin = 10ns
Tmin = 10ns tCKSRX
Tmin = 10ns
tIS
tIS tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
tDLLK
TIME BREAK
Rev. 0.1 / Nov. 2009 26
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Signal-Ended Command and Address Signals
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 39.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for
reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. There lev els apply fo r 1.35 volt (see t able above) oper a tion only. If the device is operate d at 1.5V (table
“Single Ended AC and DC Input Levels for DQ and DM” on page 27), the respective levels in JESD79-3
(VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) apply. The 1.5V levels (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when the device is operated in the 1.35 voltage
range.
Single Ended AC and DC Input Levels for Command and Address
Symbol Parameter DDR3L-800/1066/1333 Unit Notes
Min Max
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD V 1
VIL.CA(DC90) DC input logic low VSS Vref - 0.09 V 1
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 V 1, 2
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 V 1, 2
VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 V 1, 2
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 V 1, 2
VRefCA(DC)Reference Voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4
Rev. 0.1 / Nov. 2009 27
AC and DC Input Levels for Signal-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in t able below.
DDR3 SDRAM will also support corresponding tDS values (Table 41 on page 120 and Table 47on page 145
in “DDR3L Device Operation”) as well as derating tables Table 44 on page 139 in “DDR3L Device Opera-
tion” depending on Vih/Vil AC levels.
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 39.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for
reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. There levels apply for 1.35 volt (table above) oper ation only. If the device is operated at 1.5V (See table
above), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.)
apply. The 1.5V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when
the device is operated in the 1.35 voltage range.
Single Ended AC and DC Input Levels for DQ and DM
Symbol Parameter DDR3L-800/1066 DDR3L-1333 Unit Notes
Min Max Min Max
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD V 1
VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 V 1
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 - - V 1, 2,5
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 - - V 1, 2,5
VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2,5
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1, 2,5
VRefDQ(DC)Reference Voltage for DQ,
DM inputs 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4
Rev. 0.1 / Nov. 2009 28
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in
figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and
VRefDQ likewise).
VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table “Differential Input Slew Rate Definition” on page 34. Further-
more VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
Illustration of VRef(DC) tolerance and VRef ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are depen-
dent on VRef.
“VRef” shall be understood as VRef(DC), as defined in figure above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
VDD
VSS
VDD/2
VRef(DC)
VRef ac-noise
voltage
time
VRef(DC)max
VRef(DC)min
VRef(t)
Rev. 0.1 / Nov. 2009 29
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
Definition of differential ac-swing and “time above ac-level” tDVAC
time
Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
V
IL.DIFF.AC.MAX
V
IL.DIFF.MAX
0
V
IL.DIFF.MIN
V
IL.DIFF.AC.MIN
t
DVAC
half cycle
t
DVAC
Rev. 0.1 / Nov. 2009 30
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD an d VREFCA; for DQS - DQS, D QSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 39.
Differential AC and DC Input Levels
Symbol Parameter DDR3L-800, 1066, 1333 Unit Notes
Min Max
VIHdiff Differential input high + 0.180 Note 3 V 1
VILdiff Differential input logic low Note 3 - 0.180 V 1
VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2
VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns] tDVAC [ps]
@ |VIH/Ldiff (ac)| = 350mV tDVAC [ps]
@ |VIH/Ldiff (ac)| = 300mV
min max min max
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
Rev. 0.1 / Nov. 2009 31
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has
also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-lev els apply also for the single-
ended signals CK and CK.
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differ ential signals the r equirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
VDD or VDDQ
VSEHmin
VDD/2 or VDDQ/2
VSEH
VSELmax
VSS or VSSQ
CK or DQS
VSEL
time
Rev. 0.1 / Nov. 2009 32
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 39.
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Symbol Parameter DDR3L-800, 1066, 1333 Unit Notes
Min Max
VSEH Single-ended high level for strobes (VDD / 2) + 0.175 Note 3 V1,2
Single-ended high level for Ck, CK (VDD /2) + 0.175 Note 3 V1,2
VSEL Single-ended low level for strobes Note 3 (VDD / 2) = 0.175 V1,2
Single-ended low level for CK, CK Note 3 (VDD / 2) = 0.175 V1,2
Rev. 0.1 / Nov. 2009 33
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross poi nt voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Notes:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the different ial
slew rate of CK - CK is larger than 3 V/ns.
2. Ref er to the table “Single-ended levels f or CK, DQS , DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 32
for VSEL and VSEH standard values
Cross point voltage for differential input signals (CK, DQS)
Symbol Parameter DDR3L-800, 1066, 1333 Unit Notes
Min Max
VIX Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK -150 150 mV
-175 175 mV 1
VIX Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS -150 150 mV
VDD
VSS
VDD/2
VIX
VIX
VIX
CK, DQS
CK, DQS
Rev. 0.1 / Nov. 2009 34
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Der a ting” on page 138 in “D DR3L Device Operation” for sin-
gle-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 145 in “DDR3L Device Operation” for single-
ended slew rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew r ate for diff erential signals (CK, CK and DQS, DQS) ar e defined and measured as shown in table
and figure below.
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Differential Input Slew Rate Definition
Description Measured Defined by
Min Max
Diffe rential input slew rate for rising edge
(CK-CK and DQS-DQS)VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
Delta
TFdiff
Delta
TRdiff
vIHdiffmin
vILdiffmax
0
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Rev. 0.1 / Nov. 2009 35
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Notes:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low
swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Notes:
1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low
swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
Single-ended AC and DC Output Levels
Symbol Parameter DDR3L-800, 1066,
1333 Unit Notes
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V1
Differential AC and DC Output Levels
Symbol Parameter DDR3L-800, 1066,
1333 Unit Notes
VOHdiff (AC) AC differential output high measurement level (for output SR) + 0.2 x VDDQ V1
VOLdiff (AC) AC differential output low measurement level (for output SR) - 0.2 x VDDQ V1
Rev. 0.1 / Nov. 2009 36
Single Ended Output Slew Rate
When the Refer ence load for timing measurement s, output slew rate for f alling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Single Ended Output slew Rate Definition
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZ Q/7 setting
Note 1): In two cases, a maximum slew rate of 6 V/ns applies for a single DQ signal within a byte lane.
Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction
(either from high to low or low to high) while all remaining DQ signals in the same byte lane are static(i.e
they stay at either high or low).
Case_2 is defined for a single DQ signal within a byte lane which is switching into a certain direction
(either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching
into the opposite direction (i.e from low to high or high to low respectively). For the remaining DQ signal
switching into the opposite direc tion, the regul ar maximum limit of 5 V/ns applies.
Single-ended Output slew Rate Definition
Description Measured Defined by
From To
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse
Output Slew Rate (single-ended)
DDR3L-800 DDR3L-1066 DDR3L-1333 Units
Parameter Symbol Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 1.75 51) 1.75 51) 1.75 51) V/ns
Delta TFse
Delta TRse
vOH(AC)
vOl(AC)
V∏
Single Ended Output Voltage(l.e.DQ)
Single Ended Ou tput S lew R ate D e finition
Rev. 0.1 / Nov. 2009 37
Differential Output Slew Rate
With the reference load for timing measurements, output sle w rate for fa lling and rising edges is defined
and measured between VOLdiff (AC) and VOHdif f (AC) f or dif f erential signals as shown in table and figure
below.
Differential Output slew Rate Definition
Differential Output Slew Rate Definition
Description Measured Defined by
From To
Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Slew Rate
DDR3L-800 DDR3L-1066 DDR3L-1333 Units
Parameter Symbol Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 3.5 12 3.5 12 3.5 12 V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZ Q/7 setting
Delta
TFdiff
Delta
TRdiff
vOHdiff(AC)
vOLdiff(AC)
O
Different i al Output Voltage ( i.e. DQS-DQS )
Differential Output Slew Rate Definition
Rev. 0.1 / Nov. 2009 38
Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference l oad of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
Reference Load for AC Timing and Output Slew Rate
DUT DQ
DQS
DQS
VDDQ
25 Oh m VTT = VDDQ/2
CK, CK
Rev. 0.1 / Nov. 2009 39
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Definition
AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter DDR3L-
800
DDR3L-
1066
DDR3L-
1333 Units
Maximum peak amplitude allowed for overshoot area. (See figure below) 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See figure below) 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See figure below) 0.67 0.5 0.4 V-ns
Maximum undershoot area below VSS (See figure below) 0.67 0.5 0.4 V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT )
Maximum Amplitude
Overshoot Area
VDD
VSS
Maximum Amplitude Undershoot Area
Time (ns)
Address and Control Overshoot and Undershoot Definition
Volts
(V)
Rev. 0.1 / Nov. 2009 40
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter DDR3L-
800
DDR3L-
1066
DDR3L-
1333 Units
Maximum peak amplitude allowed for overshoot area. (See figure below) 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See figure below) 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See figure below ) 0.25 0.19 0.15 V-ns
Maximum undershoot area below VSS (See figure below) 0.25 0.19 0.1 5 V-ns
(CK, CK, DQ, DQS, DQS, DM)
Maximum Amplitude
Overshoot Area
VDDQ
VSSQ
Maximum Amplitude Undershoot Area
Time (ns)
Clock, Data Strobe and Mask Overshoot and Undershoot Definition
Volts
(V)
Rev. 0.1 / Nov. 2009 41
Refresh parameters by device density
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
Refresh parameters by device density
Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units
REF command ACT or
REF command time tRFC 90 110 160 300 350 ns
Average periodic
refresh interval tREFI 0 °C ≤ TCASE ≤ 85 °C7.87.87.87.87.8us
85 °C < TCASE ≤ 95 °C3.93.93.93.93.9us
For specific Notes See “Speed Bin Table Notes” on page 44.
Speed Bin DDR3-800E Unit Notes
CL - nRCD - nRP 6-6-6
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to intern a l re ad or write delay time tRCD 15 — ns
PRE command period tRP 15 — ns
ACT to ACT or REF command period tRC 52.5 — ns
ACT to PRE command period tRAS 37.5 9 * tREFI ns
CL = 5 CWL = 5 tCK(AVG) Reserved ns 1, 2, 3, 4
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1, 2, 3
Supported CL Settings 6nCK
Supported CWL Settings 5nCK
Rev. 0.1 / Nov. 2009 42
DDR3L-1066 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 44.
Speed Bin DDR3-1066F Unit Note
CL - nRCD - nRP 7-7-7
Parameter Symbol min max
Internal read command to
first data
t
AA 13.125 20 ns
ACT to internal read or
write delay time
t
RCD 13.125 — ns
PRE command period
t
RP 13.125 — ns
ACT to ACT or REF
command period
t
RC 50.625 — ns
ACT to PRE command
period
t
RAS 37.5 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) Reserved ns 1, 2, 3, 4, 5
CWL = 6
t
CK(AVG) Reserved ns 4
CL = 6 CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 5
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 7 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4
CL = 8 CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3
Supported CL Settings 6, 7, 8
n
CK
Supported CWL Settings 5, 6
n
CK
Rev. 0.1 / Nov. 2009 43
DDR3L-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 44.
Speed Bin DDR3L-1333H Unit Note
CL - nRCD - nRP 9-9-9
Parameter Symbol min max
Internal read command
to first data
t
AA 13.5
(13.125)8 20 ns
ACT to internal read or
write delay time
t
RCD 13.5
(13.125)8 —ns
PRE command period
t
RP 13.5
(13.125)8 —ns
ACT to ACT or REF
command period
t
RC 49.5
(49.125)8 —ns
ACT to PRE command
period
t
RAS 36 9 * tREFI ns
CL = 5 CWL = 5
t
CK(AVG) Reserved ns 1,2, 3,4, 6
CWL = 6, 7
t
CK(AVG) Reserved ns 4
CL = 6
CWL = 5
t
CK(AVG) 2.5 3.3 ns 1, 2, 3, 6
CWL = 6
t
CK(AVG) Reserved ns 1, 2, 3, 4, 6
CWL = 7
t
CK(AVG) Reserved ns 4
CL = 7
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 4, 6
Reserved
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 8
CWL = 5
t
CK(AVG) Reserved ns 4
CWL = 6
t
CK(AVG) 1.875 < 2.5 ns 1, 2, 3, 6
CWL = 7
t
CK(AVG) Reserved ns 1, 2, 3, 4
CL = 9 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3, 4
CL = 10 CWL = 5, 6
t
CK(AVG) Reserved ns 4
CWL = 7
t
CK(AVG) 1.5 <1.875 ns 1, 2, 3
Reserved ns
Supported CL Settings 6, 8, (7), 9, (10)
n
CK
Supported CWL Settings 5, 6, 7
n
CK
Rev. 0.1 / Nov. 2009 44
Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(A VG).MAX requirements. When making
a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements
from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - dat a and str o be output ar e synchro niz ed
by the DLL - all possib le intermediate frequencies may not be guaranteed. An application should use the
next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] =
tAA [ns] / tCK (AVG) [ns], rounding up to the next ‘Supported CL’.
3. tCK(A VG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (A VG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX
corresponding to CLSE LECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. Any DDR3L-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
6. Any DDR3L-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3L-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Hynix DDR3L SDRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy mini-
mum value of 13.125ns.SPD settings are also programmed to match. For example, DDR3L 1333H devices
supporting down binning to DDR3L-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16),
tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3L-1600K devices supporting down binning to DDR3L-
1333H or DDR3L 1600F should program 13.125 ns in SP D bytes for tAA min (Byte 16), tRCDmin (Byte 18),
and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should
be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3L-
1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3L-1600K.
Rev. 0.1 / Nov. 2009 45
Environmental Parameters
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only,
and device functional operation at or above the conditions indicated is not implied. Expousure to absolute
maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Symbol Parameter Rating Units Notes
TOPR Operating temperature See Note 3
HOPR Operating humidity (relative) 10 to 90 % 1
TSTG Storage temperature -50 to +100 oC1
HSTG Storage humidity (without condensation) 5 to 95 % 1
PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2
Rev. 0.1 / Nov. 2009 46
Pin Capacitance (VDD=1.35V, VDDQ=1.35V)
1GB: HMT112R7BFR8A
2GB: HMT125R7BFR8A
2GB: HMT125R7BFR4A
4GB: HMT151R7BFR4A
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
Rev. 0.1 / Nov. 2009 47
4GB: HMT151R7BFR8A
Note:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Pin Symbol Min Max Unit
CK0, CK0CCK TBD TBD pF
CKE, ODT, CS CCTRL TBD TBD pF
Address, RAS, CAS, WE CITBD TBD pF
DQ, DM, DQS, DQS CIO TBD TBD pF
Rev. 0.1 / Nov. 2009 48
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measur ement condit ions such as test load and patterns are defined. F igur e
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all
VDD balls of the DDR3L SDRAM under test tied together. Any IDDQ current is not included in IDD cur-
rents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3L SDRAM under test tied together. Any IDD current is not included in IDDQ
currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3L SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= VILAC(max).
• ”1” and “HIGH” is defined as VIN >= VIHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3L SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 0.1 / Nov. 2009 49
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
VDD
DDR3L
SDRAM
VDDQ
RESET
CK/CK
DQS, DQS
CS
RAS, CAS, WE
A, BA
ODT
ZQ VSS VSSQ
DQ, DM,
TDQS, TDQS
CKE RTT = 25 OhmVDDQ/2
IDD IDDQ (optional)
Application specific
memory channel
environment
Channel
IO Power
Simulation IDDQ
Simulation
IDDQ
Simulation
Channel IO Power
Number
IDDQ
Test Load
Correction
Rev. 0.1 / Nov. 2009 50
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol DDR3L-1066 DDR3L-1333 Unit
7-7-7 9-9-9
t
CK 1.875 1.5 ns
CL 7 9 nCK
n
RCD 79nCK
n
RC 27 33 nCK
n
RAS 20 24 nCK
n
RP 79nCK
n
FAW 1KB page size 20 20 nCK
2KB page size 27 30 nCK
n
RRD 1KB pag e size 4 4 nCK
2KB page size 6 5 nCK
n
RFC -512Mb 48 60 nCK
n
RFC-1 Gb 59 74 nCK
n
RFC- 2 Gb 86 107 nCK
n
RFC- 4 Gb 160 200 nCK
n
RFC- 8 Gb 187 234 nCK
Symbol Description
I
DD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
I
DD1
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); A L: 0; CS : High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active a t a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 0.1 / Nov. 2009 51
I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I
DDQ2NT
(optional)
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow
Exitc)
I
DD2P1
Precharge Power-Down C u rrent Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and R T T: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit c)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: st able at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Outp ut Buffer and RTT: Enabled in Mode Registersb); ODT S ignal: stable at 0; Pattern Details: see
Table 5.
Symbol Description
Rev. 0.1 / Nov. 2009 52
I
DD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID _LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
I
DDQ4R
(optional)
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
I
DD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: s table at 0 ; Bank Activity: all banks ope n,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
I
DD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: s table at 0 ; Bank Activity: all banks ope n,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
I
DD5B
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
I
DD6
Self-Refresh Current: Normal Temperature Range
T
CASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Ra nge (SRT): Normale); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Symbol Description
Rev. 0.1 / Nov. 2009 53
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature
range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
I
DD6ET
Self-Refresh Current: Extended Temperature Range
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
I
DD6TC
Auto Self-Refresh Current
T
CASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
I
DD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a)f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
Symbol Description
Rev. 0.1 / Nov. 2009 54
Table 3 - IDD0 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1111000000 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3, 4 D, D 1111000000 F 0 -
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern 1...4 until 2*nRC - 1, trun cate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
Rev. 0.1 / Nov. 2009 55
Table 4 - IDD1 Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-
LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00ACT001100000000 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 111100000000 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE001000000000 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
1*nRC+3,4 D, D 1111000000F0 -
... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead
Rev. 0.1 / Nov. 2009 56
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D1111000 0 0 F0 -
3D
1111000 0 0 F0 -
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead
2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead
3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead
4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead
5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead
6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead
7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00D10000000000 -
1D10000000000-
2D1111000 0 0 F0 -
3D
1111000 0 0 F0 -
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
Rev. 0.1 / Nov. 2009 57
Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1D100000000000-
2,3 D,D 111100000 0 00 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5D1000000000F0-
6,7 D,D 111100000 0 F0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1D100010000000-
2,3 D,D 111110000 0 00 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5D1000100000F0-
6,7 D,D 111110000 0 F0 -
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1
2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2
3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3
4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4
5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5
6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6
7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7
Rev. 0.1 / Nov. 2009 58
Table 9 - IDD5B Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
00REF 0 0 0 1 0 0 0 0 0 0 0 -
11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 111100000 0 F0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
9...12 repeat cycles 1...4, but BA[2:0] = 2
13...16 repeat cycles 1...4, but BA[2:0] = 3
17...20 repeat cycles 1...4, but BA[2:0] = 4
21...24 repeat cycles 1...4, but BA[2:0] = 5
25...28 repeat cycles 1...4, but BA[2:0] = 6
29...32 repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Rev. 0.1 / Nov. 2009 59
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
CK, CK
CKE
Sub-Loop
Cycle
Number
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
toggling
Static High
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
22*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
33*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
44*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
Assert and repeat above D Command until nFAW - 1, if necessary
5nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
9nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Assert and repeat above D Command until 2* nFAW - 1, if necessary
10
2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
2&nFAW+2 D 1 0 0 0 0 0 00 0 0 F 0 -
Repeat above D Command unti l 2* nFAW + nRRD - 1
11
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
2&nFAW+nRRD+2 D 1 0 0 0 0 1 00 0 0 0 0 -
Repeat above D Command unti l 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
14 2*nFAW+4*nRRD D 1 0 0 0 0 3 00 0 0 0 0 -
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, bu t BA[2:0] = 5
17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
19 3*nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 0 0 -
Assert and repeat above D Command until 4* nFAW - 1, if necessary
Rev. 0.1 / Nov. 2009 60
IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.
The actual measurements may vary according to DQ loading cap.
1GB, 128M x 72 R-DIMM: HMT112R7BFR8A
2GB, 256M x 72 R-DIMM: HMT125R7BFR8A
Symbol DDR3L 1066 DDR3L 13 33 Unit note
IDD0 1124 1169 mA
IDD1 1304 1349 mA
IDD2N 1034 1079 mA
IDD2NT 1079 1124 mA
IDD2P0 318 318 mA
IDD2P1 408 408 mA
IDD2Q 1034 1079 mA
IDD3N 1079 1124 mA
IDD3P 408 453 mA
IDD4R 1529 1619 mA
IDD4W 1529 1619 mA
IDD5B 1934 1979 mA
IDD6 318 318 mA
IDD6ET 336 336 mA
IDD6TC 336 336 mA
IDD7 1889 2159 mA
Symbol DDR3L 1066 DDR3L 13 33 Unit note
IDD0 1394 1484 mA
IDD1 1574 1664 mA
IDD2N 1304 1394 mA
IDD2NT 1394 1484 mA
IDD2P0 408 408 mA
IDD2P1 588 588 mA
IDD2Q 1304 1394 mA
IDD3N 1394 1484 mA
IDD3P 588 678 mA
IDD4R 1799 1934 mA
IDD4W 1799 1934 mA
IDD5B 2204 2294 mA
IDD6 408 408 mA
IDD6ET 444 444 mA
IDD6TC 444 444 mA
IDD7 2159 2474 mA
Rev. 0.1 / Nov. 2009 61
2GB, 256M x 72 R-DIMM: HMT125R7BFR4A
4GB, 512M x 72 R-DIMM: HMT151R7BFR4A
Symbol DDR3L 1066 DDR3L 13 33 Unit note
IDD0 1484 1574 mA
IDD1 1844 1934 mA
IDD2N 1304 1394 mA
IDD2NT 1394 1484 mA
IDD2P0 408 408 mA
IDD2P1 588 588 mA
IDD2Q 1304 1394 mA
IDD3N 1394 1484 mA
IDD3P 588 678 mA
IDD4R 2294 2474 mA
IDD4W 2294 2474 mA
IDD5B 3104 3194 mA
IDD6 408 408 mA
IDDET 444 444 mA
IDD6TC 444 444 mA
IDD7 3014 3554 mA
Symbol DDR3L 1066 DDR3L 13 33 Unit note
IDD0 2024 2204 mA
IDD1 2384 2564 mA
IDD2N 1844 2024 mA
IDD2NT 2024 2204 mA
IDD2P0 588 588 mA
IDD2P1 948 948 mA
IDD2Q 1844 2024 mA
IDD3N 2024 2204 mA
IDD3P 948 1128 mA
IDD4R 2834 3104 mA
IDD4W 2834 3104 mA
IDD5B 3644 3824 mA
IDD6 588 588 mA
IDDET 660 660 mA
IDD6TC 660 660 mA
IDD7 3554 4184 mA
Rev. 0.1 / Nov. 2009 62
4GB, 512M x 72 R-DIMM: HMT151R7BFR8A
Symbol DDR3L 1066 DDR3L 13 33 Unit note
IDD0 1934 2114 mA
IDD1 2114 2294 mA
IDD2N 1844 2024 mA
IDD2NT 2024 2204 mA
IDD2P0 588 588 mA
IDD2P1 948 948 mA
IDD2Q 1844 2024 mA
IDD3N 2024 2204 mA
IDD3P 948 1128 mA
IDD4R 2339 2564 mA
IDD4W 2339 2564 mA
IDD5B 2744 2924 mA
IDD6 588 588 mA
IDDET 660 660 mA
IDD6TC 660 660 mA
IDD7 2699 3104 mA
Rev. 0.1 / Nov. 2009 63
Module Dimensions
128Mx72 - HMT112R7BFR8A
5.175
Detail A
Detail C
2.10
±
0.15
47.00
71.00
2X3.00
±
0.10
Front
1
30.00
9.50
17.30
120
5.0
1
1
240 121
Back
133.35
128.95
Registering
Clock Driver
SPD
/
TS
4X3.00
±
0.10
1.27
± 010
mm
Side
max
3.43mm max
0.20
2.50
±
0.20
1.00
0.80
±
0.05
Detail of Contacts B
1.50
±
0.10
Detail of Contacts C
0.3
±
0.15
0.3~0.1
5.00
3.80
2.50
2.50
±
0.20
3
±
0.1
1.20
±
0.15
Detail of Contacts A
Detail B
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13±
Units: millimeters
Rev. 0.1 / Nov. 2009 64
256Mx72 - HMT125R7BFR8A
5.175
Detail B Detail C
2.10
±
0.15
47.00
71.00
2X3.00
±
0.10
Front
1
4X3.00
±
0.10
30.00
9.50
17.30
120
5.0
1
1
240 121
Back
133.35
128.95
Registering
Clock Driver
SPD
/
TS
1.27
± 010
mm
Side
max
3.43mm max
0.20
2.50
±
0.20
1.00
0.80
±
0.05
Detail of Contacts B
1.50
±
0.10
Detail of Contacts C
0.3
±
0.15
0.3+0.1
5.00
3.80
2.50
2.50
±
0.20
3
±
0.1
1.20
±
0.15
Detail of Contacts A
Detail A
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13±
Units: millimeters
Rev. 0.1 / Nov. 2009 65
256Mx72 - HMT125R7BFR4A
5.175
Detail B Detail C
2.10
±
0.15
47.00
71.00
2X3.00
±
0.10
Front
1
30.00
9.50
17.30
120
5.0
1
1
240 121
Back
133.35
128.95
Registering
Clock Driver
SPD
/
TS
4X3.00
±
0.10
1.27
± 010
mm
Side
max
3.43mm max
0.20
2.50
±
0.20
1.00
0.80
±
0.05
Detail of Contacts B
1.50
±
0.10
Detail of Contacts C
0.3
±
0.15
0.3~0.1
5.00
3.80
2.50
2.50
±
0.20
3
±
0.1
1.20
±
0.15
Detail of Contacts A
Detail A
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13±
Units: millimeters
Rev. 0.1 / Nov. 2009 66
512Mx72 - HMT151R7BFR4A
5.175 Detail C Detail D
2.10
±
0.15
47.00
71.00
2X3.00
±
0.10
Front
1
30.00
9.50
17.30
120
5.0
1
1
240 121
Back
133.35
128.95
Registering
Clock Driver
SPD
/
TS
4X3.00
±
0.10
1.27
±010
mm
Side
max
3.46mm max
0.20
2.50
±
0.20
1.00
0.80
±
0.05
Detail of Contacts C
1.50
±
0.10
Detail of Contacts D
0.3
±
0.15
0.3~0.1
5.00
3.80
2.50
2.50
±
0.20
3
±
0.1
1.20
±
0.15
0.4
13.60
14.90
Detail of Contacts A
Detail of Contacts B
Detail B
Detail A
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13±
Units: millimeters
Rev. 0.1 / Nov. 2009 67
512Mx72 - HMT151R7BFR4A - Heat Spreader
Front
30.00
120
Back
133.35
22.00
Registering
Clock Driver
127
121
Registering
Clock Driver
1.27
±010
mm
Side
max
7.19mm max
1
240
133.75
14.214
2.786
6.35
36.7
42.7
20.9
10
33.4 33.4
3.69
5.39
6.3
7.36
46.46
80.54
2.15
57.2
7.74
119.64
2.7
15.36
22.00
8
Note:
1. tolerance on all dimensions unless otherwise stated.
2.In order to uninstall FDHS, please contact sales administrator.
0.13±
Units: millimeters
Rev. 0.1 / Nov. 2009 68
512Mx72 - HMT151R7BFR8A
5.175
Detail C Detail D
2.10
±
0.15
47.00
71.00
2X3.0
±
0.10
Front
1
3
±
0.1
30.00
9.50
17.30
120
5.0
1
1
240 121
Back
0.20
2.50
±
0.20
1.00
0.80
±
0.05
Detail of Contacts C
1.50
±
0.10
Detail of Contacts D
0.3
±
0.15
0.3~0.1
5.00
3.80
2.50
2.50
±
0.20
Min 1.45
3
±
0.1
128.95
133.35
23.30
13.60
14.90
3
±
0.1
1.20
±
0.15
0.4
13.60
14.90
Detail of Contacts A
Detail of Contacts B
Registering
Clock Driver
SPD
/
TS
1.27
± 010
mm
Side
max
3.46mm max
Detail A
Detail B
Note:
1. tolerance on all dimensions unless otherwise stated.
0.13±
Units: millimeters
Rev. 0.1 / Nov. 2009 69
512Mx72 - HMT151R7BFR8A - Heat Spreader
Front
30.00
120
Back
133.35
22.00
Registering
Clock Driver
127
121
Registering
Clock Driver
1.27
±010
mm
Side
max
7.19mm max
1
240
133.75
14.214
2.786
6.35
42.7
20.9
10
33.4 33.4
3.69
5.39
6.3
7.36
46.46
80.54
2.15
57.2
7.74
119.64
2.7
15.36
22.00
8
36.7
Note:
1. tolerance on all dimensions unless otherwise stated.
2.In order to uninstall FDHS, please contact sales administrator.
0.13±
Units: millimeters
