comely NEC NEC Electronics Inc. Description -. . The uPD78310 and wPD78312 microcomputers are designed for use in process control. They perform all the usual process control functions and are particularly well-suited for driving de motors in servo loops and stepping motors. The processor includes on-chip memory, timers, input/output registers, anda powerful interrupt handling facility. The #~PD78310/312 is constructed of high-speed CMOS circuitry and operates from a +5 V power supply.. The input frequency (maximum 12 MHz) is derived from an external crystal or an external oscillator. The internal processor clock is two-phase, and thus machine states are executed at a rate of 6 MHz. The shortest instructions require three states, making the minimum time 500 ns. The CPU contains a three-byte instruction prefetch queue which allows a subsequent instruction to be fetched during execution of an instruction that does not reference memory. Program memory is 8K bytes of mask-programmable ROM (uPD78312 only), and data memory is 256 bytes of static RAM. The PD78310 is the ROM-less version. Note: uPD78P312, available in 3086, is a Prototyping chip for H#PD78312, It has an on-chip 8K EPROM instead of a mask ROM. Features - O Complete single-chip microcomputer 16-bit ALU 8K ROM (uPD78312 only) 256 bytes RAM 1-bit and 8-bit logic ; O Instruction prefetch queue ; 0 16-bit unsigned multiply and divide OQ String instructions 1 Memory expansion 0 8085A bus-compatible Total 64K address space 0 Large I/O capacity Up to 32 I/O port lines CO Extensive timer/counter system Two 16-bit up/down counters Two 16-bit timers * Free running counter with two 16-bit capture registers Pulse-width modulated outputs Timebase counter . D Four-channel 8-bit A/D converter O Two 4-bit real-time output ports ( Two nonmaskable interrupts CO Eight hardware priority interrupt levels #PD78310/312 8-BIT, SINGLE-CHIP CMOS MICROCOMPUTERS, REAL-TIME CONTROL ORIENTED 7-49-19 -0% C1 Macro service facility for interrupts Gives the effect of 8 DMA channels CD) Bidirectional serial port Either UART or interface mode Dedicated baud rate generator 0 Watchdog timer CQ Refresh output for pseudostatic RAM 0 Programmable HALT and STOP modes 0 One-byte call instruction O) On-chip clock generator 0 CMOS silicon gate technology O0+5 V power supply Pin Configurations 64-Pin DIP and QUIP 1 Vop TT) Paz7/AD7 TT} P4e/ADg FI Pas/ADs ) P44/AD4 V P43/AD3 [J P42/AD2 7} P41/AD4 [] P&g/ADg 7] ALE WA RD ] RESET PEA 7 P527/A15 } PS6/At4 J] PS5/A13 ) PS4/Aq2 E] PS3/Adt ] P52/Ato 7] P54/Ag ] PSo/Ag 7] P37/CLR1/TO1 [] Pag/CLRO/TOO FP] P35/PWMt [7] P34/PWMO P} AVss CV) AVREF PANS J AN2 Ty ANY [7] ANo ON onnaen = P2y/INTEO P22/INTE1 P2g/INTE2 P24/TxD P25/AxD P26/SCK P27/CTS RFSH P3g/C10 P31/CTALO P32/Ci1 P33/CTRL1 x1 x2 Yss uPD78310/312/P312 - 83-000822A, 4-175uPD78310/312 wwe tytvU"d NEC ve ar Pin Config urations (cont) F-SP-1Y-O8 Pin Identification (cont) Symbol Function 64-Pin Miniflat a P27/CTS 1/0 port 2/Clear to send input ; g Z g g a RFSH Refresh output orogee z ae j geegeebe ? ee? P39/C10 Up/down counter 0 input ALO P3,/CTRLO Up/down counter 0 contro! input pos C1 64 Payiady P3o/Cl1 Up/down counter 1 input Po; O - . - 1 P4g/ADo 7 Pie O a ; Date P3q/CTRL4 Up/down counter 1 control input puta . , 48 1 WA x1 External crystal/External clock input Pi2 C4 Fo 1 RD pa] . D RESET x2 . External crystal piu O7 45 EA Vss Power return Pis : ] PS7/At5 . : re Fy ie/Ata ANo AN3 A/D converter inputs P17 (| 10 pPD79310/312 42 [1 PSs/A13 AVREF A/D reference voltage - P2g/NMI CJ C] PSa/A12 p2yiNTEO CI HI P5a/Ai1 AVss Analog ground P2o/INTE1 C] 13 39 1D P52/At0 P34/PWMO 1/0 port 3/Pulse width modulated output 0 napa p an P3s/PWM1 1/0 port 3/Pulse width modulated output 1 P2s/AxD C] 16 - 36 [1 P37/CLRV/TO1 P3g/CLRO/TOO 1/0 port 3/Counter 0 clear input/Timer 0 output P26/SCK ~ [] P3g/CLRO/TOO A "i pay/eTs noe F pasipwees P37/CLR1/T0O1 1/0 port 3/Counter 1 clear input/Timer 1 output RFSH C] 19 " - 2 3 b Paq/PWMO PS9-P57/Ag-Ai5 1/0 port 5/High address byte output - SSH rec EA External access control input 8 E 8 E RR Seeeee g RES External reset input o. e268 3 * RD Read strobe output eo-covszan| WR Write strobe output ALE. Address latch enable output Ordering Information P4p-P47/ADg-ADz 1/0 port 4/External address/Data bus Max Frequency Vop Power supply Part Number Package Type of Operation uPD78310CW ~ 64-pin plastic shrink DIP 42 MHz I i nPDTB3120W : Pin Functions pPD783106-36 64-pin plastic QUIP . 12 MHz P0-P07 [Port 0] piesa . Port O consists of 8 bits, individually programmable for x input/output or two 4-bit real-time (timer controlled) uPD78310G-1B 64-pin plastic miniflat 12 MHz output ports. uPD78312G-1B L #PD78310L _68-pin PLCC 12 MHz P1o-P17 [Port 1] HPD78312L Port 1 consists of 8 bits, individually programmable for | . input/output. Pin Identification Symbol Function P2o/NMI | { -PO7 1/0 port 0 Port P2y is dedicated to NMI, the nonmaskable external 1 P i i P1g-P17 1/0 port 1 interrupt request. : P2g/NMI Nonmaskable interrupt input P2;-P23/INTEO-INTE2 P24-P23/INTEO-INTE2 Maskable interrupt inputs . P2g/TxD 70 port 2/Serialt a Ports P2,-P23 are dedicated to INTEO, INTE1, and 24/Tx port 2/Serial transmit output INTE2, the maskable external interrupt requests. P25/RxD 1/0 port 2/Serial transmit output : P2g/SCK 1/0 port 2/Serial clock output 4-176NEC 6427525 N E C ELECTRONICS INC P24/TxD P24 is an 1/O port bit or the transmitted serial data output. P2s/RxD ~ P25 is an 1/O port bit or the received serial data input. P2./SCK P2g is an I/O port bit or the serial shift clock output. P27/CTS P27 is an I/O port bit or clear-to-send input (external serial transmission control) in the asynchronous communication mode. In the serial I/O interface mode, it becomes the serial receive clock 1/O pin RFSH RFSH is the refresh pulse output to be used for external pseudostatic DRAM. P39/CIO Port P3o is dedicated to C10, the external count input for up/down counter 0. P31/CTRLO Port P3, is dedicated to CTRLO, the external control input for up/down counter 0. P32/CI1 Port P32 is dedicated to Cl1, the external count input for up/down counter 1. P33/CTRL1 Port P3g is dedicated to CTRL1, the external control input for up/down counter 1. x1 X1 is the external oscillator input or one of the connections for an external crystal. [t is used to generate the system clock. The system clock frequency is half the input frequency. X2 X2 is the second connection for an external crystal. Vss Vsg is the power supply return, normally ground. LPD78310/312 => 98D 13464 ANo-ANg T-SF$-19-OF8 ANo-ANg are the four program selectable input channels for the A/D converter. . AVREF AVrer is the reference voltage input for the A/D converter. AVss AVsgs is the analog ground pin. P34/PWMO P34 is an I/O port bit or the pulse-width modulated output 0. P35/PWM1 P35 is an 1/O port bit or the pulse- -width modulated output 1. P3,/CLRO/TOO P3g is an I/O port bit, or the clear input for up/down counter 0, or the timer 0 flip-flop output. - P37/CLR1/TO1 P37 is an I/O port bit, or the clear input for up/down counter 1, or the timer 1 flip-flop output. - P5o-P57/Ag-A1s5 [Port 5] Port 5 consists of 8 bits, individually programmable for input or output, or the high-order address bits for external memory. Under control of the memory mask register, bits P59-P53 are used for 4K memory ex- pansion, bits PS9-P55 are used for 16K memory ex- pansion, or bits P59-P57 are used for 56K memory expansion. _ EA [External Access] On pPD78312, a low on EA enables use of external memory in place of on-chip ROM. The EA pin must be low on pPD78310. RESET This pin is used for the external reset input. A low level sets all registers to their specified reset values. RD RD is the read strobe output. It is to be used by external memory (or data registers) to place data on the I/O bus during a read operation. 4-177yPD78310/312 NEG WR WR is the write strobe output. It is to be used by external memory (or data registers) to latch data from the {/O bus during a write operation. ALE ALE is the address latch enable. It is to be used by external circuitry to latch the low-order 8 address bits during the first part of a read or write cycle. Block Diagram T-SG19-OF P49-P47/ADp-AD7 [Port 4] : Port 4 consists of 8 bits, programmable as a unit for input or output, or as the multiplexed address/data bus if external memory or external interface circuitry is used. The port is controlled by the memory mapping register. Vpp Vpp is the positive power supply input. 4 POP, $F] two 4-nit Realtime Po,-PO, 4/4 Output Ports P2g/NMt-e| external > P5g-P57/Ag-Ayg P2y/INTEO > Interrupts P2g/INTE1 >1 wracre Service [NE -> ALE P23/INTE2 ~?} Controller g Lt ALS 2 (wR o a P24/TxD ] eral 5 p FSH 4 al dl Pas/RxD Communication g } FEA P2giSCK 7_ Interface <3) 3 P27/CTS > . Pe | Boolean | Baud Rate Processor > P4g-P47/ADp-AD7 Program Counter 8 : P3g/C10 {~ Prog Stat Word instruction P3,/CTALO p two . Stack Pointer Queue P32/Cll P4 16-Bit 7 P3giCTALI >} Up/Down <>, nae a i z P3giCLRoTOO m] Counters Macrosve | 2 le Xi P37/CLRITO1 ->| i Channels _j2E 2 a 8B Micto Seq 5 x2 = cro Sequencer ! 3 l RESET P24/INTEO Two 16-Bit Micro ROM 9 P2g/INTE1 w} Capture z = Vnp P34/PWMO Registers and <> < Ves P3g/PWMI 4 PWM Outputs r y 7 AVREF 7 )| AD Converter Two Timebase Ctr Six 8-Bit Input/Output Ports ANo-AN3 4 BBits <> 16-Bit & Watchdog Port f Dedicated AVss 4 Channels Lo Timers Timer Alt Others Shared : > > Feo ge ve , 1 1 ' if t t 7 iy 4h 4s 4h 2b oo . ; road <w! wt NU? et P3g/CLROTOO P37/CLAI/TO1 PO OPi PROPS PS 49-003302C 4-178NEG uPD78310/312 Functional Description . On-chip features designed to facilitate process control include two 16-bit timers, two 16-bit up/down counters, two pulse-width modulated outputs, a free-running counter with two capture registers, two 4-bit real-time (timer contro!led) output ports, an 8-bit A/D converter with 4 input channels, a timebase counter to generate widely spaced interrupts, and a watchdog timer to guard against infinite program loops. In addition there is a serial [/O port which can be used in either an interface mode or an asynchronous communication mode. HALT and STOP modes are provided to conserve power at times when the action of the CPU is not required. All {/O, timer, and contro! registers are defined as special function registers and assigned addresses in the top 256 bytes of memory. The special function registers may be operated on directly by many of the arithmetic, logic, and move instructions of the CPU. Table 2 at the end of the Functional Description describes the registers. Addressing. The PD78310/312 features 1-byte addressing of the special function registers and 1-byte addressing of the internal RAM. There are nine modes of addressing main memory, including autoincrement, autodecre- ment, indexing, and double indexing. There are 8- and 16-bit immediate operands. , External Memory External memory (figure 1) is supported by I/O port 4, an 8-bit multiplexed address/data bus. The memory mapping register controls the size of external memory as well as the number of additional wait states. High- order address bits are taken from I/O port 5 as required. No bits are required for 256 bytes of external memory; bits P5g-P53 are used for 4K bytes, P5g-P55 for 16K bytes, and P59-P57 for 56K bytes. Any remaining port 5 bits are available for |/O. Refresh The xPD78310/312 has a refresh signal for use with the pseudostatic RAM. The refresh cycle can be set to one of four intervals ranging from 2.67 to 21.3 ys. The refresh is timed to follow a read or write operation so that the CPU does not have to wait. General Registers The CPU has 16 8-bit registers (figure 2) that can also be used in pairs to function as 16-bit registers. A complete set of 16 general registers is mapped into each of 8 program-selectable register banks, stored in RAM. Three bits in the PSW specify which of the register banks is active at any given time. Each register bank has two program-selectable accumulators. Figure 1. Memory Map FFFFH FFFFH FEOHL ~ cm Special Function \ Registers Faegister | J N FeeoH| Storage | internat N Availabe t RAM \_FEOOH | Storage | External / Fixed Area OFFFH FT Qo00H c00oH | Vector Table Area 49-001304A Figure 2. Register Designation and Storage ASS =1 : RSS =0 Register Bank | FE80H i A[Ri} 1 X [RO] / Rit RO | f--~-<2 to md 7 / i AX [RPO] 5 / APO BiRs) | Cina | fo EB Re BG [RPt} / Rt RSL ORG 5 T L / A[R5] | X [R4} nee 4 / AX IRP2} R7 ft RG / B(R7] | C {RS} APs 5 / BC [RP3) vPH iS] | VFL [RB] i VP (RP4} / T 2 i | UPH (R14) UPe R10) | / UP [RPS] / : D{R13] | (R12) t if eee t---4 DE [RPS] 7 0 . PHIRIS] f LIRI4) FEFFH HL (RP7] 83-003824A, 4-179 T9949 -OFNE C ELECTRONICS INC 44 vey B4e?Se5 OOLS4b? 1 i 6427525 N E C ELECTRONICS INC > 98D PNEC yuPD78310/312 T-SP-17-O8 Program Status Word . Figure 3. Pulse-Width Modulated Output Following is the program status word format. Porn rn rn re rene nee e cee 4 . : . : im mo ' 15 -. 8. ' 4 [0 [RB.[RB, | RB] o | o | we |-0 | | ama 7 ce 0 x 4 ' |s | z [ass] ac | uF | pv |sus| cy | t sciK 1 i i) bem we mw een mm ew ew em ee ee meme wen meee RBz-RBy Active register bank number i Je lE Interrupt enable oo \ ' Ss Sign (1 if last result was negative) Became nnn mmm mmm mm *seooraask z - Zero (1 if last result was zero) RSS Register set select . AG Auxiliary carry (carry out of 3 bit) Timers UF . User flag The uPD78310/312 has two 16-bit timers. The inputs to P/V Parity or arithmetic overflow these timers may be the internal clock divided by 6 or SUB Subtract (1 if last operation was by 128. Each timer has an associated modulus register subtract) : to store the timer count. The timer counts down to zero, CY ~ Carry sets a flag, reloads from the modulus register, and then counts down again. The timer flags can be used under Input/Output program control to generate interrupt requests and/or All ports may be used for either latched output or high- impedance input. All ports except port 4 are bit- programmable for input or output. Port 0 is used for real-time or normal I/O. Port 1 is used for normal !/O. The low nibbie of ports 2 and 3 is always used for control and the high nibble for control or normal 1/0. Port 4 is used for the external address/data bus or byte-programmable I/O. Port5 is used for the high bits of the external address or for normal I/O. Real-Time Output Port The real-time output port shares pins with I/O port 0. The high and low nibbles are treated separately or together. Data is transferred from a buffer to the port latches on either a timer or software command. Serial Port The serial port can operate in UART or interface mode with the baud rate and byte format under program control. The serial port also includes a dedicated baud rate generator. . Pulse-Width Modulated Outputs The two independent pulse-width modulated outputs are controlled by two 16-bit modulus registers and counters. There are four programmable repetition rates ranging from 91.6 Hz to 23.4 kHz. Figure 3 shows one of these outputs. 4-180 a square-wave output. TMO also functions optionally as two one-shot timers. Figure 4 is a diagram of the interval timers. There is a free-running counter that counts the internal clock divided by 4 or by 16. The counter has two 16-bit capture registers. Capture is triggerd by an external interrupt request or by the up/down counter clock. The timebase counter generates a signal at one of four intervals ranging from 170 ys to 175 ms. The signal can be used to generate an interrupt request and/or an up/down counter capture. Up/Down Counters The uPD78310/312 has two 16-bit up/down counters, each of which has two capture/compare registers. There are three modes of operation: compare and interrupt, capture on external command, and capture on timebase counter command. There are five sources of counts: the internal clock divided by 3, the external clock, external independent up and down inputs, external clock with direction control, and external clock with automatic up/down discrimination. Figure 5 shows an up/down counter.N & C ELECTRONICS INC 48 veg 6427525 OO134ba 3 a NEC 8427525 NEC ELECTRONICS INC D> , Figure 4. Timer Block Diagram puPD78310/312 98D 13468 _ I ee ee 7 | | | MD} (16) | | - | | | | SCLKI6 \Z | | / Tet (16) 7 TMF2 Quiet }_O01 | seuKiiag | | | . | | mo : | | SCLK12 - 3 TMFI | | MDO(Ie) 7 | SCLK/128 | | + | SCLKIG : | THO (16) TMFO Cuiput |} O70 | SCLKN2 | | | SCLKi128 ~>| | boo LL fj ee | 4. : Internal Bus Y 49-001305C Standby Modes , ; HALT and STOP modes conserve power when CPU action is not required. In HALT mode, the CPU stops and the clock continues to run. Maskable interrupts can restart the CPU. . in STOP mode, the CPU and clock are both stopped. A RESET pulse or the nonmaskable external interrupt i is required to restart them. There is also the option of slowing the system clock by a factor of four. The standby control register contro!s the standby modes and is a protected location written to only by a special instruction. Watchdog Timer: The watchdog timer protects agains inadvertent program loops. A nonmaskable interrupt occurs if the timer is not reset before a timeout occurs. There are four program-selectable intervals ranging from 5.5 ms to 349.3 ms. The watchdog timer can be disabled by software. The watchdog timer mode register controls the watchdog timer and is a protected location written to by a special instruction. A/D Converter _ The A/D converter has four input channels and can operate in either scan or select mode. The A/D converter performs 8-bit successive approximation conversions, has a 30-y4s conversion time, and is triggered either internally or externally. The A/D converter includes an on-chip sample and hold amplifier. 4-181 4NE C ELECTRONICS INC 98 DEB Guerses co1ayed 5 a 6427525 N E C ELECTRONICS INC uPD78310/312 _> 98D 13469 NEC Figure . Up/Down Counter Block Diagram | \ cLRIO | TTT TT TT 7 | Timebase . 7 | Counter P crore L. . . \ Capture : in | . re fegest | * Comparator | cnO Sf | | Upibown Count U I Discrimination }CountOown UBCO (16) | ome FU} REE Ss | | . | | : . Comparator | cLROO AX interrupt of fAu}- St sent | I | | 4 (\ {nternal Bus. v 49-0013068 Interrupts There are two nonmaskable interrupt sources: the external nonmaskable interrupt and the watchdog timer. Their relative priorities are software selectable. There are eight hardware priority interrupt levels, level O having the highest priority and level 7 the lowest. The fifteen maskable interrupt sources (table 1) are divided into five groups, and each group can, under program control, be assigned to any one of the priority levels. interrupts may be serviced by routines entered either by vectoring or by context switching. Context switching automatically saves all the general registers, the program status word, and the program counter. Figure 6 illustrates the mechanism of context switching. _ Finally, there is an optional macro service function that transfers data between any one special function register and memory without program intervention. . 4-182 Macro Service The macro service controller can be programmed to perform word or byte transfers. It can transfer data from a special function register to memory or from memory to a special function register. Transfer events are triggered by interrupt requests and take place without software intervention. There are eight macro service channels; channel control information is stored in RAM. This information (figure 7) consists of a 16-bit memory address (optionally incremented at each transfer), an 8-bit special function register designator, and an 8-bit transfer counter (decremented at each transfer.) When the count equals 0, a context switch or vectored interrupt occurs.NE C ELECTRONICS INC 16 | B427S525 0013470 rT 6427525 N E C ELECTRONICS INC _pD NEC 88D 13470 uPD78310/312 ' Table 1. Interrupt Sources and Vector Addresses 7" V9-19 og Default Priority -- Source Interrupt Service Macro Service Vector Nonmaskable Interrupts - a BRK . Break instruction No 003EH : - NMI External nonmaskable interrupt No 0002H . = WOT Watchdog timer No QO0AH Maskable interrupts 0 CRF0O Up/down counter Yes QO1AH . 1 CRFO4 Up/down counter No Q01CH 2 CRF10 Up/down counter Yes OO1EH 3 CRF11 Up/down counter No 0020H 4 EXIFO External Interrupt 0 Yes 0004H 5 EXIF1 Externai interrupt 1 _ Yes 0006H 6 EXIF2 External interrupt 2 Yes 0008H 7 TIMFO Timer flag 0 _Yes QQOEH 8 TIMF1 Timer flag 1 Yes 0010H 9 TIMF2 Timer flag 2 Yes 0012H 10 SEF Serial port error . No . 0022H 11 SRF Serial port receive buffer Yes 0024H - 12 STF Serial port transmit buffer Yes . 0026H 3 ADF A/D converter done flag Yes 0028H 14 TBF Timebase counter flag No Q00CH - RESET External reset line - 0000H Figure 6. Hardware Context Switching Current Active Bank aX ac RP2 RPS ve uP DE ~ HE AX Bc New Active Bank 49-001307A 15 a 0 MSP4 FEE3H SFRP4 | MSC4 MSP5 FEE7H SFAPS | mMsc5 ee iets FEEBH SFRP6 | MSCE MSP7 FEEFH SFRP7 | MSC? MSPO FEFIH SFRPO | msco MSP1 FEF7H SFRPI | MSC1 ssa mre FEFBH SFRP2 | MSC2 MSP3 FEFFH SFRP3 | MSC3 Note: {1} The macro service pointers share storage with register banks 0 and 1. {2} MSP = Memory address painter SFRP = Special function register pointer MSC = Transfer counter FEEOH FEE2H FEESH FEEGH FEESH FEEAH FEECH FEEEH FEFOH FEF2H FEFAH FEFGH FEFSH FEFAH FEFCH FEFEH Figure7. kPD78312 Macro Service Pointer Addresses Channel 4 Channel 5 . Channel Channel 7 Channet o Channel 1 Channel 2 Channel 3 83-003825A 4-183NE C ELECTRONICS INC 494 veg b4Ye?SeS OOL35471 4 7: 7-49-19 -08 NEC uPD78310/312 - 6427525 N E C ELECTRONICS INC 98D 13471 Table 2. Special Function Registers Zs cote : we Read/ 16-Bit Reset Address Functiin Mnemonic | Write Transfer State FFOOH 1/0 port 0 PO R/IW No Undefined FFOIH 1/0 port1 - P41 R/W No Undefined FFO2H 1/0 port2 P2 RIW No (Note 1) Undefined FFO3H 1/0 port 3 P3 RIW No (Note 1) Undefined FFO4H - WO port4 P4 RW No Undefined FFOSH 1/0 port 5 P5 R/W No Undefined FFO8H Capture/compare register 00 CROOL R/IW Yes Undefined FFO9H 7 CROOH : . FFOAH - Capture/compare register 01 CROIL ~ R/W Yes Undefined FFOBH . CROIH . FFOCH * Capture/compare register 10 CRIOL R/W Yes Undetined FFODH : CRI0H FFOEH Capture/compare register 11 CRIIL R/W Yes Undefined FFOFH : CR11H FFIOH Capture register 0 (from FRC) CPTOL RW Yes Undefined FFI1H CPTOH .~- FF12H Capture register 1 (from FRC) CPTIL R/W Yes Undefined FFI3H -. . CPTIH oe . FFI4H PWM register 0 (duration) PWMOL R/W Yes Undefined FFI5H : PWMOH FFI6H PWM register 1 (duration) PWMIL ~ RIW Yes Undefined FFI7H : PWM1H . FFICH Presettable up/down counter 0 UDCOL R/W Yes _ Undefined FFIDH : UDCOH - : FFIEH Presettable up/down counter 1 UDCIL R/W Yes Undefined FFIFH UDC1H FF20H Port 0 mode register PMO R/W No FFH FF21H Port 1 mode register _ PM1 R/W No FFH FF22H Port 2 mode register PM2 R/IW No FFH FF23H Port 3 mode register PM3 R/W No FFH FF25H Port 5 mode register PM5 R/W No FFH FF32H Port 2 mode control register PMC2 R/W No OFH FF33H Port 3 mode control register PMC3 R/iW No OFH FF38H Real-time output port contro! register RTPC R/W No 08H 4-184NE C ELECTRONICS INC 98 Dey b427525 OULS4%2 S TU NEC UPD78310/312 6427525 NEC ELECTRONICS INC _D. 88D 13472 Table 2. Special Function Registers (cont) 7-S P/F -28 .. : Read/ 16-Bit Reset Address : . ; Functlon Mnemonic Write Transfar State FF3AH Port 0 buffer register (Note 2) POL R/W No Undefined FF3BH : : . POH R/W No Undefined FF40H Memory mapping register MM R/W No 30H FF41H Refresh mode register RFM R/IW No 10H FF42H Watchdog timer mode register WDM R/W No 00H FF44H Standby contro! register STBC R/W No 2nH (Note 3) FF46H Timebase made register TMB R/W No _ OOH FF48H Interrupt mode register INTM R/W No 00H FF4AH in-service priority register ISPR R/iW No 00H FF4EH CPU control word ccw R/W No 00H FFS50H Serial communication mode register SCM R/W No : 00H FF62H_ Serial communication control register scc R/W No QOH FF53H Baud rate generator ; BRG R/W No QOH FF56H Serial communication receive buffer . RXB R No Undefined FF57H Serial communication transmit buffer TXB. W No... Undefined FF60H Free-running counter control register FRCG R/W No * QOH FF64H - Capture mode register CPTM R/W No. _ 00H FF66H PWM mode register . PWMM . RIW No . OOH FF68H A/D converter mode register ADM R/W No 00H FF6AH A/D converter result register ADCR R No | Undefined FF70H Count unit input mode register CUIM R/W No 00H FF?2H Up/down counter control register 0 ~ UDCCO R/W No . 00H FF74H Capture/compare control register cro R/W No . OOH FF80H Timer 0 control register TMCO RIW No 00H FF82H Timer 1 control register TMC1 R/IW No 00H FF88H Timer 0 TMOL R/W Yes Undefined FF8SH ae . - TMOH . FF8AH ~ Modulus/timer register 0 MDOL R/W Yes Undefined FF8BH . MDOH . FF8CH Timer 1 TMiL R/W Yes Undefined FF80H . - no Sees ~ - - TM1H vee FF8EH Modulus register 1 MDIL R/W Yes Undefined FF8FH MD1H FFBOH- External area (Note 4). FFBFH 4-185awe NE C ELECTRONICS INC 48 vey b427525 00139473 7 iE NEC (1) Bits 0-3 of port 2 and port 3 are read-only. pPD78310/312 6427525 N E C ELECTRONICS INC DD 98D 13473 Table 2, Special Function Registers (cont) Fe S 7- / g -OF Read/ 16-Bit Reset Address - Function Mnemonle Write Transfer State FFCOH Interrupt control 00 Up/down counter CRICCO RW No 47H FFC1H Macro service control 00 Up/down counter CRMSO0 R/W No Undefined FFC2H Interrupt contro! 01 Up/down counter CRICO1 RW No 47H FFC4H Interrupt control 10 Up/down counter CRICIO R/W No 47H FFCSH Macro service control 10 Up/down counter CRMS10 R/W No Undefined FFC6H Interrupt contro! 11 Up/down counter CRICH R/W No 47H FFC8H EXIFO interrupt control External interrupt EXICO RIW No 47H FFCSH EXIFO macro service control . External interrupt EXMSO R/W No Undefined FFCAH EXIF1 interrupt control External interrupt EXIC1 R/W No 47H : FFCBH EXIF1 macro service controt External interrupt EXMS1 RIW No Undefined FFCCH EXIF2 interrupt contro! External interrupt EXI2 R/W No 47H FFCDH EXIF2 macro service contro! External interrupt EXMS2 R/W No Undefined FFCEH TMFO interrupt contro! Timer flag TMICO R/W No 47H FFCFH TMFO macro service contro! Timer flag TMMSO R/W- , No Undefined FFDOH TMF1 interrupt control Timer flag TMIC1 RW) No 47H FFD1H TMF1 macro service control Timer flag TMMS1 R/W No Undefined FFO2H TMF2 interrupt control Timer flag TMIC2 R/W No 47H FFD3H TMF2 macro service control Timer flag TMMS2 R/W No Undefined FFDAH Error interrupt control Serial port SEIC RIW No 47H FFOCH Receive interrupt control Serial port SRIC R/W No 47H FFDDH Receive macro service control Serial port SRMS R/W. No Undefined FFDEH Transmit interrupt control Serial port STIC R/W . No 47H FFDFH Transmit macro service contro! Serial port STMS R/W No Undefined FFEOH A/D converter interrupt control . ADIC R/W No 47H_ | FFEtH A/D converter macro service control ADMS R/W No Undefined FFE2H Timebase counter interrupt control TBIC R/W No 47H FFFCH Stack pointer (Note 5) SPL- R/W Yes Undefined FFFDH SPH . FFFEH Program status word (Note 5) PSWL R/W Yes 00H FFFFH PSWH Note: (2) POH and POL are 4-bit buffer registers used to store data to be loaded into the high and low nibbles of the real-time output (PO). (3) Bit 3 of the STBC is not affected by RESET (n =0 or 8). (4) External registers interfaced with these addresses can be accessed by special function register addressing. (5) SP and PSW do not have real SFR addresses and can be accessed only by special instructions. 4-186NE C ELECTRONICS INC 98 Dee b427s5e5 Oosy74 4 T NEC P09, y uPD78310/312 - 6427525 NEC ELECTRONICS INC _D 98D 13474. Instruction Set ee Symbols in the Operand and Operation Columns The instruction set for the uPD78310/312 has 8- and _Symbol Meaning 16-bit arithmetic instructions including a 16 x 16-bit + RO-R15 unsigned multiply with a 32-bit product and a 32 by 1 RO-R7 16-bit unsigned divide with a 32-bit quotient and a 2 CB 16-bit remainder. The instruction set also excutes an : - 8-bit and a 16-bit shift and rotate by count, 1-and8-bit 'P RPO-RP7* logic, and 1-, 2-, and 3-byte call instructions. String rpi RPO-RP7* manipulation instructions are also included. rp2 DE, HL, VP, UP There are four addressing modes for unconditional __sfr Special function register, 8 bits branching. Branch instructions exist to test single bits in the program status word, the 16-bit accumulator, the special function registers, and internal RAM. The instruction set also includes multiple register PUSH and POP instructions. =o = | m Following are several tables explaining symbols, designations, and codes in the instruction Set. Machine codes are omitted from the instructions but they are in the User's Manual. : sirp Special function register, 16 bits post RPO, RPi, RP2, RP3, RP4, RP5/PSW, RP6, RP7 Bits set to 1 indicate register pairs to be pushed/popped to/from the stack ~ . , RPS pushed/popped by PUSH/POP: SP is stack pointer : PSW pushed/popped by PUSHU/POPU: RPS is stack pointer mem (DE), (HL), (DE+), (HL-+), (DE), (HL), (VP), (UP); register - indirect (DE + A), (HL + A), (DE + B), (HL +B), (VP + DE), (VP + HL); base/index mode (DE + byte), (HL + byte), (VP + byte), (UP + byte), - (SP + byte); base mode . . s Word (A), word (B), word (DE), word (HL); index mode - | saddr FF20H-FFIFH: immediate byte addresses one byte in RAM, a or label saddrp FE20H-FF1FH: immediate byte (bit 0 = 0) addresses one word in RAM word 16 bits of immediate data byte 8 bits of immediate data jdisp 8-bit two's complement displacement (immediate data) bit 3 bits of immediate data (bit position in byte), or label n 3 bits of immediate data addri6 QO00H-FEFFH: 16-bit immediate address (up to FFFFH in MOV instruction) Jaddri6 O000H-FEFFH: 16-bit absolute branch address (immediate data) $addri6 Relative branch address ((PC)+jdisp)) addr11 Q800H-OFFFH: 0800H+ (11-bit immediate address}, or label addrS Q040H-007EH: 0040H + 2 x (5-bit immediate address), or label . 4-187pe mea NE C ELECTRONICS INC 14 #uPD78310/312 Del b4e75e2e5 0013475 QO a, NEC 6427525 N & CG ELECTRONICS INC 98D 13475 Symbols In the Operand and Operation Columns (cont) Flag Indicators , 7- y P~ ? Z Symbol oo Meaning ; . Symbol. Meaning - 77 -O A A register (8-bit accumulator) , (blank) No change x X register 0 Cleared to 0 B B register 1 Set to 1 C C register x Set or cleared according to result D D register P Parity of result E E register V Arithmetic overflow H H register U Undefined L L register R Restored from saved PSW RO-R15 Register 0-15 oo. : AX Register pair AX (16-bit accumulator) Execution Times of Memory Reference Instructions: BC Register pair BC - Number of Processor States DE Register pair DE Mamory Reference Mode L ist j . Register Base = AP? = Instruction Indirect Index Base Index - egister pai ger MOV A, mem 5 6. 6 6 PC Program counter __ SP Stack pointer mem. A XCH A,mem 7 8 8 8 UP User stack pointer (RP5) PSW Program status word mem, A ADD, ADDC, A, mem 6 7 7 CY . Carry flag SUB, SUBC, mem, A 7 8 AC Auxiliary carry flag AND, OR, XOR ' Z Zero flag CMP A,mem 6 7 7 7 P/V Parity/overtlow flag mem, A $ Sign flag - SUB Subtract flag Memory Addressing Modes RBS Register bank select flag Register Base 7 mem Indirect Index Base Index RSS Register set select flag - ; 000 (DE+) (DE+A) (DE+byte) word (DE) Ie Interrupt enable flag 001 (HL+)* (HL+A) (SP-+byte) word (A) Eos End of software interrupt flag di (OE (DE +B) (HL+ word (AL) , tT STBC . Standby control register O14 HL (HL +B) (P+ ove) word (8) - i WDM Watchdog timer mode register : y - ___ 100 (DE) (VP+DE) (VP + byte) - () - Contents of the location whose address is within ( _); (+) z and () indicate that the address is incremented after or 101 (HL) (VP + HL) - _ decremented before it is used. 110 (VP} ~~ ( ) Contents of the memory location defined by the contents 111 (UP) _ _ _ of the location defined by the quantity within the ((__)). XXH Hexadecimal number *1-byte instructions: defined by special! opcode and mem only. XH, XL High-order 8 bits and low-order 8 bits of X * tp and tp1 describe the same registers, but generate different machine code. 4-188NE C ELECTRONICS INC 44 Dey b4Y27525 OO347b 2 Tr T-YVP-15 -08 FOlPINR wo NE Cc. uPD78310/312 6427525 NEC ELEc . TRONICS INC 98D 13476 General Register Designatio rp R2- sR RO P2 Pl PO reg-palr 0 0 0 0 0 0 0 RPO. 0 0 0 1 0 0 1 RP1 Oo 0 1 0 0 1 - 0 RP2 0 0 1 1 n 0 1 10 RP3 0 1 0 0 1 - 0 .Q RP4 0 1 0 1 | 0 1 RP5 0 1 1 0 1 1 0 RPG 0 1 1 1 i. 1 1 RP7 1 0 0 0 , 1 0 o ff pi i i Q2 q- 00 reg-palr 1 1 0 0 0 . 0 0 RPO { 1 0 1 0 0 1 RP4 1 17 1 0 0 1 0 RP1 1 1 1 1 0 1 1 RP5 - 1 0. 0 RP2 1 --0 1 RPS 1 4 0 RP3 1 1 1 RP7 a400 +o-40/8get te emer NE C ELECTRONICS INC 94 DEB Guerses gouay7? 4 i NEC puPD78310/312 6427525 N & C ELECTRONICS INC PD. 88D 13477 instruction Set 7. - - ~ am YF-17-O8% Mnemonics Operand ~ Operation States Bytes s * AC PYV SUB cY MOV rt, #byte r1< byte 3 2 saddr, #byte (saddr) < byte 3 3 str**, #byte sfr byte 3 3 ne r<ri 3 2 An A<ri 3 1 A, saddr A= (saddr) 3 2 saddr, A {saddr) <A 3 2 addr, saddr (saddr) < (saddr) 4 3 Astr A<sfr 3 2 sfr,A sfr<-A 3 2 A, mem* A< (mem) 5 1 A,mem A= (mem) 5-6 2-4 mem, A* . (mem) A 5 1 mem, A | (mem) <- A 5-6 2-4 A, (saddrp) A= ((saddrp)) 5 2 (saddrp), A ((saddrp)) <- A 4 2 A, addr16 A<(addri6) 4 4 addri6, A (addr16) <- A 3 4 PSWL, #byte PSW, byte 3 3 Xx x xX Xx Xx PSWH, #byte PSWy <- byte 3 3 PSWL, A PSWL<A 3 2 x xX xX 4 x PSWH, A PSWy <A 3 2 A, PSWL A= PSWL 3 2 A, PSWH A= PSWy 3 2 XCH A,r Ari 4 1 rr reri 4 2 A, mem A<> (mem) 7-8 2-4 A, saddr A < (saddr) 4 2 A, sfr A+ sfr 7 3 A, (saddrp) A+ ((saddrp)) 6 2 saddr, saddr (saddr) <> (saddr) 8 3 ** A special instruction Is used to write to STBC and WDM (see below). * One-byte move instruction. 4-190NEC ELECTRONICS INC 94 vey L427525 0013478 & t NEC Zeinloie uPD78310/312 6427 : ~ S25 NEC ELECTRONICS INC _p 98D 13478 instruction Set (cont) . Mnemonic Operand Operation States Bytes Ss Zz AC P/V = =SUB OGY MOVW rp, fword tpt < word 3 3 saddrp, #word (saddrp) - word 4 4 sfrp, #word sfrp word 3 4 rp, rp1 tp< rp 3 2 AX, saddrp AX - (saddrp) 3 2 saddrp, AX (saddrp) <~ AX 3 2 saddrp, saddrp (saddrp) < (saddrp) 4 3 AX, sfrp AX < sfrp 3 2 sfrp, AX sfrp < AX. 3 2 XCHW AX, saddrp AX +=> (saddrp) 4 2 AX, sfrp AX +-> sfrp 7 3 saddrp, saddrp (saddrp) ~ (saddrp) 8 3 rp rpi rp rpi 5 2 ADD A, #byte A, CY <- A+ byte 3 2 X xX x V 0 x . saddr, #byte (saddr), CY < (saddr) + byte 4 3 X xX 4 V 0 x sfr, #byte sfr, CY < sfr + byte 7 4 x x X Vv 0 xX nr r0Yertri 3 2 X X x V 0 X A, saddr A, CY A+ (saddr) 3 2 x x 4 Vv 0 x Asfr ACY <A-+sfr 6 3 X X X V o xX saddr, saddr (saddr), CY < (saddr) + (saddr) 6 3 x xX X V 0 xX A, mem A, CY A + (mem) 6-7 2-4 x X xX V 0 x mem, A (mem), CY - (mem) +A 7-8 2-4 X xX x V 0 xX ADDC A, flbyte A, CY < A+ byte + CY 3 2 x xX xX Vv 0 Xx saddr, #byte (saddr), CY < 4 3 x xX X V 0 x (saddr) + byte + CY sir, #byte Sfr, CY < sfr + byte + CY 7 4 X x xX V 0 xX nr r,C<r+r+cy 3 2 x xX xX V 0 xX A, saddr A, CY < A+ (saddr) + CY 3 2 4 xX xX V 0 x A, sir A, CY A-+sfr+CY 6 3 x xX x Vv 0 x saddr, saddr _ (saddr), CY 6 3 x xX Xx Vv 0 X (saddr) -+ (saddr) + CY A, mem A, CY < A+ (mem) + CY 6-7 2-4 X X x v o xX mem, A (mem), CY < (mem) +A + CY 7-8 2-4 X xX xX V 0 xX 4-191 FE =NE C ELECTRONICS INC 48 pe b4u2752e5 oOLs474 & aT pPD78310/312. 6427525 N E C ELECTRONICS INC instruction Set (cont) > NEC 98D 13479 7-YP-1F-O% Flags Mnemonic Operand _ Operation States Byles: S$ Z AC P/y SUB sO SUB A, #byte A, CY < A byte 3 2 x Xx xX V 1 xX saddr, #byte (saddr)}, CY < (saddr) ~ byte 4 3 X x x Vv 1 x str, #byte sfr, CY < sfr byte 7 4 x x X Vv 1 x rr rC<-r-r 3 2 xX xX xX Vv 1 x A, saddr A, CY <~ A (saddr) 3 2. Xx x xX V 1 x Astro A, CY <-A-sfr 6 3 x X X V 1 x saddr, saddr (saddr), CY < (saddr) ~ (saddr) 6 3 xX 4 x Vv 1 xX _ A,mem A, CY <- A (mem) 6-7 2-4 x xX xX V 1 xX mem, A (mem), CY - (mem) A 78 24 X X X V 1 X SUBC A, #byte A, CY - A byte CY 3 2 xX x xX Vv 1 X saddr, #byte (saddr), CY 4 3 x xX xX V 1 xX (saddr) byte CY sfr, #byte sfr, CY sfr byte CY 7 4 x x x v 1 x ri r,cY<rriCY 3 2 x xX xX V 1 xX A, saddr A, CY < A(saddr) CY 3 2 x xX xX Vv. 1 xX A, str A, CY - AsfrCY 6 3 x Xx xX Vv 1 X saddr, saddr (saddr), CY < 6 3 x xX x V 1 x (saddr) (saddr) CY A,mem A, CY A (mem) CY 6-7 2-4 X x X Vv 1 x mem, A (mem), CY (mem) A CY 78 2-4 x x xX v 1 4 AND . A, #byte A<AAbyte 3 2 x X U P 0 0 saddr, #byte (saddr) < (saddr) A byte 4 3 x x U P 0 0 . str, #byte str sfr A byte 7 4 xX X U P 0 0 ort r-rart 3 2. xX X U P 0 0 A, saddr A= AA (saddr) 3 2 x X U P 0 0 A sir A AAsfr 6 3 xX x U P 0 0 saddr, saddr (saddr) < (saddr) A (saddr) 6 . 3 X xX u P 0 0 A, mem A+ AA (mem) 6-7 2-4 X x U P 0 0 ~ mem,A (mem) <~ (mem) AA 78 2-4 xX xX U P 0 0 OR - A, #byte A<- AV byte 3 2 Xx x U P 0 0 saddr, #byte (saddr) < (saddr) V byte 4 3 xX x U P 0 0 _ sfr, #byte sfr <- sfr V byte 7 4 x Xx U P 0 0 soon rorVri 3 2 X xX U P 0 0 A, saddr A= AV (saddr) 3 2 x x U P 0 0 A, str A~AVstr 6 3 x x U P 0 0 saddr, saddr (saddr) < (saddr) V (saddr) 6 3 xX Xx U P 0 0 A, mem A< AV (mem) 6-7 2-4 Xx x u P 0 0 mem, A (mem) < (mem) VA 7-8 2-4 x xX U P 0 0 4-192 see eee1 2G 2g enum NE C ELECTRONICS INC 98 a B4e27S25 00139480 4 J 7-7-1949 -0F N; E C uPD78310/312 ~ 6427525 N E ELECTRONICS INC D 98D 13480 "Instruction Set (cont) Flags Mnemonics Oparand Operation States Bytes Ss Zz AC P/V. SUB CY .. XOR A, #byte A~<- byte 3 2 x X U P 0 0 saddr, abyte (saddr) < (saddr)-- byte 4 3: X x U P 0 0 sfr, #byte sfr sir- byte 7 4 xX xX U P 0 0 nr ror ri 3 2 X xX U P "0 0 A, saddr A< A (saddr) 3 2 -X X U P 0 0 A, sfr A<A*sfr : 6 3 OX x U P 0 0 saddr, saddr (saddr) - (saddr)- (saddr} 6 3 x X U P 0 0 A, mem A< A (mem) 6-7 2-4 xX 4 U Pp 0 0 - mem, A . (mem) (mem) A 7-8 2-4 X X U P 0 0 CMP A, #byte A byte 3 2 4 x X V 1 xX saddr, #byte (saddr) byte 4 3 x xX x V 1 x sfr, #byte sfr byte 7 4 xX Xx xX Vv 1 Xx a rr 3 2 x X xX vo 1 X A, saddr A(saddr) 3 2 X xX xX V 1 xX A, str A-str 6 3 -X x X v 1 Xx saddr, saddr (saddr) (saddr) 6 3 xX x x V 1 x A, mem A(mem) 6-7 2-4. xX X x ~Y 1 x mem, A (mem) A 6-7 2-4 xX xX x v 1 x ADDW AX, dword AX, CY <- AX + word 4 3 xX xX U Vv 0 x saddrp, #word (saddrp), CY (saddrp) + word 4 X xX U V 0 Xx Sfrp, #word sfrp, CY sfrp + word 8 5 x x U V 0 x. rp, rpt rp, CY < rp + rpt 4 27 X x U Vv 0 X AX, saddrp AX, CY AX + (saddrp) 4 2 x X U Vv. 0 x AX, sfrp AX, CY AX + strp 7 3. X xX U V 0 x saddrp, saddrp (saddrp), CY 6 3 xX xX U V 0 Xx (saddrp) ++ (saddrp) . . , SUBW AX, word AX, CY AX word 4 3 x xX U Vv 1 X - - Saddrp, #word (saddrp), CY < (saddrp) word 5 4 X xX U V i x sfrp, #word strp, CY sfrp word 8 5 xX X U Vv 1 x rp, rp tp, GY <- rp rp 4 2 xX X U V 1 xX AX, saddrp AX, CY AX (saddrp) 4 2 xX x U V 1 x AX, sfrp AX, CY < AX sfrp 7 3 X xX U V 1 X saddrp, saddrp (saddrp), CY < 6 3 X x U V 1 x (saddrp) (saddrp) : CMPW AX, fword AX word 4 3 x xX U V 1 xX saddrp, #word (saddrp) word 5 4 xX xX U V 1 x sfrp, #word sfrp word 8 5 x x U V 1 x rp, rp1 irpt 4 2.. x x U V 1 x AX, saddrp AX=(saddrp) ~~ - - _ 4 2 x x U V 1 xX AX, sfrp AX sfrp 7 3 X X U V 1 x saddrp, saddrp (saddrp) (saddrp) 6 3 4 x U V 1 x 4-193NE C ELECTRONICS INC 94 Dey b427S52S OOl3481 b i yuPD78310/312 6427525 N E C ELECTRONICS INC DPD 98D 13481 instruction Set (cont} Mnemonic MULU Operand dl Operation AXAxt States 18 Bytes 2 NEC FzYF-(9-OF s AC P/V SUB DIU n AX (Quotient), ri (Remainder) AX=rt 18 2 MULUW rp AX (High Order 16 Bits), rp1 (Low Order 16 Bits), = AXx rp a7 DIVUX rpt AXDE (Quotient), rp1 (Remainder) < AXDE + rp! 3 ING ri marist saddr (saddr) < (saddr) + 1 DEC nm<ri-i saddr (saddr) <~ (saddr) 1 >< | >< | oe | OS >< | >< | ><] OK | ><] | <j<)<[< afer Ola INCW rp2 rp2 < rp2+1 saddrp (saddrp) < (saddrp) + 1 DECW rp2 rp2 < rp21 saddrp (saddrp) < (saddrp) 1 ROR rin (CY, r17 < rig; Mm1*7 Mm) x0 +1 al ola|o |] om] co] | co = po] clo] otm!] me) ROL rin (CY, rg < F117; Mimi Am) x0 4+3n RORC rio (CY rp; ri7< CY; Mm 1< Mm) xn 4+3n ROLC rin (CY rz; 1g < CY; Wm +147 tm) xn 4+38n SHR rin (CY = rp; 117 0; Mm 14- im) xn 4+3n SHL ri,n (CY < riz; Tip <0; . m1 tm) xn 4+ 3n SHRW SHLW RORA ROL4 ADJ4 4-194 rpi,n rpi,n (rp) (rp1) (CY < po; pip 0; Pm 1* TPm) x0 (CY < rp4s; rp <0; - Pm +4 Pm) x0 A3-9 + (rpt)3-0; (rpt)7-4 < Ag9; (Fp1) 3-9 + (rpt}7-4 A3o = (6p 1)7-4; (rp1)39 + Ago; (rpi)7-4 (rp1)3-9 Decimal Adjust Accumulator 4+3n 4+3nNE C ELECTRONICS INC 498 NEC DEB bue7ses 0013482 a o 7~-F?P-/ 9-08 UPD78310/312 6427525 N E C ELECTRONICS INC _p> 98D 13482 instruction Set (cont) : Flags Mnemonic Operand Operation States Bytes | Zz AC P/V CY MOV CY, saddr.bit CY (saddr.bit) 6 3 xX CY, sfr.bit CY sfr.bit 6 3 Xx CY, A.bit CY Avbit 6 2 x CY, X.bit CY Xbit 6 2 X CY, PSWH, bit CY PSW,,. bit 6 2 X CY, PSWL, bit CY PSW,.bit 6 2 x saddr.bit, CY (saddr.bit) CY 7 3 str.bit, CY sfr.bit CY 7 3 A.bit, CY A.bit CY 8 2 X.bit, CY X.bit CY 8 2 PSWH.bit, CY PSWy.bit CY 8 2 PSWL.bit, CY PSWL.bit CY 8 2 ANDi CY, saddr.bit CY CY A (saddr.bit) 6 3 Xx : CY,/saddr.bit CY CYA (saddr.bit) 6 3 X CY, sfr.bit CY CYA sfr.bit 6 3 xX CY,/sfr.bit CY CY Asfr.bit 6 3 x CY, A.bit CY CY AADit 6 2 X CY,/A.bit CY CY AADIt 6 2 Xx CY, X.bit CY CY AX.bit 6 2 Xx CY,/X.bit CY CYAXbit 6 2 X CY, PSWH.bit CY CY A PSWy,.bit 6 2 X CY,/PSWH.bit CY CY A PSWy.bit 6 2 X CY, PSWL.bit CY CY APSW_.bit 6 2 X CY,/PSWL.bit CY CY A PSWL.bit 6 2 X ORi CY, saddr.bit CY CY V (saddr.bit) 6 3 X CY,/saddr.bit CY = CY V (saddr.bit) 6 3 xX CY, sfr.bit CY CY V sfr.bit 6 3 X CY,/sfr.bit CY CY V sir.bit 6 3 X CY, A.bit CY CY VALbit 6 2 X CY,/A.bit CY CYVADit 6 2 x CY, X.bit CY CYV Xbit 6 2 X CY/X.bit CY + CYVXbit 6 2 Xx CY, PSWH.bit CY CY V PSWy,.bit 6 2 X CY,/PSWH.bit CY CY VPSWy.bit 6 2 X CY, PSWL.bit CY CY V PSW.bit 6 2 x CY,/PSWL.bit CY CY V PSW__.bit 6 2 X 4-195NE C ELECTRONICS INC 14 TS b427525 GO1d483 O T 7-7 ?-79-0 NEC pPD78310/312. 6427525 N E C ELECTRONICS INC D 98D 13483 instruction Set (cont) _ : Flags Mnemonic - Operand ~~ Operation States Byles s AC P/v SUB CY XOR1 CY, saddr.bit CY + CY (saddr.bit) 6 X CY, sfr.bit CY CY sfr.bit 6 3 xX CY, A.bit CY CY Abit 6 2 X CY, X.bit ; CY CY X bit 6 2 X . CY, PSWH.bit CY < CY - PSW}.bit 6 2 X _ CY, PSWL.bit | CY CY- PSW_.bit 6 2 X SET1 _ saddr.bit (saddr.bit) < 1 5 2.5 ___ Sfr.bit sfr.bit 1 6 3 Abit Abit <- 1 7 2 X.bit X.bit< 7 7 2 PSWH.bit ; PSWy. bit < 1 7 2 PSWL.bit _ PSW,bit<-1 7 2 CLR1 . saddr.bit (saddr.bit) < 0 5 2 _____sfr.bit str.bit 0 6 3 Abit Abit 0 7 2 X.bit Xbit 0 7 2 PSWH.bit PSWy.bit 0 7 2 PSWL.bit PSW_.bit <0 7 2 NOT1 . saddr.bit (saddr.bit) < (saddr.bit) 6 3 * _ Sfr.bit sfr.bit < sfr.bit 6 3 Abit Abit Abit 7 2 Xbit _ X. bit < X.bit 7 2 PSWH.bit PSWy. bit < PSW.bit 7 2 PSWL.bit PSW_.bit <- PSW,.bit 7 2 SETI oe cY+-1 3 1 1 CLAt ay cy +0 3 1 0 NOT1 cy CY CY 3 1 x CALL faddr16 (SP 1) <- (PC +-3)y; 8 3 - : (SP 2) (PC +3)L; PC < addr16; SP + SP -2 CALLF _ taddr (SP 1) < (PC + 2)y; 8 2 (SP 2) (PC + 2): - -- PC = addrtt; SP SP2 CALLT {addr5) (SP 1) < (PC + Ty: 10 1 (SP 2) < (PC + 1)L; PCy < (TPFX8000H + addr5 + 1); L PCy < (TPFXB000H + addr5); SP SP~2 4-196$50 ft anmanamninaaane NE C ELECTRONICS INC 98 DEB} b427s25 OOLayaY 1 i NEC 6427525 N E C ELECTRONICS INC instruction Set (cont) D 7 SP-19-0O8 1pp78310/312 S8D 13484 Mnemonic -- Oparand Operation States Bytes Flags z AC P/V SUB) sCY CALL rpi (SP 1) < (PC +2); (SP 2) (PC + 2); PCy < rp ty: PCL = tpt: SP SP2 13 2 (tpt) (SP 1) (PC + 2)y: (SP ~ 2) (PC + 2),; PCy = (rpt)y; PCL (rp1),; SP < SP~2 11 BRK (SP 1) PSWy; (SP ~ 2) PSWi: (SP3) ~(PC-+ 1); (SP ~ 4) + (PC + 1),: PCL (003EH); PCH < (003FH): SPSP4 16 RET PC, =~ (SP); PCH + (SP + 1); SP <-SP+2 RETI PC, = (SP); PCy < (SP + 1); PSW, <~ (SP +2); PSWy =~ (SP +3); SP =~ SP +4; EOS 0 14 PUSH post ((SP 1) posty; (SP 2) = post,; SP < SP2)xn. 7+6n PSW (SP 1) PSWy; (SP 2) + PSW; SP SP2 PUSHU post ((UP 1) posty: (UP 2) < post; UP < UP2)xn. 8+8n POP - post (post, + (SP); (posty (SP + 1); SP<=SP+2)xn. . 7+8n PSW PSWL + (SP); PSWy + (SP + 1); SP SP +2 POPU post (post, < (UP); posty < (UP + 4); UP = UP+2)xn. 8+8n MOVW SP, #word SP = word SP, AX SP < AX AX, SP AX = SP = INCW SP SP SP+1 DECW SP SP SP1 Dim] a] cj ow NL MPR)! & 4-197NE C ELECTRONICS INC 48 DEM bue7Ses OOL34as 3 Lr 6427525 N E C ELECTRONICS INC pPD78310/312 ? 98D 13485 NEC Instruction Set (cont) : 7-S9-19-OF Flags Mnemonic - Operand Operation ~~ States Bytes s Zz AC )80OP/VSs SUB) OCC BR laddri6 PC < addri6 4 3 rpi PCH rp ty: 6 2 PC, rpit: (rp1) PCy <= (rp) Hi 9 2 PCL < (rp thus oT $addri6 PG < addr16 7 2 id $addri6 PC < addri6 ifCY=i1 7(3) 2 BNC Saddri6 PC < addri6 If CY =0- 7(3) - 2 BNL 4 $addri PC < addri6 if Z=1 73) 2 BNZ $addri PC < addri if Z=0 7(8) 2 BNE BV $addri6 PC < addr16 if P/V = 1 7(3) 2 BPE BNV _ Saddri PC = addri6 if P/V =0 7(3) 2 BPO 2 . . BN $addri6 PC addri6 if S =1 73) 2 BP $addri PC + addri6 if S =0 7(3) 2 BGT Saddr16 PC < addri if (P/V- S)VZ=0 9(5) 3 BGE Saddri6 - - PC addri6 if P/VS=0 9(5) 3 BLT $addri6 PC < addri6 if P/VS=1 9(5) 3 BLE . $addri PC addri6 if (P/V S)VZ=1 9(5) 3. BH Saddri6 PC < addri6 ifZ + CY =0 9(5) 3 BNH $addri6 PC < addri6 if Z + CY =1 9(5) 3 BT saddr.bit, $addri6 PC < addr16 if (saddr. bit) = 1 97) 3. sfr.bit, $addr16 PC < addri6 if (sfr.bit) = 1 70(7) 4 -- Abit, $addri6 - PC < addri if A.bit =1 10(7) 3 X.bit, $addri6 PC addri6 if X.bit = 1 40(7) 3 PSWH.bit, $addrt6 PC < addri6 if PSWy.bit = 1 10(7) 3 PSWL.bit, $addri6 PC addri6 if PSW_.bit = 1 10(7) 3 BF saddr.bit, $addr16 PC < addr16 if (saddr.bit) =0 10(7) 4 : sfr.bit, $addri6 PC addri6 if (sfr.bit) = 0 40(7) 4 A bit, $addr16 PC < addri6 if A.bit =0 10(7) 3 X.bit, $addr1 PC addri6 if X.bit =0 10(7) 3 PSWH.bit, $addr16 PC < addri6 if PSWy.bit =0 10(7) 3 > PSWL.bit, $addri6 PC < adadr16 if PSW_-bit =0 10(7) 3 BTCLR saddr.bit, $addr16 PC. < addri6 if (saddr.bit) = 1 12(7) 4 . then reset (saddr. bit) ____._ Strbit, $addr16 PC = addri6:if (sfr.bit) = 1 27) 4 then reset (sfr.bit) A.bit, $addr16 PC addri6 if A.bit = 1 11(7) 3 then reset A.bit 4-198FrtctaSeson NE C ELECTRONICS INC 94 DER b4e?ses UULI4SE S I 7-SF-/53 -o x NE Cc 4UPD78310/312 ~~ 6427525 NEC ELECTRONICS INC D 98D 13486 Instruction Set (cont) -- : ; + / Flags Mnemonic ~.- Operand = - Operation : States Bytes s 2 AC - P/V SUB BICLR X. bit, $addr16 PC <~ addri6 if X.bit= 1 17) - 3 (cont) then reset X.bit : : PSWH. bit, Saddri6 PC = addri6 if PSWy.bit = 1 12(7) 3 then reset PSWy.bit PSWL.bit, $addr16 PC < addr6 if PSWL.bit = 1 12(7) 3 then reset PSW_.bit BFSET saddr.bit, $addri6 PC <= addri6 if (saddr.bit) =0 12(7) 4 then set (saddr.bit) - str.bit, $addri6 PC < addr'6 if (sfr.bit) = 0 f2(7). 4 then set (sfr.bit) : A. bit, $addr16 PC = addr16 if A.bit =0 11(7) 4 then set A.bit X.bit, $addri6 PC <~ addri6 if X.bit =0 11(7) 3 then set X.bit PSWH. bit, $addri6 PC <= addri6 if PSWy.bit = 0 12(7) 3 then set PSWp.bit : : PSWL.bit, $addri6 PC = addri6 if PSW, bit =0 12(7) 3 then set PSW,.bit DBNZ r2, $addri6 212-1; 8(5) 2 then PC < addr16 if r2#0 saddr, $addr 16 (saddr) < (saddr) ~ 1; 7(6) 3 then PC addri6 if saddr +0 : . BRKCS RBn PCy > RS; 13 2 PC, ~> Rd; R7 <> PSWy; R6 < PSW_; RBS2-0 < n; RSS < 0; IE-0 RETCS laddri6 PCy < R5; 6 3 PC, <= Rd; Rd, R5 < (addr 16); PSWy R7; PSW: = R6; E0S <0 . MOVM (DE+), A (DE+) A; -2+7n (2 . C-C1,EndifC=0 (DE-), A (DE) A; . 2+7n 2 C+-C1, EndifC=0 . MOVBK (DE+), (HL+) (DE+) (HL+); 2+10n 2 uo C-C1,EndifC=0 (DE), (HL-) (DE) (HL); 2+ 10n 2 C-C1,EndifC=0 XCHM (DE+), A (DE+) <> A; 2+ 12n 2 C+-Ci,EndifC=0 - (DE) < A; - 2+12n- 2: (DE-), A C~-C1, End ifC=0 4-199NE C ELECTRONICS INC 44 Dey b4275eS DUOLSA4h? i NEC pPD78310/312 6427525 N & C ELECTRONICS INC > 98D 13487 Instruction Set (cont) rs JF- ( ?- o - Flags Mnemonic | Operand Operation - States Byles AC PY 6 SUB- CY XCHBK (DE+), (HL+) (DE+) > (HL+); 2+15n. 2 C<+C1,EndifC=0 , (DE-), (Hi-) (DE-) <> (HL-); 2+ 16n 2 _ __ CMPME (DE+), A (DE+) 2+8n 2 xX Vv 1 x oo. OorZ=0 : (DE-), A (DE) 2+68n 2 xX V 1 X- ae End if =QorZ=0 : GMPBKE (DE+), (Hi+) (DE+) (HL+); 2+1in ~ 2 x V 1 xX C-C1,EndifC=00rZ=0 (DE-), (HL) (DE-) (HL-); 2+tin 2 xX V 1 X ao OorZ=0 CMPMNE (DE+), A (DE+) 2+ 8n 2 - Xx v 1 X <-C- M endif = OorZ=1 (DE-), A (DE) 2+8n 2 x V 1 xX . eo end ite OorZ=1 CMPBKNE (DE+), (HL-+) (DE+) (HL+); 2+ 11n 2 x V 1 x C-C-1,EndifC =OorzZ=1 (DE-), (HL) (DE-) -- (HL); 24+1in 2 x Vv 1 x ao OorZ=1 CMPMG (DE+), A (DE+) - 2+8n 2 4 v 1 Xx ee M endifC= OorcY=0 {DE-), A (DE-) - 2+8n 2 xX V 1 -X PE, endif = Oorcy=0 : CMPBKG (DE+), (HL+) (DE+) (HL+); 24+ 1in 2 4 V 1 X C<+G-1,EndifC =O0orCY =0 (DE-), (HL) {DE) (HL-); 2+1in 2 x Vv 1 x Oorcy=0 CMPMNG (DE+), A (DE+) 2+8n 2 x V 1 xX ae End if C =0 or CY =1 (DE), A (DE) A; 2+8n 2 x v 1 xX CC1, End ifC=0orCY=1 CMPBKNG (DE+), (HL-+) (DE+) (HL+); 2+11n 2 x V 1 x i 7 CC-1,End if =0orCY=1 (DE-), (HL) (DE) (HL) 2+11n 2 x V 1 4 ~ Pee ete= OorCY=1 MOV STBC, #byte STBC = byte 5 4 WOM, #byte WDM <= byte mt 5 4 SWRS RSS ASS . 3 1 SEL RBn RSS <- 0; 3 2 - : . RBS2-0 <n . RBn, ALT RSS <- 1; 3 2 - RBS2-0 <n - NOP No Operation 3 1 El 1E < 1 (Enable Interrupt) 3 1 Dl IE 0 (Disable Interrupt 1 4-200