General Description
The MAX19710–MAX19713 evaluation systems (EV
systems) consist of MAX19710–MAX19713 evaluation
kits (EV kits), a companion Maxim command module
(CMODUSB) interface board, and software. Order the
complete EV system (see the
Ordering Information
) for
comprehensive evaluation of the MAX19710–MAX19713
using a personal computer. Order the EV kit if the
command module has already been purchased with a
previous Maxim EV system, or for custom use in other
microcontroller-based (µC) systems.
The MAX19710–MAX19713 EV kits are fully assembled
and tested PCBs that contain all the components
necessary to evaluate the performance of the
MAX19710–MAX19713 analog front-ends (AFEs).
These AFEs integrate a dual-receive analog-to-digital
converter (Rx ADC), a dual-transmit digital-to-analog
converter (Tx DAC), a 1.024V internal voltage refer-
ence, three low-speed serial DACs, and one low-speed
serial ADC. The EV kit boards accept AC- or DC-
coupled, differential or single-ended analog inputs for
the Rx ADC and include circuitry that converts the Tx
DAC differential output signals to single-
ended analog outputs. The EV kits include circuitry that
generates a clock signal from an AC sine-wave input
signal. The EV kits operate from a +3.0V analog power
supply, a +1.8V digital power supply, a +3.0V clock
power supply, and ±5V bipolar power supplies.
The Maxim command module interface board
(CMODUSB) allows a PC to use its USB port to emulate
an SPI™ 3-wire interface. Windows®98SE/2000/XP-
compatible software, which can be downloaded from
www.maxim-ic.com/evkitsoftware, provides a user-
friendly interface to exercise the features of the
MAX19710–MAX19713. The program is menu driven
and offers a graphical user interface (GUI) with control
buttons and a status display.
SPI is a trademark of Motorola, Inc.
Windows is a registered trademark of Microsoft Corp.
Features
♦ADC/DAC Sampling Rates from 7.5Msps to
45Msps
♦Low-Voltage and Low-Power Operation
♦Adjustable-Gain, Low-Speed DAC Buffers
♦On-Board Clock-Shaping Circuitry
♦On-Board Level-Translating I/O Drivers
♦Assembled and Tested
♦Downloadable Windows 98SE/2000/XP-Compatible
Software
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
________________________________________________________________
Maxim Integrated Products
1
19-0691; Rev 1; 6/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Part Selection Table
Ordering Information
MAX19710–MAX19713 EV Kit
Software Files
+
Denotes a lead-free and RoHS-compliant EV Kit.
*
This limited temperature range applies to the EV kit PCB only. The
MAX19710–MAX19713 IC temperature range is -40°C to +85°C.
**
EP = Exposed paddle.
Note: The MAX19710–MAX19713 EV kit software is available
online; however, the CMODUSB board is required to interface
the EV kit to the computer when using the software.
*
EV Kit software dependant.
PART TEMP
RANGE*
IC
PA CK A G E
SPI
IN TER F AC E
T YPE
MAX19710EVKIT+0°C to
+70°C
56 TQFN-
EP**
Not
included
M A X1 9 7 10 EVCM O D U+
0°C to
+70°C
56 TQFN-
EP**
CMODUSB
MAX19711EVKIT+0°C to
+70°C
56 TQFN-
EP**
Not
included
M A X1 9 7 11 EVCM O D U+
0°C to
+70°C
56 TQFN-
EP**
CMODUSB
MAX19712EVKIT+0°C to
+70°C
56 TQFN-
EP**
Not
included
M A X1 9 7 12 EVCM O D U+
0°C to
+70°C
56 TQFN-
EP**
CMODUSB
MAX19713EVKIT+0°C to
+70°C
56 TQFN-
EP**
Not
included
M A X1 9 7 1 3 EVC M O D U +
0°C to
+70°C
56 TQFN-
EP**
CMODUSB
PART
SPEED (Msps)
Tx CDMA FILTERS
MAX19710EVKIT+
7.5 No
MAX19711EVKIT+
11 Yes
MAX19712EVKIT+
22 No
MAX19713EVKIT+
45 No
PROGRAM DESCRIPTION
INSTALL.EXE Installs the EV kit software
M AX 19710.E X E , M AX 19711.E X E ,
M AX 19712.E X E , MAX19713.EXE
Application program*
UNINST.INI U ni nstal l s the E V ki t softw ar e
TRO U BLE S H OOTIN G _U S B.P D F
USB driver installation
help file
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
2 _______________________________________________________________________________________
Common Component List
DESIGNATION QTY
DESCRIPTION
C1–C6, C17, C21,
C23, C24, C25, C28,
C29, C37–C40,
C45–C48, C73–C76,
C78, C80, C81
28
0.1µF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
C7–C10
4
22pF ±5%, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H220J
C11, C31–C36 0
Not installed, capacitors (0402)
C12
0
Not installed, capacitor (0603)
C13, C14, C82 3
1000pF ±5%, 50V C0G ceramic
capacitors (0603)
TDK C1608C0G1H102J
C15, C16
2
0.33µF ±10%, 10V X7R ceramic
capacitors (0603)
Murata GRM188R71C334K
C18, C19, C20,
C67–C72
9
1.0µF ±20%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105M
C22,
C26, C27
3
0.1µF ±20%, 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
C30, C41–C44,
C77, C84
7
2.2µF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J225M
C49–C60
12
220µF ±20%, 6.3V tantalum
capacitors (C-case)
AVX TPSC227M006R0250
C61–C66
6
10µF ±20%, 10V X5R ceramic
capacitors (1210)
TDK C3225X5R1A106M
C79
1
0.01µF ±5%, 25V C0G ceramic
capacitor (0603)
TDK C1608C0G1E103J
C83
1
0.33µF ±10%, 10V X5R ceramic
capacitor (0402)
Murata GRM155R61A334K
CLOCK, IA, IAN,
IAP, ID, QA, QAN,
QAP, QD
9
SMA PC mount connectors
D1
1
Dual Schottky diode (SOT23)
C entr al S em i cond uctor C M P D 6263S
Vishay BAS70-04
Diodes Inc BAS70-04
J1
1
2 x 20 right-angle female connector
DESIGNATION QTY
DESCRIPTION
J2
1
Dual-row, 40-pin header
J3
1
Dual-row, 20-pin header
J4, J5, JU2
3
2-pin headers
JU1
1
Jumper, dual-row, 8-pin header
JU3
1
Jumper, 3-pin header
R1–R4, R55,
R56, R61
7
49.9Ω ±1% resistors (0603)
R5–R16, R37–R42 0
Not installed, resistors (0402)
R17–R20
4
24.9Ω ±1% resistors (0402)
R21–R36,
R43–R46, R62, R66 0
Not installed, resistors (0603)
R47–R54
8
10kΩ ±1% resistors (0603)
R57, R58
2
4.02kΩ ±1% resistors (0603)
R59
1
6.04kΩ ±1% resistor (0603)
R60
1
2.0kΩ ±1% resistor (0603)
R63
1
5kΩ potentiometer, 19-turn, 3/8in
RA1–RA2
2
Panasonic EXB-2HV-101J
RA3–RA6
4
Panasonic EXB-2HV-510J
T1, T2
2
1:1 RF transformers
Coilcraft TTWB3010-1L
TP1–TP4
4
Test points (red)
TP5
1
Test point (black)
U1
1
Note: See the EV Kit-Specific
Component List
U2
1
16-bit buffer/driver
(48-pin TSSOP)
Texas Instruments
SN74ALVCH16244DGGR
U3
1
Dual LVDS line receiver
Maxim MAX9113ESA+ (8-pin SO)
U4, U5
2
400M H z ul tr a- l ow - d i stor ti on op am p s
Maxim MAX4108ESA+ (8-pin SO)
U6
1
Low-noise, low-distorion, wide-
band, rail-to-rail op amp
Maxim MAX4478AUD+ (14-pin
TSSOP)
_______________________________________________________________________________________ 3
Quick Start
Recommended Equipment
• DC power supplies:
Analog (VDD) +3.0V, 100mA
Clock (CVDD) +3.0V, 100mA
Digital (OVDD) +1.8V, 100mA
Op-amp positive (VOP) 5.0V, 250mA
Op-amp negative (VON) -5.0V, 250mA
• Signal generator with low phase noise and low jitter
for clock input signal (e.g., HP/Agilent 8662A,
HP/Agilent 8644B)
• Two signal generators with low phase noise for ana-
log signal inputs (e.g., HP/Agilent 8662A, HP/Agilent
8644B)
• Logic analyzer or data-acquisition system with one
data pod (e.g., HP/Agilent 16500C, TLA621)
• Analog bandpass filters (e.g., Allen Avionics, K&L
Microwave) for input and clock signal
• Two spectrum analyzers (e.g., HP/Agilent 8560E)
• One digital pattern generator with one 10-bit data
pod (e.g., Tektronix DG2020A)
Procedure
The MAX19710–MAX19713 EV kits are fully assembled
and tested surface-mount boards. Follow the steps below
to verify board operation. Caution: Do not turn on
power supplies or enable signal/data generators until
all connections are completed.
Note: In the following sections, software-related items
are identified by bolding. Text in bold refers to items
directly from the EV kit software. Text in bold and
underlined refers to items from the Windows
98SE/2000/XP operating system.
Command Module Setup (CMODUSB)
1) Visit the Maxim website (www.maxim-ic.com/evkit-
software) to download the latest version of the EV
kit software. Save the EV kit software to a temporary
folder and uncompress the ZIP file.
2) Install the EV kit software on your computer by run-
ning the INSTALL.EXE program inside the temporary
folder. The program files are copied and icons are
created in the Windows Start | Programs menu.
3) Place a shunt across pins 2-3 of the VDD select
jumper (command module working voltage set
to 3.3V).
4) Connect a USB cable from the computer’s USB
port to the command module (CMODUSB) interface
board. Use a standard USB A-B cable. A Building
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
Component Suppliers
EV Kit-Specific Component List
Common Component List
(continued)
DESIGNATION
QTY
DESCRIPTION
U7
1
Quad-level translator
M axi m MAX 3023E UD + (14- pi n TS S OP)
—
6
Shunts
—
1
PCB: MAX19710/1/2/3
Evaluation Kit+
SUPPLIER PHONE WEBSITE
AVX Corp.
843-946-0238
www.avxcorp.com
Central
Semiconductor
631-435-1110
www.centralsemi.com
Coilcraft
847-639-6400
www.coilcraft.com
Diodes Inc.
805-446-4800
www.diodes.com
Murata
770-436-1300
www.murata.com
Panasonic
714-373-7366
www.panasonic.com
TDK Corp.
847-803-6100
www.component.tdk.com
Vishay
203-268-6261
www.vishay.com
EV KIT PART
NUMBER
D ESIG N AT IO N
DESCRIPTION
M AX19713E V KIT+
Maxim MAX19713ETN+ ( 56-
p i n, 7mm x 7m m Thi n QFN- E P )
MAX19712EVKIT+
Maxim MAX19712ETN+ ( 56-
p i n, 7mm x 7m m Thi n QFN- E P )
MAX19711EVKIT+
Maxim MAX19711ETN+ ( 56-
p i n, 7mm x 7m m Thi n QFN- E P )
MAX19710EVKIT+
U1
Maxim MAX19710ETN+ ( 56-
p i n, 7mm x 7m m Thi n QFN- E P )
Note: Indicate that you are using the MAX19710, MAX19711,
MAX19712, or MAX19713 when contacting these component
suppliers.
MAX19713EVCMODU
(MAX19713 EV System)
Component List
PART QTY DESCRIPTION
CMODUSB 1 SPI interface board
MAX19713EVKIT+ 1 MAX19713 EV kit
Evaluate: MAX19710–MAX19713
Driver Database window appears in addition to a
New Hardware Found message if this is the first
time the EV kit board is connected to the PC. If you
do not see a window that is similar to the one
described above after 30 seconds, remove the USB
cable from the CMODUSB and reconnect it.
Administrator privileges are required to install the
USB device driver on Windows 2000/XP. Refer to
the document TROUBLESHOOTING_USB.PDF
included with the software if you have any problems.
5) Follow the directions of the Add New Hardware
Wizard to install the USB device driver. Choose the
Search for the best driver for your device option.
Specify the location of the device driver to be
C:\Program Files\MAX19713, \MAX19712,
\MAX19711, or \MAX19710 (default installation
directory) using the Browse button.
EV Kit Setup
6) Verify that shunts are installed in the following locations:
JU1 (1-2) →CS connected
JU1 (3-4) →SCLK connected
JU1 (5-6) →DIN connected
JU1 (7-8) →DOUT connected
JU2 (Installed) →Internal reference enabled
JU3 (1-2) →Power U2 with OVDD
7) Connect a +3.0V, 100mA power supply to VDD.
Connect the ground terminal of this supply to GND.
8) Connect a +3.0V, 100mA power supply to CVDD.
Connect the ground terminal of this supply to GND.
9) Connect a +1.8V, 100mA power supply to OVDD.
Connect the ground terminal of this supply to OGND.
10) Connect a +5V, 250mA power supply to VOP.
Connect the ground terminal of this supply to GND.
11) Connect a -5V, 250mA power supply to VON.
Connect the ground terminal of this supply to GND.
12) Carefully align the 40-pin connector of the EV kit
(J1) with the 40-pin header of the CMODUSB inter-
face board (P4). Gently press them together.
13) The MAX19710–MAX19713 support two modes of
operation:
a. To connect a logic analyzer to the EV kit and
test the Rx ADCs, skip to step 14.
b. To connect a spectrum analyzer to the EV kit
and test the Tx DACs, skip to step 34.
Rx ADC Setup
14) Connect the clock signal generator to the input of
the clock bandpass filter.
15) Connect the output of the clock bandpass filter to
the EV kit SMA connector labeled CLOCK.
16) Connect the first analog signal generator to the
input of the desired bandpass filter.
17) Connect the output of the bandpass filter to the EV
kit SMA connector labeled IA (I channel).
18) Connect the second analog signal generator to the
input of the desired bandpass filter.
19) Connect the output of the bandpass filter to the EV
kit SMA connector labeled QA (Q channel).
20) Ensure that all signal generators are phase-locked to a
common reference frequency for coherent sampling.
21) Connect the logic analyzer to J2. Use the bit labels
(AD_) located next to header J2 for proper bit align-
ment or see the
Digital Data Bit Locations
section
for header connections.
22) Set the logic analyzer to capture 10-bit CMOS data
on the falling edge for the I channel or the rising
edge for the Q channel.
23) Turn on the -5V power supply.
24) Turn on all remaining power supplies.
25) Enable the signal generators.
26) Set the clock signal generator to output a 45MHz
signal. The amplitude of the generator should
be sufficient to produce a +16dBm signal at the SMA
input of the EV kit. Insertion losses due to the
series-connected filter (step 14) and the inter-
connecting cables decrease the amount of power
seen at the EV kit input. Account for these losses
when setting the signal generator amplitude.
27) Set the analog input signal generators to output the
desired frequency. The amplitude of the generator
should produce a signal that is no larger than
+5dBm, as measured at the SMA input of the EV kit.
Insertion losses, due to the series-connected filters
(steps 17 and 19) and the interconnecting cables,
decrease the amount of power seen at the EV kit
input. Account for these losses when setting the
signal generator amplitude.
28) Start the MAX19710–MAX19713 program by open-
ing its icon in the Start menu.
29) Normal device operation can be verified by the Status:
Interface Board Operational text in the Interface box
of the program.
30) Select the Maxim device that you are using from the
Device combo box.
31) Click the POR Reset button on the EV kit software
GUI.
32) Enable the logic analyzer.
33) Capture data using the logic analyzer.
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
4 _______________________________________________________________________________________
Tx DAC Setup
34) Connect the clock signal generator to the input of
the clock bandpass filter.
35) Connect the output of the clock bandpass filter to
the EV kit SMA connector labeled CLOCK.
36) Connect the output of the clock signal generator to
the data generator synchronization input.
37) Connect the first spectrum analyzer to the EV kit
SMA connector labeled QD (Q channel).
38) Connect the second spectrum analyzer to the EV kit
SMA connector labeled ID (I channel).
39) Connect the data generator to J3. Use the bit labels
(DA_) located next to header J3 for proper bit align-
ment, or see the
Digital Data Bit Locations
section
for header connections.
40) Turn on the -5V power supply.
41) Turn on all remaining power supplies.
42) Enable the signal generator.
43) Set the clock signal generator to output a 45MHz
signal. The amplitude of the generator should be
sufficient to produce a +16dBm signal at the SMA
input of the EV kit. Insertion losses, due to the
series-connected filter (step 34) and the intercon-
necting cables, decrease the amount of power
seen at the EV kit input. Account for these losses
when setting the signal generator amplitude.
44) Load the desired test pattern into the data generator.
Data clocked on the rising edge of the clock is trans-
mitted to the Q channel. Data clocked on the falling
edge of the clock is transmitted to the I channel.
45) Start the MAX19710–MAX19713 program by open-
ing its icon in the Start menu.
46) Normal device operation can be verified by the
Status: Interface Board Operational text in the
Interface box.
47) Select the Maxim device that you are using in the
Device combo box.
48) Click the POR Reset button on the EV kit software
GUI.
49) Enable the data generator.
50) Enable the spectrum analyzers.
51) Analyze the data on the EV kit outputs (QD and ID)
with the spectrum analyzers.
Detailed Description of Software
User-Interface Panel
The user interface (Figure 1) is easy to operate; use the
mouse, or a combination of the Tab and arrow keys to
manipulate the software. Each of the buttons corre-
spond to bits in the command and configuration bytes
of the Maxim IC. By selecting them, the correct SPI
write operation is generated to update the internal reg-
isters of the MAX19710–MAX19713.
The software divides EV kit functions into logical
blocks. The Interface box indicates the Device, the
Register Address Sent, the Data Sent/Received for
the last write operation, and the SPI Clock Frequency.
This data is used to confirm proper device operation.
Adjust the SPI Clock Frequency through the combo
box. Use the Device combo box to select the proper
AFE and features.
The controls for the Tx DAC, Auxiliary DACs, and
Auxiliary ADC are accessed through tab sheets.
Device Control is accessed at the right-hand side of
the main window. Return the EV kit to its power-on-reset
state by selecting the POR Reset button.
The MAX19710–MAX19713 EV kit software features
additional functions to simplify operation. Automatic
Diagnostics probes the command module board to
make sure a connection exists between the PC and the
command module.
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
_______________________________________________________________________________________ 5
Figure 1. MAX19713 EV Kit Software Main Window
Evaluate: MAX19710–MAX19713
Device Control
Configure the operating mode of the device through the
intuitive controls in the Device Control box. Select a
mode, as outlined in the MAX19710, MAX19711,
MAX19712, MAX19713 data sheets, using the
Operating Mode control. For a detailed description of
the MAX19710–MAX19713 operating modes and their
specific names, refer to Table 4 in the MAX19710,
MAX19711, MAX19712, and MAX19713 data sheets.
The MAX19710–MAX19713 feature an 8-bit SPI signaling
mode to increase communications speed. Check the Use
Enable-8 Signaling checkbox to use this mode. Refer to
the MAX19710, MAX19711, MAX19712, and MAX19713
data sheets for more details on Enable-8 signaling.
Tx DAC Control
Adjust the Common Mode Voltage and the DAC Full
Scale voltage by selecting the desired option from the
pulldown box. Note that the DAC Full Scale control is
only available when using the MAX19711. The DAC full-
scale output of the MAX19710, MAX19712, and
MAX19713 is fixed. Refer to the respective data sheet for
more details.
The DAC I-Offset and Q-Offset voltages can be adjust-
ed in 800µV increments by adjusting the appropriate
slider in the Tx DAC Offset Control box. The
MAX19711 allows for two adjustable full-scale ranges
of 820mVP-P (yields 800µV increments), and a full-scale
range of 1.0VP-P (yields 980µV increments). The
MAX19710/MAX19712/MAX19713 only allow one full-
scale range of 800mVP-P, which yields 780µV incre-
ments. Alternatively, a value (specified in millivolts) can
be directly entered in the boxes below each slider. If no
value has been entered, 0.800/0.980 is used. The soft-
ware automatically rounds the number to the nearest
800µV/980µV increment and sends the proper data to
the MAX19710–MAX19713.
Auxiliary DAC Control
Access the MAX19710–MAX19713 auxiliary DACs
through the Auxiliary DACs tab of the EV kit software
(Figure 2). Set the output voltage of the desired auxiliary
DAC by adjusting the Aux-DAC 1, Aux-DAC 2, or Aux-
DAC 3 sliders. Enter a number in the edit box below the
slider for precise adjustments. Enable each DAC by
setting the checkbox below the slider.
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
6 _______________________________________________________________________________________
Figure 2. MAX19713 EV Kit Software Auxiliary DAC Control
Auxiliary ADC Controls
Access the MAX19710–MAX19713 auxiliary ADC through
the Auxiliary ADC tab (Figure 3) of the EV kit software.
Although these AFEs feature only one 10-bit, low-speed
ADC, they can multiplex four voltages onto their input.
Select the desired ADC Input Source in the ADC
Conversion box. Read the CODE and VOLTAGE of the
ADC by selecting the Start Conversion and Read ADC
Value button.
Other ADC features, such as ADC Averaging and
Conversion Clock Divide Ratio, are accessed
through the ADC Control box. Disable the auxiliary
ADC by checking the Shutdown Auxiliary ADC
checkbox. These AFEs can use either the Internal
2.048V reference or VDD (Internal VDD) for the auxil-
iary ADC reference. If VDD is used for the reference
voltage, enter the value of VDD in the box beside the
Internal VDD checkbox.
Simple SPI Commands
There are two methods for communicating with the
AFEs: through the normal GUI panel, or through the SPI
commands available by selecting the 3-Wire Interface
Diagnostic item from the Options pulldown menu. A
window is displayed that executes an SPI read/write
operation.
The SPI (3-Wire Interface) dialog box accepts numeric
data in hexadecimal format. Hexadecimal numbers
should be prefixed by a $ or 0x. Data entered in the
Data bytes to be written: edit box is sent to the
device. Eight-bit hexadecimal numbers should be
comma delimited. Data appearing in the Data bytes
received: box is data read from the device.
Selecting the Send Now button in Figure 4 transmits
the hexadecimal numbers 0x55 and 0xAA. 0x00 and
0x00 are the received values from the device. For a
detailed description of SPI communications, refer to the
MAX19710, MAX19711, MAX19712, and MAX19713
data sheets.
Detailed Description of Hardware
The MAX19710–MAX19713 EV kits are fully assembled
and tested PCBs that contain all the components nec-
essary to evaluate the performance of the MAX19710,
MAX19711, MAX19712, or MAX19713 AFEs.
The AFE’s receive ADCs (Rx ADCs) accept differential
input signals; however, on-board transformers (T1, T2)
convert a user’s single-ended source output to the
required differential signal. The input signals of the
MAX19710–MAX19713 are measured using a differential
oscilloscope probe at headers J4 and J5. A buffer/driver
(U2) buffers the parallel ADC digital output signals. The
digital ADC data is accessible at header J2.
The AFE’s transmit DACs (Tx DACs) are buffered with
on-board ultra-low-distortion, split-supply op amps.
The EV kits are designed as four-layer PCBs to optimize
the performance of the MAX19710–MAX19713.
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
_______________________________________________________________________________________ 7
Figure 3. MAX19713 EV Kit Software Auxiliary ADC Control
Figure 4. MAX19713 EV Kit Software 3-Wire Interface
Diagnostics
Evaluate: MAX19710–MAX19713
Separate analog, digital, clock, and buffer power planes
minimize noise coupling between analog and digital sig-
nals. Analog ADC inputs and DAC outputs use 100Ω
differential microstrip transmission lines, while 50Ω
microstrip transmission lines are used for all digital out-
puts and the clock input. The trace lengths of the ADC
input and DAC output paths are well matched to mini-
mize layout-dependent input-signal skew.
Power Supplies
For optimal performance, the MAX19710–MAX19713
EV kits require separate analog, digital, clock, and
buffer power supplies; however, two separate +3.0V
and +1.8V power supplies are recommended to power
the analog (VDD) and digital (OVDD) portions of the
AFEs, respectively. The clock circuitry (CVDD) is pow-
ered by a +3.0V power supply. The DAC outputs are
buffered by split-supply op amps. Power the positive
rail (VOP) with a +5V supply and the negative rail
(VON) with a -5V supply. A separate +1.8V power sup-
ply (BVCC) can be used to isolate the power source to
the buffer driver (U2). See Table 1 for the proper
jumper configurations for JU3.
If the OVDD current is measured at the OVDD and
OGND pads on the EV kit, a measurement error occurs
due to the extra current flowing into U2. Power U2
through BVCC for a more accurate measurement of the
OVDD current into the AFEs.
Clock
An on-board clock-shaping circuit generates a clock
signal from an AC sine-wave signal applied to the
CLOCK SMA connector. The frequency of the signal
should not exceed 45MHz for the MAX19713 (see the
Part Selection Table
for the maximum sampling rate of
other devices). The frequency of the sinusoidal input
signal determines the sampling frequency (fCLK) of the
AFEs. A differential line receiver (U3) processes the
input signal to generate the CMOS clock signal. The
signal’s duty cycle can be adjusted with potentiometer
R63. A clock signal with a 50% duty cycle (recom-
mended) is achieved by adjusting R63 until 1.32V is
produced across test points TP4 and TP5 when the
clock voltage supply (CVDD) is set to +3.0V. The clock
signal is available at J2-3 (CLKOUT), which can be used
to synchronize the output signal to the logic analyzer.
Measure the clock signal with an oscilloscope at TP3.
Rx ADC Inputs
Although the MAX19710–MAX19713 AFEs accept differ-
ential analog input signals, the EV kits only require a
single-ended analog input signal provided by the user.
Connect the single-ended sources to the IA SMA con-
nector (I channel) and QA SMA connector (Q channel).
Insertion losses due to series-connected bandpass
filters and the interconnecting cables decrease the
amount of power seen at the EV kit input. Account for
these losses when setting the signal generator
amplitude. On-board transformers (T1, T2) convert the
single-ended analog input signals and generate differ-
ential analog signals at the ADC’s differential input pins.
The AFEs also accept single-ended input signals. See
the
Configuring for Single-Ended ADC Operation
sec-
tion for details on how to modify the EV kits to support
this mode of operation.
Configuring for Single-Ended ADC Operation
The MAX19710–MAX19713 can be configured to
accept AC-coupled, single-ended signals presented at
the input. Configure the EV kit to support this mode of
operation by completing the following steps:
1) Cut open the traces at locations R11–R14.
2) Install 0Ωresistors at locations R7–R10, R15,
and R16.
3) Install 2kΩ±1% resistors at locations R21–R24.
4) Connect the single-ended sources to the IAP
connector (I channel) and/or to the QAP SMA
connector (Q channel).
Configure the EV kit for DC-coupled, single-ended sig-
nals by removing capacitors C1 and C2, removing resis-
tors R9 and R10, and installing 0Ωresistors at locations
R5 and R6.
Tx DAC Outputs
By default, on-board ultra-low-distortion op amps (U4 and
U5) buffer the DAC outputs on the MAX19710–
MAX19713 EV kits. The op amps convert the differential
signal from the AFEs to a single-ended 50Ωsignal.
Measure the buffered output signals at the QD SMA con-
nector (Q channel) and the ID SMA connector
(I channel).
Measure the differential output of the AFEs at the
IDN/IDP and QDN/QDP pads. Full-scale output, offset
voltage, and common-mode voltage functions are con-
trolled through the EV kit software.
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
8 _______________________________________________________________________________________
SHUNT
POSITION DESCRIPTION
1-2* U2 is powered through OVDD.
2-3 U2 is powered through BVCC.
(Note: BVCC must equal OVDD.)
*
Default configuration.
Table 1. U2 Power Source (JU3)
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
_______________________________________________________________________________________ 9
Reference
The MAX19710–MAX19713 feature two reference oper-
ation modes. The EV kits can be configured to use
either the internal (1.024V) reference or an external
user-supplied reference applied at the REFIN pad. The
AFEs generate the REFP and REFN voltages from the
selected reference voltage (refer to the MAX19710,
MAX19711, MAX19712, and MAX19713 data sheets for
more details). Measure the REFP and REFN voltages at
TP1 and TP2, respectively. Jumper JU2 controls the ref-
erence mode. See Table 2 for jumper configurations.
Digital Data Headers
The MAX19710–MAX19713 EV kits feature two 10-bit
parallel data buses used for full-duplex operation. The two
data buses are accessed on the EV kit through header
connectors J2 (Rx ADC bus) and J3 (Tx DAC bus).
Digital Data Bit Locations
Driver U2 buffers the digital outputs of the Rx ADC. This
driver is able to drive large capacitive loads, which may
be present at the logic analyzer connection. The out-
puts of the buffer are connected to a 40-pin header
(J2). The 20-pin header (J3) is used to connect to the
digital input of the Tx DAC. See Table 3 for bit locations
on headers J2 and J3.
Configuring the Low-Speed DAC Buffers
The MAX19710–MAX19713 EV kits feature on-board
configurable buffers. By default, these buffers are config-
ured for unity gain. Measure the buffered voltage at the
BDAC1, BDAC2, and BDAC3 pads. Measure the
unbuffered voltage at the DAC1, DAC2, and DAC3 pads.
SHUNT POSITION
DESCRIPTION
Installed* Internal reference mode.
Not installed
External reference mode.
Apply an external reference voltage to
the REFIN pad.
*
Default configuration.
Table 2. Reference Shunt Settings (JU2)
SIGNAL LOCATION TYPE DESCRIPTION
AD0 J2-37 Output Data Bit 0 (LSB)
AD1 J2-35 Output Data Bit 1
AD2 J2-33 Output Data Bit 2
AD3 J2-31 Output Data Bit 3
AD4 J2-29 Output Data Bit 4
AD5 J2-27 Output Data Bit 5
AD6 J2-25 Output Data Bit 6
AD7 J2-23 Output Data Bit 7
AD8 J2-21 Output Data Bit 8
AD9 J2-19 Output Data Bit 9 (MSB)
CLKOUT J2-3 Output Incoming Clock Signal
BDOUT J2-9 Output Aux-ADC Digital Output
(requires R38 short)
DA0 J3-19 Input Data Bit 0 (LSB)
DA1 J3-17 Input Data Bit 1
DA2 J3-15 Input Data Bit 2
DA3 J3-13 Input Data Bit 3
DA4 J3-11 Input Data Bit 4
DA5 J3-9 Input Data Bit 5
DA6 J3-7 Input Data Bit 6
DA7 J3-5 Input Data Bit 7
DA8 J3-3 Input Data Bit 8
DA9 J3-1 Input Data Bit 9 (MSB)
Note: Pins 1, 5, 7, 11, 13, 15, 17, and 39 of J2 are open. All other pins are connected to OGND.
Table 3. Digital Data Bit Locations
Evaluate: MAX19710–MAX19713
Configure the on-board buffers for a positive (noninverting)
gain by performing the following steps:
1) Cut open the trace at locations R31, R33, and R35.
2) Select a value of 10kΩfor resistors R32, R34, and
R36.
3) Calculate resistors R31, R33, and R35 using the
equations below.
4) Install R31, R33, and R35 in their respective locations:
where:
= Desired noninverting gain of buffer
R32 = R34 = R36 = 10kΩ
Driving Unbuffered Loads
The low-speed buffers (U6) on the EV kits are optional and,
if desired, can be disconnected from the DAC outputs of
the AFEs.
Disconnect the buffers from the AFEs by cutting the
trace at locations R28, R29, and R30. Connect the low-
speed DAC loads to the DAC1, DAC2, and DAC3 pads
on the EV kit. If the load capacitance is between 5pF
and 15pF, cut the trace and install 10kΩresistors at
locations R25, R26, and R27. Resistors are not required
if the load is less than 5pF.
Using an Alternative SPI Interface
The EV kits provide pads and jumpers that allow an
alternative SPI interface to be used. Connect the inter-
face to the CS, SCLK, DIN, DOUT, and OGND pads.
Ensure that the SPI voltages are compatible with all of
the AFE’s working voltages. Refer to the individual
MAX19710, MAX19711, MAX19712, and MAX19713
data sheets for suitable SPI interface voltages. Remove
the shunts from jumper JU1. See Table 4 for jumper
configurations.
BDAC
DAC
_
_
RRx
RRx
RRx
31 32
33 34
35 36
1
11
2
21
3
31
=−
⎡
⎣
⎢⎤
⎦
⎥
=−
⎡
⎣
⎢⎤
⎦
⎥
=−
⎡
⎣
⎢⎤
⎦
⎥
BDAC
DAC
BDAC
DAC
BDAC
DAC
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
10 ______________________________________________________________________________________
SHUNT POSITION
DESCRIPTION
1-2*
3-4*
5-6*
7-8*
Normal Operation.
Four shunts are installed across
pins 1-2, 3-4, 5-6, and 7-8.
Not installed
Alternative SPI Interface.
No shunts are installed on JU1, connect
the SPI signals to the CS, SCLK, DIN,
DOUT, and OGND pads.
*
Default configuration.
Table 4. Alternative SPI Interface (JU1)
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
______________________________________________________________________________________ 11
MAX4108
U4
MAX19710
U1
VDD
VR1
VR2
COM
R9
OPEN
R7
OPEN
R17
24.9Ω
1%
C5
0.1μFR15
OPEN
R19
24.9Ω
1%
R11
SHORT
R13
SHORT
R5
OPEN
IAP
C1
0.1μF
R6
OPEN
C2
0.1μF
R1
49.9Ω
1%
C7
22pF
C9
22pF
J4
IAP
IAN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OVDD
2
3
4
81139414751 24
VDD
OVDD
DVDD
VOP
VON
R2
49.9Ω
1%
IAN
IA
C3
0.1μFT1
1
2
3
6
5
4
R3
49.9Ω
1%
COM
R20
24.9Ω
1%
C6
0.1μF
R16
OPEN
R18
24.9Ω
1%
R14
SHORT
R12
SHORT
R8
OPEN
R10
OPEN
QAN
C10
22pF
C11
OPEN
C8
22pF
J5
QAN
QAP
CLK
9
10
6
REFP
1
C12
OPEN
REFN
REFIN
56
54
C15
0.33μF
C16
0.33μF
C13
1000pF
C14
1000pF
QAP
QA
C4
0.1μF
T2
1
2
3
6
5
4
R4
49.9Ω
1%
C17
0.1μF
C18
1.0μF
DVDD
C19
1.0μF
C20
1.0μF
VR2
R23
OPEN
R24
OPEN
VR1
TP1
JU2
TP2
R21
OPEN
R22
OPEN
CLK
COM
C31
OPEN
QDP 53
QDN 52
C33
OPEN
C35
OPEN
R43
OPEN
R45
OPEN
R51
10kΩ
1%
R39
OPEN
R41
OPEN
GNDN.C.
411
12 3
VMOD
VL
VCC
REFIN
QDP
C37
0.1μF
R47
10kΩ
1%
R49
10kΩ
1%
C39
0.1μF
QDN
COM
55
C82
1000pF
C83
0.33μF
JU1-1
JU1
JU1-3
38
COM
VMOD
MOSI
SCLKH
CSH
MISO
VMOD
DOUT
DOUT
CS
SCLK
SCLK
DIN
DIN
OGND
CS
CS
CS
SCLK 37 SCLK
DIN
JU1-5
JU1-7
I/OVL1
EN
I/OVL2
I/OVL3
I/OVL4
I/OVCC1
I/OVCC2
I/OVCC3
I/OVCC4
CSH
SCLKH
MOSI
MISO
JU1-2
1
7
2
5
6
14
13
10
9
8
JU1-4
JU1-6
JU1-8
36
5
7
12
40
50
23
DIN
GND
GND
GND
GND
GND
DGND
DOUT
DA9
34
DA8
33
DA7
32
DA6
31
DA5
30
DA4
29
DA3
28
DA2
27
DA1
26
DA0
25
DOUT 35
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
13
AD0
AD0
14
AD1
AD1
15
AD2
AD2
16
AD3
AD3
17
AD4
AD4
18
AD5
AD5
19
AD6
AD6
20
AD7
AD7
21
AD8
AD8
22
AD9AD9
DOUT1
J1
J1-1
J1-2
J1-3
J1-4
J1-7
J1-8
J1-36
J1-37
J1-38
J1-35
J1-5
J1-6
J1-9
J1-10
J1-11
J1-12
J1-13
J1-14
J1-15
J1-24
J1-23
J1-22
J1-21
J1-20
J1-19
J1-18
J1-17
J1-16
J1-25
J1-26
J1-27
J1-28
J1-29
J1-30
J1-31
J1-32
J1-33
J1-34
J1-39
J1-40
EN
R53
10kΩ
1%
R55
49.9Ω
1%
C41
2.2μF
C45
0.1μF
C43
2.2μF
C47
0.1μF
QD
2
8
4
7
6
5
3
VDD
C84
2.2μF
C22
0.1μF
C28
0.1μF
C23
0.1μF
C24
0.1μF
C25
0.1μF
C27
0.1μF
C26
0.1μF
MAX4108
U5
MAX4478
U6-B
VOP
VON
C32
OPEN
IDP 49
IDN 48
C34
OPEN
C36
OPEN
R44
OPEN
R46
OPEN
R37
SHORT
R38
OPEN
R52
10kΩ
1%
R32
OPEN
R40
OPEN
R42
OPEN
IDP
C38
0.1μF
R48
10kΩ
1%
R50
10kΩ
1%
C40
0.1μF
IDN
R54
10kΩ
1%
R56
49.9Ω
1%
C42
2.2μF
C46
0.1μF
C44
2.2μF
R25
SHORT
R31
SHORT
R28
SHORT
DAC1
BDAC1
C48
0.1μF
DAC1 46
DOUT
ID
28
4
7
6
5
5
6
7
2
3
R26
SHORT
R29
SHORT
DAC2
DAC2 45
MAX4478
U6-D
R36
OPEN
R27
SHORT
R35
SHORT
R30
SHORT
DAC3
BDAC3
DAC3
ADC1
44
43 ADC_IN1
ADC2 42 ADC_IN2
GND
12
13
14 MAX4478
U6-A
R34
OPEN
R33
SHORT
BDAC2
3
2
1
11
VOP C21
0.1μF
4
UNUSED AMPLIFIER
9
10
8
MAX4478
U6-C
OVDD
C29
0.1μF
C30
2.2μF
VOP
C49
220μF
6.3V
C50
220μF
6.3V
C61
10μF
C67
1.0μF
C51
220μF
6.3V
C52
220μF
6.3V
C62
10μF
C68
1.0μF
VOP
VON
VON
GND
VDD
C53
220μF
6.3V
C54
220μF
6.3V
C63
10μF
C69
1.0μF
VDD
GND
DVDD
C55
220μF
6.3V
C56
220μF
6.3V
C64
10μF
C70
1.0μF
DVDD
DGND
MAX3023
U7
Figure 5a. MAX19710 EV Kit Schematic (Sheet 1 of 2)
12 ______________________________________________________________________________________
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
MAX4108
U4
MAX19711
U1
VDD
VR1
VR2
COM
R9
OPEN
R7
OPEN
R17
24.9Ω
1%
C5
0.1μFR15
OPEN
R19
24.9Ω
1%
R11
SHORT
R13
SHORT
R5
OPEN
IAP
C1
0.1μF
R6
OPEN
C2
0.1μF
R1
49.9Ω
1%
C7
22pF
C9
22pF
J4
IAP
IAN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OVDD
2
3
4
81139414751 24
VDD
OVDD
DVDD
VOP
VON
R2
49.9Ω
1%
IAN
IA
C3
0.1μFT1
1
2
3
6
5
4
R3
49.9Ω
1%
COM
R20
24.9Ω
1%
C6
0.1μF
R16
OPEN
R18
24.9Ω
1%
R14
SHORT
R12
SHORT
R8
OPEN
R10
OPEN
QAN
C10
22pF
C11
OPEN
C8
22pF
J5
QAN
QAP
CLK
9
10
6
REFP
1
C12
OPEN
REFN
REFIN
56
54
C15
0.33μF
C16
0.33μF
C13
1000pF
C14
1000pF
QAP
QA
C4
0.1μF
T2
1
2
3
6
5
4
R4
49.9Ω
1%
C17
0.1μF
C18
1.0μF
DVDD
C19
1.0μF
C20
1.0μF
VR2
R23
OPEN
R24
OPEN
VR1
TP1
JU2
TP2
R21
OPEN
R22
OPEN
CLK
COM
C31
OPEN
QDP 53
QDN 52
C33
OPEN
C35
OPEN
R43
OPEN
R45
OPEN
R51
10kΩ
1%
R39
OPEN
R41
OPEN
GNDN.C.
411
12 3
VMOD
VL
VCC
REFIN
QDP
C37
0.1μF
R47
10kΩ
1%
R49
10kΩ
1%
C39
0.1μF
QDN
COM
55
C82
1000pF
C83
0.33μF
JU1-1
JU1
JU1-3
38
COM
VMOD
MOSI
SCLKH
CSH
MISO
VMOD
DOUT
DOUT
CS
SCLK
SCLK
DIN
DIN
OGND
CS
CS
CS
SCLK 37 SCLK
DIN
JU1-5
JU1-7
I/OVL1
EN
I/OVL2
I/OVL3
I/OVL4
I/OVCC1
I/OVCC2
I/OVCC3
I/OVCC4
CSH
SCLKH
MOSI
MISO
JU1-2
1
7
2
5
6
14
13
10
9
8
JU1-4
JU1-6
JU1-8
36
5
7
12
40
50
23
DIN
GND
GND
GND
GND
GND
DGND
DOUT
DA9
34
DA8
33
DA7
32
DA6
31
DA5
30
DA4
29
DA3
28
DA2
27
DA1
26
DA0
25
DOUT 35
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
13
AD0
AD0
14
AD1
AD1
15
AD2
AD2
16
AD3
AD3
17
AD4
AD4
18
AD5
AD5
19
AD6
AD6
20
AD7
AD7
21
AD8
AD8
22
AD9AD9
DOUT1
J1
J1-1
J1-2
J1-3
J1-4
J1-7
J1-8
J1-36
J1-37
J1-38
J1-35
J1-5
J1-6
J1-9
J1-10
J1-11
J1-12
J1-13
J1-14
J1-15
J1-24
J1-23
J1-22
J1-21
J1-20
J1-19
J1-18
J1-17
J1-16
J1-25
J1-26
J1-27
J1-28
J1-29
J1-30
J1-31
J1-32
J1-33
J1-34
J1-39
J1-40
EN
R53
10kΩ
1%
R55
49.9Ω
1%
C41
2.2μF
C45
0.1μF
C43
2.2μF
C47
0.1μF
QD
2
8
4
7
6
5
3
VDD
C84
2.2μF
C22
0.1μF
C28
0.1μF
C23
0.1μF
C24
0.1μF
C25
0.1μF
C27
0.1μF
C26
0.1μF
MAX4108
U5
MAX4478
U6-B
VOP
VON
C32
OPEN
IDP 49
IDN 48
C34
OPEN
C36
OPEN
R44
OPEN
R46
OPEN
R37
SHORT
R38
OPEN
R52
10kΩ
1%
R32
OPEN
R40
OPEN
R42
OPEN
IDP
C38
0.1μF
R48
10kΩ
1%
R50
10kΩ
1%
C40
0.1μF
IDN
R54
10kΩ
1%
R56
49.9Ω
1%
C42
2.2μF
C46
0.1μF
C44
2.2μF
R25
SHORT
R31
SHORT
R28
SHORT
DAC1
BDAC1
C48
0.1μF
DAC1 46
DOUT
ID
28
4
7
6
5
5
6
7
2
3
R26
SHORT
R29
SHORT
DAC2
DAC2 45
MAX4478
U6-D
R36
OPEN
R27
SHORT
R35
SHORT
R30
SHORT
DAC3
BDAC3
DAC3
ADC1
44
43 ADC_IN1
ADC2 42 ADC_IN2
GND
12
13
14 MAX4478
U6-A
R34
OPEN
R33
SHORT
BDAC2
3
2
1
11
VOP C21
0.1μF
4
UNUSED AMPLIFIER
9
10
8
MAX4478
U6-C
OVDD
C29
0.1μF
C30
2.2μF
VOP
C49
220μF
6.3V
C50
220μF
6.3V
C61
10μF
C67
1.0μF
C51
220μF
6.3V
C52
220μF
6.3V
C62
10μF
C68
1.0μF
VOP
VON
VON
GND
VDD
C53
220μF
6.3V
C54
220μF
6.3V
C63
10μF
C69
1.0μF
VDD
GND
DVDD
C55
220μF
6.3V
C56
220μF
6.3V
C64
10μF
C70
1.0μF
DVDD
DGND
MAX3023
U7
Figure 5b. MAX19711 EV Kit Schematic (Sheet 1 of 2)
______________________________________________________________________________________ 13
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
MAX4108
U4
MAX19712
U1
VDD
VR1
VR2
COM
R9
OPEN
R7
OPEN
R17
24.9Ω
1%
C5
0.1μFR15
OPEN
R19
24.9Ω
1%
R11
SHORT
R13
SHORT
R5
OPEN
IAP
C1
0.1μF
R6
OPEN
C2
0.1μF
R1
49.9Ω
1%
C7
22pF
C9
22pF
J4
IAP
IAN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OVDD
2
3
4
81139414751 24
VDD
OVDD
DVDD
VOP
VON
R2
49.9Ω
1%
IAN
IA
C3
0.1μFT1
1
2
3
6
5
4
R3
49.9Ω
1%
COM
R20
24.9Ω
1%
C6
0.1μF
R16
OPEN
R18
24.9Ω
1%
R14
SHORT
R12
SHORT
R8
OPEN
R10
OPEN
QAN
C10
22pF
C11
OPEN
C8
22pF
J5
QAN
QAP
CLK
9
10
6
REFP
1
C12
OPEN
REFN
REFIN
56
54
C15
0.33μF
C16
0.33μF
C13
1000pF
C14
1000pF
QAP
QA
C4
0.1μF
T2
1
2
3
6
5
4
R4
49.9Ω
1%
C17
0.1μF
C18
1.0μF
DVDD
C19
1.0μF
C20
1.0μF
VR2
R23
OPEN
R24
OPEN
VR1
TP1
JU2
TP2
R21
OPEN
R22
OPEN
CLK
COM
C31
OPEN
QDP 53
QDN 52
C33
OPEN
C35
OPEN
R43
OPEN
R45
OPEN
R51
10kΩ
1%
R39
OPEN
R41
OPEN
GNDN.C.
411
12 3
VMOD
VL
VCC
REFIN
QDP
C37
0.1μF
R47
10kΩ
1%
R49
10kΩ
1%
C39
0.1μF
QDN
COM
55
C82
1000pF
C83
0.33μF
JU1-1
JU1
JU1-3
38
COM
VMOD
MOSI
SCLKH
CSH
MISO
VMOD
DOUT
DOUT
CS
SCLK
SCLK
DIN
DIN
OGND
CS
CS
CS
SCLK 37 SCLK
DIN
JU1-5
JU1-7
I/OVL1
EN
I/OVL2
I/OVL3
I/OVL4
I/OVCC1
I/OVCC2
I/OVCC3
I/OVCC4
CSH
SCLKH
MOSI
MISO
JU1-2
1
7
2
5
6
14
13
10
9
8
JU1-4
JU1-6
JU1-8
36
5
7
12
40
50
23
DIN
GND
GND
GND
GND
GND
DGND
DOUT
DA9
34
DA8
33
DA7
32
DA6
31
DA5
30
DA4
29
DA3
28
DA2
27
DA1
26
DA0
25
DOUT 35
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
13
AD0
AD0
14
AD1
AD1
15
AD2
AD2
16
AD3
AD3
17
AD4
AD4
18
AD5
AD5
19
AD6
AD6
20
AD7
AD7
21
AD8
AD8
22
AD9AD9
DOUT1
J1
J1-1
J1-2
J1-3
J1-4
J1-7
J1-8
J1-36
J1-37
J1-38
J1-35
J1-5
J1-6
J1-9
J1-10
J1-11
J1-12
J1-13
J1-14
J1-15
J1-24
J1-23
J1-22
J1-21
J1-20
J1-19
J1-18
J1-17
J1-16
J1-25
J1-26
J1-27
J1-28
J1-29
J1-30
J1-31
J1-32
J1-33
J1-34
J1-39
J1-40
EN
R53
10kΩ
1%
R55
49.9Ω
1%
C41
2.2μF
C45
0.1μF
C43
2.2μF
C47
0.1μF
QD
2
8
4
7
6
5
3
VDD
C84
2.2μF
C22
0.1μF
C28
0.1μF
C23
0.1μF
C24
0.1μF
C25
0.1μF
C27
0.1μF
C26
0.1μF
MAX4108
U5
MAX4478
U6-B
VOP
VON
C32
OPEN
IDP 49
IDN 48
C34
OPEN
C36
OPEN
R44
OPEN
R46
OPEN
R37
SHORT
R38
OPEN
R52
10kΩ
1%
R32
OPEN
R40
OPEN
R42
OPEN
IDP
C38
0.1μF
R48
10kΩ
1%
R50
10kΩ
1%
C40
0.1μF
IDN
R54
10kΩ
1%
R56
49.9Ω
1%
C42
2.2μF
C46
0.1μF
C44
2.2μF
R25
SHORT
R31
SHORT
R28
SHORT
DAC1
BDAC1
C48
0.1μF
DAC1 46
DOUT
ID
28
4
7
6
5
5
6
7
2
3
R26
SHORT
R29
SHORT
DAC2
DAC2 45
MAX4478
U6-D
R36
OPEN
R27
SHORT
R35
SHORT
R30
SHORT
DAC3
BDAC3
DAC3
ADC1
44
43 ADC_IN1
ADC2 42 ADC_IN2
GND
12
13
14 MAX4478
U6-A
R34
OPEN
R33
SHORT
BDAC2
3
2
1
11
VOP C21
0.1μF
4
UNUSED AMPLIFIER
9
10
8
MAX4478
U6-C
OVDD
C29
0.1μF
C30
2.2μF
VOP
C49
220μF
6.3V
C50
220μF
6.3V
C61
10μF
C67
1.0μF
C51
220μF
6.3V
C52
220μF
6.3V
C62
10μF
C68
1.0μF
VOP
VON
VON
GND
VDD
C53
220μF
6.3V
C54
220μF
6.3V
C63
10μF
C69
1.0μF
VDD
GND
DVDD
C55
220μF
6.3V
C56
220μF
6.3V
C64
10μF
C70
1.0μF
DVDD
DGND
MAX3023
U7
Figure 5c. MAX19712 EV Kit Schematic (Sheet 1 of 2)
14 ______________________________________________________________________________________
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
MAX4108
U4
MAX19713
U1
VDD
VR1
VR2
COM
R9
OPEN
R7
OPEN
R17
24.9Ω
1%
C5
0.1μFR15
OPEN
R19
24.9Ω
1%
R11
SHORT
R13
SHORT
R5
OPEN
IAP
C1
0.1μF
R6
OPEN
C2
0.1μF
R1
49.9Ω
1%
C7
22pF
C9
22pF
J4
IAP
IAN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OVDD
2
3
4
81139414751 24
VDD
OVDD
DVDD
VOP
VON
R2
49.9Ω
1%
IAN
IA
C3
0.1μFT1
1
2
3
6
5
4
R3
49.9Ω
1%
COM
R20
24.9Ω
1%
C6
0.1μF
R16
OPEN
R18
24.9Ω
1%
R14
SHORT
R12
SHORT
R8
OPEN
R10
OPEN
QAN
C10
22pF
C11
OPEN
C8
22pF
J5
QAN
QAP
CLK
9
10
6
REFP
1
C12
OPEN
REFN
REFIN
56
54
C15
0.33μF
C16
0.33μF
C13
1000pF
C14
1000pF
QAP
QA
C4
0.1μF
T2
1
2
3
6
5
4
R4
49.9Ω
1%
C17
0.1μF
C18
1.0μF
DVDD
C19
1.0μF
C20
1.0μF
VR2
R23
OPEN
R24
OPEN
VR1
TP1
JU2
TP2
R21
OPEN
R22
OPEN
CLK
COM
C31
OPEN
QDP 53
QDN 52
C33
OPEN
C35
OPEN
R43
OPEN
R45
OPEN
R51
10kΩ
1%
R39
OPEN
R41
OPEN
GNDN.C.
411
12 3
VMOD
VL
VCC
REFIN
QDP
C37
0.1μF
R47
10kΩ
1%
R49
10kΩ
1%
C39
0.1μF
QDN
COM
55
C82
1000pF
C83
0.33μF
JU1-1
JU1
JU1-3
38
COM
VMOD
MOSI
SCLKH
CSH
MISO
VMOD
DOUT
DOUT
CS
SCLK
SCLK
DIN
DIN
OGND
CS
CS
CS
SCLK 37 SCLK
DIN
JU1-5
JU1-7
I/OVL1
EN
I/OVL2
I/OVL3
I/OVL4
I/OVCC1
I/OVCC2
I/OVCC3
I/OVCC4
CSH
SCLKH
MOSI
MISO
JU1-2
1
7
2
5
6
14
13
10
9
8
JU1-4
JU1-6
JU1-8
36
5
7
12
40
50
23
DIN
GND
GND
GND
GND
GND
DGND
DOUT
DA9
34
DA8
33
DA7
32
DA6
31
DA5
30
DA4
29
DA3
28
DA2
27
DA1
26
DA0
25
DOUT 35
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
13
AD0
AD0
14
AD1
AD1
15
AD2
AD2
16
AD3
AD3
17
AD4
AD4
18
AD5
AD5
19
AD6
AD6
20
AD7
AD7
21
AD8
AD8
22
AD9AD9
DOUT1
J1
J1-1
J1-2
J1-3
J1-4
J1-7
J1-8
J1-36
J1-37
J1-38
J1-35
J1-5
J1-6
J1-9
J1-10
J1-11
J1-12
J1-13
J1-14
J1-15
J1-24
J1-23
J1-22
J1-21
J1-20
J1-19
J1-18
J1-17
J1-16
J1-25
J1-26
J1-27
J1-28
J1-29
J1-30
J1-31
J1-32
J1-33
J1-34
J1-39
J1-40
EN
R53
10kΩ
1%
R55
49.9Ω
1%
C41
2.2μF
C45
0.1μF
C43
2.2μF
C47
0.1μF
QD
2
8
4
7
6
5
3
VDD
C84
2.2μF
C22
0.1μF
C28
0.1μF
C23
0.1μF
C24
0.1μF
C25
0.1μF
C27
0.1μF
C26
0.1μF
MAX4108
U5
MAX4478
U6-B
VOP
VON
C32
OPEN
IDP 49
IDN 48
C34
OPEN
C36
OPEN
R44
OPEN
R46
OPEN
R37
SHORT
R38
OPEN
R52
10kΩ
1%
R32
OPEN
R40
OPEN
R42
OPEN
IDP
C38
0.1μF
R48
10kΩ
1%
R50
10kΩ
1%
C40
0.1μF
IDN
R54
10kΩ
1%
R56
49.9Ω
1%
C42
2.2μF
C46
0.1μF
C44
2.2μF
R25
SHORT
R31
SHORT
R28
SHORT
DAC1
BDAC1
C48
0.1μF
DAC1 46
DOUT
ID
28
4
7
6
5
5
6
7
2
3
R26
SHORT
R29
SHORT
DAC2
DAC2 45
MAX4478
U6-D
R36
OPEN
R27
SHORT
R35
SHORT
R30
SHORT
DAC3
BDAC3
DAC3
ADC1
44
43 ADC_IN1
ADC2 42 ADC_IN2
GND
12
13
14 MAX4478
U6-A
R34
OPEN
R33
SHORT
BDAC2
3
2
1
11
VOP C21
0.1μF
4
UNUSED AMPLIFIER
9
10
8
MAX4478
U6-C
OVDD
C29
0.1μF
C30
2.2μF
VOP
C49
220μF
6.3V
C50
220μF
6.3V
C61
10μF
C67
1.0μF
C51
220μF
6.3V
C52
220μF
6.3V
C62
10μF
C68
1.0μF
VOP
VON
VON
GND
VDD
C53
220μF
6.3V
C54
220μF
6.3V
C63
10μF
C69
1.0μF
VDD
GND
DVDD
C55
220μF
6.3V
C56
220μF
6.3V
C64
10μF
C70
1.0μF
DVDD
DGND
MAX3023
U7
Figure 5d. MAX19713 EV Kit Schematic (Sheet 1 of 2)
______________________________________________________________________________________ 15
DA0
1
DA9
DA7
DA8
DA6
DA5
DA4
DA3
DA2
DA1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RA5
51Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RA6
51Ω
BVCC
C57
220μF
6.3V
C58
220μF
6.3V
C65
10μF
C71
1.0μF
BVCC
DGND
U3
CVDD
8
1
1
2
3
4
2
3
5
VCC
IN1-
IN2-
OUT1
OUT2
7
6
TP5
TP4
CVDD
CVDD
CLOCK
GND
CVDD
C59
220μF
6.3V
C60
220μF
6.3V
C66
10μF
C72
1.0μF
CVDD
GND
C77
2.2μF
C78
0.1μF
C79
0.01μF
C80
0.1μF
R57
4.02kΩ
1%
R63
5kΩ
R60
2kΩ
1%
TP3 R62
SHORT
R66
SHORT
CLK
D1
2
1
R
L
3
OVDD
CLKO
MAX9113
IN2+
IN1+
C81
0.1μFR61
49.9Ω
1%
R59
6.04kΩ
1%
R58
4.02kΩ
1%
J3-1
J3-3
J3-5
J3-7
J3-9
J3-11
J3-13
J3-15
J3-17
J3-19
J3-2
J3
J3-4
J3-6
J3-8
J3-10
J3-12
J3-14
J3-16
J3-18
J3-20
SN74ALVCH16244
U2
VCC
BVCC
123
JU3
OVDD
4Y4 23
4Y3 22
24
4Y2 20
4Y1 19
VCC 18
3Y4 17
3Y3 16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
3Y2 14
3Y1 13
2Y4 12
2Y3 11
2Y2 9
2Y1 8
VCC 7
IY3
IY4 5
6
GND 4
IY2 3
IY1
IA1
IA2
GND
2
GND 15
GND 10
1
J2-1
J2-3
J2-5
J2-7
J2-9
J2-11
J2-13
J2-15
J2-17
J2-19
J2-21
J2-23
J2-25
J2-27
J2-29
J2-31
J2-33
J2-35
J2-37
J2-39
J2-2
J2
J2-4
J2-6
J2-8
J2-10
J2-12
J2-14
J2-16
J2-18
J2-20
J2-22
J2-24
J2-26
J2-28
J2-30
J2-32
J2-34
J2-36
J2-38
J2-40
CLKOUT
BDOUT
RA3
51Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RA4
51Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RA1
100Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
48
47
46
IA3
44
IA4
43
2A1
41
2A2
40
2A3
38
2A4
37
3A1
36
3A2
35
GND
34
3A3
33
3A4
32
4A3
27
4A1
30 4A2
29
31
GND
39
GND
28
VCC
VCC VCC
42
45
RA2
100Ω
CLK0
DOUT1
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1OE
4OE
3OE
21
GND
2OE
C76
0.1μF
VCC
VCC
VCC
C75
0.1μF
C73
0.1μF
C74
0.1μF
4A4
26
25
Figure 6. MAX19710–MAX19713 EV Kit Schematic (Sheet 2 of 2)
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
16 ______________________________________________________________________________________
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
Figure 7. MAX19710–MAX19713 EV Kit Component Placement Guide—Component Side
______________________________________________________________________________________ 17
Figure 8. MAX19710–MAX19713 EV Kit PCB Layout—Component Side
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
18 ______________________________________________________________________________________
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
Figure 9. MAX19710–MAX19713 EV Kit PCB Layout (Inner Layer 2)—Ground Planes
______________________________________________________________________________________ 19
Figure 10. MAX19710–MAX19713 EV Kit PCB Layout (Inner Layer 3)—Power Planes
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
20 ______________________________________________________________________________________
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
Figure 11. MAX19710–MAX19713 EV Kit PCB Layout—Solder Side
Evaluate: MAX19710–MAX19713
MAX19710–MAX19713 Evaluation
Kits/Evaluation Systems
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
21
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Figure 12. MAX19710–MAX19713 EV Kit Component Placement Guide—Solder Side
___________________Revision History
Pages changed at Rev 1: 1–6, 8, 9, 11–18