Lattice Semiconductor Corporation GAL22V10 Family GAL18V10 GAL22V10 GAL26CV12 High-Performance E?CMOS* ig Welty * HIGH PERFORMANCE ECMOS? TECHNOLOGY 15 ns Maximum Propagation Delay Fmax = 50 MHz TTL Compatibie 8 - 16 mA Outputs ~~ UltraMOS Ill Advanced CMOS Technology Internal Pull-Up Resistor on all Pins + 50% REDUCTION IN POWER 75 -90mA Typ |, - E? CELL TECHNOLOGY ~~ Reconfigurable Logie Reprogrammable Calls 100% Tested/Guaranteed 100% Yields -~ High Speed Electrical Erasure (<50ms) 20 Year Data Retention + OUTPUT LOGIC MACROCELLS Maximum Flexibility for Complex Logic Designs Uses the Standard 22V10 OLMC Architecture PRELOAD AND POWER-ON RESET OF ALL REGISTERS 100% Functional Testability * APPLICATIONS INCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade + ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION The GAL22V10 Family of devices are high-speed, E7?CMOS PLDs built using the familiar 22V10 architectura. Three devices are offered in the GAL22V10 Family. They are the GAL18V10 (20- pin), GAL22V10 (24-pin), and the GAL26CV12 (28-pin). Each of these devices uses the industry standard 22V10 universal architecture which provides maximum design flexibility by allow- ing the Output Logic Macrocell (OLMC)} to be configured by the user. The devices differ in the number of I/Os, Pins, and Prod- uct Terms offered. The GAL22V10 is a 24-pin device which contains twelve (12) dedicated input pins and ten (10) input/output pins. The device has a variable number of product terms per OLMC, ranging from eight (8) to sixteen (16) per output. The GAL18V10 is a 20-pin version of the popular 22V 10 device. The GAL18V10 provides design engineers with a smaller foot- print and lower cost alternative to the 24-pin 22V10 device. The GAL18V10 contains eight (8) dedicated input pins and ten (10) input/output pins. The GAL26CV12 is a 28-pin version of the 22V10 device. The GAL26CV12 features more inputs and outputs in order to provide greater functionality and increased /O. The GAL26CV12 con- tains fourteen (14) dedicated input pins and twelve (12) input/out- put pins. Electrically raprogrammable CMOS technology allows complete AC, DC, and functional testing of every GAL device. Therefore, LATTICE guarantees 100% field programmability and function- ality of all GAL products. LATTICE also guarantees 100 erase/ rewrite cycles and that data retention exceeds 20 years. BLOCK DIAGRAM: GAL18V10, 22V10, and 26CV12 waK D GAL18V10 GAL22V10 GAL26CV12 0 3 <> vora v GAL18V10 and GAL22V10 GAL26CV12 Copyright 1990 Lattice Semiconductor Corp. GAL, EXCMOS, and UttraMOS are registerad trademarks of Lattica Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc- torCorp. The speciications herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. Tel. (503) 681-0118 or 1-800-FASTGAL; FAX (503) 681-3037 45 March 1990Lattice Semiconductor Specifications GAL22V10 Family Corporation GAL 18V10 BLOCK DIAGRAM VOLK vCLK INPUT WPUT PUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT PUT INPUT INPUT INPUT INPUT WPUT INPUT PUT Chip Carrier Skinny Dip Chip Carrier Skinny Dip CLK qd: VGh Vee vex (1 ~~ = 24[] vee 1 1 YOLK Vee O iff 1} Vora i ) Wola ' worn ' 1] vora iQ 1] vora ' bora iq] 1) vo/a 1 GaALisvio 1 | GAL pee GAL22V10 if AL bor 18V10 22V10 : Top View vero if H ora Top View Hi D vore ; von if H vor iq fj vora yor OND YOa OR WOO if [] vor if H vore vove [] [] ova id } vor ano [} 10 111] ova if H vora iq [] vara Gnp [J 12 aan} 46Lattice Semiconductor Corporation Specifications GAL22V10 Family GAL26CV12 BLOCK DIAGRAM GAL26CV12 PIN DIAGRAMS vcLK INPUT INPUT INPUT INPUT WPUT INPUT INPUT INPUT INPUT WPUT INPUT INPUT INPUT Chip Carrier GAL26CV12 9 g vora vv vora D vova D vova Top View H GND } vor 1 vova -=So0g 8883 Skinny Dip fs verk 4 aft iq 1} wore if 1 vova if N vora if vara tq GAL f voro vee | 26CV12h io ff D GND iC h vora ai Dora if H vova iq } WOvG iq Dvora 1Q14 15(] vOra PRODUCT SELECTOR GUIDE COMMERCIAL TEMP. GAL18V10 | GAL22V10 | GAL26CV12 Pins 20 24 28 Tpd (Max.) 15ns 15ns 15ns lec (Typ.) 75mA 90mA 90mA Dedicated 8 12 14 inputs Inputs/ 10 10 12 Outputs Product Terms 8-12 8-16 8-10 per macrocell Technology E?CMOS E?>CMOS E?CMOS SPEED/GRADE SELECTOR GUIDE GRADE Commercial | Industrial Military GAL18V10 15, 20ns 15, 20ns 15, 20ns GAL22V10 15, 20, 25ns | 15, 20, 25ns | 15, 20, 30ns GAL26CV12 15, 20ns 15, 20ns 15, 20ns Vee .00V+5% | 5.00V 4 10% | 5.00V+ 10% Tamperature 0->75C -40->85C | -55->125C Packaging Plastic DIP | Plastic DIP CERDIP PLCC PLCCLL ee Specifications GAL22V10 Family orporation GAL18V10 LOGIC DIAGRAM GAL18V10 ASYNCHRONOUS RESET (TO ALL REGISTERS) OLMC SYNCHRONOUS PRESET (TO ALi. REGISTERS) 48L Lattice Semiconductor Corporation Specifications GAL22V10 Family GAL22V10 LOGIC DIAGRAM GAL22V10 ASYNCHRONOUS RESET (TO ALL REGISTERS) 23 7 16 8 15 9 14 _ EYNCHRONOUS PRESET {TO ALL REGISTERS} 18 49Lattice Specifications GAL22V10 Family Corporation GAL26CV12 LOGIC DIAGRAM GAL26CV12 1 a re wn en -~- 28 ASYNCHRONOUS RESET (10 ALL REGISTERS) 27 26 - 25 24 23 22 19 18 1" ok 1? 16 13 OLMC 15 14 as SYNCHRONOUS PRESET {70 ALL REGISTERS) 50Specifications GAL22V10 Fami femiconductor p 0 Family ABSOLUTE MAXIMUM RATINGS {_ [Lattice SUPPLY VOMAQE Veg entero nestnnnninsmnninnnnntnti 5t0+7V Input voltage applied 2.5 to Von +1.0V Off-state output voltage applied .......... 2.5 10 Vig +1.0V Storage Temperature 0.00.0... cece 65 to 125C 1. Stresses above those listed under the "Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditians above thase indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). SWITCHING TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns 10% 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V *8V Output Load See Figure Tri-state levels are measured 0.5V from steady-state active Rs ievel. HAL FROM OUTPUT (O/Q - COMMERCIAL INDUSTRIAL MILITARY | FROM OUTPUT (0/Q) TEST POINT R, | a | R, ' RR, | OR, | + 2 1 | 2 1 2 i : GAL18V10 3002 | 3900 | 3002 | 3902 / 3902 | 7502 R S c i _. | 2 | GAL22V10 3002 | 3902 | 300Q | 3902! 39002 7500 : GAL26CV12 | 470Q | 390 | 470Q 39022 | 4700 | 39022 : AC Test Conditions: Cand. 1) R, per table; C, = 50pF; R, per abave table CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE Cond. 2) Active High R, =; Active Low R, per table; C, = 50pF; R, per above table Cond. 3) Active High R, =; Active Low R, per table; C, = SpF; R, per above table CAPACITANCE (T, = 25C, f = 1.0 MHz) SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C Input Capacitance 8 pF Voc = 5.0V, V, = 2.0V Cuore V/O/Q Capacitance 10 pF Veo = 8.0V, Vigg = 2.0V Guaranteed but not 100% tested. 51Lattice Specifications GAL22V10 Family Corporation ELECTRICAL CHARACTERISTICS 18V10, 22V10, 26CV12-15L Commercial Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNITS VoL Output Low Voltage lou = Max. ~ | | os VOH Output High Voltage lou = Max. 24 [| | v vio| | |- iL, [vOvQL" | Leakage Current Low Vii = OV GAL26CV12 & 18V10 100 | BA GAL22V10 | |-150 | pa lH, IVO/QH =| Leakage Current High Vin > 3.5V | 10 | pA los? Output Short Circuit Current Vec=5V Vout=0.5V T= 25C -50 |-135 | mA Vi =0.5V Vin =3.0V |GAL18V10 _ 75 115 mA Icc Operating Power Supply Current foggie = 1S5MHz GAL22V10 & 26CV12| 90 130 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems causad by tester ground degradation. Guaranteed but not 100% tested. DC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-15L Commercial SYMBOL PARAMETER MIN. MAX. | UNITS TA Ambient Temperature 0 75 C Vcc Supply Voltage 4.75 5.25 VIL Inout Low Voltage Vss-0.5! 0.8 VIH Input High Voltage 2.0 | Vec+i JO Low Level Output Current GALEN B 22V10 6 mA GAL26CV12 _ 8 mA IOH High Level Output Current _ -3.2 mA 52Semiconductor Specifications GAL22V10 Family SWITCHING CHARACTERISTICS 18V10, 22V10, 26CV12-15L Commercial Over Recommended Operating Conditions TES PARAMETER| # | FROM | TO DESCRIPTION cono:| MIN. | MAX. | UNITS tpd 1 1, O oO Input or Feedback to Combinational Output 1 15 ns GAL22V10 1 8 ns | tco 2| ckt Q Clock to Register Output GAL18V10 & 26CV12 1 _ 10 ns ten 3 vo 0,aQ Output Enable, Z~ O,Q 2 15 ns tais 4] 0 | 0,Q | Output Disable, 0,Q> Z 3 _ 15 ns tres 5 1,10 Q Asynchronous Register Reset 1 _ 20 ns 1) Reter to Switching Test Conditions section. AC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-15L Commercial PARAMETER| # DESCRIPTION TEST | MIN. | MAX. | UNITS COND. f & | Clock Frequency without Feedback = 1/(t,, + ty) _ 8 62.5 MHz clk 7 | Clock Frequency with Feedback! = 1 / (tay + tog) _ 0 50 MHz GAL22V10 _ 12 _ ns tsu 8 | Setup Time, Input, Feedback, or SP before Cik t GAL18V10 & 26CV12 _ 10 =~ ns th 9 | Hold Time, Input or Feedback, after Clk T 0 _ ns twh 10 | Clock Pulse Duration, High? _ 8 _ ns twi 11 | Clock Pulse Duration, Low? _ 8 _ ns GAL22V10 _ 15 _ ns trw 12 | Asynchronous Reset Pulse Duration GAL18V10 & 26CV12 _ 10 ~_ ns trec 13 | Asynchronous Reset to Clk T Recovery Time _ 15 _ ns 1) felk is for reference only ancl is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. 2) Clock pulses of widths less than the specification may be detected as valid clock signals. SWITCHING WAVEFORMS 1 I WePUTS: O, REQ. SYNCHRONOUS PRESET | i | i i 4 ieLattice Specifications GAL22V10 Family Corporation ELECTRICAL CHARACTERISTICS 18V10, 22V10, 26CV12-20L Commercial Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNITS VoL Output Low Voltage lo. = Max. | | 05 VOH Output High Voltage lou = Max. 24 | | lit, IvoraL | Leakage Current Low Vu = OV GAL26CV12 8 18V10) | |-100 | HA GAL22V10 | |-150 | pa \iH, 1vO/QH | Leakage Current High Vin > 3.5V | 10 | pA los? Output Short Circuit Current Veo =5V VouT=0.5V T= 25C -50 | |-135 | mA Vii =O0.5V Vin = 3.0V |GAL18V10 _ 75 W158 mA loc Operating Power Supply Current froggle = 15MHz GAL22V10 & 26CV12| 90 130 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. DC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-20L Commercial SYMBOL PARAMETER MIN. | MAX. | UNITS TA Ambient Temperature 0 75 C Vec Supply Voltage 4.75 5.25 VIL Input Low Voltage Vss-0.5] 0.8 VIH Input High Voltage 2.0 | Vec+1 GAL18V10 _ 16 mA IoL Low Level Output Current GAL22V10 & 26CV12 _ 8 mA 1OH High Level Output Current ~3.2 mA SWITCHING WAVEFORMS WPUTS | vo, REG. FEEDBACK | SYNCHRONOUS f RESET ! a | REGISTERED | ou ASYNCHROMOUS | RESET i ANT INPUT | PROGRAMMED | FOR OF CONTROL | COM MINATIONAL i On 54Lattice Specifications GAL22V10 Family Corporation SWITCHING CHARACTERISTICS 18V10, 22V10, 26CV12-20L Commercial Over Recommended Operating Conditions PARAMETER| # | FROM | TO DESCRIPTION cond. 1) MIN, | MAX. | UNITS tpa 1 1, YO oO Input or Feedback to Combinational Output 1 _ 20 ns GAL22V10 1 _ 10 ns Fi too 2) Ck Tt Q Clock to Register Output GAL18V10& 26CV12 | 1 _ 12 ns fen 3 | 4O | 0,Q | OutputEnable, Z>0,0 2 _ 20 ns tdis 4} 1vO |} 0,Q | Output Disable, 0,Q> Z 3 _ 20 ns GAL22V10 1 _ 25 ns tres 5 110 Q Asynch. Register Reset GAL18V10& 26CV12 | 1 20 ns 1) Refer to Switching Test Conditions section. AC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-20L Commercial PARAMETER| # DESCRIPTION TEST | win. | MAX. | UNITS COND. . GAL22Vi0 _ 0 50.0 MHz 6 | Clk Frequency without Feedback = 1 /(t,, + t,,) f k GAL18V10 & 26CV12 _ Q 62.5 MHz c GAL22V10 = 0 40.0 MHz 7 | Clk Frequency with Feedback = 1/(t, + t,,) GAL18V10 & 26CV12 _ 0 41.6 | MHz GAL22V10 _ 15 _- ns tsu 8 | Setup Time, Input, Feedback, or SP before Clk T GAL18V10 & 26CV12 _ 12 ~ ns th 9 |Hold Time, Input or Feedback, after Clk T _ 0 _ ns GAL22V10 _ 10 _ ns twh 10 | Clock Pulse Duration, High? GAL18V10 & 26CV12 8 _ ns GAL22V10 _ 10 _ ns twi 41. | Clock Pulse Duration, Low? GAL18V10 & 26CV12 _ 8 ~ ns GAL22V10 ~ 20 _ ns trw 12 | Asynchronous Reset Pulse Duration r | GAL18V10 & 26CV12 _ 15 ns GAL22V10 _ 20 _ ns trec 13 | Asynchronous Reset to Clk T Recovery Time GAL18V10 & 26CV12 _ 15 _ ns 1) felk is for reference only and is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. 2) Clack pulses of widths less than the specification may be detected as valid clock signals. 55Lattice Semiconductor Corporation Specifications GAL22V10 Family ELECTRICAL CHARACTERISTICS GAL22V10-25L Commercial Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNITS VoL Output Low Voltage lou = Max. -| ] a5] Vv Vou Output High Voltage lou = Max. 24} ]| | ov IIL, IvO/QL' | Leakage Current Low Vu = OV | |-150 | pA IIH, IVO/QH | Leakage Current High Vin 3.5V | 10 | pA ios2 Output Short Circuit Current Vcc =5V VouT=0.5V T= 25C ~+50 | |-135 | mA Icc Operating Power Supply Current | Vii =0.5V Vi =3.0V_ froggie = 1SMHz _ 90 130 | mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. DC RECOMMENDED OPERATING CONDITIONS GAL22V10-25L Commercial SYMBOL PARAMETER MIN. MAX. | UNITS TA Ambient Temperature Q 75 C Vcc Supply Voltage 4.75 5.25 Vv VIL input Low Voltage Vss-0.5| 0.8 Vv ViH Input High Voltage 2.0 | Vec+t Vv lou Low Level! Output Current 16 mA IOH High Level Output Current _ 3.2 mALattice Semiconductor Specifications GAL22V10 Family Corporation SWITCHING CHARACTERISTICS GAL22V10-25L Commercial Over Recommended Operating Conditions TEST j PARAMETER| # | FROM To DESCRIPTION conp.| MIN. | MAX. | UNITS tod 1 vo oO Input or Feedback to Combinational Output 1 _ 25 ns - tea 21 ckt Q Clock to Register Output 1 15 ns ten 3] |VO | 0,0 | Output Enable, Z>0,0 2 ~ 25 ns tdis 4 | LO | 0,Q | Output Disable, 0,Q> Z 3 _ 25 ns tres 5; 1,0 Q Asynchronous Register Reset 1 _ 25 ns 1) Refer to Switching Test Conditions section. AC RECOMMENDED OPERATING CONDITIONS GAL22V10-25L Commercial TEST PARAMETER| # DESCRIPTION MIN. | MAX. | UNITS COND. foi 6 | Clock Frequency without Feedback = 1/(t,, + t,,) _ 0 33.3 MHz cl 7 | Clock Frequency with Feedback = 1 / (ty +t) - 0 33.3 MHz teu 8 | Setup Time, Input, Feedback, or SP before Cik T _ 15, _ ns th 9 | Hold Time, Input or Feedback, after Clk T _ 0 ns twh 10 | Clock Pulse Duration, High? 15 ns tw 11 | Clock Pulse Duration, Low _ 15 _ ns trw 12 | Asynchronous Reset Pulse Duration _ 25 _ ns trec 13 | Asynchrorious Reset to Clk T Recovery Time _ 25 _ ns 1) felk is for reference only and is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. 2) Clock pulses of widths less than the specification may be detected as valid clock signals. SWITCHING WAVEFORMS INPUTS UO, REG. VAUD INPUT VALID INPUT PEEDRACK SYNCHRONOUS PRESET 11 12 Roe DONTHOL DISABLE ENABLE TOOK : COMBINATIONAL S L OUTPUTSLattice Specifications GAL22V10 Family Corporation ELECTRICAL CHARACTERISTICS 18V10, 22V10, 26CV12-15L industrial Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION , | MAX. | UNITS VoL Output Low Voltage lou = Max, 0.5 VOH Output High Voltage loH = Max. lL, lvorQL' | Leakage Current Low Vi = OV lH, IVOVQH | Leakage Current High Vin 2 3.5V | 10 10s? Output Short Circuit Current Vcc = 5V |-135 Vii = 0.5V \ 75 | 125 Tare Operating Power Supply Current fog mecvi2| oo | 150 1) The leakage current is due to the internal pull-up section for mare information. 2) One output at a time for a maximum duration of ( to avoid test problems caused by tester ground degradation. Guaranteed but not SYMBOL TA Vec VIL VIH GAL18V10 & 22V10 GAL26CV12 1OL Current 1OH High Output Current 58Lattice Specifications GAL22V10 Family Corporation SWITCHING CHARACTERISTICS 18V10, 22V10, 26CV12-15L Industriai Over Recommended Operating Conditions PARAMETER| # | FROM DESCRIPTION MAX. | UNITS tod 1 (Oo Input or Feedback to Combinational Output 15 ns GAL22V10 8 ns GAL18V1 10 ns ten 3 1, VO 0,Q | Output Enable, Z-+0,Q 15 ns tdis VO | 0,Q | Output Disable, 0,a~ Z 15 tres vO Q Asynchronous Register 20 tco Clk fT Q Clock to Register Output 1) Refer to Switching Test Conditions section. TEST conp.| MIN. Clock Frequency _ QO 62.5 MHz Clock Frequency _ 0 50 MHz GAL22V10 _ 12 _ ns GAL18V10 & 26CV12 10 _ ns MAX. | UNITS Setup 0 ns 8 ns 8 ns GAL22V10 15 ns GAL18V10 & 26CV12 10 ns trw 12 Pulse Duration trec 13 Reset to Cik T Recovery Time _ 15 ns 1) fclk is for reference only and is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. 2) Clock pulses of widths less than the specification may be detected as valid clock signals. Sy Eerie AEs tel sits WPUTS: vO, REG. FEEDBACK SYNCHRONOUS PRESET 59Lattice Semiconductor Specifications GAL22V10 Family Corporation ELECTRICAL CHARACTERISTICS 18V10, 22V10, 26CV12-20L Industrial Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNITS VOL Output Low Voltage lo. = Max. | | os VOH Output High Voltage fou = Max. 24 | IIL, IO/QL' | Leakage Current Low Vu = OV GAL26CVI2& 18VI0) | [100 | HA GAL22V10 | |-150 |] pA lH, 1VO/QH | Leakage Current High Vin 2 3.5V | 10 | pA los? Output Short Circuit Current Vec=5V Vour=0.5V T= 25C ~50 | |-135 | mA Vi O0.5V Vi = 3.0V |GAL18V10 | 75 | 125 | mA Icc Operating Power Supply Current floggie = 1SMHz GAL22V10 & 26CV12} | 90 | 150 | mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. DC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-20L Industrial SYMBOL PARAMETER MIN. MAX. | UNITS TA Ambient Temperature -40 a5 C Vcc Supply Voltage 45 5.5 v Vit Input Low Voltage Vss-0.5| 0.8 VIH Input High Voltage 2.0 Vec+1 GAL18V10 & 22V10 _ 16 mA GAL26CV12 _ 8 mA 10H High Level Output Current ~3.2 mA SWITCHING WAVEFORMS lou Low Level Output Current ASYNCHRONOUS RESET ANY PUT PROGRAMMED FOR OE CONTROL COMBINATIONS OUTPUTS.Lattice Semiconductor Specifications GAL22V10 Family Corporation SWITCHING CHARACTERISTICS 18V10, 22V10, 26CV12-20L industrial Over Recommended Operating Conditions PARAMETER| # | FROM | TO DESCRIPTION COND. 1| MIN. | MAX. | UNITS tpd 1 1, VO Oo Input or Feedback to Combinational Output 1 20 ns | 2 | GAL22V10 1 _ 10 ns tco 2| ckTt Q Clock to Register Output GAL18V10 &26CV12 | 1 12 ns ten 3 ae) 0,Q Output Enable, Z> 0,Q 2 _ 20 ns tdis 4 1, VO O,Q | Output Disable, O,Q> Z 3 20 ns tres 5 | 10 Q Asynch. Register Reset 1 25 ns 1) Refer to Switching Test Conditions section. AC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-20L industrial PARAMETER| # DESCRIPTION conD,| MIN. | MAX. | UNITS . GAL22V10 _ 0 50.0 MHz 6 |Clk Frequency without Feedback = 1/(t,, + tai) fork GAL18V10 & 26CV12 _ 0 62.5 | MHz c . GAL22V10 _ a 40.0 | MHz 7 | Cik Frequency with Feedback =1/{t, +t.) GAL18V10 & 26CV12 _ 0 41.6 | MHz GAL22V10 _ 15 ns tsu 8 | Setup Time, input, Feedback, or SP before Cik 7 GAL18V10 & 26CV12 _ 12 _ ns th 9 | Hold Time, Input or Feedback, after Cik T _ 0 ns GAL22V10 _ 19 _ ns twh 10 | Clock Pulse Duration, High? + GAL18V10 & 26CV12 _ 8 ns GAL22V10 _ 10 ns twi 11 | Clock Pulse Duration, Low? GALi8V10 & 26CV12 ~ 8 ns , GAL22V10 _ 20 ns trw 12 | Asynchronous Reset Pulse Duration GAL18V10 & 26CV12 _ 15 _ ns GAL22V10 _ 20 ns trec 13 | Asynchronous Reset to Clk T Recovery Time + | GAL18V10 & 26CV12 _ 15 _ ns 1) felk is for reference only and is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. 2) Clock pulses of widths less than the specification may be detected as valid clock signals. 61Semiconductor Specifications GAL22V10 Family Corporation iL Lattice ELECTRICAL CHARACTERISTICS 18V10, 22V10, 26CV12-15L military Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION VoL Output Low Voltage lou = Max. 0.5 VOH Output High Voltage lou = Max. HL, WwO/QL' | Leakage Current Low Vi = OV ~t00 |-~150 lH, IVO/QH | Leakage Current High Vin 2 3.5V | 10 los? Output Short Circuit Current Vec = 5V -50 | |-135 Vie = _ 75 135 26CV12| 90 150 1) The leakage current is due to the internal section for more information. 2) One output at a time for a maximum duration ) to avoid test problems caused by tester ground degradation. Guaranteed but icc Operating Power Supply Current SYMBOL MIN. MAX. Tc 55 125 Vcc 45 55 VIL Vss-0.5] 0.8 VIH 2.0 | Vec+t GAL18V10 & 22V10 ~ 12 GAL26CV12 8 OL Low Current ]OH High Level Output Current _ 62Lattice Semiconductor Gorporation SWITCHING CHARACTERISTICS 18V10, 22V10, 26CV12-15L Military Over Recommended Operating Conditions Specifications GAL22V10 Family PARAMETER| # | FROM To DESCRIPTION tod 1 a, @) Oo input or Feedback to Combinational Output GAL22V10 GAL18V1 Output Enable, Z > 0,Q Output Disable, 0, Q-> Z Asynchronous Register teo Clk T Q Clock to Register Output ten L vo 0,Q tdis 4 | Vo 0,Q tres 5] 1.0 Q 1} Refer to Switching Test Conditions section. TEST PARAMETER, # COND. MIN. | MAX. | UNITS feik tsu th twh twi trw trec 6 Clock Frequency Clock 8 |Setup 9 10 11 | Clock 12 13 | Asynchronous 1) felk is for reference only and is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. Duration 0 GAL18V10 & 26CV12 _ to Clk T Recovery Time _ 2) Clock pulses of widths less than the specification may be detected as valid clock signals. SWITCHING WAVEFORMS 62.5 50 45.5 8 15 15 _ MHz MHz MHz ns ns ns ns ns ns INPUTS. VO, REG. FEEDBACK SYNCHRONOUS PRESET CLK REGISTERED OUTPUTS: ASYNCHRONOUS RESET ANY INPUT PROGRAMMED FOR OF CONTROL COMBINATIONAL OUTPUTS 63Semiconductor Specifications GAL22V10 Family Corporation L Lattice ELECTRICAL CHARACTERISTICS 18V10, 22V10, 26CV12-20L Military Over Recommended Operating Conditions (Uniess Otherwise Specified) SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNITS VoL Output Low Voltage hou = Max. | | 05 VOH Output High Vohage fo = Max. 24 | | V HL, Ivara | Leakage Current Low Vit = OV GAL26CV12 & 18V10) | | -100 | HA GAL22V10 | |-150 | pa IIH, lvOVQH | Leakage Current High Vin 2 3.5V | | 10 | pA los? Output Short Circuit Current Vec=5V Vour=0.5V T= 25C ~50 | |-135 | mA Vii =O.5V Vin = 3.0V |GAL18V10 _ 75 135 | mA loc Operating Power Supply Current froggle = 15MHz GAL22V10 & 26CV12| 90 150 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. DC RECOMMENDED OPERATING CONDITIONS 18V10, 22V10, 26CV12-20L military SYMBOL PARAMETER MIN. MAX. | UNITS Tc Case Temperature 55 125 C Vcc Supply Voltage 45 5.5 Vit input Low Voltage Vss-0.5| 0.8 VIH Input High Voltage 2.0 | Vec+1 IOL Low Level Output Current GAL18V10 & 22V10 2 mA GAL26CV12 _ 8 mA IOH High Level Output Current ~2.0 mA 64Lattice Specifications GAL22V10 Family Corporation SWITCHING CHARACTERISTICS 18V10, 22V10, 26CV12-20L Military Over Recommended Operating Conditions PARAMETER! # FROM To DESCRIPTION conn, +} MIN. | MAX. | UNITS {pd 1 vo Input or Feedback to Combinational Output 1 _ 20 ns GAL22V10 1 15 ns tco 2| ckTt Q Clock to Register Output GAL18V10 & 26C6V12 1 _ 15 ns ten 3 1, oO 0,Q Output Enable, Z > 0,Q 2 20 ns tdis 4 | LWO | O,Q@ | Output Disable, 0,Q> Z 3 ~ 20 ns tres 5 io Q Asynch. Register Reset 1 _ 25 ns | 1) Refer to Switching Test Conditions section. PARAMETER| # DESCRIPTION Conp.| MIN. | MAX. | UNITS 6 | Clock Frequency without Feedback! = 1 (tun + ty) _ 0 33.3 MHz fox 7 |Clock Frequency with Feedback = 1 M+ ty) _ 0 31.2 MHz tsu 8 | Setup Time, Input, Feedback, or SP before Clk T _ 17 _ ns th 9 | Hold Time, Input or Feedback, after Cik T _ 0 _ ns twh 10 | Clock Pulse Duration, High? 15 _ ns twi 11 | Clock Pulse Duration, Low? _ 15 _ ns trw 12 | Asynchronous Reset Pulse Duration _ 20 | 47s trec 13 | Asynchronous Reset to Cik T Recovery Time _ 20 _ ns 1) felk is for reference only ancl is not 100% tested. Various paths and architecture configurations will result in differing fclk specifications. 2) Clock pulses of widths less than the specification may be detected as valid clock signals. SWITCHING WAVEFORMS | | INPUTS | i reece RE. VAUD INPUT VAUD INPUT i SYNCHRONOUS. Us PRESET 11 aK REGISTERED OUTPUTS ASYNCHRONOUS. RESET ANY INPUT PROGRAMMED FOR O CONTROL COMBINATIONAL ourPpuTs 65L Lattice Semiconductor Corporation Specifications GAL22V10 Family OUTPUT LOGIC MACROCELL ARCHITECTURE The GAL18V10, 22V10, and 26CV12 each have a variable num- ber of product terms per OLMC. Of the ten OLMCs available in the GAL18V10, eight OLMCs have access to eight product terms and two have ten product terms (refer to GAL18V10 Logie Diagram). Of the ten OLMCs available in the GAL22V 10, two OLMCs have access to eight product terms, two have ten product terms, two have twelve product terms, two have fourteen product terms, and two OLMCs have sixteen product terms (refer to GAL22V10 Logic Diagram). Of the twelve OLMCs available in the GAL26CV12, eight OLMCs have access to eight product terms, two have ten product terms, and two have twelve product terms (refer to GAL26CV12 Logic Diagram). The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinational or registered mode. This allows the user to reduce the overall number of product terms required in a design and/or to invert the output signal. GAL22V10 Family devices have a product term for AR (Asynchro- nous Reset) and a product term for SP (Synchronous Preset). These two product terms are common to all registered OLMCs. NOTE: Output polarity selection does NOT affect the behavior of the OLMC's integral "D flip-flop but does affect the value (0 or 1) of the output. The AR and SP product terms will force the flip-flop into the same state regardless of the polarity of the output. _ L/ jo GAL18V10, 22V10, and 26CV12 OUTPUT LOGIC MACROCELL (CLMC) OUTPUT LOGIC MACROCELL CONFIGURATIONS The GAL18V10, 2210, and 26CV12 have two primary functional modes which may be selected when compiling source equations (registered and combinational / input}. Each of these two primary modes are described below. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the "Q output of that OLMCs D flip-flop. Logic polarity of the output signal at the pin may be selected by speci- fying that the output buffer drive either true (active high) or invert (active low). Output tri-state control is available and can be indi- vidually selected as either on, off, or dynamically product-term driven. The D flip-flops AQ output is fed back into the AND array via the AND array buffer. Both polarities (true and invert) of the OLMC are fed back into the AND array. NOTE: In registered mode a tri-stated output pin may NOT be used as an input into the AND array. COMBINATIONAL / INPUT In combinational mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or invert (active low). Output tri-state control is available and may be individually se- lected as either on (dedicated output), off (dedicated input), or product-term driven (dynamic \/O). Feed back into the AND array is from the device pin, via the AND array buffer. Both po- larities (true and invert) of the pin are fed back into the AND ar- ray. 66L [Lattice Specifications GAL22V10 Family | am | Corporation REGISTERED MODE | | | oon . | * 1 CLK --pP a cLK Q | T SP sP ACTIVE LOW ACTIVE HIGH COMBINATIONAL MODE ACTIVE LOW ACTIVE HIGH 67Lattice Specifications GAL22V10 Family Corporation SRS eT An electronic signature (ES) is provided with every GAL18V10, When testing state machine designs, all possible states and state 22V10, and 26CV12 device. It contains 64 bits of reprogrammable transitions must be veritied in the design, not just those required memory that can contain user defined data. Some uses include in the normal machine operations. This is because in system user ID codes, revision numbers, or inventory control. The sig- operation, certain events occur that may throw the logic into an nature data is always available to the user independent of the state illegal state (power-up, line voltage glitches, brown-outs, etc.). To of the security call. test a design for proper treatment cf these conditions, a way must be provided to break the feedback paths, and force any desired BS Rese (i.@., illegal) state into the registers. Then the machine can be Asecurity cell is provided with every GAL18V10, 22V10, and Sequenced and the outputs tested for correct next state conditions. 26CV 12 device as a deterrent to unauthorized copying of the array GAL18V10, 22V10, and 26CV12 devices include circuitry that patterns. Once programmed, this cell prevents further read allows each registered output to be synchronously set either high access to the AND array. This cell can be erased only during a or low. Thus, any present state condition can be farced for test bulk erase cycle, so the original configuration can never be sequencing. If necessary, approved GAL programmers capable examined once this call is programmed. The Electronic Signa- of executing test vectors perform output register preload automati- ture is always available to the user, regardless of the state of this cally. control cell. INPUT BUFFERS SE Sa Seis GAL22V 10 Family devices are designed with TTL level compat- Before writing a new pattern into a previously programmed part, ible input buffers. These buffers, with their characteristically high the old pattern must first be erased. This erasure is done auto- impedance, load driving logic much less than bipolar logic. matically by the takes only 5G navaware a part of the program- The buffers also possess active pull-ups within their input struc- ng cy ture. Unused inputs and U/O's will float to a TTL high (logical "1), a Lattice recommends that all unused inputs and tri-stated /O pins aS aaah be connected to an adjacent active input, V.,, or GND. Doing this GAL18V10, 22V10, and 26CV12 devices are designed with an will tend to improve noise immunity and reduce |, for the device. on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input under- shoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullup instead of the traditional p- channel! pullups to eliminate any possibility of SCR induced latch- ing. Input Current (pA) oo 1.0 20 3.0 40 50 input Voltage () POWER-UP RESET Vee 90% 4 ov patie t PR Vin CuK Xn] VALID GLOCK SIGNAL Ww t RESET A INTERNAL REGISTER NEG OXON RESET TO LOGIC D FEEDBACK/EXTERNAL | EXTERRAL REGISTER AEBS OOOO OOK, Sue OUTPUT Circuitry within GAL18V10, 22V10, and 26CV12 devices provides the V,,, rise must be monotonic. Second, the clock input must a reset signal to all registers during power-up. All internal regis- become a proper TTL level within the specified time (t,,, 100ns ters will have their Q outputs set low after a specified time (t oy MAX). The registers will reset within a maximum of t,,.,, time. , 45s MAX). This feature can greatly simplify state machine As in normal system operation, avoid clocking the device until all design by providing a known state on power-up. input and feedback path setup times have been met. The timing diagram for power-up is shown above. Because of the Note that the internal register powers-up to a logic 0. The device asynchronous nature of system power-up, some conditions must pin state is determined by the user-defined polarity control bit on be met to guarantee a valid power-up reset of the device. First, each macrocell (refer to OLMC description). 68Lattice Specifications GAL22V10 Family Corporation Normalized Tpd vs. Voc Normalized Tsu vs. Voc Normalized Teo vs. Veo wi a 2 g 3. i rs 3 Bos 5 09 z os PT Hk PTL o8. aseee PT L->H PTL->H woes PTH oh OF 07 4s ays 3 $2 as 45 4.75 5 5.25 $5 45 475 5 5.25 55 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalizad Tpd vs. Ternperature Normatized Tsu vs. Temperature Normalized Teo vs. Temperature Normalized Tpd Normalized Tco o7 30-888 SB 8 7 100 125 55-25 Ba 7S 100 125 35S 25 8 3 8 7 100 125 Ambient Temperature (C) Ambient Temperature (C) Ambient Temperature (C} Delta Tpd vs. # of Outputs Switching Delta Tpd vs. Output Loading Normalized foc vs. Voc Ly 2 8 z 3 . 3 Z. E 4 2 5 0 Max.- 8 Max.- 4 Max. 100 200 300 400 45 475 5 5.25 5: # of Outputs Output Loading Capacitance (pf) Supply Voltage (V) fot vs. VoL 180 foH vs. VOH Normalized tcc vs. Temperature 2s0 mee 4.872210 OL (mA) me icc v8. Ternperature 20 nese BBCVIZIOL (mA) wens jabva, Teenperanre 400 he a => 150 = 3 2 = 3 g Bw 5 oo 5 cenennonapaneesenn4 N on we oe 0 sO 7% 100 128 2 a 2 Ambient Temperature (C}