| 002SC-L_SCH-L 7/15/98 3:28 PM Pagel | p SHARP LH28F002SC-L/SCH-L LH28FOO2SC-LISCH-L *oess**a.seuer DESCRIPTION The LH28F002SC-L/SCH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F002SC-L/SCH-L offer three levels of protection : absolute protection with VPP at GND, selective hardware block locking, or flexible software block locking.These alternatives give designers ultimate control of their code security needs. FEATURES * SmartVoltage technology 2.7 V (Read-only), 3.3 V or 5 V Vcc -3.3V,5 Vor12 V VPP * High performance read access time LH28F002SC-L85/SCH-L85 85 ns (5.0+0.25 V)/ 90 ns (5.0+0.5 V)/ 120 ns (3.340.3 V)/150 ns (2.7 to 3.6 V) LH28F002SC-L12/SCH-L12 120 ns (5.0+0.5 V)/ 150 ns (3.340.3 V)/ 170 ns (2.7 to 3.6 V) COMPARISON TABLE Enhanced automated suspend options Byte write suspend to read Block erase suspend to byte write Block erase suspend to read Enhanced data protection features Absolute protection with VPP = GND Flexible block locking Block erase/byte write lockout during power transitions * SRAM-compatible write interface High-density symmetrically-blocked architecture Four 64 k-byte erasable blocks Enhanced cycling capability 100 000 block erase cycles 0.4 million block erase cycles/chip Low power management Deep power-down mode Automatic power saving mode decreases Icc in static mode * Automated byte write and block erase Command user interface Status register * ETOX* V nonvolatile flash technology * Packages 40-pin TSOP Type | (TSOP040-P-1020) Normal bend 44-pin SOP (SOP044-P-0600) [LH28F002SC-L] 48-ball CSP (FBGA048-P-0608) * ETOX is a trademark of Intel Corporation. VERSIONS TEMPERATURE Vec deep cower down eurrent (MAX. PACKAGE LH28F002SC-L 0 to +70C 10 pA 40-pin TSOP (1), 44-pin SOP, 48-ball CSP LH28F002SCH-L -40 to +85C 20 pA 40-pin TSOP (I), 48-ball CSP In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. P| 002SC-L_SCH-L 7/15/98 3:28 PM Page2 SHARP p LH28F002SC-L/SCH-L PIN CONNECTIONS 40-PIN TSOP (Type 1) NCQ] O [40] NC NCE] [39] NC Ai7B] [38] WE# Ais 4] [37] OE# Ats GB] [36] RY/BY# AE] [35] DQ7 Ai3 ZZ] [34] DQe AB] [33] DQs CE# DB] [32] DQa Vec [a] [31] Voc vep G1] [30] GND RP# E2] [29] GND Ai [28] DQ3 Ato 4 [27] DQ2 Ao TB] [26] DQ1 As Le] [25] DQo Ar [24] Ao Ac G8] [23] Ai As Lg] [22] A2 Aa Bo] [27] As (TSOP040-P-1020) 48-BALL CSP 44-PIN SOP [LH28F002SC-L] Top viEW VePG] RP# PE] O Ai1 By AoE] AoE] Ase] Av] AcE] AsB] A4 Go] NC iy NCE A3 G3] A2 Ga] Ai GS] Ao Ee] DQo Gz] DQ: Ge] DQe2 Gg] DQs Ba] GND Eq GND (SOP044-P-0600) oO! 2 3 5 @ Pe @ @ CQO O@ 0a@ & & E @ FQ OO OOOO BH @ O BOO OO O OOOH @ (FBGA048-P-0608) [44] Voc [43] CE# [42] A12 [47] A13 [40] A14 [39] Ais [38] A16 [37] A17 [36] NC [35] NC [a4] NC [33] NC [32] NC [an] NC [30] WE# [23] OE# [23] RY/BY# [27] DQ7 [26] DQe [25] DQs [24] DQa [23] Voc |002SC-L_SCH-L 7/15/98 3:28 PM Page 3 SHARP LH28F002SC-L/SCH-L BLOCK DIAGRAM DQo-DQ7 OUTPUT BUFFER cc IDENTIFIER Voc ad REGISTER aa ic Fa in CE# ah Eb 5 STATUS <5 = ag COMMAND WE# REGISTER wy USER INTERFACE OE# RP# DATA COMPARATOR Ao-At? INPUT Y DECODER Y GATING WRITE RYIBY# BUFFER STATE Vpp MACHINE 4 64 k-BYTE X DECODER BLOCKS _ and| 002SC-L_SCH-L 7/15/98 3:28 PM Page4 | SHARP p LH28F002SC-L/SCH-L PIN DESCRIPTION SYMBOL TYPE NAME AND FUNCTION Ao-A17 INPUT ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. DQo-DQ7 INPUT/ OUTPUT DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs data during memory array, status register, and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CE# INPUT CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RP# INPUT RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provide data protection during power transitions. Exit from deep power-down sets the device to read array mode. RP# at VHH enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. Block erase, byte write, or lock-bit configuration with ViH < RP# < VHH produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE : Gates the device's outputs during a read cycle. WE# INPUT WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the WE# pulse. RY/BY# OUTPUT READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase, byte write, or lock-bit configuration). RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. VpP SUPPLY BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes, or configuring lock-bits. With Ver < VPPLk, memory contents cannot be altered. Block erase, byte write, and lock-bit configuration with an invalid VpP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. Vcc SUPPLY DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V, 3.3 V or 5 V operation. To switch from one voltage to another, ramp Vcc down to GND and then ramp Vcc to the new voltage. Do not float any power pins. With Vcc < VLko, all write attempts to the flash memory are inhibited. Device operations at invalid Vcc voltage (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. Block erase, byte write and lock-bit configuration operations with Vcc < 3.0 V are not supported. GND SUPPLY GROUND : Do not float any ground pins. NC NO CONNECT : Lead is not internal connected; recommend to be floated. P| 002SC-L_SCH-L 7/15/98 3:28 PM Page5 | SHARP p LH28F002SC-L/SCH-L 1 INTRODUCTION This datasheet contains LH28F002SC-L/SCH-L specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28FO02SC-L/ SCH-L flash memories documentation also includes ordering information which is referenced in Section 7. 1.1 New Features The LH28F002SC-L/SCH-L SmartVoltage flash memories maintain backwards-compatibility with the LH28FO008SA. Key enhancements over the LH28F008SA include : * SmartVoltage Technology * Enhanced Suspend Capabilities In-System Block Locking Both devices share a compatible pinout, status register, and software command set. These similarities enable a clean upgrade from the LH28FO008SA to LH28F002SC-L/SCH-L. When upgrading, it is important to note the following differences : * Because of new feature support, the two devices have different device codes. This allows for software optimization. * VPPLK has been lowered from 6.5 V to 1.5 V to support 3.3 V and 5 V block erase, byte write, and lock-bit configuration operations. Designs that switch VpP off during read operations should make sure that the VPP voltage transitions to GND. * To take advantage of SmartVoltage technology, allow VPP connection to 3.3 V or 5 V. 1.2 Product Overview The LH28F002SC-L/SCH-L are high-performance 2 M-bit SmartVoltage flash memories organized as 256 k-byte of 8 bits. The 256 k-byte of data is arranged in four 64 k-byte blocks which are individually erasable, lockable, and unlockable in- system. The memory map is shown in Fig. 1. SmartVoltage technology provides a choice of Vcc and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7 V Vcc consumes approximately one-fifth the power of 5 V Vcc and 3.3 V Vcc consumes approximately one-fourth the power of 5 V Vcc. But, 5 V Vcc provides the highest read performance. Vpp at 3.3 V and 5 V eliminates the need for a separate 12 V converter, while VPP = 12 V maximizes block erase and byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP < VPPLK. Table 1 Vcc and Vpp Voltage Combinations Offered by SmartVoltage Technology Vcc VOLTAGE Vpp VOLTAGE 2.7 V (NOTE 1) _ 3.3 V 3.3V,5V,12V 5V 5V,12V NOTE : 1. Block erase, byte write and lock-bit configuration operations with Vcc < 3.0 V are not supported. Internal Vcc and VpP detection circuitry auto- matically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. A block erase operation erases one of the devices 64 k-byte blocks typically within 1 second (5 V Vcc, -5- P iT[oozse-t-scHt /15/98 3:28PM Page | SHARP p LH28F002SC-L/SCH-L 12 V VPP) independent of other blocks. Each block can be independently erased 100 000 times (0.4 million block erases per device). Block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. Writing memory data is performed in byte increments typically within 6 us (5 V Vcc, 12 V Vpp). Byte write suspend mode enables the system to read data from, or write data to any other flash memory array location. Individual block locking uses a combination of bits, four block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. Lock-bit configuration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and cleared lock-bits. The status register indicates when the WSMs block erase, byte write, or lock-bit configuration operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase, byte write, or lock-bit configuration. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. The access time is 85 ns (tAvav) at the Vcc supply voltage range of 4.75 to 5.25 V over the temperature range, 0 to +70C (LH28F002SC-L)/ 40 to +85C (LH28F002SCH-L). At 4.5 to 5.5 V Vcc, the access time is 90 ns or 120 ns. At lower Vcc voltage, the access time is 120 ns or 150 ns (3.0 to 3.6 V) and 150 ns or 170 ns (2.7 to 3.6 V). The Automatic Power Saving (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical IccR current is 1 mA at 5 V Vcc and 3 mA at 2.7 V and 3.3 V Vcc. When CE# and RP# pins are at Vcc, the Icc CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQv) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. SFFFF 64 k-Byte Block 3 30000 erFFF 64 k-Byte Block 2 20000 1FFFF 64 k-Byte Block 1 10000 OFFFF 64 k-Byte Block 0 00000 Fig. 1 Memory Map| 002SC-L_SCH-L 7/15/98 3:28 PM Page? | SHARP p LH28F002SC-L/SCH-L 2 PRINCIPLES OF OPERATION The LH28F002SC-L/SCH-L SmartVoltage flash memories include an on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby, and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure, byte writing, and lock-bit configuration. All functions associated with altering memory contentsblock erase, byte write, lock-bit configuration, status, and identifier codesare accessed via the CUI and verified through the status register. Commands are written using standard micro- processor write timings. The CUI contents serve as input to the WSM, which controls the block erase, byte write, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. 2.1 Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VpP < VPPLK, memory contents cannot be altered. The CUI, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to VpP. All write functions are disabled when Vcc is below the write lockout voltage VLKo or when RP# is at VIL. The devices block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. 3 BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read -7- P| 002SC-L_SCH-L 7/15/98 3:28 PM Page 8 | SHARP p LH28F002SC-L/SCH-L array mode. Four control pins dictate the data flow in and out of the component : CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQo-DQ7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Fig. 13 illustrates a read cycle. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQo-DQ7 are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQo-DQ7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at VIL initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tPHa@v is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, byte write, or lock-bit configuration modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARPs flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.| 002SC-L_SCH-L 7/15/98 3:28 PM Page9 | SHARP p LH28F002SC-L/SCH-L 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 30002 Block 3 Lock Configuration Code 30000 1FFFF 10004 10003 10002 Block 1 Lock Configuration Code 10001 10000 OFFFF 00004 00003 Master Lock Configuration Code 00002 Block 0 Lock Configuration Code 00001 Device Code 00000 Manufacture Code Block 0 Fig. 2 Device Identifier Code Memory Map 3.6 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VpP = VPPH1/2/3, the CUI additionally controls block erasure, byte write, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte Write command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Fig. 14 and Fig. 15 illustrate WE# and CE#-controlled write operations. 4 COMMAND DEFINITIONS When the VpP voltage < VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Placing VPPH1/2/3 on VPP enables successful block erase, byte write and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.| 002SC-L_SCH-L 7/15/98 3:28 PM Page 10 | p SHARP LH28F002SC-L/SCH-L Table 2. Bus Operations MODE NOTE RP# CE# OE# WE# |ADDRESS| Vpp DQo-7 | RY/BY# Read 1, 2, 3, 8/VIH or VHH} VIL VIL VIH x x Dout x Output Disable 3 Vidor VHH VIL VIH VIH X X High Z X Standby 3 Vidor VHHVIH X X X X High Z X Deep Power-Down 4 VIL X X X X X High Z VOH Read Identifier Codes 8 Vidor VHH VIL VIL ViH_ = |See Fig. 2 X (NOTE 5)} Vou Write 3, 6, 7, 8)VIH or VHH VIL VIH VIL x x DIN x NOTES : 1. Refer to Section 6.2.3 "DC CHARACTERISTICS. 4. RP# at GND+0.2 V ensures the lowest deep power- When Vpp < VPPLK, memory contents can be read, but down current. See Section 4.2 for read identifier code data. Command writes involving block erase, byte write, or lock-bit configuration are reliably executed when VppP = VPPH1/2/3 and Vcc = Vcc23/4. Block erase, byte write, or lock-bit configuration with Vcc < 3.0 V or VIH < RP#< VHH produce spurious results and should not be attempted. Refer to Table 3 for valid Din during a write operation. Don't use the timing both OE# and WE# are VIL. not altered. 5. X can be VIL or ViH for control pins and addresses, and 6. VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages. RY/BY# is VoL when the WSM is executing internal block erase, byte write, or lock-bit configuration algorithms. It is VoH during when the WSM is not busy, in block erase suspend mode (with byte write inactive), 7. byte write suspend mode, or deep power-down mode. 8. -10-| 002SC-L_SCH-L 7/15/98 3:28 PM Page11 | p SHARP LH28F002SC-L/SCH-L Table 3 Command Definitions (NOTE 9) COMMAND BUS CYCLES NOTE FIRST BUS CYCLE SECOND BUS CYCLE REQD. Oper (NOTE 1)| Addr NOTE 2)| Data (NOTE 3) Oper (NOTE 1)| Addr (NOTE 2)| Data (NOTE 3) Read Array/Reset 1 Write X FFH Read Identifier Codes 22 4 Write x 90H Read lA ID Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase 2 5 Write BA 20H Write BA DOH Byte Write 2 5,6 Write WA 40H or 10H] Write WA WD Block Erase and { 5 Write X BoH Byte Write Suspend Block Erase and { 5 Write X DOH Byte Write Resume Set Block Lock-Bit 2 7 Write BA 60H Write BA 01H Set Master Lock-Bit 2 7 Write x 60H Write x F1H Clear Block Lock-Bits 2 8 Write Xx 60H Write Xx DOH NOTES : 1. Bus operations are defined in Table 2. X = Any valid address within the device. lA = Identifier code address : see Fig. 2. BA = Address within the block being erased or locked. WA = Address of memory location to be written. SRD = Data read from status register. See Table 6 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever ID = Data read from identifier codes. Following the Read Identifier Codes command, read operations access manufacture, device, block lock, and master lock codes. See Section 4.2 for read identifier 2. 3. goes high first). 4. code data. 5. If the block is locked, RP# must be at VHH to enable block erase or byte write operations. Attempts to issue a block erase or byte write to a locked block while RP# is VIH. Either 40H or 10H is recognized by the WSM as the byte write setup. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is ViH. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. -11-| 002SC-L_SCH-L 7/15/98 3:28 PM Page12 | SHARP p LH28F002SC-L/SCH-L 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, byte write or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and RP# can be VIH or VHH. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Fig. 2 retrieve the manufacture, device, block lock configuration and master lock configuration codes (see Table 4 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read ldentifier Codes command functions independently of the VPP voltage and RP# can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read : Table 4 Identifier Codes CODE ADDRESS Manufacture Code 00000H Device Code 00001H Block Lock Configuration XO002H (NOTE 1)F * Block is Unlocked * Block is Locked * Reserved for Future Use Master Lock Configuration 00003H * Device is Unlocked * Device is Locked * Reserved for Future Use NOTE : 1. X selects the specific block lock configuration code to be read. See Fig. 2 for the device identifier code memory map. 4.3 Read Status Register Command The status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VpP voltage. RP# can be VIH or VHH. 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 6). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. RP# can be VIH or VHH. This command is not functional during block erase or byte write suspend modes. 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by a block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, -12- P| 002SC-L_SCH-L 7/15/98 3:28 PM Page 13 | SHARP p LH28F002SC-L/SCH-L the device automatically outputs status register data when read (see Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when Vcc = Vec2a4 and VeP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP < VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to "1". Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.6 Byte Write Command Byte write is executed by a two-cycle command sequence. Byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the byte write and write verify algorithms internally. After the byte write sequence is written, the device automatically outputs status register data when read (see Fig. 4). The CPU can detect the completion of the byte write event by analyzing the RY/BY# pin or status register bit SR.7. When byte write is complete, status register bit SR.4 should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for 1"s that do not successfully write to "O"s. The CUI remains in read status register mode until it receives another command. Reliable byte writes can only occur when Vcc = Vec23/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against byte writes. If byte write is attempted while VpP < VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful byte write requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If byte write is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1". Byte write operations with VIH < RP# < VHH produce spurious results and should not be atternpted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block erase interruption to read or byte write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification twHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Byte -13- P L| 002SC-L_SCH-L 7/15/98 3:28 PM Page 14 | SHARP p LH28F002SC-L/SCH-L Write Suspend command (see Section 4.8), a byte write operation can also be suspended. During a byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/BY# output will transition to VOL. However, SR.6 will remain 1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VoL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Fig. 5). VPP must remain at VPPH1/23 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until byte write operations initiated during block erase suspend have completed. 4.8 Byte Write Suspend Command The Byte Write Suspend command allows byte write interruption to read data in other flash memory locations. Once the byte write process starts, writing the Byte Write Suspend command requests that the WSM suspend the byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the byte write operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. Specification tWHRH1 defines the byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while byte write is suspended are Read Status Register and Byte Write Resume. After Byte Write Resume command is written to the flash memory, the WSM will continue the byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to VOL. After the Byte Write Resume command is written, the device automatically outputs status register data when read (see Fig. 6). VPP must remain at VPPH1/2/3 (the same VPP level used for byte write) while in byte write suspend mode. RP# must also remain at VIH or VHH (the same RP# level used for byte write). 4.9 Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are executed by a two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Fig. 7). The CPU can detect the completion of the set lock- bit event by analyzing the RY/BY# pin output or status register bit SR.7. -14- P| 002SC-L_SCH-L 7/15/98 3:28 PM Page15 | SHARP p LH28F002SC-L/SCH-L When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1". Also, reliable operations occur only when Vcc = Vcce23/4 and VPP = VpPH1/2/3. In the absence of this high voltage, lock- bit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP# = VHH. If it is attempted with RP# = ViIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and VHH on the RP# pin. See Table 5 for a summary of hardware and software write protection options. Clear block lock-bits operation is executed by a two-cycle command sequence. A clear block lock- bits setup is first written. After the command is written, the device automatically outputs status register data when read (see Fig. 8). The CPU can detect completion of the clear block lock-bits event by analyzing the RY/BY# pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bits error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock- Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1". Also, a reliable clear block lock-bits operation can only occur when Vec = Vece2is4 and VP = VPPH1/2/3. If a clear block lock-bits operation is attempted while VPP < VPPLK, SR.3 and SR.5 will be set to "1". In the absence of this high voltage, the block lock-bit contents are protected against alteration. A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be atternpted. If a clear block lock-bits operation is aborted due to VpP or Vcc transition out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. -15- P| 002SC-L_SCH-L 7/15/98 3:28 PM Page 16 | SHARP p LH28F002SC-L/SCH-L Table 5 Write Protection Alternatives OPERATION MASTER | BLOCK RP# EFFECT LOCK-BIT|LOCK-BIT 0 ViH or VHH} Block Erase and Byte Write Enabled Block Erase , , - or Byte Write xX 1 VIH Block is Locked. Block Erase and Byte Write Disabled yt VHH Block Lock-Bit Override. Block Erase and Byte Write Enabled 0 x VIH or VHH| Set Block Lock-Bit Enabled Set Block Lock-Bit 1 Xx VIH Master Lock-Bit is Set. Set Block Lock-Bit Disabled VHH Master Lock-Bit Override. Set Block Lock-Bit Enabled Set Master X X VIH Set Master Lock-Bit Disabled Lock-Bit VHH Set Master Lock-Bit Enabled 0 x VIH or VHH| Clear Block Lock-Bits Enabled Clear Block , , Lock-Bits { X VIH Master Lock-Bit is Set. Clear Block Lock-Bits Disabled VHH Master Lock-Bit Override. Clear Block Lock-Bits Enabled Table 6 Status Register Definition | WSMS | ESS | ECLBS | BWSLBS | VPPS | BWSS | DPS | R | 7 6 5 4 3 2 1 0 NOTES : SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS (ECLBS) 1 = Error in Block Erase or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = BYTE WRITE AND SET LOCK-BIT STATUS (BWSLBS) 1 = Error in Byte Write or Set Master/Block Lock-Bit 0 = Successful Byte Write or Set Master/Block Lock-Bit SR.3 = Ver STATUS (VPPS) 1 = VepP Low Detect, Operation Abort O = VpP OK SR.2 = BYTE WRITE SUSPEND STATUS (BWSS) 1 = Byte Write Suspended 0 = Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Check RY/BY# or SR.7 to determine block erase, byte write, or lock-bit configuration completion. SR.6-0 are invalid while SR.7 = "0". If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the Vpp level only after Block Erase, Byte Write, Set Block/Master Lock-Bit, or Clear Block Lock-Bits command sequences. SR.3 is not guaranteed to reports accurate feedback only when Vpp # VPPH1/2/3. SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock- bit, block lock-bit, and RP# only after Block Erase, Byte Write, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not VHH. Reading the block lock and master lock configuration codes after writing the Read Identifier Codes command indicates master and block lock-bit status. SR.O is reserved for future use and should be masked out when polling the status register. -16- P002SC-L_SCH-L 7/15/98 3:28 PM Page 17 SHARP LH28F002SC-L/SCH-L OPERATION COMMAND COMMENTS . Data = 20H Write 20H, Write | Erase Setup | addr Within Block to be Erased Block Address Writ Erase Data = DOH v rs Confirm | Addr = Within Block to be Erased Write DOH, Read Status Register Data Block Address v Check SR.7 Standby 1 =WSM Ready Read 0 = WSM Busy Status Register Full Status Check if Desired Read Status Registe' Data (See Above) Block Erase Successful Suspend Block Erase Loop FULL STATUS CHECK PROCEDURE Vpp Range Error Device Protect Error Command Sequence Error Block Erase Error Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last block erase operation to place device in read array mode. BUS OPERATION| COMMAND COMMENTS Check SR.3 Standby 1 = Vpp Error Detect Check SR.1 1 = Device Protect Detect Standby RP# = Vin, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Check SR.4, 5 Standby Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. Fig. 3 Automated Block Erase Flowchart -17-002SC-L_SCH-L 7/15/98 3:28 PM Page18 SHARP LH28F002SC-L/SCH-L OPERATION COMMAND COMMENTS - Writ Setup Data = 40H Write 40H, rs Byte Write | Addr = Location to be Written Address Writ Byte Writ Data = Data to be Written v me yte Write Addr = Location to be Written Write Byte Read Status Register Data Data and Address v Check SR.7 Standby 1 =WSM Ready Read 0 = WSM Busy Status Register Repeat for subsequent byte writes. Suspend Byte P 4 vt Write Loop SR full status check can be done after each byte write or after a sequence of byte writes. Write FFH after the last byte write operation to place device in read array mode. Full Status Check if Desired FULL STATUS CHECK PROCEDURE Read Status Registe BUS Data (See Above) OPERATION] COMMAND COMMENTS Check SR.3 Standby 1 = Vpp Error Detect Vpp Range Error Check SR.1 1 = Device Protect Detect Standby RP# = ViH, Block Lock-Bit is Set Only required for systems implementing lock-bit configuration Device Protect Error Standb Check SR.4 andby 1 = Data Write Error SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are Byte Write Error written before full status is checked. If error is detected, clear the status register before attempting retry or other error recovery. Byte Write Successful Fig. 4 Automated Byte Write Flowchart - 18 -[oozse-t-scHt 1/15/98 3:28 PM Page 19 + SHARP LH28F002SC-L/SCH-L Write Erase Data = BOH Write BOH Suspend Addr = X Status Register Data v Read Addr = X Read Check SR.7 Status Register Standby 1 =WSM Ready 0 = WSM Busy Check SR.6 Standby 1 = Block Erase Suspended 0 = Block Erase Completed Write Erase Data = DOH Resume Addr = X Block Erase Completed Byte Write Read Array Data Byte Write Loop No Vv Write DOH Write FFH Block Erase Read Resumed Array Data ff Fig. 5 Block Erase Suspend/Resume Flowchart -19- | P[oozse-t-scHt /15/98 3:28 PM Page 20 + SHARP LH28F002SC-L/SCH-L OPERATION | COMMAND COMMENTS . Byte Write | Data =BOH Write Write BOH Suspend Addr = X Status Register Data v Read Addr = X Read Check SR.7 Status Register Standby 1 = WSM Ready 0 = WSM Busy Check SR.2 Standby 1 = Byte Write Suspended 0 = Byte Write Completed Write Read Array ren = x Byte Write Read Read array locations other Completed than that being written. . Byte Write | Data = DOH ' Write Resume Addr = X Write FFH Read Array Data y Write DOH Write FFH . Read & Write Resured) Array Data Fig.6 Byte Write Suspend/Resume Flowchart - 20 - ff002SC-L_SCH-L 7/15/98 3:28 PM Page 21 SHARP LH28F002SC-L/SCH-L a OPERATION| COMMAND COMMENTS Set ; Data = 60H Write 60H, Write Block/Master Addr = Block Address (Block), Block/Device Address ock-Bit Device Address (Master) v Setup Set Data = 01H (Block), Write 01H/F1H, Write Block or Master F1H (Master) Block/Device Address Lock-Bit Addr = Block Address (Block), v Confirm Device Address (Master) Read PB Read Status Register Data Status Register g Check SR.7 Standby 1 =WSM Ready 0 0 = WSM Busy Repeat for subsequent lock-bit set operations. Full status check can be done after each lock-bit set 1 operation or after a sequence of lock-bit set operations. Full Status Write FFH after the last lock-bit set operation to place device Check if Desired in read array mode. Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Registe BUS Data (See Above) OPERATION] COMMAND COMMENTS Check SR.3 Standby 1 = Vpp Error Detect Vpp Range Error Check SR.1 1 = Device Protect Detect RP# = VIH Standby (Set Master Lock-Bit Operation) RP# = VIH, Master Lock-Bit is Set . (Set Block Lock-Bit Operation) Device Protect Error Check SR.4, 5 Standby Both 1 = Command Sequence Error Standb Check SR.4 Command Sequence aneby 1 = Set Lock-Bit Error Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple lock-bits are set before full status is checked. Set Lock-Bit If error is detected, clear the status register before attempting Error retry or other error recovery. Set Lock-Bit Successful Fig. 7 Set Block and Master Lock-Bit Flowchart -21-002SC-L_SCH-L 7/15/98 3:28 PM Page 22 + SHARP LH28F002SC-L/SCH-L Clear Block . Data = 60H Write 60H write Locksits | agar = x Setup v / Clear Block Data = DOH Write Lock-Bits | aqgr=X Write DOH Confirm v Read Status Register Data Read a : i< Check SR.7 Status Register Standby 1 = WSM Ready 0 = WSM Busy Write FFH after the last clear block lock-bits operation to place 0 device in read array mode. 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Registe BUS Data (See Above) OPERATION] COMMAND COMMENTS Check SR.3 Standby 1 = Vpp Error Detect Vpp Range Error Check SR.1 Standby 1 = Device Protect Detect RP# = VIH, Master Lock-Bit is Set Check SR.4, 5 . Standby Both 1 = Command Sequence Error Device Protect Error Check SR.5 Standby 1 = Clear Block Lock-Bits Error SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Command Sequence Status Register command. Error If error is detected, clear the status register before attempting retry or other error recovery. Clear Block Lock-Bits Error Clear Block Lock-Bits Successful Fig. 8 Clear Block Lock-Bits Flowchart - 22 - P| 002SC-L_SCH-L 7/15/98 3:28 PM Page 23 | SHARP p LH28F002SC-L/SCH-L 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three- line control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the systems READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGCOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 RY/BY# and Block Erase, Byte Write, and Lock-Bit Configuration Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. It transitions low after block erase, byte write, or lock- bit configuration commands and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also VOH when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. 5.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 pF ceramic capacitor connected between its Vcc and GND and between its VPP and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 UF electrolytic capacitor should be placed at the arrays power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 Vpp Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the Vcc power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. 5.5 Vcc, Vpp, RP# Transitions Block erase, byte write and lock-bit configuration are not guaranteed if VPP falls outside of a valid VPPH1/2/3 range, Vcc falls outside of a valid Vec2/3/4 range, or RP# # VIH or VHH. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to VIL during block erase, byte write, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal - 23 - P| 002SC-L_SCH-L 7/15/98 3:28 PM Page 24 | SHARP p LH28F002SC-L/SCH-L operation is restored. Device power-off or RP# transitions to ViL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power- down or after Vcc transitions below VLKo. After block erase, byte write, or lock-bit configuration, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon power- up, the device is indifferent as to which power supply (VPP or Vcc) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for Vcc voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUIs two-step command sequence architecture provides added level of protection against data alteration. In-system block lock and unlock capability prevents inadvertent data alteration. The device is disabled while RP# = VIL regardless of its control inputs state. 5.7 Power Consumption When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memorys nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid- state storage can consume negligible power by lowering RP# to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQv and tPHWL wake-up cycles required after RP# is first raised to VIH. See Section 6.2.4 through 6.2.6 "AC CHARACTERISTICS READ-ONLY and WRITE OPERATIONS and Fig. 13, Fig. 14 and Fig. 15 for more information. - 24 - L| 002SC-L_SCH-L 7/15/98 3:28 PM Page 25 | SHARP p LH28F002SC-L/SCH-L 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature * LH28F002SC-L During Read, Block Erase, Byte Write and Lock-Bit Configuration -------- 0 to +70C (NOTE 1) Temperature under Bias ---+-++--+- -10 to +80C * LH28F002SCH-L During Read, Block Erase, Byte Write and Lock-Bit Configuration --- 40 to +85C (NOTE 2) Temperature under Bias::--+-+---: 40 to +85C Storage Temperature vss :t reeset 65 to +125C Voltage On Any Pin (except Vcc, VPP, and RP#)------- -2.0 to +7.0 V (NOTES) Voc Supply Voltage: -2.0 to +7.0 V (NOTES) VpepP Update Voltage during Block Erase, Byte Write and Lock-Bit Configuration ------ 2.0 to +14.0 V (NOTES, 4) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations weer eee ee eens ?2.0 to +14.0 V (NOTE 3, 4) Output Short Circuit Current +--+ 100 mA (NOTES) 6.2 Operating Conditions NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. *WARNING : Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTE : 1. Operating temperature is for commercial product defined by this specification. 2. Operating temperature is for extended temperature product defined by this specification. 3. All specified voltages are with respect to GND. Minimum DC voltage is 0.5 V on input/output pins and 0.2 V on Vcc and VP pins. During transitions, this level may undershoot to 2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins and Vcc is Vcc+0.5 V which, during transitions, may overshoot to Vcc+2.0 V for periods < 20 ns. 4. Maximum DC voltage on Ver and RP# may overshoot to +14.0 V for periods < 20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. SYMBOL PARAMETER NOTE | MIN. MAX. | UNIT VERSIONS TA Operating Temperature 1 o +70 LH26F002SC-L -40 +85 C LH28FO002SCH-L Vect Voc Supply Voltage (2.7 to 3.6 V) 2 2.7 3.6 Vv Vec2 Voc Supply Voltage (3.3+0.3 V) 3.0 3.6 Vv Vec3 Voc Supply Voltage (5.00.25 V) 4.75 5.25 Vv LH28F002SC-L85/SCH-L85 Vec4 Voc Supply Voltage (5.00.5 V) 4.50 5.50 Vv NOTES : 1. Test condition : Ambient temperature 2. Block erase, byte write and lock-bit configuration operations with Vcc < 3.0 V should not be attempted. - 25 - P ff[oozse-t-scHt /15/98 3:28 PM Page 26 + SHARP LH28F002SC-L/SCH-L 6.2.1. CAPACITANCE (NOTE 1) Ta = +25C, f = 1 MHz SYMBOL PARAMETER TYP. MAX. UNIT CONDITION CIN Input Capacitance 6 8 pF VIN =0.0 V COUT Output Capacitance 8 12 pF VouT = 0.0 V NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS ) 2.7 4 INPUT 1.35 < TEST POINTS > % 1.35 OUTPUT 0.0 ae AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) < 10 ns. Fig.9 Transient Input/Output Reference Waveform for Vcc = 2.7 to 3.6 V 3.0 INPUT 1.5 <_- TEST POINTS - 1.5 OUTPUT } 0.0 2 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. Fig. 10 Transient Input/Output Reference Waveform for Vcc = 3.340.3 V and Vcc = 5.040.25 V (High Speed Testing Configuration) 2.4 ( 2.0 a4 2.0 INPUT > TEST POINTS <C OUTPUT 0.8 0.8 0.45 f 2 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VoL (0.45 VTTL) for a Logic "0". Input timing begins at VIH (2.0 VTTL) and ViL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. Fig. 11 Transient Input/Output Reference Waveform for Vcc = 5.040.5 V (Standard Testing Configuration) - 26 - | P iT| 002SC-L_SCH-L 7/15/98 3:28 PM Page 27 | p SHARP LH28F002SC-L/SCH-L Test Configuration Capacitance Loading Value 1.3V TEST CONFIGURATION CL (pF) Vcc = 3.340.3 V, 2.7 to 3.6 V 50 1NO14 Voc = 5.0+0.25 V (NOTE 1) 30 Vcc = 5.040.5 V 100 NOTE : RL = 3.3 kQ 1. Applied to high-speed products, LH28FO02SC-L85 and LH28F002SCH-L85. DEVICE UNDER OUT TEST 7TS CL CL Includes Jig Capacitance Fig. 12 Transient Equivalent Testing Load Circuit -27- L[oozse-t-scHt /15/98 3:28 PM Page 28 + SHARP LH28F002SC-L/SCH-L 6.2.3 DC CHARACTERISTICS Vcc = 2.7 to 3.6 V| Vcc = 3.340.3 Vj Vcc = 5.040.5 V| TEST SYMBOL PARAMETER NOTE Typ. | MAX.| TyP. | MAX.| TYP.| MAX.|UN'"| CONDITIONS ILI Input Load Current 1 +0.5 +0.5 +1 | pA Voc = Vcc Max. Vin = Voc or GND ILo Output Leakage Current} 1 +0.5 +0.5 +10 | pA Voc = Vcc Max. Vout = Vcc or GND CMOS Inputs 20 100 20 100 25 100 | PA | Voc = Vcc Max. CE# = RP# = Vcc+0.2 V ff Iccs | Vcc Standby Current 1,3,6 TTL Inputs 0.1 2 0.2 2 0.4 2 mA | Vcc = Vcc Max. CE# = RP# = VIH LH28F002 10 10 10 lecp Vcc Deep Power- SC-L vA RP# = GND+0.2 V Down Current LH28F002 20 20 20 louT (RY/BY#) = 0 mA SCH-L CMOS Inputs Vcc = Vcc Max. 6 | 12 | 7 | 12 | 17 | 35 | ma | CE#= GND f = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) IccR | Vcc Read Current 1,5,6 lour = 0 mA TTL Inputs Vcc = Vcc Max. 7 | 138 | 8 | 18 | 20 | 50 | ma] CE#= GND f = 5 MHz (3.3 V, 2.7 V), 8 MHz (5 V) louT=OmA Vcc Byte Write or 17 mA | VpP = 3.3+0.3 V Iccw . 1,7; _ 17 35 mA | VPP = 5.0+0.5 V Set Lock-Bit Current 12 30 mA | Vep = 12.0+0.6 V Vcc Block Erase or _ _ 17 _ _ mA | VPP = 3.3+0.3 V IccE | Clear Block Lock-Bits 1,7/ _ 17 30 mA | Vep = 5.0+0.5 V Current _ _ 12 25 mA | VPP = 12.0+0.6 V Iccws | Vcc Byte Write or Block 1,2| _ 1 6 1 10 | mA|CE#=ViH Icces | Erase Suspend Current IPPs | VPP Standby or { +2 +15 +2 +15 +2 +15 | pA | VPP < Voc IPPR_ | Read Current 10 200 10 200 10 200 | PA | VPP > Voc Vpp Deep Power-Down IPPD 1 0.1 5 0.1 5 0.1 5 A | RP# = GND+0.2 V Current Vpp Byte Write or 40 mA | VpP = 3.3+0.3 V IPPW : 1,7| _ 40 40 mA | Vpp = 5.040.5 V Set Lock-Bit Current 15 15 mA | Vep = 12.0+0.6 V VpP Block Erase or _ _ 20 _ _ mA | VPP = 3.3+0.3 V IPPE | Clear Block Lock-Bits 1,7/ _ 20 20 mA | VPP = 5.0+0.5 V Current _ _ 15 15 mA | VPP = 12.0+0.6 V Ippws | Vp Byte Write or Block | 4 | _ | _ | 40 | 200 | 10 | 200 | pa | Ver = VePHias IPPES_ | Erase Suspend Current - 28 -| 002SC-L_SCH-L 7/15/98 3:28 PM Page 29 | SHARP p LH28F002SC-L/SCH-L 6.2.3 DC CHARACTERISTICS (contd.) Vcc = 2,7 to 3.6 V| Vcc = 3.340.3 V| Voc = 5.040.5 V TEST SIMBO! PARAMETER (NOTED Min. [MAX.| MIN. | MAX.| MIN. | MAX.|-"| CONDITIONS VIL Input Low Voltage 7 | -05| 08 | -05|] 08 | -05] 08 Vv . Vcc Vcc Vcc VIH Input High Voltage 7 2.0 40.5 2.0 405 2.0 405 Vv Vec = Vcc Min. VoL | Output Low Voltage 3,7 0.4 0.4 0.45 | V | loL=5.8 mA (5 V) lo. = 2.0 mA (3.3 V, 2.7 V) . Vec = Vcc Min. Vout chy tHigh Voltage | 37] 24 2.4 2.4 V | lon =-2.5 mA (5 V) loH = -2.0 mA (3.3 V, 2.7 V) 0.85 0.85 0.85 Vec = Vcc Min. Output High Voltage Voc Vcc Vcc V loH = -2.5 mA Vor | (mos) 3.7 Veg Voc Voc Voc = Voc Min. 0.4 0.4 0.4 V loH = -100 PA VPPLK Vpp Lockout Voltage during 4,7 15 15 15 V Normal Operations VpP Voltage during VPPH1| Byte Write, Block Erase _ _ 3.0 3.6 _ _ Vv or Lock-Bit Operations VpP Voltage during VPPH2] Byte Write, Block Erase _ _ 4.5 5.5 4.5 5.5 Vv or Lock-Bit Operations VpP Voltage during VPPH3] Byte Write, Block Erase _ _ 11.4] 12.6 | 11.4) 12.6 Vv or Lock-Bit Operations VLKo | Voc Lockout Voltage 2.0 2.0 2.0 Vv Set master lock-bit VHH | RP# Unlock Voltage 8,9} _ 11.4] 12.6] 11.4} 12.6 V_ | Override master and block lock-bit NOTES : 1. All currents are in RMS unless otherwise noted. Typical 6. CMOS inputs are either Vect0.2 V or GND+0.2 V. TTL values at nominal Vcc voltage and Ta = +25C. These inputs are either VIL or VIH. currents are valid for all product versions (packages and 7. Sampled, not 100% tested. speeds). 8. Master lock-bit set operations are inhibited when RP# = 2. Iccws and Icces are specified with the device de- ViH. Block lock-bit configuration operations are inhibited selected. If reading or byte writing in erase suspend when the master lock-bit is set and RP# = VIH. Block mode, the devices current draw is the sum of Iccws or erases and byte writes are inhibited when the Icces and Iccr or Iccw, respectively. corresponding block lock-bit is set and RP# = ViH. Block 3. Includes RY/BY#. erase, byte write, and lock-bit configuration operations 4. Block erases, byte writes, and lock-bit configurations are are not guaranteed with Vcc < 3.0 V or VIH < RP# < inhibited when VPP < VPPLK, and not guaranteed in the VHH and should not be attempted. range between VPPLK (max.) and VPPH1 (min.), between 9. RP# connection to a VHH supply is allowed for a VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.) maximum cumulative period of 80 hours. and VPPHS (min.), and above VPPH3 (max.). 5. Automatic Power Saving (APS) reduces typical Iccr to 1 mA at 5 V Vcc and 3 mA at 2.7 V and 3.3 V Vcc in static operation. - 29 - P[oozse-t-scHt /15/98 3:28 PM Page 30 + SHARP LH28F002SC-L/SCH-L 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (NOTE 1) * Vcc = 2.7 to 3.6 V, Ta = 0 to 70C or 40 to +85C LH28F002SC-L85 LH28F002SC-L12 VERSIONS LH28F002SCH-L85 | LH28FOO2SCH-L12 |UNIT SYMBOL PARAMETER NOTE MIN. MAX. MIN. MAX. tavav | Read Cycle Time 150 170 ns tavav | Address to Output Delay 150 170 ns teLqv | CE# to Output Delay 2 150 170 ns tPHQV | RP# High to Output Delay 600 600 ns taLav | OE# to Output Delay 2 50 55 ns teELQx | CE# to Output in Low Z 3 0 0 ns teHQz | CE# High to Output in High Z 3 55 55 ns taLax | OE# to Output in Low Z 3 0 0 ns taHaz | OE# High to Output in High Z 3 20 25 ns Output Hold from Address, CE# or tOH OE# Change, Whichever Occurs First 3 0 0 ns Vcc = 3.340.3 V, Ta = 0 to +70C or 40 to +85C LH28F002SC-L85 LH28F002SC-L12 VERSIONS LH28F002SCH-L85 | LH28F002SCH-L12 | UNIT SYMBOL PARAMETER NOTE MIN. MAX. MIN. MAX. tavav | Read Cycle Time 120 150 ns tavav | Address to Output Delay 120 150 ns teLqv | CE# to Output Delay 2 120 150 ns tPHQV | RP# High to Output Delay 600 600 ns taLav | OE# to Output Delay 2 50 55 ns tELQx | CE# to Output in Low Z 3 0 0 ns teHQz =| CE# High to Output in High Z 3 55 55 ns taLax | OE# to Output in Low Z 3 0 0 ns taHaz | OE# High to Output in High Z 3 20 25 ns Output Hold from Address, CE# or tOH . . 3 0 0 ns OE# Change, Whichever Occurs First NOTES : 1. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. 2. OE# may be delayed up to teLav-taLav after the falling edge of CE# without impact on tELav. 3. Sampled, not 100% tested. - 30 - ff| 002SC-L_SCH-L 7/15/98 3:28 PM Page 31 | SHARP p LH28F002SC-L/SCH-L 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) (NOTE 1) e Vcc = 5.040.25 V, 5.00.5 V, Ta = 0 to +70C or 40 to +85C (NOTE 4) Vect0.25 V | LH28F002SC-L85 LH28F002SCH-L85 VERSIONS (NOTE 5) (NOTE 5) UNIT Vect0.5 V LH28F002SC-L85 | LH28F002SC-L12 LH28F002SCH-L85 | LH28F002SCH-L12 SYMBOL PARAMETER NOTE| MIN. MAX. MIN. MAX. MIN. MAX. tavav | Read Cycle Time 85 90 120 ns tavev | Address to Output Delay 85 90 120 ns teELqv | CE# to Output Delay 2 85 90 120 ns tPHav. | RP# High to Output Delay 400 400 400 ns teLaqv | OE# to Output Delay 2 40 45 50 ns tELQx | CE# to Output in Low Z 3 0 0 0 ns tEHQZ | CE# High to Output in High Z 3 55 55 55 ns teLax | OE# to Output in Low Z 3 0 0 0 ns tGHQz | OE# High to Output in High Z 3 10 10 15 ns Output Hold from Address, tOH CE# or OE# Change, 3 0 0 0 ns Whichever Occurs First NOTES : 1. See AC Input/Output Reference Waveform (Fig. 9 through Fig. 11) for maximum allowable input slew rate. 2. OE# may be delayed up to tELav-taLav after the falling edge of CE# without impact on tELav. 3. Sampled, not 100% tested. 4. See Fig. 10 "Transient Input/Output Reference Waveform and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Speed Configuration) for testing characteristics. 5. See Fig. 11 "Transient Input/Output Reference Waveform and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. -31-[oozse-t-scHt 1/15/98 3:28 PM Page 32 + SHARP LH28F002SC-L/SCH-L Device Standby Address Selection Data Valid VER VOTO T TR EO 0 r VYYYYYY ADDRESSES (A) KXKXXK XX Address Stable xX XXXXKXKX VIL mw XXXKXXX VAV ViH CE# (E) / \ 7 \ a teHaz Vin yf S~S OE# (G) / \ \ tcnaz \ VIL A _/ TELaV V4o>6--e Se WE (W) / | tevav \ Vit taLax LE teLax . a| tou DATA (DIQ) OY Highz + i Vane, - FVVS high z (DQo - DQ7) \ L alid Output | a Vow tavav tT Vec / ~ \ . tPHav | Vin DD RP# (P) \ VIL ff Fig. 13 AC Waveform for Read Operations - 32- | P[oozse-t-scHt 1/15/98 3:28 PM Page 33 + SHARP LH28F002SC-L/SCH-L 6.2.5 AC CHARACTERISTICS - WRITE OPERATION (NOTE 1) Vcc = 2.7 to 3.6 V, Ta = 0 to +70C or 40 to +85C LH28F002SC-L85 LH28F002SC-L12 VERSIONS LH28F002SCH-L85 | LH28F002SCH-L12 |UNIT SYMBOL PARAMETER NOTE MIN. MAX. MIN. MAX. tavav_| Write Cycle Time 150 170 ns tpHwL_ | RP# High Recovery to WE# Going Low 2 1 1 Us teLwL | CE# Setup to WE# Going Low 10 10 ns twLwH_ | WE# Pulse Width 50 50 ns tavwi__| Address Setup to WE# Going High 3 50 50 ns tpvwH | Data Setup to WE# Going High 3 50 50 ns twHDx | Data Hold from WE# High 5 5 ns twHAx | Address Hold from WE# High 5 5 ns tWHEH | CE# Hold from WE# High 10 10 ns twHwL_ | WE# Pulse Width High 30 30 ns tWHGL | Write Recovery before Read 0 0 ns Vcc = 3.340.3 V, Ta = 0 to +70C or 40 to +85C LH28F002SC-L85 LH28F002SC-L12 VERSIONS LH28F002SCH-L85 | LH28FO02SCH-L12 |UNIT SYMBOL PARAMETER NOTE MIN. MAX. MIN. MAX. tavav_| Write Cycle Time 120 150 ns tPpHwL_ | RP# High Recovery to WE# Going Low 2 1 1 Us teELWL_ | CE# Setup to WE# Going Low 10 10 ns twLwH | WE# Pulse Width 50 50 ns tPHHWH | RP# VHH Setup to WE# Going High 2 100 100 ns tvPWH_ | VPP Setup to WE# Going High 2 100 100 ns tavwH__| Address Setup to WE# Going High 3 50 50 ns tovwH | Data Setup to WE# Going High 3 50 50 ns twHDx | Data Hold from WE# High 5 5 ns tWHAX | Address Hold from WE# High 5 5 ns tWHEH | CE# Hold from WE# High 10 10 ns twHwL_ | WE# Pulse Width High 30 30 ns tWHRL | WE# High to RY/BY# Going Low 100 100 ns tWHGL_ | Write Recovery before Read 0 0 ns tQVVL VppP Hold from Valid SRD, RY/BY# High 2,4 0 0 ns tavPpH | RP# VHH Hold from Valid SRD, RY/BY# High | 2, 4 0 0 ns NOTES : 1. Read timing characteristics during block erase, byte write 3. Refer to Table 3 for valid Ain and DIN for block erase, and lock-bit configuration operations are the same as byte write, or lock-bit configuration. during read-only operations. Refer to Section 6.2.4 "AC 4. Vpp should be held at VPPH1/23 (and if necessary RP# CHARACTERISTICS" for read-only operations. should be held at VHH) until determination of block erase, 2. Sampled, not 100% tested. byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). - 33 - | P ff| 002SC-L_SCH-L 7/15/98 3:29 PM Page 34 | SHARP p LH28F002SC-L/SCH-L 6.2.5 AC CHARACTERISTICS - WRITE OPERATION (contd.) (NOTE 1) e Vcc = 5.0+0.25 V, 5.040.5 V, Ta = 0 to +70C or 40 to +85C (NOTE 5) Vcct0.25 V | LH28F002SC-L85 LH28F002SCH-L85 VERSIONS (NOTE 6) (NOTE 6) UNIT Vcct0.5 V LH28F002SC-L85 | LH28F002SC-L12 LH28F002SCH-L85 | LH28FO02SCH-L12 SYMBOL PARAMETER NOTE}; MIN. MAX. MIN. MAX. MIN. MAX. tavav | Write Cycle Time 85 90 120 ns RP# High Recovery to WE# TPHWL . 2 1 1 1 Us Going Low teLwL_ | CE# Setup to WE# Going Low 10 10 10 ns twlwH_ | WE# Pulse Width 40 40 40 ns tPHHWH | RP# VHH Setup to WE# Going High] 2 100 100 100 ns tvPwH_ | VPP Setup to WE# Going High 2 100 100 100 ns tavwH__| Address Setup to WE# Going High 3 40 40 40 ns tpvwH_ | Data Setup to WE# Going High 3 40 40 40 ns twHDx | Data Hold from WE# High 5 5 5 ns twHax | Address Hold from WE# High 5 5 5 ns tWHEH =| CE# Hold from WE# High 10 10 10 ns twHwL | WE# Pulse Width High 30 30 30 ns twHRL_ | WE# High to RY/BY# Going Low 90 90 90 ns twHeL_ | Write Recovery before Read 0 0 0 ns tow. Vpp Hold from Valid SRD, 24 0 0 0 ng RY/BY# High , RP# V i tov # VHH Hold from Valid SRD, 24 0 0 0 ns RY/BY# High NOTES : 1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. Refer to Section 6.2.4 "AC CHARACTERISTICS" for read-only operations. Sampled, not 100% tested. Refer to Table 3 for valid Ain and DIN for block erase, byte write, or lock-bit configuration. Vpp should be held at VPPH1/23 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 10 "Transient Input/Output Reference Waveform and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Seed Configuration) for testing characteristics. 6. See Fig. 11 "Transient Input/Output Reference Waveform and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. - 34 - ff[oozse-t-scHt 1/15/98 3:29 PM Page 35 + SHARP LH28F002SC-L/SCH-L (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) ms <{!AU 7 * oF . _ ViH ADDRESSES (A) AIN VIL ViH CE# (E) VIL ViH OE# (G) VIL TWHQV1/2/3/4 ViH WE# (W) VIL ViH DATA (D/Q) VIL Vou RY/BY# (R) VoL TPHHWH VHH RP#(P) VIH VIL VPPH1/2/3 Vpp(V) VPPLK VIL NOTES : Vcc power-up and standby. Write block erase or byte write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. Oar WON > Fig. 14 AC Waveform for WE#-Controlled Write Operations -35- | P[oozse-t-scHt /15/98 3:29 PM Page 36 + SHARP LH28F002SC-L/SCH-L 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1) Vcc = 2.7 to 3.6 V, Ta = 0 to +70C or 40 to +85C LH28F002SC-L85 LH28F002SC-L12 VERSIONS LH28F002SCH-L85 | LH28FO02SCH-L12 |UNIT SYMBOL PARAMETER NOTE MIN. MAX. MIN. MAX. tavav | Write Cycle Time 150 170 ns tPHEL | RP# High Recovery to CE# Going Low 2 1 1 ys twLeL_ | WE# Setup to CE# Going Low 0 0 ns tELEH | CE# Pulse Width 70 70 ns taveEH | Address Setup to CE# Going High 3 50 50 ns tpvEH | Data Setup to CE# Going High 3 50 50 ns teEHDx | Data Hold from CE# High 5 5 ns tEHAX | Address Hold from CE# High 5 5 ns tEHWH | WE# Hold from CE# High 0 0 ns tEHEL | CE# Pulse Width High 25 25 ns tEHGL | Write Recovery before Read 0 0 ns Vcc = 3.340.3 V, Ta = 0 to +70C or 40 to +85C LH28F002SC-L85 LH28F002SC-L12 VERSIONS LH28F002SCH-L85 | LH28FO02SCH-L12 |UNIT SYMBOL PARAMETER NOTE MIN. MAX. MIN. MAX. tavav | Write Cycle Time 120 150 ns tPHEL | RP# High Recovery to CE# Going Low 2 1 1 ys twLeL_ | WE# Setup to CE# Going Low 0 0 ns tELEH | CE# Pulse Width 70 70 ns tPHHEH | RP# VHH Setup to CE# Going High 2 100 100 ns tvPpEH | Vep Setup to CE# Going High 2 100 100 ns taveH | Address Setup to CE# Going High 3 50 50 ns tovEH | Data Setup to CE# Going High 3 50 50 ns teEHDx | Data Hold from CE# High 5 5 ns tEHAX | Address Hold from CE# High 5 5 ns tEHWH | WE# Hold from CE# High 0 0 ns tEHEL | CE# Pulse Width High 25 25 ns tEHRL | CE# High to RY/BY# Going Low 100 100 ns teEHGL | Write Recovery before Read 0 0 ns tavwL | Vep Hold from Valid SRD, RY/BY# High 2,4 0 0 ns tavPH | RP# VHH Hold from Valid SRD, RY/BY# High | 2, 4 0 0 ns NOTES : 1. In systems where CE# defines the write pulse width 3. Refer to Table 3 for valid Ain and DIN for block erase, (within a longer WE# timing waveform), all setup, hold, byte write, or lock-bit configuration. and inactive WE# times should be measured relative to 4. Vpp should be held at VPPH1/2/3 (and if necessary RP# the CE# waveform. should be held at VHH) until determination of block erase, 2. Sampled, not 100% tested. byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). - 36 - ff| 002SC-L_SCH-L 7/15/98 3:29 PM Page 37 | SHARP p LH28F002SC-L/SCH-L 6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1) e Vcc = 5.040.25 V, 5.00.5 V, Ta = 0 to +70C or 40 to +85C (NOTE 5) Vect0.25 V | LH28F002SC-L85 LH28F002SCH-L85 VERSIONS (NOTE 6) (NOTE 6) UNIT Vect0.5 V LH28F002SC-L85 | LH28F002SC-L12 LH28F002SCH-L85 | LH28F002SCH-L12 SYMBOL PARAMETER NOTE} MIN. MAX. MIN. MAX. MIN. MAX. tavav | Write Cycle Time 85 90 120 ns RP# High Recovery to CE# TPHEL . 2 1 1 1 Us Going Low twLeL | WE# Setup to CE# Going Low 0 0 0 ns tELEH =| CE# Pulse Width 50 50 50 ns tPHHEH | RP# VHH Setup to CE# Going High 2 100 100 100 ns tvPEH | VPP Setup to CE# Going High 2 100 100 100 ns tavEH __| Address Setup to CE# Going High 3 40 40 40 ns tpveEH | Data Setup to CE# Going High 3 40 40 40 ns teEHDx =| Data Hold from CE# High 5 5 5 ns tEHAX _| Address Hold from CE# High 5 5 5 ns tEHWH | WE# Hold from CE# High 0 0 0 ns tEHEL | CE# Pulse Width High 25 25 25 ns tEHRL | CE# High to RY/BY# Going Low 90 90 90 ns tEHGL | Write Recovery before Read 0 0 0 ns tow. VpP Hold from Valid SRD, 24 0 0 0 ng RY/BY# High , RP# VHH Hold from Valid SRD, taQvPH . 2,4 0 0 0 ns RY/BY# High NOTES : 1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. Refer to Table 3 for valid Ain and DIN for block erase, byte write, or lock-bit configuration. Vpp should be held at VPPH1/23 (and if necessary RP# should be held at VHH) until determination of block erase, byte write, or lock-bit configuration success (SR.1/3/4/5 = 0). 5. See Fig. 10 "Transient Input/Output Reference Waveform and Fig. 12 "Transient Equivalent Testing Load Circuit" (High Seed Configuration) for testing characteristics. See Fig. 11 "Transient Input/Output Reference Waveform and Fig. 12 "Transient Equivalent Testing Load Circuit" (Standard Configuration) for testing characteristics. -37-[oozse-t-scHt /15/98 3:29 PM Page 38 + SHARP LH28F002SC-L/SCH-L (NOTE 1) (NOTE 2) (NOTE 3) (NOTE 4) (NOTE 5) (NOTE 6) Vv ao "_ M7 " 7 _ IH ADDRESSES (A) AIn AIN VIL VIH WE# (W) VIL VIH OE# (G) VIL TEHQV1/2/3/4 VIH CE# (E) VIL VIH DATA (D/Q) VIL Vou RY/BY# (R) VoL TPHHEH VHH RP#(P) VIH VIL VPPH1/2/3 Vpp(V) VPPLK VIL NOTES : Vcc power-up and standby. Write block erase or byte write setup. Write block erase confirm or valid address and data. Automated erase or program delay. Read status register data. Write Read Array command. Oar wNn > Fig. 15 AC Waveform for CE#-Controlled Write Operations - 38 - | P[oozse-t-scHt 1/15/98 3:29 PM Page 39 + | SHARP LH28F002SC-L/SCH-L 6.2.7 RESET OPERATIONS Vou RY/BY# (R) VoL ViH RP# (P)} \ VIL TPLPH (A) Reset During Read Array Mode Vou RY/BY# (R) VoL TPLRH ViH RP# (P) \ Vv " TPLPH (B) Reset During Block Erase, 2.7 V/I3.3 VIBV Byte Write, or Lock-Bit Configuration Vec Vit t235VPH ViH RP# (P) VIL (C) RP# Rising Timing Fig. 16 AC Waveform for Reset Operation Reset AC Specifications (NOTE 1) Vec = 2.7 t0 3.6 V|_ Vcc = 3.340.3 V | Vcc = 5.040.5 V SYMBOL) PARAMETER NOTE MIN. MAX. MIN. MAX. MIN. MAX. UNIT RP# Pulse Low Time tPLPH (If RP# is tied to Vcc, this 100 100 100 ns specification is not applicable) RP# Low to Reset during tPLRH Block Erase, Byte Write or 2,3 _ 20 12 Us Lock-Bit Configuration Vcc 2.7 V to RP# High te35VPH | Voc 3.0 V to RP# High 4 100 100 100 ns Vcc 4.5 V to RP# High NOTES : 1. These specifications are valid for all product versions 3. (packages and speeds). 2. If RP# is asserted while a block erase, byte write, or 4. lock-bit configuration operation is not executing, the reset will complete within 100 ns. A reset time, tPHav, is required from the latter of RY/BY# or RP# going high until outputs are valid. When the device power-up, holding RP#-low minimum 100 ns is required after Vcc has been in predefined range and also has been in stable there. - 39 - P ff| 002SC-L_SCH-L 7/15/98 3:29 PM Page 40 | SHARP p LH28F002SC-L/SCH-L 6.2.8 BLOCK ERASE, BYTE WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (NOTE 3, 4) Vcc = 3.340.3 V, Ta = 0 to +70C or 40 to +85C Ver = 3,340.3 V Vep = 5.0+0.5 V Vep = 12.040.6 V SYMBOL! PARAMETER NOTE MIN. |TYP.SOE 0) MAX.) MIN. |TYP!NCTED! MAX. | MIN. |TYP.SOE 1) MAX. UNIT tWHOV1 teHovt Byte Write Time 2 15 17 TBD 8.2 9.3 | TBD 6.7 7.6 | TBD | ps Block Write Time 2 1 1.1 TBD 0.5 0.5 | TBD 0.4 0.5 | TBD s twHave ; Block Erase Time 2 1.5 1.8 | TBD 1 1.2 | TBD 0.8 1.1 TBD s tEHQV2 WHOVS | sot Lock-Bit Time 2 | 18 | 21 | TaD] 14.21 133} TBD | 97 | 11.6 | TBD | ps tEHQV3 Clear Block Lock-Bi WHAVS | Clear Block Lock-BiS | 5 | 45] 18|tap| 1 | 12 |}7e| os | 11 | TaD] s tEHQv4 | Time tWHRH1 | Byte Write Suspend . 7.1 10 6.6 9.3 7.4 10.4 | us tEHRH1 | Latency Time to Read tWHRH2 | Erase Suspend Latency ; 15.2 | 21.1 12.3 | 17.2 12.3 | 17.2 | us tEHRH2 | Time to Read e Vcc = 5.0+0.25 V, 5.040.5 V, Ta = 0 to +70C or 40 to +85C SYMBOL PARAMETER NOTE Vep = 5.0+0.5 V Vep = 12.040.6 V MIN. [vp] MAX. | MIN. [TPO 1] max, [UNIT t WHY | Byte Write Time 2/65] 8 |TBaD] 48 | 6 | TBD] ps tEHQV1 Block Write Time 2 0.4 0.5 | TBD 0.3 0.4 | TBD s tWHaV: * | Block Erase Time 2 |o9 | 141 | TBD] 03 | 1.0 | TBD] s tEHQV2 t WHYS | Set Lock-Bit Time 2 | 95] 12 | TBD] 78 | 10 | TBD] ps tEHQV3 t WHOV* | Clear Block Lock-Bits Time 2 |o9 | 14 | TBD] 03 | 1.0 | TBD] s tEHQV4 t ae Byte Write Suspend Latency Time to Read 5.6 7 5.2 75 Us t WHRH2 Erase Suspend Latency Time to Read 9.4 | 13.1 9.8 | 12.6 | ps tEHRH2 NOTES : 1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, not 100% tested. - 40 - Lp | LH28F002SC-L/SCH-L | 002SC-L_SCH-L 7/15/98 3:29 PM Page 41 ff SHARP 7 ORDERING INFORMATION Product line designator for all SHARP Flash products L|H|2])8]/F/0/0|2)S|C\(H) Device Density | 002 = 2 N-bit Ty -;L]8 15 LH Access Speed (ns) 85 : 85 ns (5.0+0.25 V), 90 ns (5.0+0.5 V), 120 ns (3.3+0.3 V), 150 ns (2.7 to 3.6 V) 12 : 120 ns (5.0+0.5 V), 150 ns (3.3+0.3 V), 170 ns (2.7 to 3.6 V) Architecture S = Symmetrical Block Package T = 40-pin TSOP (I) (TSOP040-P-1020) Normal bend N = 44-pin SOP (SOP044-P-0600) [LH28F002SC-L] B = 48-ball CSP (FBGA048-P-0608) Power Supply Type C = SmartVoltage Technology Operating Temperature | Blank = 0 to +70C = 40 to +85C VALID OPERATIONAL COMBINATIONS Vcc = 2.7 to 3.6 V Vcc = 3.340.3 V Vcc = 5.0+0.5 V Vec = 5.0+0.25 V OPTION) ORDER CODE 50 pF load, 50 pF load, 100 pF load, 30 pF load, 1.35 V I/O Levels 1.5 V I/O Levels TTL I/O Levels 1.5 V I/O Levels 1 LH28F002SCXX-L85 150 ns 120 ns 90 ns 85 ns 2 LH28F002SCXX-L12 170 ns 150 ns 120 ns -41-_|| Packaging 7/15/98 2:24 PM Page5 PACKAGING 40 TSOP (TSOP040-P-1020) oLo |v zor0 0} KA) 800 |B goord O-0F dALG O-d SUM & oO oO ~ TMNT & Package base plane xvn0e'l oF S660 sero SeL'0 Vor Sho 20. Q+0. 3 18.4#0.2 le so'0F S20 19,020.83| Packaging 7/15/98 2:24 PM Page2 + | SHARP PACKAGING 44 SOP (SOP044-P-0600) 44-0.429.1 4.27TYP. [@Lo15 @ 44 23 DOO TAO ANIM OOo 2 16,0+0.4 13,2+0.2 O (14.4) O UUUUUUUUU UU UU UU EU = 1 28, 240.2 22 a 2 iS e 0.15+0.05 y 4 {|_| Package base plane al 5 || | Packaging 7/15/98 2:24 PM Page9 SHARP p PACKAGING 48 CSP (FBGA048-P-0608) . %&Q.ATYP. g N 3 ~ |Z \ _) Soot et wo 3 O.gTYP. : oat. ge |e st] c/o oO;oOl|~ FOOQOQO|O000 od000|j0000 | OCN00/0000 O000|0000 oo000|l0000 AQgoog|Io000 1 8 4.2TYP. @0.45#0.03 | 90.30 @] Ss |AB $/90.15 @] s |cp 6.06? *Land hole diameter for ball mounting