MR4A08BUYS45 - EVERSPIN TECHNOLOGIES

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

The MR4A08BUYS45 [x8] is a 16,777,216-bit magnetoresistive random access memory

(MRAM) device organized as 2,097,152 words of 8 bits. It is available in a 44-pin thin small

outline package (TSOP Type 2), compatible with similar low-power SRAM products and other

nonvolatile RAM products.

The MR4A16BUYS45 [x16] is a 16,777,216-bit magnetoresistive random access memory

(MRAM) device organized as 1,048,576 words of 16 bits. It is available in a 54-pin thin small

outline package (TSOP Type 2), compatible with similar low-power SRAM products and other

nonvolatile RAM products.

Both products have a -40/+125°C operating temperature range and oer SRAM-compatible

45ns read/write timing with unlimited endurance. Data is always non-volatile for greater

than 20 years and automatically protected on power loss by low-voltage inhibit circuitry to

prevent writes with voltage out of specication. Data retention is duty cycle limited at the

temperature extremes.

These products are the ideal memory solution for applications that must permanently store

and retrieve critical data and programs quickly, providing high reliability storage over the

automotive temperature range of -40/+125°C. These products are not AEC Q-100 qualied.

16Mb [x8 or x16] Automotive Temperature Range MRAM

• Automotive -40 /+125°C temperature range.

• 45 ns Read/Write cycle.

• 3.3 Volt power supply.

• Unlimited Read & Write endurance.

• Retains data on power loss.

• Data non-volatile for >20 years at temperature.

• SRAM compatible timing with existing SRAM controllers.

• Replaces Flash, SRAM, EEPROM or BBSRAM.

• Meets MSL-3 moisture sensitivity requirements.

• RoHS-compliant, SRAM-compatible TSOP2 Package RoHS

FEATURES

INTRODUCTION

MR4A08BUYS45

44-TSOP2

MR4A16BUYS45

54-TSOP2

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

TABLE OF CONTENTS

FEATURES .............................................................................................................................................1

INTRODUCTION ...................................................................................................................................1

BLOCK DIAGRAMS AND DEVICE PIN FUNCTIONS ............................................................................4

Figure 1 – MR4A08BUYS45 Block Diagram ......................................................................................................... 4

Table 1 – MR4A08BUYS45 Pin Functions ............................................................................................................. 4

Figure 2 – MR4A16BUYS45 Block Diagram ......................................................................................................... 5

Table 2 – MR4A16BUYS45 Pin Functions ............................................................................................................. 5

PACKAGE PINOUTS AND OPERATING MODES ..................................................................................6

Figure 3 – MR4A08BUYS45 TSOP2 Package Pinouts ........................................................................................ 6

Table 3 – MR4A08BUYS45 Operating Modes ..................................................................................................... 6

Figure 4 – MR4A16BUYS45 TSOP2 Package Pinouts ........................................................................................ 7

Table 4 – MR4A16BUYS45 Operating Modes ..................................................................................................... 7

ELECTRICAL SPECIFICATIONS ............................................................................................................8

Absolute Maximum Ratings ...........................................................................................................8

Table 5 – Absolute Maxium Ratings ....................................................................................................................... 8

Operating Conditions .....................................................................................................................9

Table 6 – Operating Conditions ............................................................................................................................... 9

Power Up and Power Down Sequencing .................................................................................... 10

Figure 5 – Power Up and Power Down Sequencing ......................................................................................10

DC and Power Supply Characteristics ......................................................................................... 11

Table 7 – DC Characteristics ....................................................................................................................................11

Table 8 – Power Supply Characteristics ..............................................................................................................11

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

TIMING SPECIFICATIONS ................................................................................................................. 12

Table 9 – Capacitance 1 ........................................................................................................................................12

Table 10 – AC Measurement Conditions ............................................................................................................12

Figure 6 – Output Load Test Low and High .......................................................................................................12

Figure 7 – Output Load Test All Other Parameters .........................................................................................12

Read Mode .................................................................................................................................... 13

Table 11 – Read Cycle Timing .................................................................................................................................13

Figure 8 – Read Cycle 1 ............................................................................................................................................. 14

Figure 9 – Read Cycle 2 ............................................................................................................................................. 14

Write Mode ................................................................................................................................... 15

Table 12 – Write Cycle Timing 1 (W Controlled) 1 .................................................................................... 15

Figure 10 – Write Cycle Timing 1 (W Controlled) ...................................................................................... 16

Table 13 – Write Cycle Timing 2 (E Controlled) 1 ...................................................................................17

Figure 11 – Write Cycle Timing 2 (E Controlled) ........................................................................................ 18

Table 14 – Write Cycle Timing 3 (LB/UB Controlled) 1 ........................................................................19

Figure 12 – Write Cycle Timing 3 (LB/UB Controlled) ..............................................................................20

ORDERING INFORMATION ............................................................................................................... 21

Table 15 – Part Number Decoder ........................................................................................................................21

Table 16 – Ordering Part Numbers ......................................................................................................................21

PACKAGE OUTLINE DRAWINGS ....................................................................................................... 22

Figure 13 – 44-TSOP2 Package Outline Drawing ............................................................................................22

Figure 14 – 54-TSOP2 Package Outline Drawing ............................................................................................23

REVISION HISTORY ........................................................................................................................... 25

HOW TO CONTACT US ....................................................................................................................... 26

Table of Contents - Cont’d

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

Figure 1 – MR4A08BUYS45 Block Diagram

CHIP

ENABLE

BUFFER

OUTPUT

ENABLE

BUFFER

ADDRESS

BUFFER

WRITE

ENABLE

BUFFER

OUTPUT ENABLE

2M x 8 BIT

MEMORY

ARRAY

ROW

DECODER COLUMN

DECODER

SENSE

AMPS

OUTPUT

BUFFER

WRITE

DRIVER

FINAL

WRITE

DRIVERS

WRITE ENABLE

A[20:0]

DQ[7:0]

Signal Name Function

A Address Input

E Chip Enable

W Write Enable

G Output Enable

DQ Data I/O

VDD Power Supply

VSS Ground

DC Do Not Connect

NC No Connection

Table 1 – MR4A08BUYS45 Pin Functions

BLOCK DIAGRAMS AND DEVICE PIN FUNCTIONS

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

CHIP

ENABLE

BUFFER

OUTPUT

ENABLE

BUFFER

ADDRESS

BUFFER

WRITE

ENABLE

BUFFER

UPPER BYTE OUTPUT ENABLE

LOWER BYTE OUTPUT ENABLE

1M x 16

BIT

MEMORY

ARRAY

ROW

DECODER COLUMN

DECODER

SENSE

AMPS

LOWER

BYTE

WRITE

DRIVER

LOWER

BYTE

OUTPUT

BUFFER

UPPER

BYTE

OUTPUT

BUFFER

FINAL

WRITE

DRIVERS

UPPER BYTE WRITE ENABLE

LOWER BYTE WRITE ENABLE

BYTE

ENABLE

BUFFER

A[19:0]

DQL[7:0]

8DQU[15:8]

UPPER

BYTE

WRITE

DRIVER

Signal Name Function

A Address Input

E Chip Enable

W Write Enable

G Output Enable

UB Upper Byte Enable

LB Lower Byte Enable

DQ Data I/O

VDD Power Supply

VSS Ground

DC Do Not Connect

NC No Connection

Figure 2 – MR4A16BUYS45 Block Diagram

Table 2 – MR4A16BUYS45 Pin Functions

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

44-TSOP2

Figure 3 – MR4A08BUYS45 TSOP2 Package Pinouts

Table 3 – MR4A08BUYS45 Operating Modes

E 1G 1W 1Mode VDD Current DQ[7:0] 2

H X X Not selected ISB1, ISB2 Hi-Z

L H H Output disabled IDDR Hi-Z

L L H Byte Read IDDR DOut

L X L Byte Write IDDW Din

1. H = high, L = low, X = don’t care

2. Hi-Z = high impedance

PACKAGE PINOUTS AND OPERATING MODES

VDD

VSS

DC 22

44 DC

VSS

VDD

A20 19

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

A19

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

A18

A17

A16

A15

A14

A13

A12

A11

A10

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

54-TSOP2

E 1G 1W 1LB 1UB 1Mode VDD Current DQL[7:0] 2DQU[15:8] 2

H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z

L H H X X Output disabled IDDR Hi-Z Hi-Z

L X X H H Output disabled IDDR Hi-Z Hi-Z

L L H L H Lower Byte Read IDDR DOut Hi-Z

L L H H L Upper Byte Read IDDR Hi-Z DOut

L L H L L Word Read IDDR DOut DOut

L X L L H Lower Byte Write IDDW Din Hi-Z

L X L H L Upper Byte Write IDDW Hi-Z Din

L X L L L Word Write IDDW Din Din

1. H = high, L = low, X = don’t care

2. Hi-Z = high impedance

Table 4 – MR4A16BUYS45 Operating Modes

Figure 4 – MR4A16BUYS45 TSOP2 Package Pinouts

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

These devices contain circuitry to protect the inputs against damage caused by high static voltages or

electric elds; however, it is advised that normal precautions be taken to avoid application of any

voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic elds. Precautions should be taken

to avoid application of any magnetic eld greater than the maximum eld intensity specied

in the maximum ratings.

Table 5 – Absolute Maxium Ratings

Parameter Symbol Value Unit

Supply voltage 2VDD -0.5 to 4.0 V

Voltage on any pin 2 VIN

-0.5 to VDD +

0.5 V

Output current per pin IOUT ±20 mA

Package power dissipation 3PD0.600 W

Temperature under bias TBIAS -45 to 130 °C

Storage Temperature Tstg -55 to 150 °C

Lead temperature during solder (3 minute max) TLead 260 °C

Maximum magnetic eld during write Hmax_write 8000 A/m

Maximum magnetic eld during read or standby Hmax_read 8000 A/m

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation

should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic

elds could aect device reliability.

2. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than

0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than

20mA.

3. Power dissipation capability depends on package characteristics and use environment.

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Operating Conditions

Parameter Symbol Min Typical Max Unit

Power supply voltage VDD 3.0 13.3 3.6 V

Write inhibit voltage VWI 2.5 2.7 3.0 1 V

Input high voltage VIH 2.2 - VDD + 0.3 2 V

Input low voltage VIL -0.5 3- 0.8 V

Ambient Operating Temperature 4TA-40 - +125 °C

1. There is a 2 ms startup time once VDD exceeds VDD,(min). See “Power Up and Power Down Sequencing”

below.

2. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

3. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.

4. The ambient operature temperature rating assumes a 10% duty cycle (2 years out of 20 years life) for operating

temperatures between +85°C and +125°C.

Table 6 – Operating Conditions

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds

VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory

power supplies to stabilize.

The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and

remain high for the startup time. In most systems, this means that these signals should be pulled up with

a resistor so that a signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E

and W should hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be

observed when power returns above VDD(min).

BROWNOUT or POWER LOSS

NORMAL

OPERATION

VDD

READ/WRITE

INHIBITED

VWI

2 ms

READ/WRITE

INHIBITED

VIH

STARTUP

NORMAL

OPERATION

2 ms

RECOVER

VIH

Power Up and Power Down Sequencing

Figure 5 – Power Up and Power Down Sequencing

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Symbol Parameter Conditions Min Max Unit

Ilkg(I) Input leakage current All - ±1 μA

Ilkg(O) Output leakage current All - ±1 μA

VOL Output low voltage

IOL = +4 mA - 0.4 V

IOL = +100 μA VSS + 0.2 V

VOH Output high voltage

IOH = -4 mA 2.4 - V

IOH = -100 μA VDD - 0.2 - V

Table 2.3 DC Characteristics

Symbol Parameter Typical Max Unit

IDDR

AC active supply current - read modes 1

IOUT = 0 mA, VDD = max.

60 68 mA

IDDW

AC active supply current - write modes1

VDD = max 152 180 mA

ISB1

AC standby current

VDD = max, E = VIH

No other restrictions on other inputs.

9 14 mA

ISB2

CMOS standby current

E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V

VDD = max, f = 0 MHz

5 9 mA

1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.

Table 7 – DC Characteristics

DC and Power Supply Characteristics

Table 8 – Power Supply Characteristics

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

Symbol Parameter Typical Max Unit

CIn Address input capacitance - 6 pF

CIn Control input capacitance - 6 pF

CI/O Input/Output capacitance - 8 pF

1. f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.

Parameter Value Unit

Logic input timing measurement reference level 1.5 V

Logic output timing measurement reference level 1.5 V

Logic input pulse levels 0 or 3.0 V

Input rise/fall time 2 ns

Output load for low and high impedance parameters See Figure 6

Output load for all other timing parameters See Figure 7

Output

L= 1.5 V

RL= 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

5 pF

3.3 V

TIMING SPECIFICATIONS

Table 9 – Capacitance 1

Table 10 – AC Measurement Conditions

Figure 6 – Output Load Test Low and High

Figure 7 – Output Load Test All Other Parameters

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Symbol Parameter Min Max Unit

tAVAV Read cycle time 45 - ns

tAVQV Address access time - 45 ns

tELQV Enable access time 2- 45 ns

tGLQV Output enable access time - 15 ns

tBLQV Byte enable access time - 15 ns

tAXQX Output hold from address change 3 - ns

tELQX Enable low to output active 33 - ns

tGLQX Output enable low to output active 30 - ns

tBLQX Byte enable low to output active 30 - ns

tEHQZ Enable high to output Hi-Z 30 15 ns

tGHQZ Output enable high to output Hi-Z 30 10 ns

tBHQZ Byte high to output Hi-Z 30 10 ns

1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

2. Addresses valid before or at the same time E goes low.

3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.

Read Mode

Table 11 – Read Cycle Timing

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

A (ADDRESS)

Q (DATA OUT)

AVAV

AXQX

AVQV

Previous Data Valid

Note: Device is continuously selected (E≤V

, G≤V

Data Valid

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

Q (DATA OUT) Data Valid

AVAV

AVQV

ELQV

ELQX

BHQZ

GHQZ

EHQZ

BLQV

BLQX

GLQV

GLQX

LB, UB (BYTE ENABLE)

Figure 8 – Read Cycle 1

Figure 9 – Read Cycle 2

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Symbol Parameter Min Max Unit

tAVAV Write cycle time 245 - ns

tAVWL Address set-up time 0 - ns

tAVWH Address valid to end of write (G high) 30 - ns

tAVWH Address valid to end of write (G low) 30 - ns

tWLWH

tWLEH Write pulse width (G high) 15 - ns

tWLWH

tWLEH Write pulse width (G low) 15 - ns

tDVWH Data valid to end of write 10 - ns

tWHDX Data hold time 0 - ns

tWLQZ Write low to data Hi-Z 30 15 ns

tWHQX Write high to output active 33 - ns

tWHAX Write recovery time 12 - ns

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or

after W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal

must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E

being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the rst transition address.

3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any

given voltage or temperate, tWLQZ(max) < tWHQX(min).

Table 12 – Write Cycle Timing 1 (W Controlled) 1

Write Mode

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

W (WRITE ENABLE)

A (ADDRESS)

E (CHIP ENABLE)

UB, LB (BYTE ENABLED)

tAVAV

tAVWH tWHAX

tAVWL

tWLEH

tWLWH

DATA VALID

tDVWH tWHDX

Q (DATA OUT)

D (DATA IN)

tWLQZ

tWHQX

Hi -Z Hi -Z

Figure 10 – Write Cycle Timing 1 (W Controlled)

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Symbol Parameter Min Max Unit

tAVAV Write cycle time 245 - ns

tAVEL Address set-up time 0 - ns

tAVEH Address valid to end of write (G high) 30 - ns

tAVEH Address valid to end of write (G low) 30 - ns

tELEH

tELWH

Enable to end of write (G high) 15 - ns

tELEH

tELWH Enable to end of write (G low) 315 - ns

tDVEH Data valid to end of write 10 - ns

tEHDX Data hold time 0 - ns

tEHAX Write recovery time 12 - ns

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or

after W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal

must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E

being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the rst transition address.

3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

Table 13 – Write Cycle Timing 2 (E Controlled) 1

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

Q (DATA OUT)

D (DATA IN)

tAVAV

tAVEH tEHAX

tELEH

tEHDX

tDVEH

tAVEL

Hi-Z

tELWH

Data Valid

UB, LB (BYTE ENABLE)

Figure 11 – Write Cycle Timing 2 (E Controlled)

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Symbol Parameter Min Max Unit

tAVAV Write cycle time 245 - ns

tAVBL Address set-up time 0 - ns

tAVBH Address valid to end of write (G high) 30 - ns

tAVBH Address valid to end of write (G low) 30 - ns

tBLEH

tBLWH Write pulse width (G high) 15 - ns

tBLEH

tBLWH Write pulse width (G low) 15 - ns

tDVBH Data valid to end of write 10 - ns

tBHDX Data hold time 0 - ns

tBHAX Write recovery time 12 - ns

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must

remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no

more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in

a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the rst transition address.

Table 14 – Write Cycle Timing 3 (LB/UB Controlled) 1

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

W (WRITE ENABLE)

A (ADDRESS)

E (CHIP ENABLE)

UB, LB (BYTE ENABLED)

tAVAV

tAVEH tBHAX

tAVBL tBLEH

tBLWH

Data Valid

tDVBH tBHDX

Q (DATA OUT)

D (DATA IN)

Hi -Z Hi -Z

Figure 12 – Write Cycle Timing 3 (LB/UB Controlled)

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Grade Temp Range Density I/O Width Package Shipping

Container Order Part Number

Automotive 1-40 to +125 °C 16Mb

x8 44-TSOP2 Trays MR4A08BUYS45

Tape & Reel MR4A08BUYS45R

x16 54-TSOP2 Trays MR4A16BUYS45

Tape & Reel MR4A16BUYS45R

1. Not AEC Q-100 Qualied.

Table 15 – Part Number Decoder

Table 16 – Ordering Part Numbers

ORDERING INFORMATION

Memory Density Type I/O Width Rev. Temp Package Speed Packing Grade

Example Ordering Part Number MR 4 A 08 B U YS 45 R ES

MRAM MR

16 Mb 4

Async 3.3v

8-bit 08

16-bit 16

Rev B B

Automove -40 to 125°C U

TSOP2 YS

45 ns 45

Tray Blank

Tape and Reel R

Engineering Samples ES

Customer Samples CS

Mass Producon Blank

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

Figure 13 – 44-TSOP2 Package Outline Drawing

PACKAGE OUTLINE DRAWINGS

Not To Scale

1. Dimensions and tolerances per ASME Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protrusion.

4. Dimension does not include DAM bar protrusions.

5. DAM Bar protrusion shall not cause the lead width to

exceed 0.58.

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

5. MECHANICAL DRAWING

0.10

SEATING PLANE

0.71 REF.

54 28

A2 A1

0.21(0.008)REF.

GAGE PLANE

0.25 mm

0.665(0.026)REF.

⊕0.20(0.008) M

Figure 14 – 54-TSOP2 Package Outline Drawing

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

1. Dimensions in Millimeters.

2. Package dimensions refer to JEDEC MS-024

Ref Min Nominal Max

A 1.20

A1 0.05 0.10 0.15

A2 0.95 1.00 1.05

b0.30 0.35 0.45

c0.12 0.21

D22.10 22.22 22.35

E11.56 11.76 11.95

E1 10.03 10.16 10.29

e0.80 BSC

L0.40 0.50 0.60

L1 0.80 REF

R1 0.12 - -

R2 0.12 - 0.25

θ0° - 8°

θ1 0.40 - -

θ2 15° REF

θ3 15° REF

Figure 14 - 54-TSOP2 Package Outline Drawing - Cont’d

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

Rev Date Description of Change

1.0 November 18,

2015 Initial release.

REVISION HISTORY

MR4A08BUYS45/MR4A16BUYS45 Rev. 1.0, 11/2015

MR4A08BUYS45 [x8]

MR4A16BUYS45[x16]

Everspin Technologies, Inc.

Information in this document is provided solely to enable system and software

implementers to use Everspin Technologies products. There are no express or

implied licenses granted hereunder to design or fabricate any integrated cir-

cuit or circuits based on the information in this document. Everspin Technolo-

gies reserves the right to make changes without further notice to any products

herein. Everspin makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Everspin

Technologies assume any liability arising out of the application or use of any

product or circuit, and specically disclaims any and all liability, including

without limitation consequential or incidental damages. “Typical” parameters,

which may be provided in Everspin Technologies data sheets and/or speci-

cations can and do vary in dierent applications and actual performance

may vary over time. All operating parameters including “Typicals” must be

validated for each customer application by customer’s technical experts. Ever-

spin Technologies does not convey any license under its patent rights nor the

rights of others. Everspin Technologies products are not designed, intended,

or authorized for use as components in systems intended for surgical implant

into the body, or other applications intended to support or sustain life, or for

any other application in which the failure of the Everspin Technologies product

could create a situation where personal injury or death may occur. Should

Buyer purchase or use Everspin Technologies products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Everspin Tech-

nologies and its ocers, employees, subsidiaries, aliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury

or death associated with such unintended or unauthorized use, even if such

claim alleges that Everspin Technologies was negligent regarding the design

or manufacture of the part. Everspin™ and the Everspin logo are trademarks of

Everspin Technologies, Inc. All other product or service names are the property

of their respective owners.

Home Page:

www.everspin.com

World Wide Information Request

WW Headquarters - Chandler, AZ

1347 N. Alma School Road, Suite 220

Chandler, Arizona 85224

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

Europe, Middle East and Africa

Everspin Sales Oce

Tel: +49 8168 998019

Japan

Everspin Sales Oce

Tel: +1 (719) 650-5012

Asia Pacic

Everspin Sales Oce

Tel: +86-136-0307-6129

Fax: +1-480-347-1175

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