CY7C1297H
1-Mbit (64K x 18) Flow-Through Sync SRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05669 Rev. *C Revised March 19, 2010
Features
• 64K x 18 common I/O
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1297H is a 64K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP
, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1297H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1297H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
ADDRESS
REGISTER
ADV
CLK BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE
1
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE
2
CE
3
GW
BWE
A0,A1,A
BW
B
BW
A
DQ
B
,DQP
B
WRITE REGISTER
DQ
A
,DQP
A
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQPA
DQPB
DQ
B
,DQP
B
WRITE DRIVER
DQ
A
,DQP
A
WRITE DRIVER
SLEEP
CONTROL
ZZ
Logic Block Diagram
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 2 of 15
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum Standby Current 40 40 mA
Pin Configuration
100-Pin TQFP
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/9M
A
A
A
A
A
NC/4M
A
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSP
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE A
NC/2M
ADV
ADSC
ZZ
MODE
NC/18M
NC
BYTE B
CY7C1297H
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 3 of 15
Pin Descriptions
Name I/O Description
A0, A1, A Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the 2-bit counter.
BWA, BWBInput-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
GW Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
BWE Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
CLK Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
loaded.
OE Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a Read cycle when emerging from a
deselected state.
ADV Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH
ADSC Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ Input-
Asynchronous
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
DQPA, DQPB
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed in a tri-state condition.
VDD Power Supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ I/O Power
Supply
Power supply for the I/O circuitry.
MODE Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC No Connects. Not Internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M
and 1G are address expansion pins and are not internally connected to the die.
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 4 of 15
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The CY7C1297H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:B]) are ignored during this first
clock cycle. If the Write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During byte writes, BWA controls DQA and BWB controls DQB.
All I/Os are tri-stated during a Byte Write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a Write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the Write input signals (GW, BWE, and BW[A:B])
indicate a write access. ADSC is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:B] will be
written into the specified address location. Byte Writes are
allowed. During Byte Writes, BWA controls DQA and BWB
controls DQB. All I/Os are tri-stated when a write is detected,
even a Byte Write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1297H provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 5 of 15
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD– 0.2V 40 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Truth Table[2, 3, 4, 5, 6]
Cycle Description Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle,
Power-down
None H X X L X L X X X L-H Tri-State
Deselected Cycle,
Power-down
None L L X L L X X X X L-H Tri-State
Deselected Cycle,
Power-down
None L X H L L X X X X L-H Tri-State
Deselected Cycle,
Power-down
None L L X L H L X X X L-H Tri-State
Deselected Cycle,
Power-down
None X X X L H L X X X L-H Tri-State
Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 6 of 15
Truth Table for Read/Write[2, 3]
Function GW BWE BWBBWA
Read H H X X
Read H L H H
Write Byte (A, DQPA)HLHL
Write Byte (B, DQPB)HLLH
Write All Bytes H L L L
Write All Bytes L X X X
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 7 of 15
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65C to + 150C
Ambient Temperature with
Power Applied............................................–55C to + 125C
Supply Voltage on VDD Relative to GND....... –0.5V to + 4.6V
Supply Voltage on VDDQ Relative to GND ..... –0.5V to + VDD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature VDD VDDQ
Commercial 0C to +70C 3.3V
5%/+10%
2.5V –5%
to VDD
Industrial –40C to +85C
Electrical Characteristics Over the Operating Range [7, 8]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ I/O Supply Voltage for 3.3V I/O 3.135 VDD V
for 2.5V I/O 2.375 2.625 V
VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V
for 2.5V I/O, IOH = –1.0 mA 2.0 V
VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA 0.4 V
for 2.5V I/O, IOL = 1.0 mA 0.4 V
VIH Input HIGH Voltage[7] for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 VDD + 0.3V V
VIL Input LOW Voltage[7] for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
IXInput Leakage Current
except ZZ and MODE
GND VI VDDQ 55A
Input Current of MODE Input = VSS –30 A
Input = VDD 5A
Input Current of ZZ Input = VSS –5 A
Input = VDD 30 A
IOZ Output Leakage Current GND VI VDDQ, Output Disabled –5 5 A
IDD VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
7.5-ns cycle, 133 MHz 225 mA
10.0-ns cycle, 100 MHz 205 mA
ISB1 Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
7.5-ns cycle, 133 MHz 90 mA
10.0-ns cycle, 100 MHz 80 mA
ISB2 Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN VDD – 0.3V or VIN 0.3V,
f = 0, inputs static
All speeds 40 mA
ISB3 Automatic CE
Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN VDDQ – 0.3V or VIN 0.3V,
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz 75 mA
10.0-ns cycle, 100 MHz 65 mA
ISB4 Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN VDD – 0.3V or VIN 0.3V,
f = 0, inputs static
All speeds 45 mA
Notes:
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 8 of 15
Capacitance[9]
Parameter Description Test Conditions
100 TQFP
Max. Unit
CIN Input Capacitance TA = 25C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
5pF
CCLK Clock Input Capacitance 5 pF
CI/O Input/Output Capacitance 5 pF
Thermal Resistance[9]
Parameter Description Test Conditions
100 TQFP
Package Unit
JA Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51
30.32 C/W
JC Thermal Resistance
(Junction to Case)
6.85 C/W
AC Test Loads and Waveforms
Note:
9. Tested initially and after any design or process change that may affect these parameters.
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
V
T
= 1.5V
3.3V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
OUTPUT
R = 1667
R =1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25V
2.5V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns
1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 9 of 15
Switching Characteristics Over the Operating Range [10, 11]
Parameter Description
133 MHz 100 MHz
UnitMin. Max. Min. Max.
tPOWER VDD(Typical) to the First Access[12] 11ms
Clock
tCYC Clock Cycle Time 7.5 10.0 ns
tCH Clock HIGH 2.5 4.0 ns
tCL Clock LOW 2.5 4.0 ns
Output Times
tCDV Data Output Valid after CLK Rise 6.5 8.0 ns
tDOH Data Output Hold after CLK Rise 2.0 2.0 ns
tCLZ Clock to Low-Z[13, 14, 15] 00ns
tCHZ Clock to High-Z[13, 14, 15] 3.5 3.5 ns
tOEV OE LOW to Output Valid 3.5 3.5 ns
tOELZ OE LOW to Output Low-Z[13, 14, 15] 00ns
tOEHZ OE HIGH to Output High-Z[13, 14, 15] 3.5 3.5 ns
Set-up Times
tAS Address Set-up before CLK Rise 1.5 2.0 ns
tADS ADSP, ADSC Set-up before CLK Rise 1.5 2.0 ns
tADVS ADV Set-up before CLK Rise 1.5 2.0 ns
tWES GW, BWE, BW[A:B] Set-up before CLK Rise 1.5 2.0 ns
tDS Data Input Set-up before CLK Rise 1.5 2.0 ns
tCES Chip Enable Set-up 1.5 2.0 ns
Hold Times
tAH Address Hold after CLK Rise 0.5 0.5 ns
tADH ADSP, ADSC Hold after CLK Rise 0.5 0.5 ns
tWEH GW, BWE, BW[A:B] Hold after CLK Rise 0.5 0.5 ns
tADVH ADV Hold after CLK Rise 0.5 0.5 ns
tDH Data Input Hold after CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns
Notes:
10. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
can be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 10 of 15
Timing Diagrams
Read Cycle Timing[16]
Note:
16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
Data Out (Q) High-Z
tCLZ tDOH
tCDV
tOEHZ
tCDV
Single READ BURST
READ
tOEV tOELZ tCHZ
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2) Q(A2 + 1) Q(A2 + 2)
Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2)Q(A2 + 3)
A2
ADV suspends burst.
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
GW, BWE,BW[A:B]
CE
ADV
OE
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 11 of 15
Write Cycle Timing[16, 17]
Note:
17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Timing Diagrams (continued)
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
High-Z
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1)
D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
A2 A3
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
tOEHZ
tADVH
tADVS
tWEH
tWES
tDH
tDS
tWEH
tWES
Byte write signals are ignored for first cycle when
ADSP initiates burst.
ADSC extends burst.
ADV suspends burst.
DON’T CARE UNDEFINED
ADSP
ADSC
BWE,
BW[A:B]
GW
CE
ADV
OE
Data in (D)
Data Out (Q)
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 12 of 15
Read/Write Timing[16, 18, 19]
Notes:
18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP
, ADSC, or ADV cycle is performed.
19. GW is HIGH.
Timing Diagrams (continued)
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3 A4
BURST READBack-to-Back READs
High-Z
Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)
tWEH
tWES
tOEHZ
tDH
tDS
tCDV
tOELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW[A:B]
CE
ADV
OE
Data In (D)
Data Out (Q)
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 13 of 15
ZZ Mode Timing[20, 21]
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in High-Z when exiting ZZ sleep mode.
Timing Diagrams (continued)
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 14 of 15
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress
maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code
Package
Diagram Package Type
Operating
Range
133 CY7C1297H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
Package Diagram
51-85050 *C
[+] Feedback
CY7C1297H
Document #: 38-05669 Rev. *C Page 15 of 15
© Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Document History
Document Title: CY7C1297H 1-Mbit (64K x 18) Flow-Through Sync SRAM
Document Number: 38-05669
REV. ECN NO. Issue Date
Orig. of
Change Description of Change
** 345879 See ECN PCI New Data Sheet
*A 430677 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for VDDQ relative to GND
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Modified test condition from VIH < VDD to VIH VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
*B 482139 See ECN VKN Converted from Preliminary to Final.
Updated the Ordering Information table.
*C 2896202 03/19/2010 NJY Removed Inactvie parts from the Ordering Information table; Updated
package diagram.
[+] Feedback