32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
2M-WORD BY 18-BIT / 1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD44323182
,
44323362
Document No. M16379EJ3V0DS00 (3rd edition)
Date Published November 2003 NS CP(K)
Printed in Japan
The mark Ì
ÌÌ
Ì shows major revised points.
2002
Description
The
µ
PD44323182 is a 2,097,152 words by 18 bits, and the
µ
PD44323362 is a 1,048,576 words by 36 bits
synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
µ
PD44323182 and
µ
PD44323362 are suitable for applications which require high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The
µ
PD44323182 and
µ
PD44323362 are packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
• Fully synchronous operation
• HSTL Input / Output levels
• Fast clock access time: 2.0 ns / 250 MHz, 2.5 ns / 200 MHz
• Asynchronous output enable control: /G
• Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
• Common I/O using three-state outputs
• Internally self-timed write cycle
• Late write with 1 dead cycle between Read-Write
• User-configurable outputs: Controlled impedance outputs or push-pull outputs
• Boundary scan (JTAG) IEEE 1149.1 compatible
• 2.5 ± 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
• 119 bump BGA package, 1.27 mm pitch, 14 mm × 22 mm
• Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number Access time Clock frequency Package
µ
PD44323182F1-C40-FJ1 Note 2.0 ns 250 MHz 119-pin PLASTIC BGA
µ
PD44323182F1-C50-FJ1 Note 2.5 ns 200 MHz
µ
PD44323362F1-C40-FJ1 2.0 ns 250 MHz
µ
PD44323362F1-C50-FJ1 2.5 ns 200 MHz
Note Under development
2 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Pin Configurations
/xxx indicates active low signal.
119-pin PLASTIC BGA (2M Words by 18 Bits Pin Assignment)
[
µ
µµ
µ
PD44323182F1]
123445671234567
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View Bottom View
1 2 3 4 5 6 7 7 6 5 4 3 2 1
VDDQ SA12 SA9 NC SA6 SA2 VDDQ A VDDQ SA2 SA6 NC SA9 SA12 VDDQ
NC SA19 SA17 SA20 SA16 SA18 NC B NC SA18 SA16 SA20 SA17 SA19 NC
NC SA13 SA10 VDD SA7 SA3 NC C NC SA3 SA7 VDD SA10 SA13 NC
DQb1 NC VSS ZQ VSS DQa9 NC D NC DQa9 VSS ZQ VSS NC DQb1
NC DQb2 VSS /SS VSS NC DQa8 E DQa8 NC VSS /SS VSS DQb2 NC
VDDQ NC VSS /G VSS DQa7 VDDQ F VDDQ DQa7 VSS /G VSS NC VDDQ
NC DQb3 /SBb NC NC NC DQa6 G DQa6 NC NC NC /SBb DQb3 NC
DQb4 NC VSS NC VSS DQa5 NC H NC DQa5 VSS NC VSS NC DQb4
VDDQ VDD VREF VDD VREF VDD VDDQ J VDDQ VDD VREF VDD VREF VDD VDDQ
NC DQb5 VSS K VSS NC DQa4 K DQa4 NC VSS K VSS DQb5 NC
DQb6 NC NC /K /SBa DQa3 NC L NC DQa3 /SBa /K NC NC DQb6
VDDQ DQb7 VSS /SW VSS NC VDDQ M VDDQ NC VSS /SW VSS DQb7 VDDQ
DQb8 NC VSS SA0 VSS DQa2 NC N NC DQa2 VSS SA0 VSS NC DQb8
NC DQb9 VSS SA1 VSS NC DQa1 P DQa1 NC VSS SA1 VSS DQb9 NC
NC SA14 M1 VDD M2 SA4 NC R NC SA4 M2 VDD M1 SA14 NC
NC SA15 SA11 NC SA8 SA5 ZZ T ZZ SA5 SA8 NC SA11 SA15 NC
VDDQ TMS TDI TCK TDO NC VDDQ U VDDQ NC TDO TCK TDI TMS VDDQ
3
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Pin Name and Functions [
µ
µµ
µ
PD44323182F1]
Pin name Description Function
VDD Core Power Supply Supplies power for RAM core
VSS Ground
VDDQ Output Power Supply Supplies power for output buffers
VREF Input Reference
K, /K Main Clock
SA0 to SA20 Synchronous Address Input
DQa1 to DQb9 Synchronous Data Input / Output
/SS Synchronous Chip Select Logically selects SRAM
/SW Synchronous Byte Write Enable Write command
/SBa Synchronous Byte "a" Write Enable Write DQa1 to DQa9
/SBb Synchronous Byte "b" Write Enable Write DQb1 to DQb9
/G Asynchronous Output Enable Asynchronous input
ZZ Asynchronous Sleep Mode Enables sleep mode, active high
ZQ Output Impedance Control
M1, M2 Mode Select Selects operation mode Note
NC No Connection
TMS Test Mode Select (JTAG)
TDI Test Data Input (JTAG)
TCK Test Clock Input (JTAG)
TDO Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input / Registered Output.)
4 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
119-pin plastic BGA (1M Words by 36 Bits Pin Assignment)
[
µ
µµ
µ
PD44323362F1]
123445671234567
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View Bottom View
1 2 3 4 5 6 7 7 6 5 4 3 2 1
VDDQ SA12 SA9 NC SA5 SA2 VDDQ A VDDQ SA2 SA5 NC SA9 SA12 VDDQ
NC SA18 SA16 SA19 SA15 SA17 NC B NC SA17 SA15 SA19 SA16 SA18 NC
NC SA13 SA10 VDD SA6 SA3 NC C NC SA3 SA6 VDD SA10 SA13 NC
DQc8 DQc9 VSS ZQ VSS DQb9 DQb8 D DQb8 DQb9 VSS ZQ VSS DQc9 DQc8
DQc6 DQc7 VSS /SS VSS DQb7 DQb6 E DQb6 DQb7 VSS /SS VSS DQc7 DQc6
VDDQ DQc5 VSS /G VSS DQb5 VDDQ F VDDQ DQb5 VSS /G VSS DQc5 VDDQ
DQc3 DQc4 /SBc NC /SBb DQb4 DQb3 G DQb3 DQb4 /SBb NC /SBc DQc4 DQc3
DQc1 DQc2 VSS NC VSS DQb2 DQb1 H DQb1 DQb2 VSS NC VSS DQc2 DQc1
VDDQ VDD VREF VDD VREF VDD VDDQ J VDDQ VDD VREF VDD VREF VDD VDDQ
DQd1 DQd2 VSS K VSS DQa2 DQa1 K DQa1 DQa2 VSS K VSS DQd2 DQd1
DQd3 DQd4 /SBd /K /SBa DQa4 DQa3 L DQa3 DQa4 /SBa /K /SBd DQd4 DQd3
VDDQ DQd5 VSS /SW VSS DQa5 VDDQ M VDDQ DQa5 VSS /SW VSS DQd5 VDDQ
DQd6 DQd7 VSS SA0 VSS DQa7 DQa6 N DQa6 DQa7 VSS SA0 VSS DQd7 DQd6
DQd8 DQd9 VSS SA1 VSS DQa9 DQa8 P DQa8 DQa9 VSS SA1 VSS DQd9 DQd8
NC SA14 M1 VDD M2 SA4 NC R NC SA4 M2 VDD M1 SA14 NC
NC NC SA11 SA8 SA7 NC ZZ T ZZ NC SA7 SA8 SA11 NC NC
VDDQ TMS TDI TCK TDO NC VDDQ U VDDQ NC TDO TCK TDI TMS VDDQ
5
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Pin Name and Functions [
µ
µµ
µ
PD44323362F1]
Pin name Description Function
VDD Core Power Supply Supplies power for RAM core
VSS Ground
VDDQ Output Power Supply Supplies power for output buffers
VREF Input Reference
K, /K Main Clock
SA0 to SA19 Synchronous Address Input
DQa1 to DQd9 Synchronous Data Input / Output
/SS Synchronous Chip Select Logically selects SRAM
/SW Synchronous Byte Write Enable Write command
/SBa Synchronous Byte "a" Write Enable Write DQa1 to DQa9
/SBb Synchronous Byte "b" Write Enable Write DQb1 to DQb9
/SBc Synchronous Byte "c" Write Enable Write DQc1 to DQc9
/SBd Synchronous Byte "d" Write Enable Write DQd1 to DQd9
/G Asynchronous Output Enable Asynchronous input
ZZ Asynchronous Sleep Mode Enables sleep mode, active high
ZQ Output Impedance Control
M1, M2 Mode Select Selects operation mode Note
NC No Connection
TMS Test Mode Select (JTAG)
TDI Test Data Input (JTAG)
TCK Test Clock Input (JTAG)
TDO Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input / Registered Output.)
6 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Late Write Block Diagram
K
/SBa
K
/K
/SS
/SW
/SBa
/SBb
/SBc
/SBd
Data
in
register
Write
control
logic
Address
register
Write address
register
Read
comp.
Memory
array
Data
in Data
out
Mux
Output
Register
/SW
/SBc
Note 2
/SBb
DQ
/SBd
Note 2
/G
/K
/SS
SA0 to SA20
Note 1
SA0 to SA19
Note 2
Mux
ZZ
Write
clock
genelator
/G
ZZ
Notes 1. SA0 to SA20 are used in the
µ
PD44323182.
2. SA0 to SA19, /SBc and /SBd are used in the
µ
PD44323362.
7
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Programmable Impedance / Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow for the SRAM to
adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by
the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175
ohm and 350 ohm. Periodic readjustment of the output driver impedance is necessary as the impedance is greatly
affected by drifts in supply voltage and temperature. The impedance update of the output driver occurs only when the
SRAM is in high impedance. Write and Deselect operations will synchronously switch the SRAM into and out of high
impedance, therefore, triggering an update. Power up requirements for the SRAM are that VDD must be powered
before or simultaneously with VDDQ followed by VREF; inputs should be powered last. The limitation on VDDQ is that it
must not exceed VDD during power up. In order to guarantee the optimum internally regulated supply voltage, the
SRAM requires 4096 clock cycles of power-up time after VDD reaches its operating range. And CID impedance is not
updated during the clock stopped.
Sleep Mode
Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep Mode, the output
will go to a high impedance state and the SRAM will draw standby current. SRAM data will be preserved and a
recovery time (tZZR) is required before the SRAM resumes normal operation. And CID impedance is not updated
during the sleep mode.
8 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Synchronous Truth Table
ZZ /SS /SW /SBa /SBb /SBc /SBd Mode DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 Power
L H × × × × × Not selected High-Z High-Z High-Z High-Z Active
L L H × × × × Read Dout Dout Dout Dout Active
L L L L L L L Write Din Din Din Din Active
L L L L H H H Write Din High-Z High-Z High-Z Active
L L L H L L L Write High-Z Din Din Din Active
H × × × × × × Sleep Mode High-Z High-Z High-Z High-Z Standby
Remark × : Don't care
Output Enable Truth Table
Mode /G DQ
Read L Dout
Read H High-Z
Sleep (ZZ = H) × High-Z
Write (/SW = L) × High-Z
Deselect (/SS = H) × High-Z
Mode Select (I/O) Note 1
M1 M2 Mode
VSS VDD Single Differential Clock (K, /K), R/R Mode Note 2
Notes 1. This device only supports Single Differential Clock, R/R Mode. Mode Select Pins (M1, M2) are to be tied
to either VDD or VSS.
2. R/R: Registered Input / Registered Output
Mode Select (Output Buffer)
ZQ Mode Note
IZQ × RQ Controlled impedance push-pull output buffer mode 1
VDD Push-pull output buffer mode 2
Notes 1. See figure.
ZQ
2. See figure.
ZQ
VDD
9
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition MIN. TYP. MAX. Unit Note
Supply voltage VDD –0.5 +3.0 V 1
Output supply voltage VDDQ –0.5 +3.0 V 1
Input voltage VIN –0.5 VDD + 0.3 (3.0 V MAX) V 1
Input / Output voltage VI/O –0.5 VDD + 0.3 (3.0 V MAX) V 1
Operating temperature Tj 5 110 °C 2
Storage temperature Tstg –55 +125 °C
Notes 1. −1.0 V MIN. (Pulse width 10% Tcyc)
2. T
j = Junction temperature
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (Tj = 5 to 110 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Core supply voltage VDD 2.375 2.5 2.625 V
Output buffer supply voltage VDDQ 1.4 1.9 V
Input reference voltage VREF 0.68 0.95 V
Low level input voltage VIL –0.3
Note VREF – 0.1 V
High level input voltage VIH VREF + 0.1 VDDQ + 0.3 V
Note −1.0 V MIN. (Pulse width 10% Tcyc)
Recommended AC Operating Conditions (Tj = 5 to 110 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input reference voltage VREF (RMS) –5% +5% V
Low level input voltage VIL –0.3 VREF – 0.2 V
High level input voltage VIH VREF + 0.2 VDDQ + 0.3 V
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Note Symbol Test conditions MAX. Unit
Input capacitance CIN VIN = 0 V 6 pF
Input / Output capacitance CI/O VI/O = 0 V 7 pF
Clock input capacitance Cclk Vclk = 0 V 7 pF
Note These parameters are sampled and not 100% tested.
10 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input leakage current ILI VIN = 0 to VDD –5 +5
µ
A
DQ leakage current ILO VI/O = 0 to VDDQ, /SS = VIH or /G = VIH –5 +5
µ
A
Operating supply current ICC VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 550 mA
cycle = 250 MHz, IDQ = 0 mA
Quiescent active power ICC2 VIN = VIH or VIL, /SS = VIL, ZZ = VIL, 250 mA
supply current Cycle = 4 MHz, IDQ = 0 mA
Sleep mode power supply ISBZZ ZZ = VIH, All other inputs = VIH or VIL, 150 mA
current Cycle = DC, IDQ = 0 mA
Power supply standby ISBSS VIN = VIH or VIL, /SS = VIH, ZZ = VIL, 300 mA
current Cycle = 250 MHz, IDQ = 0 mA
Output Voltage on Controlled Impedance Push-Pull Output Buffer Mode (VZQ = IZQ ×
××
× RQ)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low level output voltage VOL IOL = (VDDQ/2) / (RQ/5) ± 15% VSS VDDQ/2 V
@VOL = VDDQ / 2 (175 Ω < RQ < 350 Ω)
High level output voltage VOH IOH = (VDDQ/2) / (RQ/5) ± 15% VDDQ/2 VDDQ V
@VOH = VDDQ / 2 (175 Ω < RQ < 350 Ω)
Output Voltage on Push-Pull Output Buffer Mode (VZQ = VDD)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low level output voltage VOL IOL = +4 mA – 0.3 V
High level output voltage VOH IOH = –4 mA VDDQ – 0.3 – V
11
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions (TA = 0 to 70 °
°°
°C, VDD = 2.375 to 2.625 V, VDDQ = 1.5 V)
Parameter Symbol Conditions Unit
High level input voltage VIH 1.25 V
Low level input voltage VIL 0.25 V
Input reference voltage VREF 0.75 V
Input rise time TR 0.5 ns
Input fall time TF 0.5 ns
Input and output timing reference level Cross point
Remark Parameter tested with RQ = 250 Ω and VDDQ = 1.5 V.
Input waveform (rise and fall time = 0.5 ns (20 to 80%))
V
TT
or V
DD
Q / 2
1.25 V
0.25 V
Output waveform
V
TT
or V
DD
Q / 2
12 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Read and Write Cycle
Parameter Symbol -C40 (250 MHz) -C50 (200 MHz) Unit Note
MIN. MAX. MIN. MAX.
Clock cycle time tKHKH 4.0 – 5.0 – ns
Clock phase time tKHKL / tKLKH 1.5 – 1.5 – ns
Setup times Address tAVKH 0.5 – 0.5 – ns
Write data tDVKH
Write enable tWVKH
Chip select tSVKH
Hold times Address tKHAX 0.5 – 1.0 – ns
Write data tKHDX
Write enable tKHWX
Chip select tKHSX
Clock access time tKHQV – 2.0 – 2.5 ns 1
K high to Q change tKHQX 0.5 – 0.5 – ns 2
/G low to Q valid tGLQV – 2.0 – 2.5 ns 1
/G low to Q change tGLQX 0.5 – 0.5 – ns 2
/G high to Q High-Z tGHQZ 1.0 2.0 1.0 2.5 ns 2
K high to Q High-Z (/SW) tKHQZ 1.0 2.5 1.0 3.0 ns 2
K high to Q High-Z (/SS) tKHQZ2 1.0 2.5 1.0 3.0 ns 2
K high to Q Low-Z tKHQX2 0.7 – 0.7 – ns
/G high Pulse width tGHGL 4.0 – 5.0 – ns 3
/G high to K high tGHKH 1.0 – 1.0 – ns 3
K high to /G low tKHGL 2.5 – 2.5 – ns 3
Sleep mode recovery tZZR 2 – 2 – Cycle 4
Sleep mode enable tZZE – 2 – 2 Cycle 4
Notes 1. See figure. (VTT = 0.75 V, RQ = 250 Ω)
DQ (Output) Zo = 50 Ω50 Ω
V
TT
2. See figure. (VTT = 0.75 V, RQ = 250 Ω)
DQ (Output)
5 pF
50 Ω
V
TT
3. Controlled impedance push-pull output buffer mode only.
4. /SS must be 'high' before sleep mode entry.
13
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
a
Qa Qc Qe Qf Qg
bcdefghijk
Qi
tKHAX
tAVKH tKHKH tKHKL tKLKH
tKHSX
tSVKH
tWVKH
tKHWX
tGHQZ
tGHGL
tGLQX
tGLQV tKHQZ2
tKHQV
tKHQX
tKHQX2
Read Operation
/K
K
Address
/SS
/SW
/G
DQ Qb High-Z High-Z
14 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
l
Ql Qo Qp Qq
mnopqrstuv
t
KHAX
t
AVKH
t
KHKH
t
KHKL
t
KLKH
t
KHSX
t
SVKH
t
WVKH
t
KHWX
t
GLQX
t
GHKH
t
GLQV
t
KHQZ
t
KHDX
t
DVKH
t
KHQX2
Write Operation
/K
K
Address
/SS
/SW
/G
DQ Dn QtDs
t
GHQZ
t
KHGL
High-Z High-Z
15
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
a
Qa Qc
bcdefghijk
t
ZZE
t
ZZR
Sleep Mode
/K
K
Address
/SS
/ZZ
DQ Qb
l
Qj
High-Z
16 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
JTAG Specifications
The
µ
PD44323182 and
µ
PD44323362 support a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name Pin assignments Description
TCK 4 U Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS 2 U Test Mode Select. This is the command input for the TAP controller state machine.
TDI 3 U
Test Data Input. This is the input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in the TAP instruction.
TDO 5 U Test Data Output. Output changes in response to the falling edge of TCK. This is the output
side of the serial registers placed between TDI and TDO.
Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (Tj = 5 to 110 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
JTAG input high voltage VIH 2.2 VDD + 0.3 (3.0 V MAX) V
JTAG input low voltage VIL –0.3 +0.5 V
JTAG output high voltage VOH IOH = –8 mA 2.4 – V
JTAG output low voltage VOL IOL = 8 mA – 0.4 V
17
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
JTAG AC Test Conditions (Tj = 5 to 110 °
°°
°C)
Input waveform (rise / fall time = 1 ns (20 to 80%
%%
%))
V
DD
/ 2 Test Points
V
DD
V
DD
/ 2
0 V
Output waveform
V
DD
/ 2 Test Points V
DD
/ 2
Output load (VTT = 1.5 V)
TDO Z0 = 50 Ω50 Ω
V
TT
18 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
JTAG AC Characteristics (Tj = 5 to 110 °
°°
°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Note
Clock cycle time (TCK) tTHTH 100 – ns
Clock phase time (TCK) tTHTL / tTLTH 40 – ns
Setup time (TMS / TDI) tMVTH / tDVTH 10 – ns
Hold time (TMS / TDI) tTHMX / tTHDX 10 – ns
TCK low to TDO valid (TDO) tTLQV – 20 ns
JTAG Timing Diagram
19
Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
Scan Register Definition (1)
Register name Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is moved
into the run-test/idle or the various data register state. The register can be loaded when it is placed
between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE
instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test
data to be passed through the RAMs TAP to another device in the scan chain with as little delay as
possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the
controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The
register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs
I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins
when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the
boundary register. The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The shift register bit
nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input
or I/O at the bump and the third column is the bump number
Scan Register Definition (2)
Register name
µ
PD44323182
µ
PD44323362 Unit
Instruction register 3 3 bit
Bypass register 1 1 bit
ID register 32 32 bit
Boundary register 51 70 bit
ID Register Definition
Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit
µ
PD44323182 2M × 18 XXXX 0000 0000 0011 1011 00000010000 1
µ
PD44323362 1M × 36 XXXX 0000 0000 0011 1100 00000010000 1
20 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
µ
PD44323182, 44323362
SCAN Exit Order
[
µ
µµ
µ
PD44323182 (2M words by 18 bits)] [
µ
µµ
µ
PD44323362 (1M words by 36 bits)]
Bit Signal Bump Bit Signal Bump Bit Signal Bump Bit Signal Bump
no. name ID no. name ID no. name ID no. name ID
1 M2 5R 26 SA17 3B 1 M2 5R 36 SA16 3B
2 SA5 6T 27 SA19 2B 37 SA18 2B
3 SA1 4P 28 SA9 3A 2 SA1 4P 38 SA9 3A
29 SA10 3C 3 SA8 4T 39 SA10 3C
4 SA4 6R 30 SA13 2C 4 SA4 6R 40 SA13 2C
5 SA8 5T 31 SA12 2A 5 SA7 5T 41 SA12 2A
6 ZZ 7T 6 ZZ 7T 42 DQc9 2D
32 DQb1 1D 7 DQa9 6P 43 DQc8 1D
7 DQa1 7P 33 DQb2 2E 8 DQa8 7P 44 DQc7 2E
8 DQa2 6N 9 DQa7 6N 45 DQc6 1E
10 DQa6 7N 46 DQc5 2F
34 DQb3 2G 11 DQa5 6M 47 DQc4 2G
9 DQa3 6L 12 DQa4 6L 48 DQc3 1G
13 DQa3 7L 49 DQc2 2H
35 DQb4 1H 14 DQa2 6K 50 DQc1 1H
10 DQa4 7K 36 /SBb 3G 15 DQa1 7K 51 /SBc 3G
11 /SBa 5L 37 ZQ 4D 16 /SBa 5L 52 ZQ 4D
12 /K 4L 38 /SS 4E 17 /K 4L 53 /SS 4E
13 K 4K 39 SA20 4B 18 K 4K 54 SA19 4B
14 /G 4F 19 /G 4F
40 NC 4H 20 /SBb 5G 55 NC 4H
41 /SW 4M 21 DQb1 7H 56 /SW 4M
15 DQa5 6H 22 DQb2 6H 57 /SBd 3L
16 DQa6 7G 23 DQb3 7G 58 DQd1 1K
42 DQb5 2K 24 DQb4 6G 59 DQd2 2K
17 DQa7 6F 43 DQb6 1L 25 DQb5 6F 60 DQd3 1L
18 DQa8 7E 26 DQb6 7E 61 DQd4 2L
44 DQb7 2M 27 DQb7 6E 62 DQd5 2M
45 DQb8 1N 28 DQb8 7D 63 DQd6 1N
19 DQa9 6D 29 DQb9 6D 64 DQd7 2N
20 SA2 6A 30 SA2 6A 65 DQd8 1P
21 SA3 6C 46 DQb9 2P 31 SA3 6C 66 DQd9 2P
22 SA7 5C 47 SA11 3T 32 SA6 5C 67 SA11 3T
23 SA6 5A 48 SA14 2R 33 SA5 5A 68 SA14 2R
24 SA18 6B 49 SA0 4N 34 SA17 6B 69 SA0 4N
25 SA16 5B 50 SA15 2T 35 SA15 5B
51 M1 3R 70 M1 3R
21
Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
JTAG Instructions
Instructions Description
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to high impedance any time the instruction is loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in
the test-logic-reset state.
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board
level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the
TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive
drive state (high impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
JTAG Instruction Cording
IR2 IR1 IR0 Instruction Note
0 0 0 EXTEST 1
0 0 1 IDCODE
0 1 0 SAMPLE-Z 1
0 1 1 BYPASS
1 0 0 SAMPLE
1 0 1 BYPASS
1 1 0 BYPASS
1 1 1 BYPASS
Note 1. TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
22 Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
TAP Controller State Diagram
Test-Logic-Reset
Run-Test / Idle Select-DR-Scan
Capture-DR Capture-IR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Select-IR-Scan
0
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
10 10
11 1
0
1
1
0
1
0
11
Disabling The Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and
may be left unconnected. But they may also be tied to VDD through a 1k Ω resistor.
TDO should be left unconnected.
23
Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
Test Logic Operation (Instruction Scan)
TCK
Contoroller
state
TDI
TMS
TDO
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Shift-IR
Exit1-IR
Update-IR
Run-Test/Idle
IDCODE
Instruction
Register state New Instruction
Output Inactive
24 Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
Test Logic (Data Scan)
Controller
state
TDI
TMS
TDO
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Shift-DR
Exit1-DR
Update-DR
Test-Logic-Reset
Instruction
Instructin
Register state IDCODE
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Output Inactive
TCK
25
Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
Package Drawing
ITEM DIMENSIONS
D
E
D1
E1
w
e
A
A1
A2
b
x
y
y1
ZD
ZE
14.00±0.20
22.00±0.20
2.06±0.30
0.60±0.10
12.00
0.30
19.50
1.27
0.35
3.19
0.84
1.46
0.15
0.75±0.15
0.15
(UNIT:mm)
P119F1-127-FJ1
SwA
SwB
ZE
ZD
A
B
7
6
5
4
3
2
1
ABCDEFGHJKLMNPRTU
E1
E
S
25°
e
xbAB
M
φφ
S
A
A2
A1
y1 S
S
y
D1
INDEX MARK
4–C1.05
D
119-PIN PLASTIC BGA (14x22)
26 Preliminary Data Sheet M16379EJ3V0DS
µ
µµ
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PD44323182, 44323362
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD44323182 and
µ
PD44323362.
Types of Surface Mount Device
µ
PD44323182F1-FJ1: 119-pin plastic BGA
µ
PD44323362F1-FJ1: 119-pin plastic BGA
27
Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
3rd edition/ p.1 p.1 Addition Ordering Number "Note Under development" has been added
Nov. 2003 to
µ
PD44323182.
p.9 p.9 Addition Capacitance Cclk has been added.
p.10 p.10 Addition DC Characteristics ICC2 and ISBSS have been determined.
ICC2: 250 mA
ISBSS: 300 mA
p.19 p.19
Addition ID Register Definition ID [27:12] part no. has been determined.
x18: 0000 0000 0011 1011
x36: 0000 0000 0011 1100
p.25 p.25
Modification Package Drawing Preliminary version → Standardize version
28 Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
[MEMO]
29
Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
[MEMO]
30 Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
[MEMO]
31
Preliminary Data Sheet M16379EJ3V0DS
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PD44323182, 44323362
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
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PD44323182, 44323362
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
