4
3
2
26
INVERTING INPUT
DIRECT INPUT
OFFSET ADJUST
REFERENCE HOLD
27
32, 33 7, 35, 37
DATA VALID
DIGITAL GROUND ANALOG GROUND
25
23
10
24
6
START CONVERT
BIT 1 (MSB)
BIT 14 (LSB)
OUT-OF-RANGE
+2.4V REFERENCE OUTPU
T
+12V
A
–5V
A
+5V
A
+5V
D
39 38 36 34
TIMING
AND
CONTROL
SAMPLING
A/D
NON-INVERTING INPUT
75
Ω
523
Ω
0.01µF
5K
Ω
1 FINE GAIN ADJUST
5
INPUT AMPLIFIER
30 31
A1
CORRELATED
DOUBLE
SAMPLER
AØ
FEATURES
••
••
•14-bit resolution
••
••
•3MPPS throughput rate (14-bits)
••
••
•Functionally complete
••
••
•V ery low noise
••
••
•Excellent Signal-to-Noise ratio
••
••
•Edge triggered
••
••
•Small, 40-pin, TDIP package
••
••
•Low power , 500mW typical
••
••
•Low cost
••
••
•Programmable Analog Bandwidth
GENERAL DESCRIPTION
The ADCDS-1403 is an application-specific video signal
processor designed for electronic-imaging applications that
employ CCD's (charge coupled devices) as their photodetector.
The ADCDS-1403 incorporates a "user configurable" input
amplifier, a CDS (correlated double sampler) and a sampling A/
D conver ter in a single package, providing the user with a
complete, high performance, low-cost, low-power, integrated
solution.
The key to the ADCDS-1403's performance is a unique, high-
speed, high-accuracy CDS circuit, which eliminates the effects
of residual charge, charge injection and "kT/C" noise on the
CCD's output floating capacitor, producing a "valid video"
output signal. The ADCDS-1403 digitizes this resultant "valid
video" signal using a high-speed, low-noise sampling
A/D conv erter .
The ADCDS-1403 requires only the rising edge of start conve rt
pulse to initiate its conversion process. Additional features of
the ADCDS-1403 include gain adjust, offset adjust, precision
+2.4V reference, and a programmable analog bandwidth
function.
Figure 1. ADCDS-1403 Functional Block Diagram
1 FINE GAIN ADJUST 40 NO CONNECT
2 OFFSET ADJUST 39 +12V
3 DIRECT INPUT 38 –5VA
4 INVERTING INPUT 37 ANALOG GROUND
5 NON-INVERTING INPUT 36 +5 VA
6 +2.4V REF. OUTPUT 35 ANALOG GROUND
7 ANALOG GROUND 34 +5VD
8 NO CONNECT 33 DIGITAL GROUND
9 NO CONNECT 32 DIGITAL GROUND
10 BIT 14 (LSB) 31 A1
11 BIT 13 30 A
12 BIT 12 29 NO CONNECT
13 BIT 11 28 NO CONNECT
14 BIT 10 27 DATA VALID
15 BIT 9 26 REFERENCE HOLD
16 BIT 8 25 STA RT CONVERT
17 BIT 7 24 OUT-OF-RANGE
18 BIT 6 23 BIT 1 (MSB)
19 BIT 5 22 BIT 2
20 BIT 4 21 BIT 3
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION PIN FUNCTION
®®
PRELIMINARY PRODUCT DATA
DATEL, Inc., Mansfield, MA 02048 (USA) • Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356 • Email: sales@datel.com • Internet: www.datel.com
ADCDS-1403
14-Bit, 3 Megapixels/Second
Imaging Signal Pr ocessor
ADCDS-1403
2
®®
ANALOG INPUT MIN. TYP. MAX. UNITS
Input Voltage Rang e
(externally configurable) 0.350 2.8 — V olts p-p
Input Resistance — 5000 — Ohm
Input Capacitance —10—pF
DIGIT AL INPUTS
Logic Levels
Logic 1 +3.5 — — V olts
Logic 0 — — +.80 Volts
Logic Loading
Logic 1 — — +10 uA
Logic 0 — — –10 uA
DIGIT AL OUTPUTS
Logic Levels
Logic 1 (IOH = .5ma) +2.4 — — Volts
Logic 1 (IOH = 50µa) +4.5 — — Volts
Logic 0 (IOL = 1.6ma) — — +0.4 Volts
Logic 0 (IOL = 50ua) — — +0.1 Volts
Internal Reference
Voltage
(Fine gain adjust pin (1) grounded)
+25°C 2.35 2.4 2.45 Volts
0 to 70°C 2.35 2.4 2.45 Volts
–55 to +125°C 2.35 2.4 2.45 Volts
External Current — 1.0 — mA
ST A TIC PERFORMANCE
Differential Nonlinearity
(Histogram, 98kHz) +25°C –0.90 ±0.5 +.90 LSB
0 to 70°C –0.90 ±0.5 +.90 LSB
–55 to +125°C –1.0 ±0.6 +1.0 LSB
Integral Nonlinearity
+25°C — ±2.5 — LSB
0 to 70°C — ±2.5 — LSB
–55 to +125°C — ±2.5 — LSB
Guaranteed No Missing Codes
0 to 70°C 14 — — L S B
–55 to +125°C 14 — — L SB
DC Noise
+25°C — 1.0 2.0 LSB
0 to 70°C — 1.0 2.0 L S B
–55 to +125°C — 1.25 3.0 LS B
Offset Error
+25°C — ±0.6 ±1.07 %FSR
0 to 70°C — ±0.6 ±1.25 %FSR
–55 to +125°C — ±0.7 ±1.35 %FSR
Gain Error
+25°C — ±1.43 ±2.8 %FSR
0 to 70°C — ±1.35 ±2.8 %FSR
–55 to +125°C — ±1.35 ±2.8 %FSR
PARAMETERS MIN. TYP. MAX. UNITS
+12V Supply (Pin 32) 0 — +1 4 Volts
–5V Supply (Pin 31) –0.3 — +6.5 Volts
+5V Supply (Pin 28, 29) 0 — –6.5 Volts
Digital Input (Pin 23, 24) –0.3 — Vdd+0.3V Volts
Analog Input (Pin 3,4,5) –5 — +5 Volts
Lead Temperature (10 seconds) — — 30 0 °C
ABSOLUTE MAXIMUM RATINGS
FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range, under the following conditions:
Vcc=+12V, +Vdd=+5V, Vee=–5V, fin=98KHz, sample rate=3MHz.
D YNAMIC PERFORMANCE
Reference Hold
Aquisition Time 100 — — ns
Droop
@ +25°C — 25 — mV/us
@ –55 to +125°C — 100 — mV/us
Peak Harmonic (SFDR)
(CDD-IN, input on pin (3)
Input @ 98 KHZ)
@ +25 °C — –76 –72 d B
@ 0 to +70°C — –76 –72 d B
@ –55 to +125°C — –74 –72 d B
Peak Harmonic (SFDR)
(Input on pin (5)
Input @ 98 KHZ)
@ +25 °C — –76 –72 d B
@ 0 to +70°C — –76 –72 d B
@ –55 to +125°C — –74 –72 d B
Total Harmonic Distortion
(CDD-IN, input on pin (3)
Input @ 98 KHZ)
@ +25 °C — –75 –72 d B
@ 0 to +70°C — –75 –72 d B
@ –55 to +125°C — –74 –69 d B
(Input on pin (5)
Input @ 98 KHZ)
@ +25 °C — –76 –72 d B
@ 0 to +70°C — –76 –72 d B
@ –55 to +125°C — –74 –69 d B
Signal-to-Noise Ratio
Without Distortion
(CDD-IN, input on pin (3)
Input @ 98 KHZ)
@ +25 °C 73 75 — dB
@ 0 to +70°C 72 75 — dB
@ –55 to +125°C 68 75 — dB
(Input on pin (5)
Input @ 98 KHZ)
@ +25 °C 73 75 — dB
@ 0 to +70°C 72 75 — dB
@ –55 to +125°C 68 75 — dB
Signal-to-Noise Ratio
With Distortion
(CDD-IN, input on pin (3)
Input @ 98 KHZ)
@ +25 °C 69 71 — dB
@ 0 to +70°C 69 71 — dB
@ –55 to +125°C 67 70 — dB
(Input on pin (5)
Input @ 98 KHZ)
@ +25 °C 70 71 — dB
@ 0 to +70°C 70 71 — dB
@ –55 to +125°C 67 70 — dB
SIGNAL TIMING
Conversion Rate
–55 to +125°C 3 — — M Hz
Conversion Time — 200 — nsec
Start Convert Pulse Width 20 150 — nsec
POWER REQUIREMENTS MIN. TYP. MAX. UNITS
Power Supply Range
+12V Supply +11.4 +12.0 +12.6 V olts
+5V Supply +4.75 +5.0 +5.25 V olts
–5V Supply –4.75 –5.0 –5.25 V olts
Power Supply Current
+12V Supply — +13 +16 mA
ADCDS-1403
3
®®
TECHNICAL NO TES
1. Obtaining fully specified performance from the
ADCDS-1403 requires careful attention to pc-card layout
and power supply decoupling. The device's analog and
digital grounds are connected to each other internally.
Depending on the level of digital switching noise in the
overall CCD system, the performance of the ADCDS-1403
may be improved by connecting all ground pins (7,32,33,35,
37) to a large
analog
ground plane beneath the package.
The use of a single +5V
analog
supply for both the +5VA
(pin 36) and +5VD (pin 34) may also be beneficial.
2. Bypass all power supplies to ground with a 4.7µf tantalum
capacitor in parallel with a 0.1µf ceramic capacitor. Locate
the capacitors as close to the package as possible.
3. If using the suggested offset and gain adjust circuits
(Fig. 3 & 5), place them as close to the ADCDS-1403's
package as possible.
ADCDS-1403 Modes of Operation
The input amplifier stage of the ADCDS-1403 provides the
designer with a tremendous amount of flexibility. The
architecture of the ADCDS-1403 allows its input-amplifier to be
configured in any of the following configurations:
• Direct Mode (AC coupled)
• Non-Inverting Mode
• Inve r ting Mode
When applying inputs which are less than 2.8Vp-p, a coarse
gain adjustment (applying an external resistor to pin 4) must be
performed to ensure that the full scale video input signal
(saturated signal) produces a 2.8Vp-p signal at the input-
amplifier's output (Vout).
In all three modes of operation, the video portion of the signal
at the CDS input (i.e. input-amplifier's Vout) must be more
negative than its associated reference level and Vout should
not exceed ±2.8V DC.
The ADCDS-1403 achieves it specified accuracies without the
need for exter nal calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using the
FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2)
features.
PO WER REQUIREMENTS MIN. TYP . MAX. UNITS
Power Supply Current
+5V Supply — +40 +46 mA
–5V Supply –140 –27 –35 mA
Power Dissipation — 0.50 0.60 Watts
Power Supply Rejection
(5%) @ +25°C — — ±0.007 %FSR/%V
ENVIRONMENTAL
Operating T emperature Range
–MC 0 — +70 °C
–MC –55 — +125 °C
Storage Temperature –65 — +150 °C
Package Type 40-pin, TDIP
Weight 16.10 grams
Figure 2a.
Figure 2b.
Direct Mode (AC Coupled)
This is the most common input configuration as it allows the
ADCDS-1403 to interface directly to the output of the CCD with
a minimum amount of analog "front-end" circuitry. This mode of
operation is used with full-scale video input signals from
0.350Vp-p to 2.8Vp-p.
Figure 2a. descr ibes the typical configuration for applications
using a video input signal with a maximum amplitude of
0.350Vp-p. The coarse gain of the input amplifier is
determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors
having a 1% tolerance. Additional fine gain adjustment can be
accomplished using the Fine Gain Adjust (pin 1).
Figure 2b. describes the typical configuration for applications
using a video input signal with an amplitude greater than
0.350Vp-p and less than 2.8Vp-p. Using a single external
series resistor (see Fig. 4.), the coarse gain of the ADCDS-
1403 can be set, with additional fine gain adjustments being
made using the Fine Gain Adjust function (pin 1). The coarse
gain of the input amplifier can be determined from the
following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all inter nal
resistors having a 1% tolerance.
4
3
5
75
Ω
523
Ω
V
IN
NO CONNECT
V
OUT
= 2.8Vp-p
5k
Ω
0.01µF
Rext
4
3
5
75
Ω
523
Ω
V
IN
NO CONNECT V
OUT
= 2.8Vp-p
5k
Ω
0.01µF
Rext
Figure 2c.
4
3
5
75
Ω
523
Ω
V
IN
NO CONNECT
V
OUT
= 2.8Vp-p
5k
Ω
0.01µF
ADCDS-1403
4
®®
Inverting Mode
The inverting mode of operation can be used in applications
where the analog input to the ADCDS-1403 has a video input
signal whose amplitude is more positive than its associated
reference level.
The ADCDS-1403's correlated double
sampler (i.e. input amplifier's V
OUT
) requires that the video
signal's amplitude be more negative than its reference
level at all times (see timing diagram for details).
Using the
ADCDS-1403 in the inve rting mode allows the designer to
perform an additional signal inversion to correct for any analog
"front end" pre-processing that may have occurred prior to the
ADCDS-1403.
Figure 2e. descr ibes the typical configuration for applications
using a video input signal with a maximum amplitude of
0.400Vp-p. Additional fine gain adjustments can be made
using the Fine Gain Adjust function (pin 1). The coarse gain of
this circuit can be determined from the following equation:
VOUT = 2.8Vp-p = –VIN*(523/75), with all inter nal resistors
having a 1% tolerance.
Figure 2f. describes the typical configuration used in
applications needing to invert video input signals whose
amplitude is greater than 0.400Vp-p. Using a single external
series resistor (see Fig. 4.), the initial gain of the ADCDS-1403
can be set, with additional fine gain adjustments being made
using the Fine Gain Adjust function (pin 1). The coarse gain of
this circuit can be determined from the following equation:
VOUT = 2.8Vp-p = –VIN*(523/75+Rext), with all internal resistors
having a 1% tolerance.
Figure 3. Offset Adjustment Circuit
Offset
Adjust
2
External
Series
Resistor
ADCDS-1403
+5V
–5V
20K
Ω
Figure 2d.
Non-Inverting Mode
The non-inverting mode of the ADCDS-1403 allows the designer
to either attenuate or add non-inverting gain to the video input
signal. This configuration also allows bypassing the ADCDS-
1403's internal coupling capacitor , allowing the user to provide an
external capacitor of appropriate value.
Figure 2c. describes the typical configuration for applications
using video input signals with amplitudes greater than
0.350Vp-p and less than 2.8Vp-p (with common mode limit of
±2.5V DC). Using a single external ser ies resistor
(see Fig. 4.), the coarse gain of the ADCDS-1403 can be set
with additional fine gain adjustments being made using the
Fine Gain Adjust function (pin 1). The coarse gain of the circuit
can be determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal
resistors having a 1% tolerance.
Figure 2d. descr ibes the typical configuration for applications
using a video input signal whose amplitude is greater than
2.8Vp-p. Using a single external ser ies resistor (Rext 1) in
conjunction with the internal 5K (1%) resistor to ground, an
attenuation of the input signal can be achieved. Additional fine
gain adjustments being made using the Fine Gain Adjust
function (pin 1). The coarse gain of this circuit can be
determined from the following equation:
VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]*
[1+(523/(75+Rext2))], with all internal resistors having
a 1% tolerance.
Figure 2e.
4
3
5
75
Ω
523
Ω
NO CONNECT V
OUT
= 2.8Vp-p
5k
Ω
0.01µF
Rext1
V
IN
Rext2
4
3
5
75
Ω
523
Ω
NO CONNECT V
OUT
= 2.8Vp-p
5k
Ω
0.01µf
–V
IN
4
3
5
75
Ω
523
Ω
NO CONNECT V
OUT
= 2.8Vp-p
5k
Ω
0.01µf
–V
IN
Rext
Figure 2f.
ADCDS-1403
5
®®
Figure 4. Coarse Gain Adjustment Plot
Offset Adjustment
Manual offset adjustment for the ADCDS-1403 can be
accomplished using the adjustment circuit shown in Figure 3.
A software controlled D/A converter can be substituted for the
20KΩ potentiometer. The offset adjustment feature allows the
user to adjust the Offset/Dark Current level of the ADCDS-
1403 until the output bits are 00 0000 0000 0000 and the LSB
flickers between 0 and 1. Offset adjust should be performed
before gain adjust to avoid interaction. The ADCDS-1403's
offset adjustment is dependent on the value of the exter nal
series resistor used in the offset adjust circuit (Fig. 3). The
Offset Adjustment graph (Fig. 6) illustrates the typical
relationship between the exter nal ser ies resistor value and its
offset adjustment capability utilizing ±5V supplies.
Coarse Gain A d justment P lot
External Gain R es isto r vs. Fu ll Sc ale Vid eo Inp ut
10
100
1000
10000
0.25
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
Full Scale Video Signal (Volts)
External Gain Resistor (Ohms)
Inverting Mode
Direct Mode & Non-Inverting Mode
Figure 6. Offset Adjustment vs. External Series Resistor
Offset Adjustment vs. External Series Resistor
10
100
1000
10000
0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60
k
External Series Resistor (Ohm 's)
±LSB's of A d justm e n t
Figure 5. Fine Gain Adjustment Circuit
ADCDS-1403
Fine
Gain
Adjust
1
+5V
–5V
2
0K
Ω
External Series Resistor Value
(
Ohms
)
0.01
0.1
1
10
100
0 5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
Offset Adju stment S en sitivity
External Series Resistor vs. Outpu t Variation (LSB 's)
Output Variation (LSB's)
Peak-Peak
variation at
potentiometer
1mV
10mV
100mV
Figure 7. Offset Adjustment Sensitivity
ADCDS-1403
6
®®
T able 1. Out-of-Range Conditions
OUT-OF-RANGE MSB OVERRANGE UNDERRANGE INPUT SIGNAL
0 0 0 0 In Range
0 1 0 0 In Range
1 0 0 1 Underrrange
1 1 1 0 Overrange
Offset Adjustment Sensitivity
It should be noted that with increasing amounts of offset
adjustment (smaller values of exter nal ser ies resistors), the
ADCDS-1403 becomes more susceptible to power supply
noise or voltage var iations seen at the wiper of the offset
potentiometer.
For Example:
External 50KΩΩ
ΩΩ
Ω resistor:
1. 10mV of noise or voltage variation at the potentiometer
will produce 0.25LSB's of output variation.
2.100mV of noise or voltage variation at the potentiometer
will produce 2.5LSB's of output variation.
The Offset Adjustment Sensitivity graph (Fig. 7) illustrates the
offset adjustment sensitivity over a wide range of external
resistor and noise values. If a large offset voltage is required, it
is recommended that a very low noise external reference be
used in the offset adjust circuit in place of power supplies. The
ADCDS-1403's +2.4V reference output could be configured to
provide the reference voltage for this type of application.
Fine Gain Adjustment
Fine gain adjustment (Pin 1) is provided to compensate for the
tolerance of the external coarse gain resistor (Rext) and/or the
unavailability of exact coarse gain resistor (Rext) values. Note,
the fine gain adjustment will not change the expected input
amplifier's full scale VOUT (2.8Vp-p.) Instead, the gain of the
ADCDS-1403's internal A/D is adjusted allowing the actual
input amplifier's full scale VOUT to produce an output code of all
ones (11 1111 1111 1111).
MSB
OUT-OF-RANGE
"OVERRANGE"
"UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
Fine gain adjustment for the ADCDS-1403 is accomplished using
the adjustment circuit shown below (Fig. 5). A software controlled
D/A conv erter can be substituted for the 20KΩ potentiometer.
The fine gain adjust circuit ensures that the video input signal
(saturated signal) will be properly scaled to obtain the desired
Full Scale digital output of 11 1111 1111 1111, with the LSB
flickering between 0 and 1. Fine gain adjust should be performed
following the offset adjust to av oid interaction. The fine gain adjust
provides ±256 codes of adjust when ±5V supplies are used for
the Fine Gain Adjust Circuit.
Out-of-Range Indicator
The ADCDS-1403 provides a digital Out-of-Range output
signal (pin 24) for situations when the video input signal
(saturated signal) is beyond the input range of the internal A/D
converter . The digital output bits and the Out-of-Range signal
correspond to a particular sampled video input voltage, with both
of these signals having a common pipeline dela y .
Using the circuit described in Figure 8., both overrange
and underrange conditions can be detected (see Table 1). When
combined with a D/A converter , digital detection and correction
can be performed for both the gain and offset errors.
ADCDS-1403
7
®®
Ta ble 2. Output Coding
Notes: ➀ Input Amplifier VOUT = (Video Signal - Ref erence Le vel)
➁ The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated ref erence
level and VOUT should not exceed ±2.8V DC .
Video Signal-Reference Signal > –2.80000 >Full Scale –1LSB 11 1111 1111 1111 1
–2.80000 Full Scale –1LSB 11 1111 1111 1111 0
–2.10000 3/4FS 11 0000 0000 0000 0
–1.40000 1/2FS 10 0000 0000 0000 0
– 0.70000 1/4FS 01 0000 0000 0000 0
– 0.35000 1/8FS 00 1000 0000 0000 0
–0.000171 1 LSB 00 0000 0000 0001 0
0 0 00 0000 0000 0000 0
Video Signal-Ref erence Signal <0 ➁<0 00 0000 0000 0000 1
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-
out" rates, the ADCDS-1403's input stage must have sufficient
analog bandwidth to accurately reproduce the output signals of
the CCD array. The amount of analog bandwidth determines
how quickly and accurately the "Reference Hold" and the "CDS
output" signals will settle. If only a single analog bandwidth was
offered, the ADCDS-1403's bandwidth would be set to acquire
and digitize CCD output signals to 14-bit accuracy, at maximum
conversion rate of 3MHz (333ns see Figure 11. for details).
Applications not requiring the maximum conversion rate would
INPUT AMPLIFIER VOUT, ➀ ➀
➀ ➀
➀ (VOLTS P-P) SCALE DIGITAL OUTPUT OUT-OF-RANGE
Output Coding
The ADCDS-1403's output coding is Straight Binary as
indicated in Table 2. The table shows the relationship between
the output data coding and the difference between the
reference signal voltage and its corresponding video signal
voltage. (These voltages are referred to the output of the
ADCDS-1403's input amplifier's VOUT).
Ta ble 3. Programmable Analog Bandwidth
REFERENCE HOLD CDS OUTPUT A0 A1 ADCDS-1403 MAXIMUM
"AQUISITION TIME" "SETTLING TIME" (Pin 30) (Pin 31) CONVERSION RATE
100ns 120ns 0 0 3MHz
200ns 250ns 1 0 2MHz
450ns 500ns 0 1 1MHz
600ns 1000ns 1 1 0.5MHz
Note: See Figure 11. for timing details
be forced to use the full analog bandwidth at the possible
expense of noise performance.
The ADCDS-1403 avoids this situation by offering a fully
programmable analog bandwidth function. The ADCDS-1403
allows the user to "bandwidth limit" the input stage in order to
realize the highest level of noise performance for the
application being considered. Table 3. describes how to select
the appropriate reference hold "aquisition time" and CDS
output "settling time" needed for a particular application. Each
of the selections listed in Table 3. have been optimized to
provide only enough analog bandwidth to acquire a full scale
input step, to 14-bit accuracy, in a single conversion.
Increasing the analog bandwidth (using a faster settling and
acquisition time) would only serve to potentially increase the
amount of noise at the ADCDS-1403's output. The ADCDS-
1403 uses a two bit digital word to select four different analog
bandwidths for the ADCDS-1403's input stage (See Table 3.
for details).
ADCDS-1403
8
®®
Figure 9. ADCDS-1403 Connection Diagram
Timing
The ADCDS-1403 requires two independently operated signals
to accurately digitize the analog output signal from the CCD
array.
•Reference Hold (pin 26)
•Star t Conver t (pin 25)
The "Reference Hold" signal controls the operation of an
internal sample-hold circuit. A logic "1" places the sample-hold
into the hold mode, capturing the value of the CCD's reference
signal. The Reference Hold Signal allows the user to control the
exact moment when the sample-hold is placed into the "hold"
mode. For optimal performance the sample-hold should be
placed into the "hold" mode once the reference signal has fully
settled from all switching transients to the desired accuracy
(user defined).
Once the reference signal has been "held" and the video
por tion of the CCD's analog output signal appears at the
ADCDS-1403's input, the ADCDS-1403's correlated double
+ + +
+12V +5VD –5VA
4.7µF
0.1µF
39 36 38
1
20K
Ω
+5V
–5V
5
4
3
23
22
21
20
19
18
17
16
15
14
13
12
11
10
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14 (LSB)
6
24
27
+2.4V REFERENCE OU
T
OUT-OF-RANGE
DATA VALID
ADCDS-1403
4.7µF
0.1µF
4.7µF
0.1µF
ANALOG GROUND
NON-INVERTING INPUT
INVERTING INPUT
DIRECT INPUT
+5VA
36
7, 35, 37
+
4.7µF
0.1µF
26
25
REF. HOLD
START CONVERT
2
20K
Ω
+5V
–5V
OFFSET ADJUST
FINE GAIN ADJUST
External Series
Resistor
32, 33 DIGITAL GROUND
30
31 A1
A
sampler produces a "CDS Output" signal (see figure 11.)
which is the difference between the "held" reference level and
its associated video level. When the "CDS Output" signal has
settled to the desired accuracy (user defined), the A/D
conversion process can be initiated with the r ising edge of a
single start convert (Pin 25) signal.
Once the A/D conversion has been initiated, Reference Hold
(Pin 26) can be placed back into the "Acquisition" mode in
order to begin aquiring the next reference level. For optimal
performance the ADCDS-1403's internal sample-hold should
be placed back into the "Aquisition" mode (Reference Hold to
logic "0") during the CCD's "Reference Quiet Time"
("Reference Quiet Time" is defined as the period when the
CCD's reference signal has settled from all switching
transients to the desired accuracy (see Figure 10.)). Placing
the sample-hold back into the "aquisition" mode during the
"Reference Quiet Time" prevents the ADCDS-1403's internal
amplifiers from unecessarily tracking (reproducing) the large
switching transients that occur during the CCD's reset to
reference transition.
ADCDS-1403
9
®®
Figure 11. ADCDS-1403 Timing Diagram
Figure 10. Reference Hold Timing
Reset N Reset N+1 Reset N+2 Reset N+3 Reset N+4
Note: As described in Figure 10, the 60ns min. is dependant on the quality of the CCD's Reference when the ADCDS-1403 is switched bac k into the tr a c k mode
CCD OUTPUT
CDS OUTPUT
START CONVERT
DATA OUTPUT
REFERENCE HOLD IN
CDS OUTPUT
DATA OUTPUT
100ns min.
133ns min
120ns min settling line
Full Scale
Step
150ns min
DATA N-4 VALID DATA N-3 VALID DATA N-2 VALID DATA N-1 VALID DATA N VALID
20ns min
N
Ref N
Video N
Ref. N+1 Video N+1
100ns min.
333ns min.
120ns min. settling time
150ns typ.
20ns max
Ref. N
Video N Video N+1 Ref. N+2 Video N+1Video N+2 Ref. N+3
Video N+1Video N+3
Ref. N+4
N+2 N+3
NN+1 N+2 N+3
Hold
Acqu is ition
Time
N+1
Invalid data
30ns min., 50ns max.
DATA VALID
CCD OUTPUT
REFERENCE HOLD
Note: For optimal performance (Fastest Acquisition Time), the ADCDS-1403 should be placed into the Acquisition mode (Reference Hold to lo g ic "0 ") d u rin g th e C CD o u tpu t's R e fe re nc e
"Quiet Time". Reference "Quiet Time" is defined as the period when the reference si
g
nal's switchin
g
transients have settled to an acceptable
(
user defined
)
accurac
y
.
HOLD
Reset
Video
Reference
Reference
"Quiet T ime"
100NS MIN.
Acquisition Time
Acquis it io n mo d e d u r in g
Reference "Quiet Time"
MECHANICAL DIMENSIONS INCHES (mm)
ORDERING INFORMATION
OPERATING 40-PIN
MODEL TEMPERATURE RANGE PACKAGE
ADCDS-1403MC 0 to 70°C TDIP
ADCDS-1403MM –55 to 125°C TDIP
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
Internet: www.datel.com Email: sales@datel.com
Data sheet f ax back: (508) 261-2857
D ATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein
do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.
DATEL (UK) LTD. Tadley, England Tel: (01256)-880444
DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01
DATEL GmbH Munchen, Ger many Tel: 89-544334-0
DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025
DS-332 1/99
®®
ISO 9001
I
SO 9001
REGISTERED
ADCDS-1403
®®
0.100 TYP.
(2.540)
120
21
40
1.900 ±0.008
(48.260)
Dimension Tolerances
(unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)
0.900 ±0.010
(22.86)
