1
LTC1771
■
Very Low Standby Current: 10µA
■
Available in Space-Saving 8-Lead MSOP Package
■
Output Currents: Up to 5A
■
Wide V
IN
Range: 2.8V to 20V Operation
■
V
OUT
Range: 1.23V to 18V
■
High Efficiency: Over 93% Possible
■
±2% Output Accuracy
■
Very Low Dropout Operation: 100% Duty Cycle
■
Current Mode Operation for Excellent Line and
Load Transient Response
■
Defeatable Burst Mode
TM
Operation
■
Short-Circuit Protected
■
Optional Programmable Soft-Start
■
Micropower Shutdown: I
Q
= 2µA
The LTC
®
1771 is a high efficiency current mode step-
down DC/DC controller that draws as little as 10µA DC
supply current to regulate the output at no load while
maintaining high efficiency for loads up to several amps.
The LTC1771 drives an external P-channel power MOSFET
using a current mode, constant off-time architecture. An
external sense resistor is used to program the operating
current level. Current mode control provides short-circuit
protection, excellent transient response and controlled
start-up behavior. Burst Mode operation enables the
LTC1771 to maintain high efficiency down to extremely
low currents. Shutdown mode further reduces the supply
current to a mere 2µA. For low noise applications, Burst
Mode operation can be easily disabled with the MODE pin.
Wide input supply range of 2.8V to 18V (20V maximum)
and 100% duty cycle operation for low dropout make the
LTC1771 ideal for a wide variety of battery-powered appli-
cations where maximizing battery life is important.
The LTC1771’s availability in both 8-lead MSOP and SO
packages provides for a minimum area solution.
■
Cellular Telephones and Wireless Modems
■
1- to 4-Cell Lithium-Ion-Powered Applications
■
Portable Instruments
■
Battery-Powered Equipment
■
Battery Chargers
■
Scanners
Figure 1. High Efficiency Step-Down Converter
10µA Quiescent Current
High Efficiency Step-Down
DC/DC Controller
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
RUN/SS
I
TH
V
FB
V
IN
V
IN
V
IN
4.5V TO 18V
R
C
10k
R
SENSE
0.05Ω
R2
1.64M
1%
R1
1M
1%
M1
Si6447DQ
UPS5817
L1
15µH
C
C
22OpF
C
FF
5pF
22µF
25V
C
OUT
150µF
6.3V
V
OUT
3.3V
2A
1771 F01
C
SS
0.01µF
PGATE
MODE
LTC1771
GND
SENSE
+
+
LTC1771 Efficiency
LOAD CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
400.1 1 100 1000 10000
1771 F01b
10
V
IN
= 5V
V
IN
= 10V
V
IN
= 15V
V
OUT
= 3.3V
R
SENSE
= 0.05Ω
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1771
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 10V, VRUN = open unless otherwise specified.
LTC1771EMS8
T
JMAX
= 125°C, θ
JA
= 200°C/W
ORDER PART
NUMBER
Input Supply Voltage (V
IN
)........................ –0.3V to 20V
Peak Driver Output Current < 10µs (PGATE) ............. 1A
RUN/SS Voltage ......................... –0.3V to (V
IN
+ 0.3V)*
MODE Voltage .......................................... –0.3V to 20V
I
TH
, V
FB
Voltage .......................................... –0.3V to 5V
SENSE Voltage (V
IN
> 12V)..(V
IN
– 12V) to (V
IN
+ 0.3V)*
SENSE Voltage (V
IN
≤ 12V) ........ –0.3V to (V
IN
+ 0.3V)*
(Note 1)
Consult factory for Military grade parts.
Junction Temperature (Note 2)............................ 125°C
Operating Temperature Range (Note 3)
LTC1771E......................................... –40°C to 85°C
LTC1771I ......................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
LTC1771ES8
LTC1771IS8
ORDER PART
NUMBER
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
TOP VIEW
MODE
SENSE
V
IN
PGATE
RUN/SS
I
TH
V
FB
GND
S8 PACKAGE
8-LEAD PLASTIC SO
1
2
3
4
8
7
6
5
T
JMAX
= 125°C, θ
JA
= 110°C/W
S8 PART MARKING
1771
1771I
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
FB
Feedback Voltage (Note 5) ●1.205 1.230 1.255 V
I
FB
Feedback Current (Note 5) ●110 nA
I
SUPPLY
No-Load Supply Current V
IN
= 10V, I
LOAD
= 0 (Note 6) 10 µA
∆V
LINEREG
Reference Voltage Line Regulation V
IN
= 5V to 15V (Note 5) ●0.003 0.03 %/V
∆V
LOADREG
Output Voltage Load Regulation I
TH
= 0.5V to 2V, Burst Disabled (Note 5) ●0.25 1 %
I
Q
Input DC Supply Current (Note 4)
Active Mode (PGATE = 0V) V
IN
= 2.8V to 18V 150 235 µA
Sleep Mode (Note 6) V
IN
= 2.8V to 18V, V
FB
= 1.5V 9 15 µA
Shutdown V
IN
= 2.8V to 18V, V
RUN
= 0V 2 6 µA
Short Circuit V
IN
= 2.8V to 18V, V
FB
= 0V 175 275 µA
∆V
SENSE(MAX)
Maximum Current Sense Threshold V
FB
= V
REF
– 20mV ●110 140 180 mV
∆V
SENSE(MIN)
Minimum Current Sense Threshold V
FB
= V
REF
+ 20mV, Burst Disabled –25 mV
∆V
SENSE(SLEEP)
Sleep Current Sense Threshold I
TH
= 1V 50 mV
t
OFF
Switch Off Time V
FB
at Regulated Value 3 3.5 4 µs
V
FB
= 0V 70 µs
V
MODE
Mode Pin Threshold V
MODE
Rising ●0.5 1.3 2 V
LTKD
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
*RUN/SS and SENSE cannot exceed 20V.
3
LTC1771
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC1771S8: T
J
= T
A
+ (P
D
)(110°C/W)
LTC1771MS8: T
J
= T
A
+ (P
D
)(150°C/W)
Note 3: The LTC1771E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC1771I is guaranteed and tested
over the –40°C to 85°C operating temperature range.
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 10V, VRUN = open unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
RUN/SS
RUN/SS Pin Threshold V
RUN/SS
Rising ●0.5 1.0 2 V
I
RUN
Source Current V
RUN
= 0V, V
IN
= 2.8V to 18V 0.3 1 3 µA
PGATE t
r
, t
f
PGATE Transition Time (Note 7)
Rise Time C
LOAD
= 2000pF 70 140 ns
Fall Time C
LOAD
= 2000pF 70 140 ns
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: The LTC1771 is tested in a feedback loop that servos V
FB
to the
balance point for the error amplifier (V
ITH
= 1.23V).
Note 6: No-load supply current consists of sleep mode current (9µA
typical) plus a small switching component necessary to overcome
Schottky diode leakage and feedback resistor current.
Note 7: t
r
and t
f
are measured at 10% to 90% levels.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs Input Voltage
INPUT VOLTAGE (V)
2
60
EFFICIENCY (%)
70
80
90
100
46810
1771 G01
12 14 16 18 20
I
LOAD
= 50mA
I
LOAD
= 1mA
FIGURE 1 CIRCUIT
I
LOAD
= 1A
LOAD CURRENT (mA)
0.1
40
EFFICIENCY (%)
50
60
70
80
1 10 1000100
1771 G02
30
20
10
0
90
100 Burst Mode OPERATION
ENABLED
Burst Mode OPERATION
DISABLED
V
IN
= 10V
FIGURE 1 CIRCUIT
INPUT VOLTAGE (V)
0
∆V
OUT
(%)
0
0.1
0.2
20
1771 G03
–0.1
–0.2
–0.4 510 15
–0.3
0.4
0.3
I
LOAD
= 100mA
I
LOAD
= 1A
FIGURE 1 CIRCUIT
Efficiency vs Load Current Line Regulation
4
LTC1771
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Load Regulation Active Mode Quiescent Current
vs Input Voltage Sleep Quiescent Current
vs Input Voltage
LOAD CURRENT (A)
0
–0.2
0V
IN
= 15V
V
IN
= 5V
0.4
1.5
1771 G04
–0.4
–0.6
0.5 1.0 2.0
–0.8
–1.0
0.2
∆V
OUT
(%)
Burst Mode OPERATION
DISABLED
Burst Mode
OPERATION
ENABLED
FIGURE 1 CIRCUIT
INPUT VOLTAGE (V)
0
ACTIVE MODE QUIESCENT CURRENT (µA)
100
150
16
1771 G05
50
04810 20
200
12
2618
14
T
A
= –50°C
T
A
= 100°C
T
A
= 25°C
INPUT VOLTAGE (V)
0
SLEEP QUIESCENT CURRENT (µA)
4
8
12
2
6
10
4 8 12 16
1771 G06
2020 6 10 14 18
T
A
= –50°C
T
A
= 25°C
T
A
= 100°C
Shutdown Quiescent Current
vs Input Voltage Run/SS Current vs Input Voltage Current Sense Voltage
vs Temperature
INPUT VOLTAGE (V)
0
SHUTDOWN QUIESCENT CURRENT (µA)
4
6
16
1771 G07
2
04810 20
8
12
2618
14
T
A
= –50°C
T
A
= 100°C
T
A
= 25°C
INPUT VOLTAGE (V)
0
SOFT-START CURRENT (µA)
3
4
5
16
1771 G08
2
1
04812
218
610 14 20
T
A
= –50°C
T
A
= 25°C
T
A
= 100°C
TEMPERATURE (°C)
–50
–50
CURRENT SENSE VOLTAGE (mV)
0
50
100
150
200
–25 02550
1771 G09
75 100
V
IN
= 10V
MAXIMUM
MINIMUM
BURST THRESHOLD
Reference Voltage
vs Temperature
TEMPERATURE (°C)
–50
1.21
REFERENCE VOLTAGE (V)
1.22
1.23
1.24
1.25
–25 0 25 50
1771 G10
75 100
V
IN
= 10V
Load Step Transient Response
V
OUT
100mV/DIV
INDUCTOR
CURRENT
1A/DIV
V
IN
= 10V 50µs/DIV 1771 G11
V
OUT
= 3.3V
I
LOAD
= 100mA TO 2A
FIGURE 1 CIRCUIT
Burst Mode Operation
V
OUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
V
IN
= 10V 10µs/DIV 1771 G12
V
OUT
= 3.3V
I
LOAD
= 100mA
FIGURE 1 CIRCUIT
5
LTC1771
–
+
EA
–
+
C
ON
ON
+
C
SS
RUN/SS
V
IN
V
OUT
V
IN
1
MODE
MODE
READY
SLEEP
READY
250k
22k R
SENSE
1.23V
1V
1V
2V
1µA
(BURST ENABLE)
10% CURRENT
10% CURRENT
SOFT-START
8
V
IN
V
IN
V
OUT
L
C
IN
+
C
OUT
R2
D1
R1
6
SENSE
7
PGATE
3.5µs
1771 BD
5
V
FB
3
I
TH
R
C
C
C
*
*
OPTIONAL FOR FOLDBACK
CURRENT LIMITING
2
GND
4+
–B
ON TRIGGER
1.23V
REFERENCE
BLANKING
1-SHOT
STRETCH
FUNCTIONAL BLOCK DIAGRA
UU
W
RUN/SS (Pin 1): The voltage level on this pin controls
shutdown/run mode (ground = shutdown, open/high =
run). Connecting an external capacitor to this pin provides
soft-start.
I
TH
(Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 3V.
V
FB
(Pin 3): Feedback of Output Voltage for Comparison
to Internal 1.23V Reference. An external resistive divider
across the output is returned to this pin.
GND (Pin 4): Ground Pin.
PGATE (Pin 5): High Current Gate Driver for External
P-Channel MOSFET Switch. Voltage swing is from ground
to V
IN
.
V
IN
(Pin 6): Main Input Voltage Supply Pin.
SENSE (Pin 7): Current Sense Input for Monitoring Switch
Current. Maximum switch current and Burst Mode
threshold is programmed with an external resistor be-
tween SENSE and V
IN
.
MODE (Pin 8): Burst Mode Enable/Disable Pin. Connect-
ing this pin to V
IN
(or above 2V) enables Burst Mode
operation, while connecting this pin to ground disables
Burst Mode operation. Do not leave floating.
UU
U
PI FU CTIO S
6
LTC1771
(Refer to Functional Block Diagram)
Main Control Loop
The LTC1771 uses a constant off-time, current mode
step-down architecture. During normal operation, the
P-channel MOSFET is turned on at the beginning of each
cycle and turned off when the current comparator C
triggers the 1-shot timer. The external MOSFET switch
stays off for the 3.5µs 1-shot duration and then turns back
on again to begin a new cycle. The peak inductor current
at which C triggers the 1-shot is controlled by the voltage
on Pin 3 (I
TH
), the output of the error amplifier EA. An
external resistive divider connected between V
OUT
and
ground allows EA to receive an output feedback voltage
V
FB
. When the load current increases, it causes a slight
decrease in V
FB
relative to the 1.23V reference, which in
turn causes the I
TH
voltage to increase until the average
inductor current matches the new load current.
The main control loop is shut down by pulling Pin 1
(RUN/SS) low. Releasing RUN/SS allows an internal 1µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1V, the main control loop is enabled with the
I
TH
voltage clamped at approximately 40% of its maxi-
mum value. As C
SS
continues to charge, I
TH
is gradually
released allowing normal operation to resume.
Burst Mode Operation
The LTC1771 provides outstanding low current efficiency
and ultralow no-load supply current by using Burst Mode
operation when the MODE pin is pulled above 2V. During
Burst Mode operation, short burst cycles of normal switch-
ing are followed by a longer idle period with the switch off
and the load current is supplied by the output capacitor.
During this idle period, only the minimum required cir-
cuitry—1.23V reference and error amp—are left on, and
the supply current is reduced to 9µA. At no load, the output
capacitor is still discharged very slowly by leakage current
in the Schottky diode and feedback resistor current result-
ing in very low frequency burst cycles that add a few more
microamps to the supply current.
Burst Mode operation is provided by clamping the mini-
mum I
TH
voltage at 1V which represents about 25% of
maximum load current. If the load falls below this level, i.e.
the I
TH
voltage tries to fall below 1V, the burst comparator
B switches state signaling the LTC1771 to enter sleep
mode. During this time, EA is reduced to 10% of its normal
operating current and the external compensation capaci-
tor is disconnected and clamped to 1V so that the EA can
drive its output with the lower available current. As the load
discharges the output capacitor, the internal I
TH
voltage
increases. When it exceeds 1V the burst comparator exits
sleep mode, reconnects the external compensation com-
ponents to the error amplifier output, and returns EA to full
power along with the other necessary circuitry. This
scheme (patent pending) allows the EA to be reduced to
such a low operating current during sleep mode without
adding unacceptable delay to wake up the LTC1771 due to
the compensation capacitor on I
TH
required for stability in
normal operation.
Burst Mode operation can be disabled by pulling the
MODE pin to ground. In this mode of operation, the burst
comparator B is disabled and the I
TH
voltage allowed to go
all the way to 0V. The load can now be reduced to about 1%
of maximum load before the loop skips cycles to maintain
regulation. This mode provides a low noise output spec-
trum, useful for reducing both audio and RF interference,
at the expense of reduced efficiency at light loads.
Off-Time
The off-time duration is 3.5µs when the feedback voltage
is close to the reference voltage; however, as the feedback
voltage drops, the off-time lengthens and reaches a maxi-
mum value of about 70µs when V
FB
is zero. This ensures
that the inductor current has enough time to decay when
the reverse voltage across the inductor is low such as
during short circuit, thus protecting the MOSFET and
inductor.
OPERATIO
U
7
LTC1771
The basic LTC1771 application circuit is shown in Figure
1 on the first page. External component selection is driven
by the load requirement and begins with the selection of
R
SENSE
. Once R
SENSE
is known, L can be chosen. Next, the
MOSFET and D1 are selected. The inductor is chosen
based largely on the desired amount of ripple current and
for Burst Mode operation. Finally C
IN
is selected for its
ability to handle the required RMS input current and C
OUT
is chosen with low enough ESR to meet the output voltage
ripple and transient specifications.
R
SENSE
Selection
R
SENSE
is chosen based on the required output current.
The LTC1771 current comparator has a maximum thresh-
old of 140mV/R
SENSE
. The current comparator threshold
sets the peak inductor current, yielding a maximum aver-
age output current I
MAX
equal to the peak less half the
peak-to-peak ripple current ∆I
L
. For best performance
when Burst Mode operation is enabled, choose ∆I
L
equal
to 35% of peak current. Allowing a margin for variations in
the LTC1771 and external components gives the following
equation for choosing R
SENSE
:
R
SENSE
= 100mV/I
MAX
At higher supply voltages, the peak currents may be
slightly higher due to overshoot from current comparator
delay and can be predicted from the second term in the
following equation:
IR
VV
LH
PEAK SENSE
IN OUT
≅+ µ
014 05
12
..–
()
/
Inductor Value Selection
Once R
SENSE
is known, the inductor value can be deter-
mined. The inductance value has a direct effect on ripple
current. The ripple current decreases with higher induc-
tance and increases with higher V
OUT
. The ripple current
during continuous mode operation is set by the off-time
and inductance to be:
∆= +
It
VV
L
L CONT OFF OUT D
()
where t
OFF
= 3.5µs. However, the ripple current at low
loads during Burst Mode operation is:
∆I
L(BURST)
≈ 35% of I
PEAK
≈ 0.05/R
SENSE
For best efficiency when Burst Mode operation is enabled,
choose:
∆I
L(CONT)
≤ ∆I
L(BURST)
so that the inductor current is continuous during the burst
periods. This sets a minimum inductor value of:
L
MIN
= (75µH)(V
OUT
+ V
D
)(R
SENSE
)
When burst is disabled, ripple currents less than ∆I
L(BURST)
can be achieved by choosing L > L
MIN
. Lower ripple
current reduces output voltage ripple and core losses, but
too low of ripple current will adversely effect efficiency.
Inductor Core Selection
Once the value of L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy or Kool Mµ
®
cores. Actual core loss is
independent of core size for a fixed inductor value, but is
very dependent on inductance selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent increase in voltage ripple.
Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are space efficient, especially
when you can use several layers of wire. Because they
generally lack a bobbin, mounting is more difficult. How-
ever, designs for surface mount are available that do not
increase the height significantly.
Kool Mµ is a registered trademark of Magnetics, Inc.
APPLICATIO S I FOR ATIO
WUUU
8
LTC1771
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1771. The main selection criteria for
the power MOSFET are the threshold voltage V
GS(TH)
and
the “on” resistance R
DS(ON)
, reverse transfer capacitance
and total gate charge.
Since the LTC1771 can operate down to input voltages as
low as 2.8V, a sublogic level threshold MOSFET (R
DS(ON)
guaranteed at V
GS
= 2.5V) is required for applications that
work close to this voltage. When these MOSFETs are used,
make sure that the input supply to the LTC1771 is less than
the absolute maximum V
GS
rating (typically 12V), as the
MOSFET gate will see the full supply voltage.
The required R
DS(ON)
of the MOSFET is governed by its
allowable power dissipation. For applications that may
operate the LTC1771 in dropout, i.e. 100% duty cycle, at
its worst case the required R
DS(ON)
is given by:
RP
I
DS ON P
OUT MAX P
()
()
=
()
+
()
2
1δ
where P
P
is the allowable power dissipation and δ
P
is the
temperature dependency of R
DS(ON)
. (1 + δ
P
) is generally
given for a MOSFET in the form of a normalized R
DS(ON)
vs
temperature curve, but = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC1771 is in continuous mode, the R
DS(ON)
is governed by:
RP
DC I
DC VV
VV
DS ON P
OUT P
OUT D
IN D
()
=
()
+
()
=+
+
2
1δ
where DC is the maximum operating duty cycle of the
LTC1771.
Catch Diode Selection
The catch diode carries load current during the off-time.
The average diode current is therefore dependent on the
P-channel switch duty cycle. At high input voltages the
diode conducts most of the time. As V
IN
approaches V
OUT
the diode conducts only a small fraction of the time. The
most stressful condition for the diode is when the output
is short-circuited. Under this condition, the diode must
safely handle I
PEAK
at close to 100% duty cycle.
To maximize both low and high current efficiencies, a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage current is
critical to maximize low current efficiency since the leak-
age can potentially exceed the magnitude of the LTC1771
supply current. Low forward drop is critical for high
current efficiency since loss is proportional to forward
drop. The effect of reverse leakage and forward drop on
no- load supply current and efficiency for various Schottky
diodes is shown in Table 1. As can be seen, these are
conflicting parameters and the user must weigh the
importance of each spec in choosing the best diode for the
application.
Table 1. Effect of Catch Diode on Performance
LEAKAGE NO-LOAD EFFICIENCY
DIODE (V
R
= 3.3V) V
F
@ 1A SUPPLY CURRENT AT 10V/1A
MBR0540 0.25µA 0.50V 10.4µA 86.3%
UPS5817 2.8µA 0.41V 11.8µA 88.2%
MBR0520 3.7µA 0.36V 12.2µA 88.4%
MBRS120T3 4.4µA 0.43V 12.2µA 87.9%
MBRM120LT3 8.3µA 0.32V 14.0µA 89.4%
MBRS320 19.7µA 0.29V 20.0µA 89.8%
C
IN
and C
OUT
Selection
At higher load currents, when the inductor current is
continuous, the source current of the P-channel MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
capacitor current is given by:
CIVVV
V
IN MAX OUT IN OUT
IN
required IRMS =−
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
APPLICATIO S I FOR ATIO
WUUU
9
LTC1771
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Do not underspecify this component. An addi-
tional 0.1µF ceramic capacitor is also helpful on V
IN
for
high frequency decoupling.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple (∆V
OUT
) in continuous mode is approxi-
mated by:
∆≈ +
V I ESR fC
OUT RIPPLE OUT
1
8
where f is the operating frequency, C
OUT
is the output
capacitance and I
RIPPLE
is the ripple current in the
inductor. For output ripple less than 100mV, assure C
OUT
required ESR is <2R
SENSE
.
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The I
TH
pin OPTI-LOOP
TM
compensation compo-
nents can be optimized to provide stable, high perfor-
mance transient response regardless of the output
capacitors selected.
When running into dropout, extra input and output capaci-
tance may be necessary for optimal performance due to
the drop in frequency as the duty cycle approaches 100%.
Compare Figure 1 to the low dropout regulators shown in
the Typical Applications section for recommended C
IN
,
C
OUT
, C
FF
and C
C
values for low dropout regulators vs
regulators not requiring low dropout.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest ESR for its
size of any aluminum electrolytic at a somewhat higher
price. Typically once the ESR requirement is satisfied, the
RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytics and dry tantalum capacitors are both available
in surface mount configurations. In case of tantalum, it is
critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the
AVX TPS, AVX TPSV and KEMET T510 series of surface
mount tantalums, available in case heights ranging from
2mm to 4mm. Other capacitor types include Sanyo
OS-CON, Sanyo POSCAP, Nichicon PL series and
Panasonic SP.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 +L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in the LTC1771 circuits: the LTC1771 DC bias
current, MOSFET gate charge current, I
2
R losses and
catch diode losses.
1. The DC bias current is 9µA at no load and increases
proportionally with load up to a constant 150µA during
continuous mode. This bias current is so small that this
loss is negligible at loads above a milliamp but at no
load accounts for nearly all of the loss.
2. The MOSFET gate charge current results from switch-
ing the gate capacitance of the power MOSFET switch.
Each time the gate is switched from high to low to high
again, a packet of charge dQ moves from V
IN
to ground.
The resulting dQ/dt is the current out of V
IN
which is
typically much larger than the DC bias current. In
OPTI-LOOP is a trademark of Linear Technology Corporation.
APPLICATIO S I FOR ATIO
WUUU
10
LTC1771
continuous mode, IGATECHG = fQP where QP is the gate
charge of the internal switch. Both the DC bias and gate
charge losses are proportional to VIN and thus their
effects will be more pronounced at higher supply
voltages.
3. I
2
R losses are predicted from the internal switch, induc-
tor and current sense resistor. In continuous mode the
average output current flows through L but is “chopped”
between the P-channel MOSFET in series with R
SENSE
and the output diode. The MOSFET R
DS(ON)
plus R
SENSE
multiplied by the duty cycle can be summed with the
resistance of L to obtain I
2
R losses.
4. The catch diode loss is proportional to the forward drop
as the diode conducts current during the off-time and is
more pronounced at high supply voltages where the
off-time is long. However, as discussed in the Catch
Diode section, diodes with lower forward drops often
have higher leakage currents, so although efficiency is
improved, the no-load supply current will increase. The
diode loss is calculated by multiplying the forward
voltage drop times the diode duty cycle multiplied by
the load current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
Output Voltage Programming
The output voltage is programmed with an external divider
from V
OUT
to V
FB
(Pin 1) as shown in Figure 2. The
regulated voltage is determined by:
VR
R
OUT =+
123 1 2
1
.
To minimize no-load supply current, resistor values in the
megohm range should be used. The increase in supply
current due to the feedback resistors can be calculated
from:
∆=
+
IV
RR
V
V
OUT OUT
IN
VIN
12
A 5pF feedforward capacitor across R2 is recommended
to minimize output voltage ripple in Burst Mode operation.
Run/Soft-Start Function
The RUN/SS pin is a dual purpose pin that provides the
soft- start function and a means to shut down the LTC1771.
Soft-start reduces the input surge current from V
IN
by
gradually increasing the internal current limit. Power
supply sequencing can also be accomplished using
this pin.
An internal 1µA current source charges up an external
capacitor C
SS
. When the voltage on the RUN/SS reaches
1V, the LTC1771 begins operating. As the voltage on the
RUN/SS continues to ramp from 1V to 2.2V, the internal
current limit is also ramped at a proportional linear rate.
The current limits begins near 40% maximum load at
V
RUN/SS
= 1V and ends at maximum load at V
RUN/SS
=
2.2V. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If the RUN/SS has been pulled all the way to
ground, there will be a delay before the current limit starts
increasing and is given by:
t
DELAY
≈ C
SS
/I
CHG
where ICHG ≅ 1µA. Pulling the RUN/SS pin below 0.5V
puts the LTC1771 into a low quiescent current shutdown
(IQ < 2µA).
Foldback Current Limiting
As described in the Catch Diode Selection, the worst-case
dissipation for diode occurs with a short-circuit output,
when the diode conducts the current limit value almost
continuously. In most applications this will not cause
excessive heating, even for extended fault intervals. How-
ever, when heat sinking is at a premium or higher forward
voltage drop diodes are being used, foldback current
V
FB
R2 C
FF
5pF
R1
V
OUT
1771 F02
LTC1771
GND
Figure 2. LTC1771 Adjustable Configuaration
APPLICATIO S I FOR ATIO
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11
LTC1771
limiting should be added to reduce the current in propor-
tion to the severity of the fault.
Foldback current limiting is implemented by adding two
diodes in series between the output and the I
TH
pin as
shown in the Functional Diagram. In a hard short (V
OUT
=
0V) the current will be reduced to approximately 25% of
the maximum output current.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1771 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
ttVV
VV t
ON OFF OUT D
IN OUT ON MIN
=+
−
>
()
where t
OFF
= 3.5µs and t
ON(MIN)
is generally about 0.4µs
for the LTC1771.
As the on-time approaches t
ON(MIN)
, the LTC1771 will
remain in Burst Mode operation for an increasingly larger
portion of the load range (see Figure 3) and at or below
t
ON(MIN)
will remain in Burst Mode operation 100% of the
time. The output voltage will continue to be regulated, but
the ripple current and ripple voltage will increase.
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
low noise output spectrum, useful for reducing both audio
and RF interference. It does this by keeping the frequency
constant (for fixed V
IN
) down to much lower load current
(1% to 2% of I
MAX
) and reducing the amount of output
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175µA.
Low Supply Operation
Although the LTC1771 can function down to 2.8V, the
maximum allowable output current is reduced when V
IN
decreases below 3.2V. Figure 4 shows the amount of
change as the supply is reduced below 3.2V, where 100%
of maximum load equals 0.1/R
SENSE
. To ensure adequate
output current at V
IN
< 3.2V, simply lower R
SENSE
by the
same percentage as the current reduction in Figure 4.
APPLICATIO S I FOR ATIO
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ON-TIME (µs)
0
% OF MAXIMUM LOAD
60
80
100
2.0
1771 F03
40
20
00.5 1.0 1.5 2.5
Figure 3. Burst Threshold vs On-Time
INPUT VOLTAGE (V)
2.5
100
120
140
4.0 4.5
1771 F04
80
60
3.0 3.5 5.0
40
20
0
MAXIMUM LOAD (%)
Figure 4. Maximum Load vs Input Voltage
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout:
1. Is the Schottky diode
closely
connected to the drain of
the external MOSFET and the input cap ground?
12
LTC1771
2. Is the 0.1µF input decoupling capacitor
closely
con-
nected between V
IN
(Pin 6) and ground (Pin 4)? This
capacitor carries the high frequency peak currents.
3. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
OUT
and signal
ground. Locate the feedback resistors right next to the
LTC1771. The V
FB
line should not be routed close to any
nodes with high slew rates.
4. Is the 1000pF decoupling capacitor for the current
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
5. Is the (+) plate of C
IN
closely
connected to the sense
resistor ? This capacitor provides the AC current to the
MOSFET.
6. Are the signal and power grounds segregated? The
signal ground consists of the (–) plate of C
OUT
, Pin 4 of
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of C
IN
which should have as short lead lengths as
possible.
7. Keep the switching node (SW) and the gate node
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (V
FB
), and mini-
mize their PC trace area.
Design Example
As a design example, assume V
IN
= 10V (nominal), V
IN
=
15V
(MAX)
, V
OUT
= 3.3V, and I
MAX
= 2A. With this informa-
tion, we can easily calculate all the important components.
R
SENSE
= 100mV/2A = 0.05Ω
To optimize low current efficiency, MODE pin is tied to V
IN
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
L
MIN
= 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH
15µH is chosen for the application.
∆= +
=Is
VV
HA
L
35 33 05
15 089... .µµ
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
R2 = (V
OUT
/1.23 – 1) • R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
P
P
= 0.25W.
If T
A
= 70°C and the thermal resistance of the MOSFET is
83°C/W, then the junction temperatures will be 91°C and
δ
P
= 0.33. The required R
DS(ON)
for the MOSFET can now
be calculated:
PW
VV
VV
A
-Channel R
DS(ON)
=+
+
()( )
=
025
33 05
10 0 5 2133
0 130
2
.
..
..
.Ω
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose V
GS(MAX)
> 15V. A
P-channel MOSFET that meets both the V
GS(MAX)
and
R
DS(ON)
requirement is the Si6447DQ.
The most stringent requirement for the Schottky diode
occurs when V
OUT
= 0V (i.e., short circuit) at maximum
V
IN
. In this case the worst-case dissipation rises to:
PI V V
VV
SC AVG D IN
IN D
D
=
()
+
()
Figure 5. LTC1771 Layout Diagram
APPLICATIO S I FOR ATIO
WUUU
RUN/SS
I
TH
V
FB
GND
V
OUT
R
ITH
C
ITH
C
FF
0.1µF
Q1
D1
R2
R1
1
2
3
4
8
7
6
5
1771 F05
C
SS
C
IN
MODE
MODE
SENSE
V
IN
PGATE
LTC1771
BOLD LINES INDICATE HIGH CURRENT PATHS
+
C
OUT
L
+
13
LTC1771
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
LTC1771 1000pF
Si3443DV
D1
1771 TA01
L1
22µH
R
SENSE
0.1ΩC
IN
33µF
16V
V
IN
3.3V
TO 12V
V
OUT
2.5V
1A
+
0.01µF
5pF
220pF 10k
1.02M
1%
C
IN
: AVX TPSC336M016R0300
C
OUT
: SANYO POSCAP 6TPB150M
D1: MICROSEMI UPS5817
L1: SUMIDA CDRH6D38-220
1M
1%
C
OUT
150µF
6.3V
+
3.3V to 2.5V/1A Regulator with Burst Mode Operation Enabled
Low Dropout 5V/2A Regulator with Burst Mode Operation Disabled
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
LTC1771 1000pF
Si6447DQ
D1
1771 TA04
L1
22µH
R
SENSE
0.05ΩC
IN
22µF
25V
×2
V
IN
5.5V
TO 18V
V
OUT
5V
2A
+
0.01µF
15pF
330pF 10k
3.09M
1%
1M
1%
C
OUT
150µF
6.3V
+
C
IN
: AVX TPSD226M025R0200
C
OUT
: SANYO POSCAP 6TPB150M
D1: MICROSEMI UPS5817
L1: SUMIDA CR75-220
TYPICAL APPLICATIO S
U
APPLICATIO S I FOR ATIO
WUUU
With a 0.05Ω sense resistor I
SC(AVG)
= 2A will result,
increasing the 0.5V Schottky diode dissipation to 1W.
C
IN
is chosen for a RMS current rating of at least 1A at
temperature. C
OUT
is chosen with an ESR of 0.05Ω for low
output ripple. The output voltage ripple due to ESR is
approximately:
V
ORIPPLE
≈ (R
ESR
)(∆I
L
) = 0.05Ω (0.89A
P-P
) = 45mV
P-P
14
LTC1771
Low Dropout Single Cell Lithium-Ion to 3V
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
LTC1771 1000pF
MODE
Si3443DV
D1
1771 TA02
L1
15µH
R
SENSE
0.05ΩC
IN
47µF
10V
Li-Ion
3.4V TO 4.2V
V
OUT
3V
2A
+
0.01µF
15pF
330pF 10k
1.43M
1%
1M
1%
C
OUT
220µF
4V
+
C
IN
: TAIYO YUDEN LMK550BJ476MM
C
OUT
: SANYO POSCAP 4TPB220M
D1: MICROSEMI UPS5817
L1: SUMIDA CR75-150
12V/1A Zeta Converter
RUN/SS
ITH
VFB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
VIN
PGATE
LTC1771 1000pF
MODE
Si6459DQ
D1
1771 TA05
L1B
47µH
•
•
L1A
47µH
C1
33µF
20V
×2
RSENSE
0.025ΩCIN
22µF
25V
×2
VIN
5V
TO 18V
VOUT
12V
1A
+
+
0.01µF
5pF
220pF
VIN
10k
Q1
3.01M
1%
280k
1%
402k
1%
8.66M
1%
1M
1%
COUT
100µF
20V
+
VIN (V)
4.5
5
10
15
18
ILOAD(MAX) (A)
0.7
0.9
1.8
2.4
2.6
CIN: AVX TPSD226M025R0200
COUT: AVX TPSV107M020R0085
C1: AVX TPSD336M020R0200
D1: MOTOROLA MBRS140T3
L1A, L1B: COILTRONICS VP4-0075, B H ELECTRONICS Q10549
Q1: MOTOROLA MMBT2N2222LT1
TYPICAL APPLICATIO S
U
2.5V/1A Regulator with Foldback Current Limit
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
LTC1771 1000pF
MODE
1771 TA06
L1
22µH
I
TH
U1
1234
8
1N4148
×2
765
R
SENSE
0.1ΩC
IN
33µF
16V
V
IN
2.8V
TO 12V
V
OUT
2.5V
1A
+
0.01µF
5pF
220pF 10k
1.02M
1%
1M
1%
C
OUT
150µF
6.3V
+
C
IN
: AVX TPSC336M016R0300
C
OUT
: SANYO POSCAP 6TPB150M
L1: SUMIDA CDRH6D38-220
U1: INTERNATIONAL RECTIFIER
FETKY
TM
IRF7422D2
15
LTC1771
TYPICAL APPLICATIONS
U
4-NiCd/NiMH Battery Charger
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
LTC1771 1000pF
MODE
Si6447DQ
D1
D2
1771 TA07
L1
47µH
R
SENSE
0.1ΩC
IN
22µF
25V
V
IN
8V
TO 18V
V
OUT
4-NiCd
1A
+
0.01µF
5pF
220pF 10k
4.69M
1%
1M
1%
C
OUT
100µF
10V
+
C
IN
: AVX TPSD226M025R0200
C
OUT
: SANYO POSCAP 10TPB100M
D1, D2: MICROSEMI UPS5817
L1: COILTRONICS UP2B-470, GOWANDA SMP3316-472M
Dimension in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MSOP (MS8) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021 ± 0.006
(0.53 ± 0.015)
0° – 6° TYP
SEATING
PLANE
0.007
(0.18)
0.040 ± 0.006
(1.02 ± 0.15)
0.012
(0.30)
REF
0.006 ± 0.004
(0.15 ± 0.102)
0.034 ± 0.004
(0.86 ± 0.102)
0.0256
(0.65)
BSC 12
34
0.193 ± 0.006
(4.90 ± 0.15)
8765
0.118 ± 0.004*
(3.00 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
0.016 – 0.050
(0.406 – 1.270)
0.010 – 0.020
(0.254 – 0.508)× 45°
0°– 8° TYP
0.008 – 0.010
(0.203 – 0.254)
SO8 1298
0.053 – 0.069
(1.346 – 1.752)
0.014 – 0.019
(0.355 – 0.483)
TYP
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
1234
0.150 – 0.157**
(3.810 – 3.988)
8765
0.189 – 0.197*
(4.801 – 5.004)
0.228 – 0.244
(5.791 – 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
16
LTC1771
1771f LT/TP 1000 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
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IN
, MS8
LTC1624 High Efficiency SO-8 N-Channel Switching Regulator Controller 95% DC, 3.5V to 36V V
IN
LT®1761 Series 100mA, Low Noise, LDO Micropower Regulators in SOT-23 20µA Quiescent Current, 20µV
RMS
Noise
LT1763 Series 500mA, Low Noise, LDO Micropower Regulators 30µA Quiescent Current, 20µV
RMS
Noise
LTC1772 Constant Frequency Step-Down DC/DC Controller SOT-23, 2.2V to 9.8V V
IN
LTC1877 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, V
IN
Up to 10V, I
Q
= 10µA,
I
OUT
to 600mA
LTC1878 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, V
IN
Up to 6V, I
Q
= 10µA,
I
OUT
to 600mA
5V/1A Zeta Converter
RUN/SS
I
TH
V
FB
GND
1
2
3
4
8
7
6
5
MODE
SENSE
V
IN
PGATE
LTC1771 1000pF
MODE
Si3443DV
D1
1771 TA03
L1B
22µH
•
•
L1A
22µH
C1
100µF
10V
R
SENSE
0.025ΩC
IN
33µF
20V
×2
V
IN
2.8V
TO 12V
V
OUT
5V
1A
+
+
0.01µF
5pF
220pF 10k
3.09M
1%
1M
1%
C
OUT
100µF
10V
+
V
IN
(V)
2.8
3.3
5
7.5
10
12
I
LOAD(MAX)
(A)
0.8
1.1
1.7
2.3
2.7
2.9
C
IN
: AVX TPSD336M020R0200
C
OUT
: SANYO POSCAP 10TPB100M
C1: AVX TPSD107M010R065
D1: MICROSEMI UPS5817
L1A, L1B: COILTRONICS CTX10-4, BH ELECTRONICS S10-1013
TYPICAL APPLICATIO
U
