LTC3892/
LTC3892-1/LTC3892-2
1
38921fc
For more information www.linear.com/LTC3892
TYPICAL APPLICATION
FEATURES DESCRIPTION
60V Low IQ, Dual, 2-Phase
Synchronous Step-Down
DC/DC Controller
The LT C
®
3892/LTC3892-1/LTC3892-2 is a high perfor-
mance dual step-down DC/DC switching regulator control-
ler that drives all N-channel synchronous power MOSFET
stages. Power loss and noise are minimized by operating
the two controller output stages out-of-phase.
The gate drive voltage can be programmed from 5V to
10V to allow the use of logic or standard-level FETs and
to maximize efficiency. Internal switches in the top gate
drivers eliminate the need for external bootstrap diodes.
A wide 4.5V to 60V input supply range encompasses a wide
range of intermediate bus voltages and battery chemistries.
Output voltages up to 99% of VIN can be regulated. OPTI-
LOOP
®
compensation allows the transient response and
loop stability to be optimized over a wide range of output
capacitance and ESR values.
The 29μA no-load quiescent current extends operating run
time in battery powered systems. For a comparison of the
LTC3892 to the LTC3892-1 and LTC3892-2, see Table 1
in the Pin Functions section of this data sheet.
High Efficiency Dual 5V/12V Output Step-Down Converter
n Wide VIN Range: 4.5V to 60V (65V Abs Max)
n Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 99% • VIN
n Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
n No External Bootstrap Diodes Required
n Low Operating IQ: 29μA (One Channel On)
n Selectable Gate Drive UVLO Thresholds
n Out-of-Phase Operation Reduces Required Input
Capacitance and Power Supply Induced Noise
n Phase-Lockable Frequency: 75kHz to 850kHz
n Selectable Continuous, Pulse Skipping or Low Ripple
Burst Mode
®
Operation at Light Loads
n Selectable Current Limit (LTC3892/LTC3892-2)
n Very Low Dropout Operation: 99% Duty Cycle
n Power Good Output Voltage Monitors (LTC3892/LTC3892-2)
n Low Shutdown IQ: 3.6μA
n Small 32-Lead 5mm × 5mm QFN Package (LTC3892/
LTC3892-2) or TSSOP Package (LTC3892-1)
L, LT , LT C , LT M , Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are
registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194,
6177787, 6580258.
4.7µF
0.1µF
15µH
8mΩ
100pF
100k
7.15k
34.8k
150µF
0.1µF
0.1µF
5.6µH
5mΩ
7.5k
47µF
100pF
0.1µF
2.2nF
0.1µF
220µF
LTC3892
VIN
RUN2
INTV
CC
GND
SW2
BG2
TG2
BOOST2
SENSE2+
V
FB2
ITH2
TRACK/SS2
12V
SENSE2–
DRVUV
DRV
CC
RUN1
SW1
BG1
TG1
BOOST1
SENSE1+
V
FB1
ITH1
TRACK/SS1
SENSE1–
DRVSET
VPRG1
V
OUT2
5A
VIN
12.5V TO 60V
5V
V
OUT1
8A
3892 TA01
APPLICATIONS
n Automotive and Industrial Power Systems
n Distributed DC Power Systems
n High Voltage Battery Operated Systems
V
IN
= 12V
V
OUT
= 5V
Burst Mode OPERATION
GATE DRIVE
DRV
CC
=5V
DRV
CC
=6V
DRV
CC
=8V
DRV
CC
=10V
LOAD CURRENT (A)
0.01
0.1
1
10
88
89
90
91
92
93
94
95
96
EFFICIENCY (%)
Efficiency vs Output Current
3892 F01b
Efficiency vs Output Current
LTC3892/
LTC3892-1/LTC3892-2
2
38921fc
For more information www.linear.com/LTC3892
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN) ......................... –0.3V to 65V
Top Side Driver Voltages
(BOOST1, BOOST2) ............................... –0.3V to 76V
Switch Voltage (SW1, SW2) .......................... –5V to 70V
DRVCC, (BOOST1-SW1),
(BOOST2-SW2) .......................................–0.3V to 11V
BG1, BG2, TG1, TG2 ........................................... (Note 8)
RUN1, RUN2 Voltages ................................ –0.3V to 65V
SENSE1+, SENSE2+, SENSE1–
SENSE2– Voltages ................................. –0.3V to 65V
PLLIN/MODE, FREQ Voltages ...................... –0.3V to 6V
EXTVCC Voltage ......................................... –0.3V to 14V
ITH1, ITH2, VFB1, VFB2 Voltages ..................... –0.3V to 6V
DRVSET, DRVUV Voltages ........................... –0.3V to 6V
(Notes 1, 3)
PIN CONFIGURATION
TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 6V
PGOOD1, PGOOD2 Voltages
(LTC3892/LTC3892-2) ............................. –0.3V to 6V
VPRG1, ILIM Voltages
(LTC3892/LTC3892-2) ............................. –0.3V to 6V
Operating Junction Temperature Range (Note 2)
LTC3892E, LTC3892I,
LTC3892E-1, LTC3892I-1,
LTC3892E-2, LTC3892I-2 ................... –40°C to 125°C
LTC3892H,
LTC3892H-1, LTC3892H-2 ................. –40°C to 150°C
LTC3892MP, LTC3892MP-1,
LTC3892MP-2 .................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
LTC3892/LTC3892-2 LTC3892-1
32
33
GND
31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1FREQ
PLLIN/MODE
PGOOD1
PGOOD2
INTVCC
RUN1
RUN2
ILIM
BOOST1
BG1
VIN
EXTVCC
DRVCC
BG2
BOOST2
SW2
SENSE1–
SENSE1+
VFB1
ITH1
VPRG1
TRACK/SS1
TG1
SW1
SENSE2–
SENSE2+
VFB2
ITH2
DRVUV
DRVSET
TRACK/SS2
TG2
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE CONNECTED TO GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
FE PACKAGE
28-LEAD PLASTIC TSSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ITH1
VFB1
SENSE1+
SENSE1–
FREQ
PLLIN/MODE
INTVCC
RUN1
RUN2
SENSE2–
SENSE2+
VFB2
ITH2
DRVUV
TRACK/SS1
TG1
SW1
BOOST1
BG1
VIN
EXTVCC
DRVCC
BG2
BOOST2
SW2
TG2
TRACK/SS2
DRVSET
29
GND
TJMAX = 150°C, θJA = 30°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND
LTC3892/
LTC3892-1/LTC3892-2
3
38921fc
For more information www.linear.com/LTC3892
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3892EUH#PBF LTC3892EUH#TRPBF 3892 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3892IUH#PBF LTC3892IUH#TRPBF 3892 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3892HUH#PBF LTC3892HUH#TRPBF 3892 32-Lead (5mm × 5mm) Plastic QFN –40°C to 150°C
LTC3892MPUH#PBF LTC3892MPUH#TRPBF 3892 32-Lead (5mm × 5mm) Plastic QFN –55°C to 150°C
LTC3892EFE-1#PBF LTC3892EFE-1#TRPBF LTC3892FE-1 28-Lead Plastic TSSOP –40°C to 125°C
LTC3892IFE-1#PBF LTC3892IFE-1#TRPBF LTC3892FE-1 28-Lead Plastic TSSOP –40°C to 125°C
LTC3892HFE-1#PBF LTC3892HFE-1#TRPBF LTC3892FE-1 28-Lead Plastic TSSOP –40°C to 150°C
LTC3892MPFE-1#PBF LTC3892MPFE-1#TRPBF LTC3892FE-1 28-Lead Plastic TSSOP –55°C to 150°C
LTC3892EUH-2#PBF LTC3892EUH-2#TRPBF 38922 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3892IUH-2#PBF LTC3892IUH-2#TRPBF 38922 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3892HUH-2#PBF LTC3892HUH-2#TRPBF 38922 32-Lead (5mm × 5mm) Plastic QFN –40°C to 150°C
LTC3892MPUH-2#PBF LTC3892MPUH-2#TRPBF 38922 32-Lead (5mm × 5mm) Plastic QFN –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC3892#orderinfo
LTC3892/
LTC3892-1/LTC3892-2
4
38921fc
For more information www.linear.com/LTC3892
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG1 = FLOAT unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range 4.5 60 V
VFB1 Channel 1 Regulated Feedback
Voltage
(Note 4) ITH1 Voltage = 1.2V
0°C to 85°C, VPRG1 = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
VPRG1 = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
VPRG1 = 0V (LTC3892/LTC3892-2)
VPRG1 = INTVCC (LTC3892/LTC3892-2)
l
l
l
0.792
0.788
3.234
4.890
0.800
0.800
3.3
5.0
0.808
0.812
3.366
5.110
V
V
V
V
VFB2 Channel 2 Regulated Feedback
Voltage
(Note 4) ITH2 Voltage = 1.2V
0°C to 85°C
l
0.792
0.788
0.800
0.800
0.808
0.812
V
V
IFB2 Channel 2 Feedback Current (Note 4) –2 ±50 nA
IFB1 Channel 1 Feedback Current (Note 4)
VPRG1 = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
VPRG1 = 0V (LTC3892/LTC3892-2)
VPRG1 = INTVCC (LTC3892/LTC3892-2)
–0.002
4
4
±0.05
6
6
µA
µA
µA
VREFLNREG Reference Voltage Line Regulation (Note 4) VIN = 4.5V to 60V 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l0.01 0.1 %
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 2V
l–0.01 –0.1 %
gm1,2 Transconductance Amplifier gm(Note 4) ITH1,2 = 1.2V, Sink/Source 5µA 2 mmho
IQInput DC Supply Current (Note 5) VDRVSET = 0V
Pulse-Skipping or Forced Continuous
Mode (One Channel On)
RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V,
VFB1,2 = 0.83V (No Load)
1.6 mA
Pulse-Skipping or Forced Continuous
Mode (Both Channels On)
RUN1,2 = 5V, VFB1,2 = 0.83V (No Load) 2.8 mA
Sleep Mode (One Channel On) RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V,
VFB1,2 = 0.83V (No Load)
l29 55 µA
Sleep Mode (Both Channels On) RUN1,2 = 5V, VFB1,2 = 0.83V (No Load) 34 55 µA
Shutdown RUN1,2 = 0V 3.6 10 µA
UVLO Undervoltage Lockout DRVCC Ramping Up
DRVUV = 0V
DRVUV = INTVCC
l
l
4.0
7.5
4.2
7.8
V
V
DRVCC Ramping Down
DRVUV = 0V
DRVUV = INTVCC
l
l
3.6
6.4
3.8
6.7
4.0
7.0
V
V
VOVL1,2 Feedback Overvoltage Protection Measured at VFB1,2 Relative to Regulated VFB1,2
(LTC3892/LTC3892-1)
7 10 13 %
ISENSE1,2+ SENSE+ Pin Current ±1 µA
ISENSE1,2– SENSE– Pins Current VOUT1,2 < VINTVCC – 0.5V
VOUT1,2 > VINTVCC + 0.5V
700
±1 µA
µA
DFMAX(TG) Maximum Duty Factor for TG In Dropout, FREQ = 0V 97.5 99 %
ITRACK/SS1,2 Soft-Start Charge Current VTRACK/SS1,2 = 0V 8 10 12 µA
LTC3892/
LTC3892-1/LTC3892-2
5
38921fc
For more information www.linear.com/LTC3892
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG1 = FLOAT unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VRUN1,2 ON RUN Pin On Threshold VRUN1, VRUN2 Rising l1.22 1.275 1.33 V
VRUN1,2 Hyst RUN Pin Hysteresis 75 mV
VSENSE(MAX) Maximum Current Sense Threshold VFB1,2 = 0.7V, VSENSE1,2– = 3.3V
ILIM = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
ILIM = 0V (LTC3892/LTC3892-2)
ILIM = INTVCC (LTC3892/LTC3892-2)
l
l
l
66
43
90
75
50
100
84
58
109
mV
mV
mV
VSENSE(MATCH)Matching Between VSENSE1(MAX) and
VSENSE2(MAX)
VFB1,2 = 0.7V, VSENSE1,2– = 3.3V
ILIM = FLOAT (LTC3892/LTC3892-2) or LTC3892-1
ILIM = 0V (LTC3892/LTC3892-2)
ILIM = INTVCC (LTC3892/LTC3892-2)
l
l
l
–8
–8
–8
0
0
0
8
8
8
mV
mV
mV
Gate Driver
TG1,2 Pull-Up On-Resistance
Pull-Down On-Resistance
VDRVSET = INTVCC 2.2
1.0
Ω
Ω
BG1,2 Pull-Up On-Resistance
Pull-Down On-Resistance
VDRVSET = INTVCC 2.2
1.0
Ω
Ω
BDSW1,2 BOOST to DRVCC Switch On-
Resistance
VSW = 0V, VDRVSET = INTVCC 3.7 Ω
TG1,2 tr
TG1,2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
BG1,2 tr
BG1,2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On
Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC 55 ns
BG/TG t1D Bottom Gate Off to Top Gate On
Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC 50 ns
tON(MIN)1,2 TG Minimum On-Time (Note 7) VDRVSET = INTVCC 80 ns
DRVCC Linear Regulator
VDRVCC(INT) DRVCC Voltage from Internal VIN LDO VEXTVCC = 0V
7V < VIN < 60V, DRVSET = 0V
11V < VIN < 60V, DRVSET = INTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
VLDOREG(INT) DRVCC Load Regulation from VIN
LDO
ICC = 0mA to 50mA, VEXTVCC = 0V 0.9 2.0 %
VDRVCC(EXT) DRVCC Voltage from Internal EXTVCC
LDO
7V < VEXTVCC < 13V, DRVSET = 0V
11V < VEXTVCC < 13V, DRVSET = INTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
VLDOREG(EXT) DRVCC Load Regulation from Internal
EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 8.5V,
VDRVSET = 0V
0.7 2.0 %
VEXTVCC EXTVCC LDO Switchover Voltage EXTVCC Ramping Positive
DRVUV = 0V
DRVUV = INTVCC
4.5
7.4
4.7
7.7
4.9
8.0
V
V
VLDOHYS EXTVCC Hysteresis 250 mV
VDRVCC(50kΩ) Programmable DRVCC RDRVSET = 50kΩ, VEXTVCC = 0V 5.0 V
VDRVCC(70kΩ) Programmable DRVCC RDRVSET = 70kΩ, VEXTVCC = 0V 6.4 7.0 7.6 V
VDRVCC(90kΩ) Programmable DRVCC RDRVSET = 90kΩ, VEXTVCC = 0V 9.0 V
LTC3892/
LTC3892-1/LTC3892-2
6
38921fc
For more information www.linear.com/LTC3892
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2,3 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG1 = FLOAT unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator and Phase-Locked Loop
f25kΩ Programmable Frequency RFREQ =25kΩ, PLLIN/MODE = DC Voltage 105 kHz
f65kΩ Programmable Frequency RFREQ = 65kΩ, PLLIN/MODE = DC Voltage 375 440 505 kHz
f105kΩ Programmable Frequency RFREQ = 105kΩ, PLLIN/MODE = DC Voltage 835 kHz
fLOW Low Fixed Frequency VFREQ = 0V, PLLIN/MODE = DC Voltage 320 350 380 kHz
fHIGH High Fixed Frequency VFREQ = INTVCC, PLLIN/MODE = DC Voltage 485 535 585 kHz
fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l75 850 kHz
PLLIN VIH
PLLIN VIL
PLLIN/MODE Input High Level
PLLIN/MODE Input Low Level
PLLIN/MODE = External Clock
PLLIN/MODE = External Clock
l
l
2.5
0.5
V
V
PGOOD1 and PGOOD2 Outputs (LTC3892/LTC3892-2)
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
Hysteresis
–13
–10
2.5
–7
%
%
VFB with Respect to Set Regulated Voltage
VFB Ramping Positive
Hysteresis
7
10
2.5
13
%
%
tPG Delay for Reporting a Fault 35 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Ratings for extended periods may affect device reliability and lifetime.
Note 2: The LTC3892/LTC3892-1/LTC3892-2 is tested under pulsed load
conditions such that TJ ≈ TA. The LTC3892E/LTC3892E-1/LTC3892E-2
is guaranteed to meet performance specifications from 0°C to 85°C.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3892I/LTC3892I-1/LTC3892I-2 is
guaranteed over the –40°C to 125°C operating junction temperature
range, the LTC3892H/LTC3892H-1/LTC3892H-2 is guaranteed over
the –40°C to 150°C operating junction temperature range, and the
LTC3892MP/LTC3892MP-1/LTC3892MP-2 is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature (TJ, in °C) is calculated from the ambient temperature
(TA, in °C) and power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA = 44°C/W for the QFN package and where θJA = 30°C/W for the
TSSOP package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3892/LTC3892-1/LTC3892-2 is tested in a feedback loop
that servos VITH1,2 to a specified voltage and measures the resultant
VFB1,2. The specification at 85°C is not tested in production and is assured
by design, characterization and correlation to production testing at other
temperatures (125°C for the LTC3892E/LTC3892E-1/LTC3892E-2 and
LTC3892I/LTC3892I-1/LTC3892I-2, 150°C for the LTC3892H/LTC3892H-1/
LTC3892H-2 and LTC3892MP/LTC3892MP-1/LTC3892MP-2). For
the LTC3892I/LTC3892I-1/LTC3892I-2 and LTC3892H/LTC3892H-1/
LTC3892H-2, the specification at 0°C is not tested in production and
is assured by design, characterization and correlation to production
testing at –40°C. For the LTC3892MP/LTC3892MP-1/LTC3892MP-2, the
specification at 0°C is not tested in production and is assured by design,
characterization and correlation to production testing at –55°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section)
Note 8: Do not apply a voltage or current source to these pins. They must be
connected to capacitive loads only, otherwise permanent damage may occur.
LTC3892/
LTC3892-1/LTC3892-2
7
38921fc
For more information www.linear.com/LTC3892
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
Burst Mode Operation
Load Step
Pulse-Skipping Mode
Load Step
Forced Continuous Mode
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
vs Load Current
Efficiency and Power Loss
3892 G01
V
OUT
= 5V
BURST EFFICIENCY
FCM LOSS
BURST LOSS
PULSE-SKIPPING
EFFICIENCY
FCM EFFICIENCY
PULSE-
SKIPPING
LOSS
V
IN
= 12V
FIGURE 11 CIRCUIT
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
Efficiency vs Output Current
3892 G02
V
IN
= 10V
V
IN
= 20V
V
IN
= 30V
V
IN
= 40V
V
IN
= 50V
V
IN
= 60V
FIGURE 11 CIRCUIT
V
OUT
= 5V
Burst Mode OPERATION
INPUT VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
86
87
88
89
90
91
92
93
94
95
96
EFFICIENCY (%)
Efficiency vs Input Voltage
3892 G03
FIGURE 11 CIRCUIT
V
OUT
= 5V
I
LOAD
=8A
DRVSET=INTV
CC
DRVSET=0V
50µs/DIV
VOUT
100mV/DIV
AC COUPLED
IL
2A/DIV
3892 G04
VIN = 12V
VOUT = 5V
FIGURE 13 CIRCUIT
50µs/DIV
VOUT
100mV/DIV
AC COUPLED
IL
2A/DIV
3892 G05
VIN = 12V
VOUT = 5V
FIGURE 13 CIRCUIT
50µs/DIV
VOUT
100mV/DIV
AC COUPLED
IL
2A/DIV
3892 G06
VIN = 12V
VOUT = 5V
FIGURE 13 CIRCUIT
LTC3892/
LTC3892-1/LTC3892-2
8
38921fc
For more information www.linear.com/LTC3892
DRVCC and EXTVCC
vs Load Current
EXTVCC Switchover and DRVCC
Voltages vs Temperature
Undervoltage Lockout
Threshold vs Temperature
LOAD CURRENT (mA)
0
DRVCC VOLTAGE (V)
6.4
5.6
4.8
6
5.2
4.4
6.2
5.4
4.6
5.8
5
4.2
41507525 12550 100
3892 G10
EXTVCC = 0V
EXTVCC = 8.5V
VIN = 12V
DRVSET = GND
EXTVCC = 5V
TEMPERATURE (°C)
–75
DRVCC VOLTAGE (V)
11
10
8
7
5
9
6
4
3892 G11
150125250–50 75 100–25 50
DRVCC (DRVSET = INTVCC)
EXTVCC RISING
EXTVCC FALLING
EXTVCC RISING
EXTVCC FALLING
DRVCC (DRVSET = 0V)
DRVUV = INTVCC
DRVUV = GND
TEMPERATURE (°C)
–75
DRVCC VOLTAGE (V)
8
7.5
5.5
4.5
6.5
3.5
3
7
5
6
4
3892 G12
150125250–50 75 100–25 50
RISING
FALLING
RISING
FALLING
DRVUV = INTVCC
DRVUV = GND
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load Soft Start-Up
Regulated Feedback Voltage vs
Temperature
2µs/DIV
FORCED
CONTINUOUS
MODE
Burst Mode
OPERATION
1A/DIV
PULSE
SKIPPING
MODE
3892 G07
VIN = 12V
VOUT = 5V
ILOAD = 1mA
FIGURE 13 CIRCUIT
2ms/DIV
RUN1, 2
5V/DIV
VOUT2
2V/DIV
VOUT1
2V/DIV
3892 G08
FIGURE 13 CIRCUIT
TEMPERATURE (°C)
-75
REGULATED FEEDBACK VOLTAGE (mV)
808
806
802
800
796
804
798
794
792
3892 G09
150500-50 100 12525-25 75
LTC3892/
LTC3892-1/LTC3892-2
9
38921fc
For more information www.linear.com/LTC3892
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE Pins Total Input Current
vs VSENSE Voltage
SENSE– Pin Input Bias Current vs
Temperature
Foldback Current Limit
Maximum Current Sense
Threshold vs Duty Cycle
Maximum Current Sense
Threshold vs ITH Voltage
Shutdown (RUN) Threshold
vs Temperature
VSENSE COMMON MODE VOLTAGE (V)
0
SENSE CURRENT (µA)
800
700
300
100
500
0
600
200
400
3892 G13
656025155 45 5510 3520 40 5030
TEMPERATURE (°C)
–75
SENSE CURRENT (µA)
900
500
300
700
100
0
800
400
600
200
3892 G14
150125250–50 75 100–25 50
VOUT > INTVCC + 0.5V
VOUT < INTVCC – 0.5V
FEEDBACK VOLTAGE (mV)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
120
100
110
90
50
30
70
10
0
80
40
60
20
3892 G15
800400300100 600 700200 500
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
LTC3892-2
LTC3892/LTC3892-1
DUTY CYCLE (%)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
100
90
50
30
70
10
0
80
40
60
20
3892 G16
100403010 60 90807020 50
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
VITH (V)
0
CURRENT SENSE VOLTAGE (mV)
100
0
–20
–40
80
40
60
20
3892 G17
1.40.2 0.6 1.210.80.4
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
Burst Mode
OPERATION
5% DUTY CYCLE
PULSE-SKIPPING
FORCED CONTINUOUS MODE
TEMPERATURE (°C)
–75
RUN PIN VOLTAGE (V)
1.4
1.25
1.15
1.35
1.05
1
1.2
1.3
1.1
3892 G18
150125250–50 75 100–25 50
RISING
FALLING
LTC3892/
LTC3892-1/LTC3892-2
10
38921fc
For more information www.linear.com/LTC3892
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency vs
Temperature
TRACK/SS Pull-Up Current vs
Temperature
DRVCC Line Regulation Shutdown Current vs Temperature
Shutdown Current vs
Input Voltage Quiescent Current vs Temperature
INPUT VOLTAGE (V)
0
DRVCC VOLTAGE (V)
11
10
6
8
5
9
7
3892 G19
656025155 45 5510 3520 40 5030
DRVSET = INTVCC
DRVSET = GND
TEMPERATURE (°C)
–75
SHUTDOWN CURRENT (µA)
8
4
7
0
2
6
3
1
5
3892 G20
150125250–50 75 100–25 50
VIN = 12V
INPUT VOLTAGE (V)
0
SHUTDOWN CURRENT (µA)
14
10
6
8
0
12
4
2
3892 G21
706010 20 40 5030
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
70
80
QUIESCENT CURRENT (µA)
Quiescent Current vs Temperature
3899 G22
V
IN
=12V
ONE CHANNEL ON
Burst Mode OPERATION
DRVSET = 70kΩ
DRVSET=INTV
CC
DRVSET=GND
TEMPERATURE (°C)
-75
FREQUENCY (kHz)
600
500
550
450
350
400
300 -25 25-50 0 75 100
3892 G23
15050 125
FREQ = INTVCC
FREQ = GND
TEMPERATURE (°C)
–75
TRACK/SS CURRENT (µA)
12
10
11.5
8
9
11
9.5
8.5
10.5
3892 G24
150125250–50 75 100–25 50
LTC3892/
LTC3892-1/LTC3892-2
11
38921fc
For more information www.linear.com/LTC3892
PIN FUNCTIONS
(QFN (LTC3892 and LTC3892-2)/TSSOP (LTC3892-1))
FREQ (Pin 1/ Pin 5): The frequency control pin for the
internal VCO. Connecting this pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting this pin
to INTVCC forces the VCO to a fixed high frequency of
535kHz. Other frequencies between 50kHz and 900kHz can
be programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
PLLIN/MODE (Pin 2/Pin 6): External Synchronization Input
to Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, the phase-locked loop
will force the rising TG1 signal to be synchronized with the
rising edge of the external clock, and the regulators will oper-
ate in forced continuous mode on the LTC3892/LTC3892-1
and in pulse-skipping mode on the LTC3892-2. When not
synchronizing to an external clock, this input, which acts on
both controllers, determines how the LTC3892/LTC3892-1/
LTC3892-2 operates at light loads. Pulling this pin to ground
selects Burst Mode operation. An internal 100k resistor to
ground also invokes Burst Mode operation when the pin is
floated. Tying this pin to INTVCC forces continuous inductor
current operation. Tying this pin to a voltage greater than
1.1V and less than INTVCC – 1.3V selects pulse-skipping
operation. This can be done by connecting a 100k resistor
from this pin to INTVCC.
PGOOD1, PGOOD2 (Pins 3, 4/NA): Open-Drain Logic
Output. PGOOD1,2 is pulled to ground when the voltage
on the respective VFB1,2 pin is not within ±10% of its
set point. These pins are available on the LTC3892 and
LTC3892-2, but not on the LTC3892-1.
INTVCC (Pin 5/Pin 7): Output of the Internal 5V Low Drop-
out Regulator. The low voltage analog and digital circuits
are powered from this voltage source. A low ESR 0.1µF
ceramic bypass capacitor should be connected between
INTVCC and GND, as close as possible to the IC. INTVCC
should not be used to power or bias any external circuitry
other than to configure the FREQ, PLLIN/MODE, DRVSET,
DRVUV and VPRG1 pins.
RUN1, RUN2 (Pins 6, 7/Pins 8, 9): Run Control Inputs for
Each Controller. Forcing any of these pins below 1.2V shuts
down that controller. Forcing both of these pins below 0.7V
shuts down the entire LTC3892/LTC3892-1/LTC3892-2,
reducing quiescent current to approximately 3.6µA.
ILIM (Pin 8/NA): Current Comparator Sense Voltage Range
Input. Tying this pin to GND or INTVCC or floating it sets
the maximum current sense threshold (for both channels)
to one of three different levels (50mV, 100mV, or 75mV
respectively). This pin is available on the LTC3892 and
LTC3892-2, but not on the LTC3892-1. For the LTC3892-1,
the maximum current sense threshold is 75mV.
VFB2 (Pin 11/Pin 12): This pin receives the remotely sensed
feedback voltage for channel 2 from an external resistor
divider across the output.
DRVUV (Pin13/Pin 14): Determines the higher or lower
DRVCC UVLO and EXTVCC switchover thresholds, as listed
on the Electrical Characteristics table. Connecting DRVUV
to GND chooses the lower thresholds whereas tying DRVUV
to INTVCC chooses the higher thresholds.
DRVSET (Pin 14/Pin 15): Sets the regulated output volt-
age of the DRVCC LDO regulator. Connecting this pin to
GND sets DRVCC to 6V whereas connecting it to INTVCC
sets DRVCC to 10V. Voltages between 5V and 10V can be
programmed by placing a resistor (50k to 100k) between
the DRVSET pin and GND.
DRVCC (Pin 20/Pin 21): Output of the Internal or External
Low Dropout (LDO) Regulator. The gate drivers are pow-
ered from this voltage source. The DRVCC voltage is set
by the DRVSET pin. Must be decoupled to ground with a
minimum of 4.7µF ceramic or other low ESR capacitor.
Do not use the DRVCC pin for any other purpose.
EXTVCC (Pin 21/Pin 22): External Power Input to an Inter-
nal LDO Connected to DRVCC. This LDO supplies DRVCC
power, bypassing the internal LDO powered from VIN
whenever EXTVCC is higher than its switchover threshold
(4.7V or 7.7V depending on the DRVUV pin). See EXTVCC
Connection in the Applications Information section. Do not
float or exceed 14V on this pin. Do not connect EXTVCC
to a voltage greater than VIN. Connect to GND if not used.
VIN (Pin 22/Pin 23): Main Supply Pin. A bypass capacitor
should be tied between this pin and the GND pin.
BG1, BG2 (Pins 23, 19/Pins 24, 20): High Current Gate
Drives for Bottom N-Channel MOSFETs. Voltage swing at
these pins is from ground to DRVCC.
LTC3892/
LTC3892-1/LTC3892-2
12
38921fc
For more information www.linear.com/LTC3892
PIN FUNCTIONS
(QFN (LTC3892 and LTC3892-2)/TSSOP (LTC3892-1))
BOOST1, BOOST2 (Pins 24, 18/Pins 25, 19): Bootstrapped
Supplies to the Topside Floating Drivers. Capacitors are
connected between the BOOST and SW pins. Voltage
swing at BOOST1 and BOOST2 pins is from approximately
DRVCC to (VIN1,2 + DRVCC).
SW1, SW2 (Pins 25, 17/Pins 26, 18): Switch Node Con-
nections to Inductors.
TG1, TG2 (Pins 26, 16/Pins 27, 17): High Current Gate
Drives for Top N-Channel MOSFETs. These are the outputs
of floating drivers with a voltage swing equal to DRVCC
superimposed on the switch node voltage SW.
TRACK/SS1, TRACK/SS2 (Pins 27, 15/Pins 28, 16):
External Tracking and Soft-Start Input. The LTC3892/
LTC3892-1/LTC3892-2 regulates the negative input (EA–)
of the error amplifier to the smaller of 0.8V or the voltage
on the TRACK/SS pin. An internal 10µA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time at start-up to the final regulated
output voltage. Alternatively, a resistor divider on another
supply connected to the TRACK/SS pin allows the LTC3892/
LTC3892-1/LTC3892-2 output voltage to track the other
supply during start-up. The TRACK/SS pin is pulled low
in shutdown or in undervoltage lockout.
VPRG1 (Pin 28/NA): Channel 1 Output Voltage Control Pin.
This pin sets channel 1 to adjustable output mode using
external feedback resistors or fixed 3.3V/5V output mode.
Floating this pin allows the output to be programmed from
0.8V to 60V with an external resistor divider, regulating
VFB1 to 0.8V. This pin is available on the LTC3892 and
LTC3892-2, but not on the LTC3892-1.
ITH1, ITH2 (Pins 29, 12/Pins 1, 13): Error Amplifier
Outputs and Switching Regulator Compensation Points.
Each associated channel’s current comparator trip point
increases with this control voltage.
VFB1 (Pin 30/Pin 2): For the LTC3892-1, this pin receives
the remotely sensed feedback voltage for channel 1 from
an external resistor divider across the output.
For the LTC3892 and LTC3892-2, if the VPRG1 pin is float-
ing, the VFB1 pin receives the remotely sensed feedback
voltage for channel1 from an external resistor divider
across the output. If VPRG1 is tied to GND or INTVCC,
the VFB1 pin receives the remotely sensed output voltage
directly.
SENSE1+, SENSE2+ (Pins 31, 10/Pins 3, 11): The (+)
Input to the Differential Current Comparators. The ITH pin
voltage and controlled offsets between the SENSE– and
SENSE+ pins in conjunction with RSENSE set the current
trip threshold.
SENSE1–, SENSE2– (Pins 32, 9/Pins 4, 10): The (–) Input
to the Differential Current Comparators. When SENSE1,2– is
greater than INTVCC, then SENSE1,2– pin supplies current
to the current comparator.
GND (Exposed Pad Pin 33/Exposed Pad Pin 29): Ground.
The exposed pad must be soldered to the PCB for rated
electrical and thermal performance.
Table 1. Summary of the Differences Between the LTC3892, LTC3892-1 and LTC3892-2
LTC3892 LTC3892-1 LTC3892-2
ILIM pin for selectable current sense
voltage?
Yes; 50mV, 75mV, or 100mV No; fixed 75mV Yes; 50mV, 75mV, or 100mV
VPRG1 pin for fixed or adjustable VOUT1?Yes; fixed 3.3V or 5V (with internal
resistor divider) or adjustable with
external resistor divider
No; only adjustable with external
resistor divider
Yes; fixed 3.3V or 5V (with internal
resistor divider) or adjustable with
external resistor divider
Independent PGOOD output for each
channel?
Yes; PGOOD1 and PGOOD2 No PGOOD function Yes; PGOOD1 and PGOOD2
Output overvoltage protection bottom gate
"crowbar?"
Yes; BG forced on Yes; BG forced on No; BG not forced on
Current foldback during overcurrent events?Yes Yes No
Light load operation when synchronized to
external clock using PLLIN/MODE
Forced Continuous Forced Continuous Pulse-skipping
(Discontinuous)
Package 32-Pin 5mm x 5mm QFN
(UH32)
28-Lead TSSOP
(FE28)
32-Pin 5mm x 5mm QFN
(UH32)
LTC3892/
LTC3892-1/LTC3892-2
13
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For more information www.linear.com/LTC3892
FUNCTIONAL DIAGRAMS
BOOST1,2
DRVCC
TG1,2TOP
BOT
CHANNELS 1 AND 2
S
CLK1
CLK2
PFD
SYNC
DET
VCO
Q
RQBOT
SHDN
SLEEP
0.425V
TOP ON
SW1,2
BG1,2
DRVCC
GND
SENSE1,2+
SENSE1,2–
ITH1,2
TRACK/SS1,2
SHDN
RUN1,2
SHDN
RST
2(VFB)
FOLDBACK
10µA
VFB1,2
RA
RC
RB
CC
0.80V
TRACK/SS
0.88V
OV
CB
COUT
VIN1,2
V
OUT1,2
RSENSE
L
SWITCHING
LOGIC
DROPOUT
DET
+
–
+
–
+
–
–
+
+
IR
3mV
ICMP
2.8V
0.65V
SLOPE COMP
+–
+–
CIN
+
–
R2
R1
CC2
CSS
38921 FD
150nA
3.5V
20µA
FREQ
PLLIN/MODE
100k
INTVCC
LDO
DRVCC LDO/UVLO
CONTROL
4.7V/
7.7V
EN
+
–
EN
2.00V
1.20V
DRVSET
EXTVCC
DRVUV
VIN
DRVCC
20µA
4R
R
+
–
+
–
INTVCC
EA–
PGOOD1
EA1–
0.88V
0.72V
+
–
+
–
+
–
+
–
PGOOD2
EA2–
0.88V
0.72V
CURRENT
LIMIT
ILIM
VPRG1
LTC3892 AND LTC3892-2
NOT ON LTC3892-1
VPRG1 AFFECTS CHANNEL 1 ONLY,
VOUT2 IS ALWAYS ADJUSTABLE (R1 = 0, R2 = ∞)
LTC3892-1 (R1 = 0, R2 = ∞)
VPRG1
FLOAT
GND
INTVCC
R1
0
625k
1.05M
R2
∞
200k
200k
VOUT1
ADJUSTABLE
3.3V FIXED
5V FIXED
LTC3892 AND LTC3892-1
LTC3892/
LTC3892-1/LTC3892-2
14
38921fc
For more information www.linear.com/LTC3892
OPERATION
(Refer to the Functional Diagrams)
Main Control Loop
The LTC3892/LTC3892-1/LTC3892-2 uses a constant
frequency, current mode step-down architecture. The two
controller channels operate 180° out of phase with each
other. During normal operation, the external top MOSFET
is turned on when the clock for that channel sets the RS
latch, and is turned off when the main current compara-
tor, ICMP, resets the RS latch. The peak inductor current
at which ICMP trips and resets the latch is controlled by
the voltage on the ITH pin, which is the output of the er-
ror amplifier, EA. The error amplifier compares the output
voltage feedback signal at the VFB pin (which is generated
with an external resistor divider connected across the
output voltage, VOUT, to ground) to the internal 0.800V
reference voltage. When the load current increases, it
causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
DRVCC/EXTVCC/INTVCC Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be pro-
grammed from 5V to 10V through control of the DRVSET
pin. When the EXTVCC pin is tied to a voltage below its
switchover voltage (4.7V or 7.7V depending on the DRVSET
voltage), the VIN LDO (low dropout linear regulator) sup-
plies power from VIN to DRVCC. If EXTVCC is taken above
its switchover voltage, the VIN LDO is turned off and an
EXTVCC LDO is turned on. Once enabled, the EXTVCC LDO
supplies power from EXTVCC to DRVCC. Using the EXTVCC
pin allows the DRVCC power to be derived from a high
efficiency external source such as one of the LTC3892/
LTC3892-1/LTC3892-2 switching regulator outputs.
Each top MOSFET driver is biased from the floating boot-
strap capacitor, CB, which normally recharges during each
cycle through an internal switch whenever SW goes low.
If the input voltage decreases to a voltage close to its
output, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for about one-
twelfth of the clock period every tenth cycle to allow CB to
recharge, resulting in about 99% duty cycle.
The INTVCC supply powers most of the other internal circuits
in the LTC3892/LTC3892-1/LTC3892-2. The INTVCC LDO
regulates to a fixed value of 5V and its power is derived
from the DRVCC supply.
Shutdown and Start-Up (RUN, TRACK/SS Pins)
The two channels of the LTC3892/LTC3892-1/LTC3892-2
can be independently shut down using the RUN1 and
RUN2 pins. Pulling a RUN pin below 1.2V shuts down
the main control loop for that channel. Pulling both pins
below 0.7V disables both controllers and most internal
circuits, including the DRVCC and INTVCC LDOs. In this
state, the LTC3892/LTC3892-1/LTC3892-2 draws only
3.6μA of quiescent current.
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Each RUN pin
may be externally pulled up or driven directly by logic. Each
RUN pin can tolerate up to 65V (absolute maximum), so it
can be conveniently tied to VIN in always-on applications
where one or both controllers are enabled continuously
and never shut down.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the TRACK/SS pin (TRACK/
SS1 for channel 1, TRACK/SS2 for channel 2). When the
voltage on the TRACK/SS pin is less than the 0.8V internal
reference, the LTC3892/LTC3892-1/LTC3892-2 regulates
the VFB voltage to the TRACK/SS pin voltage instead of the
0.8V reference. This allows the TRACK/SS pin to be used
to program a soft-start by connecting an external capacitor
from the TRACK/SS pin to GND. An internal 10μA pull-up
current charges this capacitor creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises linearly
from 0V to 0.8V (and beyond up to about 4V), the output
voltage VOUT rises smoothly from zero to its final value.
LTC3892/
LTC3892-1/LTC3892-2
15
38921fc
For more information www.linear.com/LTC3892
OPERATION
(Refer to the Functional Diagrams)
Alternatively the TRACK/SS pins can be used to make the
start-up of VOUT to track that of another supply. Typically,
this requires connecting to the TRACK/SS pin an external
resistor divider from the other supply to ground (see
Applications Information section).
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC3892/LTC3892-1/LTC3892-2 can be enabled to
enter high efficiency Burst Mode operation, pulse-skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to GND. To select forced continuous opera-
tion, tie the PLLIN/MODE pin to INTVCC. To select pulse-
skipping mode, tie the PLLIN/MODE pin to a DC voltage
greater than 1.1V and less than INTVCC – 1.3V. This can
be done by connecting a 100kΩ resistor between PLLIN/
MODE and INTVCC.
When a controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to ap-
proximately 25% of the maximum sense voltage even
when the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the load cur-
rent, the error amplifier, EA, will decrease the voltage on
the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current that the LTC3892/
LTC3892-1/LTC3892-2 draws. If one channel is in sleep
mode and the other channel is shut down, the LTC3892/
LTC3892-1/LTC3892-2 draws only 29μA of quiescent
current (with DRVSET = 0V). If both channels are in sleep
mode, it draws only 34μA of quiescent current. In sleep
mode, the load current is supplied by the output capacitor.
As the output voltage decreases, the EA’s output begins
to rise. When the output voltage drops enough, the ITH
pin is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller operates discontinuously.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3892/LTC3892-1/LTC3892-2 operates in
PWM pulse-skipping mode at light loads. In this mode,
constant frequency operation is maintained down to ap-
proximately 1% of designed maximum output current.
At very light loads, the current comparator, ICMP, may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
When an external clock is connected to the PLLIN/MODE
pin to synchronize the internal oscillator (see the Frequency
Selection and Phase-Locked Loop section), the LTC3892/
LTC3892-1 operate in forced continuous mode while the
LTC3892-2 operates in discontinuous pulse skipping mode.
LTC3892/
LTC3892-1/LTC3892-2
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OPERATION
(Refer to the Functional Diagrams)
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3892/LTC3892-1/
LTC3892-2’s controllers can be selected using the FREQ
pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
INTVCC or programmed through an external resistor. Tying
FREQ to GND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 9.
A phase-locked loop (PLL) is available on the LTC3892/
LTC3892-1/LTC3892-2 to synchronize the internal oscil-
lator to an external clock source that is connected to the
PLLIN/MODE pin. The LTC3892/LTC3892-1/LTC3892-2’s
phase detector adjusts the voltage (through an internal
lowpass filter) of the VCO input to align the turn-on of
controller 1’s external top MOSFET to the rising edge of
the synchronizing signal. Thus, the turn-on of controller
2’s external top MOSFET is 180° out of phase to the rising
edge of the external clock source.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3892/LTC3892-1/
LTC3892-2’s phase-locked loop is from approximately
55kHz to 1MHz, with a guarantee to be between 75kHz
and 850kHz. In other words, the LTC3892/LTC3892-1/
LTC3892-2’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling). It is recommended
that the external clock source swing from ground (0V) to
at least 2.5V.
When an external clock is connected to the PLLIN/MODE
pin to synchronize the internal oscillator, the LTC3892/
LTC3892-1 operate in forced continuous mode while the
LTC3892-2 operates in discontinuous pulse skipping mode.
Output Overvoltage Protection (LTC3892/LTC3892-1,
Not On LTC3892-2)
Each channel has an overvoltage comparator that guards
against transient overshoots as well as other more seri-
ous conditions that may overvoltage the output. When
the VFB1,2 pin rises by more than 10% above its regula-
tion point of 0.800V, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared.
Foldback Current (LTC3892/LTC3892-1, Not On
LTC3892-2)
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB1,2 voltage is keeping up with
the TRACK/SS1,2 voltage).
Current foldback limiting is intended to limit power
dissipation during overcurrent and short-circuit fault
conditions. Note that while the current foldback func-
tion does not exist on the LTC3892-2 version, it is still
inherently protected during these fault conditions. The
LTC3892/LTC3892-1/LTC3892-2’s peak current mode
control architecture constantly monitors the inductor
current and prevents current runaway under all conditions.
LTC3892/
LTC3892-1/LTC3892-2
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APPLICATIONS INFORMATION
38921 F03
TO SENSE FILTER
NEXT TO THE CONTROLLER
INDUCTOR OR R
SENSE
CURRENT FLOW
COUT
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
The Typical Application on the first page is a basic
LTC3892/LTC3892-1/LTC3892-2 application circuit.
LTC3892/LTC3892-1/LTC3892-2 can be configured to
use either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 65V (absolute maximum), enabling
the LTC3892/LTC3892-1/LTC3892-2 to regulate output
voltages up to a nominal 60V (allowing margin for toler-
ances and transients). The SENSE+ pin is high impedance
over the full common mode range, drawing at most ±1μA.
This high impedance allows the current comparators to
be used in inductor DCR sensing. The impedance of the
SENSE– pin changes depending on the common mode
voltage. When SENSE– is less than INTVCC – 0.5V, a
small current of less than 1μA flows out of the pin. When
SENSE– is above INTVCC + 0.5V, a higher current (≈700μA)
flows into the pin. Between INTVCC – 0.5V and INTVCC +
0.5V, the current transitions from the smaller current to
the higher current.
Filter components mutual to the sense lines should be
placed close to the LTC3892/LTC3892-1/LTC3892-2, and
the sense lines should run close together to a Kelvin con-
nection underneath the current sense element (shown in
Figure 1). Sensing current elsewhere can effectively add
parasitic inductance and capacitance to the current sense
element, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
If DCR sensing is used (Figure 2b), resistor R1 should be
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes.
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
Each controller’s current comparator has a maximum
threshold VSENSE(MAX). For the LTC3892-1, VSENSE(MAX)
is fixed at 75mV, while for the LTC3892 and LTC3892-2,
VSENSE(MAX) is either 50mV, 75mV or 100mV, as deter-
mined by the state of the ILIM pin. The current comparator
threshold voltage sets the peak of the inductor current,
yielding a maximum average output current, IMAX, equal
to the peak value less half the peak-to-peak ripple current,
∆IL. To calculate the sense resistor value, use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +∆IL
2
When using a controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability criteria
for buck regulators operating at greater than 50% duty
factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3892/LTC3892-1/LTC3892-2
is capable of sensing the voltage drop across the induc-
tor DCR, as shown in Figure2b. The DCR of the inductor
represents the small amount of DC winding resistance of
LTC3892/
LTC3892-1/LTC3892-2
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38921 F04b
LTC3892/
LTC3892-1/
LTC3892-2
V
IN1,2
V
OUT1,2
C1* R2
*PLACE C1 NEAR SENSE PINS R
SENSE(EQ)
= DCR(R2/(R1+R2))
L DCR
INDUCTOR
R1
(R1||R2) • C1 = L/DCR
BOOST
TG
SW
BG
GND
SENSE1,2–
SENSE1,2+
the copper, which can be less than 1mΩ for today’s low
value, high current inductors. In a high current application
requiring such an inductor, power loss through a sense
resistor would cost several points of efficiency compared
to inductor DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +∆IL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for VSENSE(MAX) in the Electrical Charac-
teristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD=
R
SENSE(EQUIV)
DCRMAX atTL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
R1R2 =
L
(DCR at 20°C)•C1
The sense resistor values are:
R1=
R1
R2
R
D
; R2=
R1•R
D
1−R
D
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=VIN(MAX) −VOUT
( )
• VOUT
R1
APPLICATIONS INFORMATION
38921 F04a
LTC3892/
LTC3892-1/
LTC3892-2
BOOST
TG
SW
BG
GND
SENSE1,2–
SENSE1,2+
V
IN1,2
V
OUT1,2
RSENSE
CAP
PLACED NEAR SENSE PINS
(2b) Using the Inductor DCR to Sense Current
(2a) Using a Resistor to Sense Current
Figure 2. Current Sensing Methods
LTC3892/
LTC3892-1/LTC3892-2
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Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current, ∆IL, decreases with higher induc-
tance or higher frequency and increases with higher VIN:
∆IL=1
f
( )
L
( )
VOUT 1−VOUT
VIN
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. Core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
T
wo external power MOSFETs must be selected for each
controller in the LTC3892/LTC3892-1/LTC3892-2: one
N-channel MOSFET for the top (main) switch and one
N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the DRVCC volt-
age. This voltage can range from 5V to 10V depending
on configuration of the DRVSET pin. Therefore, both
logic-level and standard-level threshold MOSFETs can be
used in most applications depending on the programmed
DRVCC voltage. Different UVLO thresholds appropriate
for logic-level or standard-level threshold MOSFETs can
be selected by the DRVUV pin. Pay close attention to the
BVDSS specification for the MOSFETs as well.
The LTC3892/LTC3892-1/LTC3892-2’s unique ability to
adjust the gate drive level between 5V to 10V (OPTI-DRIVE)
allows an application circuit to be precisely optimized
for efficiency. When adjusting the gate drive level, the
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
APPLICATIONS INFORMATION
LTC3892/
LTC3892-1/LTC3892-2
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APPLICATIONS INFORMATION
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
VIN
Synchronous Switch Duty Cycle = VIN −VOUT
V
IN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
V
OUT
VIN
IOUT(MAX)
( )
21+δ
( )
RDS(ON) +
(VIN)2IOUT(MAX)
2
(RDR )(CMILLER )•
1
VDRVCC −VTHMIN
+1
VTHMIN
(f)
PSYNC =VIN −VOUT
V
IN
IOUT(MAX)
( )
21+δ
( )
RDS(ON)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Optional Schottky diodes placed across the synchronous
MOSFET conduct during the dead-time between the con-
duction of the two power MOSFETs. This prevents the
body diode of the synchronous MOSFET from turning
on, storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula shown in Equation 1 to determine the maximum
RMS capacitor current requirement. Increasing the out-
put current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The opt-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
I
MAX
V
IN
VOUT
( )
VIN −VOUT
( )
1/2
(1)
LTC3892/
LTC3892-1/LTC3892-2
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APPLICATIONS INFORMATION
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the
high operating frequency of the LTC3892/LTC3892-1/
LTC3892-2, ceramic capacitors can also be used for CIN.
Always consult the manufacturer if there is any question.
The benefit of the LTC3892/LTC3892-1/LTC3892-2
2-phase operation can be calculated by using Equation 1
for the higher power controller and then calculating the
loss that would have resulted if both controller channels
switched on at the same time. The total RMS power lost
is lower when both controllers are operating due to the
reduced overlap of current pulses required through the
input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller
is adequate for the dual controller design. Also, the input
protection fuse resistance, battery resistance, and PC
board trace resistance losses are also reduced due to the
reduced peak currents in a 2-phase system. The overall
benefit of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the efficiency testing. The drains of the top
MOSFETs should be placed within 1cm of each other and
share a common CIN(s). Separating the drains and CIN may
produce undesirable voltage and current resonances at VIN.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3892/LTC3892-
1/LTC3892-2, is also suggested. A 2.2Ω to 10Ω resistor
placed between CIN (C1) and the VIN pin provides further
isolation, but is not required.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
∆VOUT ≈ ∆ILESR+1
8 • f •COUT
where f is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
Setting Output Voltage
The LTC3892/LTC3892-1/LTC3892-2 output voltages are
set by an external feedback resistor divider carefully placed
across the output, as shown in Figure 3a. The regulated
output voltage is determined by:
VOUT =0.8V 1+RB
RA
To improve the frequency response, a feedforward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
For the LTC3892 and LTC3892-2, channel 1 has the
option to be programmed to a fixed 5V or 3.3V output
through control of the VPRG1 pin (not available on the
LTC3892-1). Figure3b shows how the VFB1 pin is used
to sense the output voltage in fixed output mode. Tying
VPRG1 to INTVCC or GND programs VOUT1 to 5V or 3.3V,
respectively. Floating VPRG1 sets VOUT1 to adjustable
output mode using external resistors.
38921 F05a
1/2 LTC3892/
LTC3892-1/
LTC3892-2
VFB
RBCFF
RA
VOUT
38921 F05b
LTC3892/
LTC3892-2
VFB1
VPRG1
INTVCC/GND
COUT
VOUT1
5V/3.3V
Figure 3. Setting Buck Output Voltage
(3a) Setting Adjustable Output Voltage
(3b) Setting CH1 (LTC3892) to Fixed 5V/3.3V Voltage
LTC3892/
LTC3892-1/LTC3892-2
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APPLICATIONS INFORMATION
RUN Pins
The LTC3892/LTC3892-1/LTC3892-2 is enabled using
the RUN1 and RUN2 pins. The RUN pins have a rising
threshold of 1.275V with 75mV of hysteresis. Pulling a RUN
pin below 1.2V shuts down the main control loop for that
channel. Pulling both RUN pins below 0.7V disables the
controllers and most internal circuits, including the DRVCC
and INTVCC LDOs. In this state, the LTC3892/LTC3892-1/
LTC3892-2 draws only 3.6µA of quiescent current.
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Because of
condensation or other small board leakage pulling the pin
down, it is recommended the RUN pins be externally pulled
up or driven directly by logic. Each RUN pin can tolerate
up to 65V (absolute maximum), so it can be conveniently
tied to VIN in always-on applications where one or more
controllers are enabled continuously and never shut down.
The RUN pins can be implemented as a UVLO by con-
necting them to the output of an external resistor divider
network off VIN, as shown in Figure 4.
3892 F04
1/2 LTC3892/
LTC3892-1/
LTC3892-2
RUN
RB
RA
VIN
Figure 4. Using the RUN Pins as a UVLO
The rising and falling UVLO thresholds are calculated using
the RUN pin thresholds and pull-up current:
VUVLO(RISING) =1.275V 1+RB
RA
– 150nA •RB
VUVLO(FALLING) =1.20V 1+RB
RA
– 150nA • RB
Tracking and Soft-Start (TRACK/SS1, TRACK/SS2 Pins)
The start-up of each VOUT is controlled by the voltage on
the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/SS2
for channel 2). When the voltage on the TRACK/SS pin
is less than the internal 0.8V reference, the LTC3892/
LTC3892-1/LTC3892-2 regulates the VFB pin voltage to
the voltage on the TRACK/SS pin instead of the internal
reference. The TRACK/SS pin can be used to program
an external soft-start function or to allow VOUT to track
another supply during start-up.
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure5.
An internal 10μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin. The
LTC3892/LTC3892-1/LTC3892-2 will regulate its feedback
voltage (and hence VOUT) according to the voltage on the
TRACK/SS pin, allowing VOUT to rise smoothly from 0V
to its final regulated value. The total soft-start time will be
approximately:
tSS =CSS •
0.8V
10µA
38921 F06
1/2 LTC3892/
LTC3892/
LTC3892-2
TRACK/SS
GND
CSS
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
LTC3892/
LTC3892-1/LTC3892-2
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APPLICATIONS INFORMATION
Alternatively, the TRACK/SS1 and TRACK/SS2 pins can
be used to track two (or more) supplies during start-up,
as shown qualitatively in Figures 6a and 6b. To do this, a
resistor divider should be connected from the master sup-
ply (VX) to the TRACK/SS pin of the slave supply (VOUT),
as shown in Figure 7. During start-up VOUT will track VX
according to the ratio set by the resistor divider:
V
X
VOUT
=
R
A
RTRACKA
•
R
TRACKA
+R
TRACKB
RA+RB
For coincident tracking (VOUT = VX during start-up),
RA = RTRACKA
RB = RTRACKB
Figure 6. Two Different Modes of Output Voltage Tracking
38921
F07a
VX(MASTER)
VOUT(SLAVE)
OUTPUT (V
OUT
)
TIME
(6a) Coincident Tracking
38921 F07b
VX(MASTER)
VOUT(SLAVE)
OUTPUT (V
OUT
)
TIME
(6b) Ratiometric Tracking
38921
F08
1/2 LTC3892/
LTC3892-1/
LTC3892-2
VFB
TRACK/SS
RB
RA
V
OUT
RTRACKB
RTRACKA
VX
Figure 7. Using the TRACK/SS Pin for Tracking
DRVCC and INTVCC Regulators and EXTVCC
(OPTI-DRIVE)
The LTC3892/LTC3892-1/LTC3892-2 features two separate
internal P-channel low dropout linear regulators (LDO) that
supply power at the DRVCC pin from either the VIN supply
pin or the EXTVCC pin depending on the connections of
the EXTVCC, DRVSET, and DRVUV pins. A third P-channel
LDO supplies power at the INTVCC pin from the DRVCC pin.
DRVCC powers the gate drivers whereas INTVCC powers
much of the LTC3892/LTC3892-1/LTC3892-2’s internal
circuitry. The VIN LDO and the EXTVCC LDO regulate DRVCC
between 5V to 10V, depending on how the DRVSET pin
is set. Each of these LDOs can supply a peak current of
at least 50mA and must be bypassed to ground with a
minimum of 4.7μF ceramic capacitor. Good bypassing is
needed to supply the high transient currents required by
the MOSFET gate drivers and to prevent interaction between
the channels. The INTVCC supply must be bypassed with
a 0.1μF ceramic capacitor.
The DRVSET pin programs the DRVCC supply voltage and
the DRVUV pin selects different DRVCC UVLO and EXTVCC
switchover threshold voltages. Table 2a summarizes the
different DRVSET pin configurations along with the volt-
age settings that go with each configuration. Table 2b
summarizes the different DRVUV pin settings. Tying the
LTC3892/
LTC3892-1/LTC3892-2
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APPLICATIONS INFORMATION
DRVSET pin to INTVCC programs DRVCC to 10V. Tying the
DRVSET pin to GND programs DRVCC to 6V. By placing
a 50k to 100k resistor between DRVSET and GND the
DRVCC voltage can be programmed between 5V to 10V,
as shown in Figure 8.
Table 2a
DRVSET PIN DRVCC VOLTAGE
GND 6V
INTVCC 10V
Resistor to GND 50k to 100k 5V to 10V
Table 2b
DRVUV PIN
DRVCC UVLO
RISING / FALLING
THRESHOLDS
EXTVCC SWITCHOVER
RISING / FALLING
THRESHOLD
GND 4.0V / 3.8V 4.7V / 4.45V
INTVCC 7.5V / 6.7V 7.7V / 7.45V
IC in this case is highest and is equal to VIN • IDRVCC. The
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
For example, using the LTC3892 in the QFN package, the
DRVCC current is limited to less than 31mA from a 40V
supply when not using the EXTVCC supply at a 70°C ambi-
ent temperature:
TJ = 70°C + (31mA)(40V)(44°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the VIN supply current must be checked while
operating in forced continuous mode (PLLIN/MODE =
INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above its
switchover threshold, the VIN LDO is turned off and the
EXTVCC LDO is enabled. The EXTVCC LDO remains on as
long as the voltage applied to EXTVCC remains above the
switchover threshold minus the comparator hysteresis.
The EXTVCC LDO attempts to regulate the DRVCC voltage
to the voltage as programmed by the DRVSET pin, so while
EXTVCC is less than this voltage, the LDO is in dropout
and the DRVCC voltage is approximately equal to EXTVCC.
When EXTVCC is greater than the programmed voltage,
up to an absolute maximum of 14V, DRVCC is regulated
to the programmed voltage.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC3892/
LTC3892-1/LTC3892-2’s switching regulator outputs
(4.7V/7.7V ≤ VOUT ≤ 14V) during normal operation and
from the VIN LDO when the output is out of regulation (e.g.,
start-up, short circuit). If more current is required through
the EXTVCC LDO than is specified, an external Schottky
diode can be added between the EXTVCC and DRVCC pins.
In this case, do not apply more than 10V to the EXTVCC
pin and make sure that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering DRVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
Figure 8. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
DRVSET PIN RESISTOR (kΩ)
50
4
DRV
CC
VOLTAGE (V)
5
7
8
9
11
55 75 85
38921 F09
6
10
70 95
100
60 65 80 90
High input voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum
junction temperature rating for the LTC3892/LTC3892-1/
LTC3892-2 to be exceeded. The DRVCC current, which is
dominated by the gate charge current, may be supplied by
either the VIN LDO or the EXTVCC LDO. When the voltage
on the EXTVCC pin is less than its switchover threshold
(4.7V or 7.7V as determined by the DRVUV pin described
above), the VIN LDO is enabled. Power dissipation for the
LTC3892/
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For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (31mA)(8.5V)(44°C/W) = 82°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive DRVCC power from the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC grounded. This will cause DRVCC to be
powered from the internal VIN regulator resulting in
increased power dissipation in the LTC3892/LTC3892-1/
LTC3892-2 at high input voltages.
2. EXTVCC connected directly to VOUT. This is the normal
connection for a 5V to 14V regulator and provides the
highest efficiency.
3.
EXTVCC connected to an external supply. If an external
supply is available in the 5V to 14V range, it may be used to
power EXTVCC providing it is compatible with the MOSFET
gate drive requirements. Ensure that EXTVCC < VIN.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V/7.7V.
Topside MOSFET Driver Supply (CB)
External bootstrap capacitors, CB, connected to the
BOOST pins supply the gate drive voltage for the topside
MOSFET. The LTC3892/LTC3892-1/LTC3892-2 features
an internal switch between DRVCC and the BOOST pin
for each controller. These internal switches eliminate the
need for external bootstrap diodes between DRVCC and
BOOST. Capacitor CB in the Functional Diagram is charged
through this internal switch from DRVCC when the SW
pin is low. When the topside MOSFET is to be turned on,
the driver places the CB voltage across the gate-source
of the MOSFET. This enhances the top MOSFET switch
and turns it on. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply: VBOOST = VIN
+ VDRVCC. The value of the boost capacitor, CB, needs to
be 100 times that of the total input capacitance of the
topside MOSFET(s).
Fault Conditions: Current Limit and
Current Foldback
The LTC3892/LTC3892-1 (not the LTC3892-2) includes
current foldback to help limit load current when an output
is shorted to ground. If the output voltage falls below
70% of its nominal output level, then the maximum sense
voltage is progressively lowered from 100% to 40% of its
maximum selected value.
Under short-circuit conditions with very low duty cycles,
the channel will begin cycle skipping in order to limit
the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC3892/LTC3892-1/LTC3892-2 (≈80ns), the input voltage
and inductor value:
∆IL(SC) =tON(MIN)
V
IN
L
The resulting average short-circuit current is:
ISC =40%•ILIM(MAX) −
1
2
∆IL(SC)
(LTC3892/LTC3892-1)
ISC =ILIM(MAX) −
1
2
∆IL(SC
)
(LTC3892-2)
Fault Conditions: Overvoltage Protection (Crowbar)
(LTC3892/LTC3892-1; not on LTC3892-2)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller
is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
LTC3892/
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APPLICATIONS INFORMATION
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if VOUT returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal power
dissipation causes excessive self heating on chip (such as
DRVCC short to ground), the overtemperature shutdown cir-
cuitry will shut down the LTC3892/LTC3892-1/LTC3892-2.
When the junction temperature exceeds approximately
175°C, the overtemperature circuitry disables the DRVCC
LDO, causing the DRVCC supply to collapse and effectively
shutting down the entire LTC3892/LTC3892-1/LTC3892-2
chip. Once the junction temperature drops back to the ap-
proximately 155°C, the DRVCC LDO turns back on. Long-
term overstress (TJ > 125°C) should be avoided as it can
degrade the performance or shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3892/LTC3892-1/LTC3892-2 has an internal
phase-locked loop (PLL) comprised of a phase frequency
detector, a lowpass filter, and a voltage-controlled oscilla-
tor (VCO). This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn-on
of controller 2’s top MOSFET is thus 180° out of phase
with the external clock. The phase detector is an edge
sensitive digital type that provides zero degrees phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics
of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than fOSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3892/LTC3892-1/LTC3892-2 can only
be synchronized to an external clock whose frequency is
within range of the LTC3892/LTC3892-1/LTC3892-2’s
internal VCO, which is nominally 55kHz to 1MHz. This is
guaranteed to be between 75kHz and 850kHz. Typically,
the external clock (on the PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.1V.
The LTC3892/LTC3892-1/LTC3892-2 is guaranteed to
synchronize to an external clock that swings up to at least
2.5V and down to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
38921 F10
400
200
500
700
900
300
100
065 75 85 95 105 115
125
Figure 9. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
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Table 3 summarizes the different states in which the FREQ
pin can be used. When synchronized to an external clock,
the LTC3892/LTC3892-1/LTC3892-2 operates in forced
continuous mode at light loads.
Table 3
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor to GND DC Voltage 50kHz to 900kHz
Any of the Above External Clock
75kHz to 850kHz
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3892/LTC3892-1/LTC3892-2 is capable of
turning on the top MOSFET. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle applications may approach
this minimum on-time limit and care should be taken to
ensure that:
tON(MIN) <
V
OUT
V
IN
(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3892/LTC3892-1/
LTC3892-2 is approximately 80ns. However, as the peak
sense voltage decreases, the minimum on-time gradually
increases up to about 130ns. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3892/LTC3892-1/LTC3892-2 circuits: 1) IC
VIN current, 2) DRVCC regulator current, 3) I2R losses, 4)
Topside MOSFET transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (<0.1%) loss.
2. DRVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from DRVCC to ground. The resulting dQ/dt is a cur-
rent out of DRVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying DRVCC from an output-derived source power
through EXTVCC will scale the VIN current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of DRVCC current results in approximately 2.5mA
of VIN current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs
have approximately the same RDS(ON), then the resis-
tance of one MOSFET can simply be summed with the
resistances of L, RSENSE and ESR to obtain I2R losses.
LTC3892/
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APPLICATIONS INFORMATION
For example, if each RDS(ON) = 30mΩ, RL = 50mΩ,
RSENSE = 10mΩ and RESR = 40mΩ (sum of both input
and output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the top MOSFET(s), and
become significant only when operating at high input
voltages (typically 20V or greater). Transition losses
can be estimated from:
Transition Loss = (1.7) • VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including Schottky conduction losses during
dead-time and inductor core losses generally account
for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recov-
ery time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response to
be optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 12 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output ca-
pacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
LTC3892/
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A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise-time
should be controlled so that the load rise-time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V (maximum), VOUT = 3.3V, IMAX =
5A, VSENSE(MAX) = 75mV and f = 350kHz. The inductance
value is chosen first based on a 30% ripple current as-
sumption. The highest value of ripple current occurs at
the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
∆IL=VOUT
f
( )
L
( )
1−VOUT
VIN(NOM)
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
V
OUT
VIN(MAX) f
( )
=
3.3V
22V 350kHz
( )
=429ns
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (66mV):
RSENSE ≤
66mV
5.73A
≈0.01
Ω
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
PMAIN =
3.3V
22V 5A
( )
21+0.005
( )
50°C−25°C
( )
0.035Ω
( )
+22V
( )
25A
22.5Ω
( )
215pF
( )
•
1
6V−2.3V +1
2.3V
350kHz
( )
=308mW
A short-circuit to ground will result in a folded back current of:
ISC =34mV
0.01Ω−1
2
80ns 22V
( )
4.7µH
=3.21A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = (3.21A)2 (1.125) (0.022Ω) = 255mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VO(RIPPLE) = RESR (∆IL) = 0.02Ω (1.45A) = 29mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Figure 10 illustrates the current waveforms present in
the various branches of the 2-phase synchronous buck
regulators operating in the continuous mode. Check the
following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
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2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CDRVCC must return to the combined COUT (–) termi-
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Does the LTC3892/LTC3892-1/LTC3892-2 VFB pin’s
resistive divider connect to the (+) terminal of COUT?
The resistive divider must be connected between the
(+) terminal of COUT and signal ground. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the DRVCC and decoupling capacitor connected close
to the IC, between the DRVCC and the ground pin? This
capacitor carries the MOSFET drivers’ current peaks.
6. Keep the switching nodes (SW1, SW2), top gate (TG1,
TG2), and boost nodes (BOOST1, BOOST2) away from
sensitive small-signal nodes, especially from the op-
R
L1
L1
SW1 RSENSE1 VOUT1
COUT1
VIN
CIN
R
IN
R
L2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L2
SW2
38921 F11
RSENSE2 VOUT2
COUT2
Figure 10. Branch Current Waveforms
LTC3892/
LTC3892-1/LTC3892-2
31
38921fc
For more information www.linear.com/LTC3892
APPLICATIONS INFORMATION
posites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the output side
of the LTC3892/LTC3892-1/LTC3892-2 and occupy
minimum PC trace area.
7. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the DRVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold—typi-
cally 25% of the maximum designed current level in Burst
Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both should multiple controllers be turned on at the same
time. A particularly difficult region of operation is when
one channel is nearing its current comparator trip point
when the other channel is turning on its top MOSFET. This
occurs around 50% duty cycle on either channel due to
the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
LTC3892/
LTC3892-1/LTC3892-2
32
38921fc
For more information www.linear.com/LTC3892
TYPICAL APPLICATIONS
C
DRVCC
4.7µF
MBOT2
MTOP2
C
B2
0.1µF
L2
15µH
8mΩ
R
SNS2
CITH2B
100pF
R
A2
100k
R
B2
7.15k
C
OUT2B
10µF
RITH2
34.8k
C
ITH2A
1nF
C
OUT2A
150µF
C
SNS2
1nF
C
SS2
0.1µF
C
INTVCC
0.1µF
MBOT1
MTOP1
C
B1
0.1µF
L1
5.6µH
5mΩ
R
SNS1
C
ITH1B
100pF
C
OUT1B
10µF
RITH1
7.5k
CITH1A
2.2nF
C
OUT1A
220µF
C
SNS1
1nF
C
SS1
0.1µF
RPG1
1000k
RPG2
1000k
C
INB
2.2µF
x5
C
INA
47µF
R
FREQ
35.7k
LTC3892
VIN
RUN2
INTV
CC
PLLIN/MODE
GND
FREQ
SW2
BG2
TG2
BOOST2
SENSE2+
V
FB2
ITH2
TRACK/SS2
12V*
SENSE2–
DRVUV
EXTV
CC
PGOOD2
DRV
CC
RUN1
SW1
BG1
TG1
BOOST1
SENSE1+
V
FB1
ITH1
TRACK/SS1
SENSE1–
DRVSET
VPRG1
PGOOD1
V
OUT2
V
OUT2
5A
5V
V
OUT1
8A
VIN
TOP1, TOP2: BSC057N08NS3
8V TO 60V
BOT1, BOT2: BSC036NE7NS3
L1: COILCRAFT XAL1010-562ME
L2: COILCRAFT XAL1010-153ME
ILIM
3892 TA02
*V
OUT2
FOLLOWS V
IN
WHEN V
IN
≤ 12V
Figure 11. High Efficiency Dual 5V/12V Step-Down Converter with 10V Gate Drive
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
vs Load Current
Efficiency and Power Loss
3892 TA02b
EFFICIENCY
V
IN
= 12V
V
OUT
= 5V
POWER LOSS
LTC3892/
LTC3892-1/LTC3892-2
33
38921fc
For more information www.linear.com/LTC3892
TYPICAL APPLICATIONS
Figure 12. High Efficiency Dual 3.3V/8.5V Step-Down Converter with 6V Gate Drive
C
DRVCC
4.7µF
MBOT2
MTOP2
C
B2
0.1µF
L2
8.0µH
10mΩ
R
SNS2
C
ITH2B
OPT
R
A2
100k
R
B2
10.5k
C
OUT2B
10µF
R
ITH2
34.8k
C
ITH2A
470pF
C
OUT2A
330µF
C
SNS2
1nF
C
SS2
0.01µF
C
INTVCC
0.1µF
MBOT1
MTOP1
C
B1
0.1µF
L1
4.7µH
8mΩ
R
SNS1
C
ITH1B
100pF
C
OUT1B
10µF
R
ITH1
20k
C
ITH1A
1nF
C
OUT1A
470µF
C
SNS1
1nF
C
SS1
0.01µF
R
PG1
100k
R
PG2
100k
C
INB
2.2µF
C
INA
100µF
R
FREQ
41.2k
LTC3892
VIN
RUN2
INTV
CC
PLLIN/MODE
GND
FREQ
SW2
BG2
TG2
BOOST2
SENSE2+
V
FB2
ITH2
TRACK/SS2
SENSE2–
DRVUV
EXTV
CC
PGOOD2
DRV
CC
RUN1
SW1
BG1
TG1
BOOST1
SENSE1+
V
FB1
ITH1
TRACK/SS1
SENSE1–
DRVSET
VPRG1
PGOOD1
V
OUT2
VOUT2
8.5V*
3A
3.3V
V
OUT1
5A
VIN
TOP1, TOP2, BOT1, BOT2: RJK0651DPB
4.5V TO 60V
L1: COILCRAFT SER1360-472KL
L2: COILCRAFT SER1360-802KL
x3
C
OUT2A
: SANYO 10TPE330M
C
OUT1A
: SANYO 6TPE470M
ILIM
3892 TA03
*VOUT2 FOLLOWS VIN WHEN VIN ≤ 8.5V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
0.1
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
vs Load Current
Efficiency and Power Loss
3892 TA03b
V
IN
= 12V
V
OUT
= 3.3V
EFFICIENCY
POWER LOSS
LTC3892/
LTC3892-1/LTC3892-2
34
38921fc
For more information www.linear.com/LTC3892
TYPICAL APPLICATIONS
Figure 13. High Efficiency Dual-Phase Step-Down 5V/8.5V Converter with 8V Gate Drive
CDRVCC
4.7µF
MBOT2
MTOP2
C
B2
0.1µF
L2
6.5µH
15mΩ
R
SNS2
CITH2B
68pF
R
A2
649k
R
B2
68.1k
C
4.7µF
OUT2B
R
ITH2
15kk
CITH2A
2.2nF
C
OUT2A
68µF
C
SNS2
1nF
CSS2
0.1µF
CINTVCC
0.1µF
MBOT1
MTOP1
C
B1
0.1µF
L1
4.9µH
9mΩ
R
SNS1
C
ITH1B
100pF
COUT1B
22µF
R
ITH1
15k
C
ITH1A
1.5nF
COUT1A
220µF
CSNS1
1nF
CSS1
0.1µF
CINB
2.2µF
x3
C
INA
33µF
R
80.6k
DRVCC
R
A1
357k
R
B1
68.1k
LTC3892
-1
VIN
RUN2
INTVCC
PLLIN/MODE
GND
SW2
BG2
TG2
BOOST2
SENSE2+
V
FB2
ITH2
TRACK/SS2
SENSE2–
DRVUV
EXTV
CC
DRV
CC
RUN1
SW1
BG1
TG1
BOOST1
SENSE1+
V
FB1
ITH1
TRACK/SS1
SENSE1–
DRVSET
V
OUT2
VOUT2
8.5V*
3A
VOUT1
5V
5A
VIN
4.5V TO 60V
TOP1, TOP2, BOT1, BOT2: BSZ123N08NS3
L1: WURTH 744314490
L2: WURTH 744314490
C
OUT2A
: SANYO 10TPC68M
C
OUT1A
: SANYO 6TPB220ML
FREQ
3892 TA05
*VOUT2 FOLLOWS VIN WHEN VIN ≤ 8.5V
LTC3892/
LTC3892-1/LTC3892-2
35
38921fc
For more information www.linear.com/LTC3892
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3892#packaging for the most recent package drawings.
FE28 (EA) TSSOP REV L 0117
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678 9 10 11 12 13 14
192022 21 151618 17
9.60 – 9.80*
(.378 – .386)
7.56
(.298)
3.05
(.120)
28 2726 25 24 23
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
7.56
(.298)
3.05
(.120)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EA
LTC3892/
LTC3892-1/LTC3892-2
36
38921fc
For more information www.linear.com/LTC3892
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3892#packaging for the most recent package drawings.
5.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
0.75 ±0.05 R = 0.115
TYP
0.25 ±0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.50 REF
(4 SIDES)
4.10 ±0.05
5.50
±0.05
0.25 ±0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
3.45 ±0.05
3.45 ±0.05
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
LTC3892/
LTC3892-1/LTC3892-2
37
38921fc
For more information www.linear.com/LTC3892
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/15 Add LTC3892-2 Version 1 to 38
B 05/16 Modified graph, Oscillator Frequency vs Temperature 10
C 07/17 Corrected LTC3892-2 Part Marking
Corrected EXTVCC Pin Description
5
11
LTC3892/
LTC3892-1/LTC3892-2
38
38921fc
For more information www.linear.com/LTC3892
LINEAR TECHNOLOGY CORPORATION 2015
LT 0717 REV C • PRINTED IN USA
www.linear.com/LTC3892
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LTC3890/LTC3890-1
LTC3890-2/LTC3890-3
60V, Low IQ, Dual 2-Phase Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V≤VOUT≤24V, IQ = 50μA
LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC Controller
with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V≤VOUT≤24V, IQ = 50μA
LTC3864 60V, Low IQ, High Voltage DC/DC Controller
with 100% Duty Cycle
Fixed Frequency 50kHz to 850kHz, 3.5V ≤ VIN ≤ 60V,
0.8V≤VOUT≤VIN, IQ = 40μA, MSOP-12E, 3mm × 4mm DFN-12
LTC3899 60V, Triple Output, Buck/Buck/Boost Synchronous
Controller with 29µA Burst Mode IQ
4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V,
Buck VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V
LTC3859AL 38V, Low IQ, Triple Output, Buck/Buck/Boost Synchronous
Controller with 28µA Burst Mode IQ
4.5V (Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V,
Buck VOUT Range: 0.8V to 24V, Boost VOUT Up to 60V,
LTC3857/LTC3857-1
LTC3858/LTC3858-1
38V, Low IQ, Dual Output 2-Phase Synchronous
Step-Down DC/DC Controller with 99% Duty Cycle
PLL Fixed Operating Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 24V, IQ = 50μA/170μA
LTC3807 38V, Low IQ, Synchronous Step-Down Controller with
24V Output Voltage Capability
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
0.8V≤VOUT≤24V, IQ = 50μA
C
DRVCC
4.7µF
MBOT2
MTOP2
C
B2
0.1µF
L2
10µH
3mΩ
R
SNS2
C
OUT2B
10µF
C
OUT2A
150µF
C
SNS2
1nF
C
INTVCC
0.1µF
MBOT1
MTOP1
C
B1
0.1µF
L1
10µH
3mΩ
R
SNS1
C
ITH1B
47pF
C
OUT1B
10µF
R
ITH1
9.78k
C
ITH1A
4.7nF
C
OUT1A
150µF
C
SNS1
1nF
C
SS1
0.1µF
C
INB
2.2µF
C
INA
100µF
R
FREQ
29.4k
R
A1
100k
R
B1
7.15k
C
ITH2A
47pF
LTC3892
-1
VIN
RUN2
INTV
CC
PLLIN/MODE
GND
FREQ
SW2
BG2
TG2
BOOST2
SENSE2+
V
FB2
ITH2
TRACK/SS2
12V
SENSE2–
DRVUV
EXTV
CC
DRV
CC
RUN1
SW1
BG1
TG1
BOOST1
SENSE1+
V
FB1
ITH1
TRACK/SS1
SENSE1–
DRVSET
VOUT
VOUT
30A
VIN
TOP1, TOP2: BSC123N08NS3G
16V TO 60V
BOT1, BOT2: BSC047N08NS3G
L1, L2: COILCRAFT SER2918H-103KL
x5
x2
x2
x2
x2
3892 TA04
Figure 14. High Current Dual-Phase Single Output Step-Down 12V Converter