Data Sheet No. PD60200 revB
Features
•Floating channel designed for bootstrap operation
to +600V. Tolerant to negative transient voltage
dV/dt immune
•Gate drive supply range from 10 to 20V
•Under voltage lockout for both channels
•3.3V, 5V, and 15V input logic input compatible
•Cross-conduction prevention logic
•Matched propagation delay for both channels
•Lower di/dt gate driver for better noise immunity
•Internal 100ns dead-time
•Output in phase with input
HALF-BRIDGE DRIVER
Product Summary
VOFFSET 600V max.
IO+/- (min) 60 mA/130 mA
VOUT 10 - 20V
Delay Matching 50 ns
Internal deadtime 100 ns
ton/off (typ.) 220/220 ns
IR2304(S) & (PbF)
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LIN
HIN
VCC
COM
VB
HO
VS
LO
Vcc
HIN
LIN
up to 600V
TO
LOAD
IR2304
Block Diagram
Package
8 Lead SOIC
8-Lead PDIP
Part Input
logic
Cross-
conduction
prevention
logic
Dead-Time Ground Pins
2106/2301 COM
21064 HIN/LIN no none VSS/COM
2108 Internal 540ns COM
21084 HIN/LIN yes Programmable 0.54~5 µsVSS/COM
2109/2302 Internal 540ns COM
21094 IN/SD yes Programmable 0.54~5 µsVSS/COM
2304 HIN/LIN yes Internal 100ns COM
2106/2301/2108/2109/2302/2304 Feature Comparison
•Available in Lead-Free
Description
The IR2304(S) are a high voltage, high speed
power MOSFET and IGBT driver with inde-
pendent high and low side referenced output
channels. Proprietary HVIC and latch immune
CMOS technologies
enable ruggedized monolithic construction.
The logic input is compatible with standard
CMOS or LSTTL output, down to 3.3V logic.
The output driver features a high pulse cur-
rent buffer stage designed for minimum driver
cross-conduction. The floating channel can be
used to drive an N-channel power MOSFET
or IGBT in the high side configuration which
operates up to 600 volts.
IR2304(S)&(PbF)
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Note 1: Logic operational for VS of COM -5 to COM +600V. Logic state held for VS of COM -5V to COM -VBS.
Symbol Definition Min. Max. Units
VSHigh side offset voltage VB - 25 VB + 0.3
VBHigh side floating supply voltage -0.3 625
VHO High side floating output voltage HO VS - 0.3 VB + 0.3
VCC Low side and logic fixed supply voltage -0.3 25
VLO Low side output voltage LO -0.3 VCC + 0.3
VIN Logic input voltage (HIN, LIN) -0.3 VCC + 0.3
Com Logic ground VCC -25 VCC + 0.3
dVS/dt Allowable offset voltage SLEW RATE — 50 V/ns
PDPackage power dissipation @ TA ≤ +25°C 8-Lead SOIC — 0.625
8-Lead PDIP — 1.0
RthJA Thermal resistance, junction to ambient 8-Lead SOIC — 200
8-Lead PDIP — 125
TJJunction temperature — 15 0
TSStorage temperature -50 150
TLLead temperature (soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
V
°C
Symbol Definition Min. Max. Units
VBHigh side floating supply voltage VS + 10 VS + 20
VSHigh side floating supply offset voltage Note 1 600
VHO High side (HO) output voltage VSVB
VLO Low side (LO) output voltage COM VCC
VIN Logic input voltage (HIN, LIN) COM VCC
VCC Low side supply voltage 10 20
TAAmbient temperature -40 125 °C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
V
W
°C/W
IR2304(S)&(PbF)
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Symbol Definition Min. Typ. Max. Units Test Conditions
VCCUV+ VCC and VBS supply undervoltage positive going 8 8.9 9.8
VBSUV+ threshold
VCCUV- VCC and VBS supply undervoltage negative going 7.4 8.2 9
VBSUV- threshold
VCCUVH VCC supply undervoltage lockout hysteresis 0.3 0.7 —
VBSUVH
ILK Offset supply leakage current — — 50 VB = VS = 600V
IQBS Quiescent VBS supply current 20 60 150 VIN = 0V or 5V
IQCC Quiescent VCC supply current 50 120 240 VIN = 0V or 5V
VIH Logic “1” input voltage 2.3 ——
VIL Logic “0” input voltage — — 0.8
VOH High level output voltage, VBIAS - VO— — 2.8
VOL Low level output voltage, VO— — 1.2
IIN+ Logic “1” input bias current — 5 40 VIN = 5V
IIN- Logic “0” input bias current — 1 . 0 2.0 VIN = 0V
IO+ Output high short circuit pulse current 60 — —
IO- Output low short circuit pulsed current 130 — —
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
COM. The VO and IO parameters are referenced to COM and VS is applicable to HO and LO.
V
V
Symbol Definition Min. Typ. Max. Units Test Conditions
ton T urn-on propagation delay 120 220 320 VS = 0V
toff Turn-off propagation delay 130 220 330 VS = 0V or 600V
trTurn-on rise time 60 200 300
tfTurn-off fall time 20 100 170
DT Dead time 80 100 190
MT Delay matching, HS & LS turn-on/off — — 50
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, VS = COM, CL = 1000 pF and TA = 25°C unless otherwise specified.
VO = 0V
PW ≤ 10 µs
ns
µA
IO = 20mA
mA
µA
IR2304(S)&(PbF)
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Functional Block Diagram
2304
LIN
UV
DETECT
DELAY COM
LO
VCC
HIN VS
HO
VB
PULSE
FILTER
HV
LEVEL
SHIFTER
R
R
S
Q
UV
DETECT
PULSE
GENERATOR
SHOOT-
THROUGH
PREVENTION
Lead Definitions
Symbol Description
VCC Low side supply voltage
COM Logic ground and low side driver return
HIN Logic input for high side gate driver output
LIN Logic input for low side gate driver output
VBHigh side floating supply
HO High side driver output
VSHigh voltage floating supply return
LO Low side driver output
IR2304(S)&(PbF)
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8
7
6
4
3
2
1LIN
COM
HIN
VCC
LO
HO
VB
VS
5
8-Lead PDIP
8
7
6
4
3
2
1LIN
COM
HIN
VCC
LO
HO
VB
VS
5
Lead Assignments
8-Lead SOIC
HIN
LIN
HO
LO
Figure 1. Input/Output Functionality Diagram
Internal Deadtime
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Figure 3. Internal Deadtime Timing
Figure 2. Switching Time Waveforms
HIN LIN
HO
LO
ton tr
50%
90%
10%
50%
90%
10%
toff tf
HIN
LIN
DT DT
90%
10%
50%
90%
10%
50%
LO
HO
IR2304(S)&(PbF)
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01-6027
01-0021 11 (MS-012AA)
8 Lead SOIC
87
5
65
D B
E
A
e
6X
H
0.25 [.0 10] A
6
4312
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. D IMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES].
7
K x 45°
8X L 8X c
y
FOOTPRINT
8X 0.72 [.028]
6.46 [.255]
3X 1.2 7 [.050] 8X 1.78 [.070]
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUS IONS.
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUS IONS.
MOLD PROTRUSIONS NOT TO EXCEED 0 .25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0 .15 [.006].
0.25 [. 010] C A B
e1 A
A1
8X b
C
0.10 [.004 ]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BA SIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BA SIC 0.635 BASIC
01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
Case outlines
IR2304(S)&(PbF)
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This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web Site.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
09/10/04
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