19-3065; Rev 0; 1/04 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs The MAX5520/MAX5521 are single, 10-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs) offering Rail-to-Rail(R) buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and consume less than 6A, making them desirable for lowpower and low-voltage applications. A shutdown mode reduces overall current, including the reference input current, to just 0.18A. The MAX5520/MAX5521 use a 3-wire serial interface that is compatible with SPITM, QSPITM, and MICROWIRETM. At power-up, the MAX5520/MAX5521 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that must be off during power-up. The zero-scale outputs enable glitch-free power-up. The MAX5520 accepts an external reference input. The MAX5521 contains an internal reference and provides an external reference output. Both devices have forcesense-configured output buffers. The MAX5520/MAX5521 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin QFN package and are guaranteed over the extended -40C to +85C temperature range. For 12-bit compatible devices, refer to the MAX5530/ MAX5531 data sheet. For 8-bit compatible devices, refer to the MAX5510/MAX5511 data sheet. Applications Features Single +1.8V to +5.5V Supply Ultra-Low 6A Supply Current Shutdown Mode Reduces Supply Current to 0.18A (max) Small 4mm x 4mm x 0.8mm Thin QFN Package Flexible Force-Sense-Configured Rail-to-Rail Output Buffers Internal Reference Sources 8mA of Current (MAX5521) Fast 16MHz 3-Wire SPI-/QSPI-/MICROWIRECompatible Serial Interface TTL- and CMOS-Compatible Digital Inputs with Hysteresis Glitch-Free Outputs During Power-Up Ordering Information TEMP RANGE PIN-PACKAGE MAX5520ETC PART -40C to +85C 12 Thin QFN-EP* MAX5521ETC -40C to +85C 12 Thin QFN-EP* *EP = Exposed paddle (internally connected to GND). Portable Battery-Powered Devices Instrumentation Automatic Trimming and Calibration in Factory or Field Programmable Voltage and Current Sources Pin Configuration TOP VIEW Industrial Process Control and Remote Industrial Devices Remote Data Conversion and Monitoring CS 1 Programmable Liquid Crystal Display (LCD) Bias SCLK 2 Selector Guide DIN 3 FB N.C. OUT 12 11 10 9 GND 8 VDD 7 N.C. Chemical Sensor Cell Bias for Gas Monitors PART REFERENCE TOP MARK MAX5520ETC External AACQ MAX5521ETC Internal AACR MAX5520 MAX5521 4 5 REFIN (MAX5520) N.C. REFOUT(MAX5521) 6 N.C. THIN QFN Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5520/MAX5521 General Description MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT to GND ...............................................-0.3V to (VDD + 0.3V) FB to GND ..................................................-0.3V to (VDD + 0.3V) SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V) REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) Thin QFN (derate 16.9mW/C above +70C).............1349mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ..................................................... +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS STATIC ACCURACY (MAX5520 EXTERNAL REFERENCE) Resolution N Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Error (Note 2) INL DNL VOS MIN 1 4 VDD = 1.8V, VREF = 1.024V 1 4 Guaranteed monotonic, VDD = 5V, VREF = 4.096V 0.2 1 Guaranteed monotonic, VDD = 1.8V, VREF = 1.024V 0.2 PSRR LSB LSB 1 VDD = 5V, VREF = 4.096V 1 20 VDD = 1.8V, VREF = 1.024V 1 20 2 GE UNITS Bits VDD = 5V, VREF = 4.096V 1 2 VDD = 1.8V, VREF = 1.024V 1 2 1.8V VDD 5.5V mV V/C VDD = 5V, VREF = 4.096V Gain-Error Temperature Coefficient Power-Supply Rejection Ratio MAX 10 Offset-Error Temperature Drift Gain Error (Note 3) TYP LSB 4 ppm/C 85 dB STATIC ACCURACY (MAX5521 INTERNAL REFERENCE) Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Offset Error (Note 2) N INL DNL VOS 10 VDD = 5V, VREF = 3.9V 1 4 VDD = 1.8V, VREF = 1.2V 1 4 Guaranteed monotonic, VDD = 5V, VREF = 3.9V 0.2 1 Guaranteed monotonic, VDD = 1.8V, VREF = 1.2V 0.2 Gain-Error Temperature Coefficient 2 1 1 20 VDD = 1.8V, VREF = 1.2V 1 20 2 GE LSB LSB VDD = 5V, VREF = 3.9V Offset-Error Temperature Drift Gain Error (Note 3) Bits V/C VDD = 5V, VREF = 3.9V 1 2 VDD = 1.8V, VREF = 1.2V 1 2 4 _______________________________________________________________________________________ mV LSB ppm/C +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs (VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Power-Supply Rejection Ratio SYMBOL PSRR CONDITIONS MIN 1.8V VDD 5.5V TYP MAX 85 UNITS dB REFERENCE INPUT (MAX5520) Reference-Input Voltage Range VREFIN Reference-Input Impedance RREFIN 0 Normal operation VDD 4.1 In shutdown V M 2.5 G REFERENCE OUTPUT (MAX5521) Initial Accuracy VREFOUT Output-Voltage Temperature Coefficient VTEMPCO Line Regulation Load Regulation Output Noise Voltage Short-Circuit Current (Note 6) Capacitive Load Stability Range No external load, VDD = 1.8V 1.197 1.214 1.231 No external load, VDD = 2.5V 1.913 1.940 1.967 No external load, VDD = 3V 2.391 2.425 2.459 No external load, VDD = 5V 3.828 3.885 3.941 TA = -40C to +85C (Note 4) 12 30 ppm/C VREFOUT < VDD - 200mV (Note 5) 0.3 2 V/V 0 IREFOUT 1mA, sourcing, VDD = 1.8V, VREF = 1.2V 0.3 2 0 IREFOUT 8mA, sourcing, VDD = 5V, VREF = 3.9V 0.3 2 -150A IREFOUT 0, sinking 0.2 0.1Hz to 10Hz, VREFOUT = 3.9V 150 10Hz to 10kHz, VREFOUT = 3.9V 600 0.1Hz to 10Hz, VREFOUT = 1.2V 50 10Hz to 10kHz, VREFOUT = 1.2V 450 VDD = 5V 30 VDD = 1.8V 14 V V/A VP-P mA (Note 7) 0 to 10 nF Thermal Hysteresis (Note 8) 200 ppm Reference Power-Up Time (from Shutdown) REFOUT unloaded, VDD = 5V 5.4 REFOUT unloaded, VDD = 1.8V 4.4 Long-Term Stability ms 200 ppm/ 1khrs 1000 pF DAC OUTPUT (OUT) Capacitive Driving Capability Short-Circuit Current (Note 6) CL VDD = 5V, VOUT set to full scale, OUT shorted to GND, source current 65 VDD = 5V, VOUT set to 0V, OUT shorted to VDD, sink current 65 VDD = 1.8V, VOUT set to full scale, OUT shorted to GND, source current 14 VDD = 1.8V, VOUT set to 0V, OUT shorted to VDD, sink current 14 mA _______________________________________________________________________________________ 3 MAX5520/MAX5521 ELECTRICAL CHARACTERISTICS (continued) MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS TYP VDD = 5V VDD = 1.8V 3.8 Coming out of standby (MAX5521) VDD = 1.8V to 5.5V 0.4 DAC Power-Up Time Output Power-Up Glitch MIN Coming out of shutdown (MAX5520) MAX UNITS 3 CL = 100pF FB_ Input Current ms 10 mV 10 pA DIGITAL INPUTS (SCLK, DIN, CS) 4.5V VDD 5.5V Input High Voltage VIH 2.4 2.7V < VDD 3.6V VIL 4.5V VDD 5.5V 2.7V < VDD 3.6V 1.8V VDD 2.7V Input Leakage Current IIN (Note 9) Input Capacitance CIN Input Low Voltage V 2.0 1.8V VDD 2.7V 0.7 x VDD 0.8 0.6 0.3 x VDD 0.05 0.5 V A 10 pF Positive and negative (Note 10) 10 V/ms 0.1 to 0.9 of full scale to within 0.5 LSB (Note 10) 660 s DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Voltage-Output Settling Time 0.1Hz to 10Hz Output Noise Voltage 10Hz to 10kHz VDD = 5V 80 VDD = 1.8V 55 VDD = 5V 620 VDD = 1.8V 476 VP-P POWER REQUIREMENTS Supply Voltage Range VDD 1.8 MAX5520 Supply Current (Note 9) IDD MAX5521 Standby Supply Current Shutdown Supply Current 4 IDDSD IDDPD (Note 9) (Note 9) 5.5 VDD = 5V 2.6 4 VDD = 3V 2.6 4 VDD = 1.8V 3.6 5 VDD = 5V 5.3 7.0 VDD = 3V 4.8 7.0 VDD = 1.8V 5.4 7.0 VDD = 5V 3.3 4.5 VDD = 3V 2.8 4.0 VDD = 1.8V 2.4 3.5 0.05 0.25 _______________________________________________________________________________________ V A A A +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs (VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 16.7 MHz TIMING CHARACTERISTICS (VDD = 4.5V TO 5.5V) Serial Clock Frequency fSCLK 0 DIN to SCLK Rise Setup Time tDS 15 ns DIN to SCLK Rise Hold Time tDH 0 ns SCLK Pulse-Width High tCH 24 ns SCLK Pulse-Width Low tCL 24 ns CS Pulse-Width High tCSW 100 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CS Fall to SCLK Rise Setup Time tCSS 20 ns SCLK Fall to CS Fall Setup tCSO 0 ns CS Rise to SCK Rise Hold Time tCS1 20 ns TIMING CHARACTERISTICS (VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 MHz TIMING CHARACTERISTICS (VDD = 1.8V TO 5.5V) Serial Clock Frequency fSCLK 0 DIN to SCLK Rise Setup Time tDS 24 DIN to SCLK Rise Hold Time tDH 0 ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns CS Pulse-Width High tCSW 150 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns CS Fall to SCLK Rise Setup Time tCSS 30 ns SCLK Fall to CS Fall Setup tCSO 0 ns CS Rise to SCK Rise Hold Time tCS1 30 ns ns Note 1: Linearity is tested within codes 24 to 1020. Note 2: Offset is tested at code 24. Note 3: Gain is tested at code 1000. FB is connected to OUT. Note 4: Guaranteed by design. Not production tested. Note 5: VDD must be a minimum of 1.8V. Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that the package power dissipation is not exceeded. Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25C output voltage after cycling the device from TMAX to TMIN. Note 9: All digital inputs at VDD or GND. Note 10: Load = 10k in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521). _______________________________________________________________________________________ 5 MAX5520/MAX5521 TIMING CHARACTERISTICS Typical Operating Characteristics (VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5521) 6 5 4 3 7 6 5 4 3 2 2 1 1 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 35 60 85 -40 10 35 60 CS = LOGIC LOW CODE = 0 VREF = 1.2V 1.5 VDD = 5V 100 10 VDD = 1.8V ALL DIGITAL INPUTS SHORTED TOGETHER 4.5 4.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (A) VREF = 1.9V 5.0 MAX5520 toc05 1000 1.0 85 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 0 0 1 -15 10 35 60 85 0.01 0.1 1 10 100 0 1000 10000 100000 FREQUENCY (kHz) LOGIC INPUT VOLTAGE (V) INL vs. INPUT CODE (VDD = VREF = 1.8V) INL vs. INPUT CODE (VDD = VREF = 5V) DNL vs. INPUT CODE (VDD = VREF = 1.8V) 0.2 0 -0.2 -0.2 INL (LSB) 0 -0.4 0.05 0.04 0.03 DNL (LSB) 0.2 0.06 -0.4 0.02 0.01 -0.6 -0.6 -0.8 -0.8 -0.01 -1.0 -1.0 -0.02 -1.2 0 -0.03 -1.2 200 400 600 800 DIGITAL INPUT CODE 1000 1200 MAX5520 toc09 0.4 MAX5520 toc07 0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (C) MAX5520 toc08 -40 6 -15 SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE MAX5520 toc04 STANDBY SUPPLY CURRENT (A) 10 SUPPLY CURRENT vs. CLOCK FREQUENCY 2.5 2.0 -15 STANDBY SUPPLY CURRENT vs. TEMPERATURE (MAX5521) VREF = 2.4V 3.0 0.1 -40 TEMPERATURE (C) VREF = 3.9V 3.5 1 TEMPERATURE (C) VDD = 5V 4.0 10 SUPPLY VOLTAGE (V) 5.0 4.5 100 MAX5520 toc06 7 1000 MAX5520 toc03 8 SUPPLY CURRENT (A) 8 9 SHUTDOWN SUPPLY CURRENT (nA) 10 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5521) MAX5520 toc02 9 SUPPLY CURRENT (A) SUPPLY CURRENT vs. TEMPERATURE (MAX5521) MAX5520 toc01 10 INL (LSB) MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs 0 200 400 600 800 DIGITAL INPUT CODE 1000 1200 0 200 400 600 800 DIGITAL INPUT CODE _______________________________________________________________________________________ 1000 1200 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs OFFSET VOLTAGE vs. TEMPERATURE 0.02 0.01 0 -0.01 0.2 0 -0.2 -0.4 0 200 400 600 800 1000 0.04 0.02 0 -0.02 -0.04 -0.06 -0.8 -0.08 -0.10 -40 1200 -15 10 35 60 85 -40 -15 10 35 60 85 DIGITAL INPUT CODE TEMPERATURE (C) TEMPERATURE (C) DIGITAL FEEDTHROUGH RESPONSE DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT DIN 5V/div 0.6048 VDD = 1.8V DAC CODE = MIDSCALE VREF = 1.2V 0.6046 0.6044 0.6042 OUT 50mV/div DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT 3 VDD = 5V 2 VDD = 3V VDD = 1.8V 1 4.5 DAC OUTPUT VOLTAGE (V) 4 0.01 0.10 1.9415 1.9410 1.9400 -10 -8 -6 -4 -2 0 2 4 6 8 10 DAC OUTPUT CURRENT (mA) DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 1.8V, VREF = 1.2V) MAX5520 toc18 VREF = VDD CODE = MIDSCALE 4.0 3.5 VDD = 5V 3.0 2.5 VOUT 200mV/div VDD = 3V 2.0 1.5 1.0 0.5 0 0.001 1.9420 MAX5520 toc17 VREF = VDD CODE = MIDSCALE 1.9425 DAC OUTPUT CURRENT (A) 5.0 MAX5520 toc16 5 1.9430 VDD = 5.0V DAC CODE = MIDSCALE VREF = 3.9V 1.9405 0.6040 -1000-800 -600 -400 -200 0 200 400 600 800 1000 20s/div 1.9435 DAC OUTPUT VOLTAGE (V) SCLK 5V/div DAC OUTPUT VOLTAGE (V) CS 5V/div 1.9440 MAX5520 toc14 0.6050 MAX5520 toc15 MAX5520 toc13 ZERO SCALE OUTPUT VOLTAGE (V) 0.06 -0.6 -1.0 -0.03 VDD = 5V VREF = 3.9V 0.08 0.4 MAX5520 toc12 VDD = 5V VREF = 3.9V 0.6 -0.02 0.10 MAX5520 toc11 0.8 OFFSET VOLTAGE (mV) 0.03 DNL (LSB) 1.0 MAX5520 toc10 0.04 GAIN-ERROR CHANGE vs. TEMPERATURE GAIN-ERROR CHANGE (LSB) DNL vs. INPUT CODE (VDD = VREF = 5V) 1 10 OUTPUT SOURCE CURRENT (mA) 100 MAX5520/MAX5521 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25C, unless otherwise noted.) 0 0.001 VDD = 1.8V 0.01 0.1 1 10 100 100s/div OUTPUT SINK CURRENT (mA) _______________________________________________________________________________________ 7 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5520/MAX5521 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25C, unless otherwise noted.) OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 5V, VREF = 3.9V) OUTPUT MINIMUM SERIES RESISTANCE vs. LOAD CAPACITANCE MAX5520 toc19 MAX5520 toc20 MINIMUM SERIES RESISTANCE () FOR NO OVERSHOOT VOUT 500mV/div POWER-UP OUTPUT VOLTAGE GLITCH MAX5520 toc21 600 500 VDD 2V/div 400 300 200 VOUT 10mV/div 100 0 0.0001 0.001 200s/div 0.01 0.1 1 100 10 20ms/div CAPACITANCE (F) MAJOR CARRY OUTPUT VOLTAGE GLITCH (CODE 7FFh TO 800h) (VDD = 5V, VREF = 3.9V) MAX5520 toc22 REFERENCE OUTPUT VOLTAGE (V) 3.940 VOUT AC-COUPLED 5mV/div MAX5520 toc23 REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE VDD = 5V 3.935 3.930 3.925 3.920 3.915 3.910 3.905 3.900 -40 100s/div -15 10 35 60 85 TEMPERATURE (C) 1.218 1.217 1.216 1.215 3.91 3.90 3.89 1.21750 1.21748 MAX5520 toc26 VDD = 5V REFERENCE OUTPUT VOLTAGE (V) 1.219 3.92 MAX5520 toc25 REFERENCE OUTPUT VOLTAGE (V) VDD = 1.8V REFERENCE OUTPUT VOLTAGE (V) MAX5520 toc24 1.220 REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT NO LOAD 1.21746 1.21744 1.21742 1.21740 1.21738 1.21736 1.21734 1.21732 -500 1500 3500 5500 7500 REFERENCE OUTPUT CURRENT (A) 8 1.21730 3.88 1.214 -500 2000 4500 7000 9500 12,000 14,500 REFERENCE OUTPUT CURRENT (A) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs REFERENCE LINE-TRANSIENT RESPONSE (VREF = 1.2V) REFERENCE LINE-TRANSIENT RESPONSE (VREF = 3.9V) MAX5520 toc27 MAX5520 toc28 2.8V 5.5V VDD VDD 1.8V 4.5V VREF 500mV/div VREF 500mV/div 3.9V 100s/div 100s/div REFERENCE LOAD TRANSIENT (VDD = 1.8V) REFERENCE LOAD TRANSIENT (VDD = 5V) MAX5520 toc29 MAX5520 toc30 REFOUT SOURCE CURRENT 0.5mA/div REFOUT SOURCE CURRENT 0.5mA/div VREFOUT 500mV/div 3.9V VREFOUT 500mV/div 200s/div 200s/div REFERENCE LOAD TRANSIENT (VDD = 1.8V) REFERENCE LOAD TRANSIENT (VDD = 5V) MAX5520 toc31 200s/div MAX5520 toc32 REFOUT SINK CURRENT 50A/div REFOUT SINK CURRENT 100A/div VREFOUT 500mV/div VREFOUT 500mV/div 3.9V 200s/div _______________________________________________________________________________________ 9 MAX5520/MAX5521 Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 5.0V, VREF = 4.096V (MAX5520) or VREF = 3.9V (MAX5521), TA = +25C, unless otherwise noted.) REFERENCE PSRR vs. FREQUENCY REFERENCE PSRR vs. FREQUENCY 60 50 40 30 20 10 0 80 MAX5520 toc34 VDD = 1.8V 70 POWER-SUPPLY REJECTION RATIO (dB) MAX5520 toc33 80 POWER-SUPPLY REJECTION RATIO (dB) MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs VDD = 5V 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 FREQUENCY (kHz) REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V) REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V) MAX5520 toc36 MAX5520 toc35 100V/div 100V/div 1s/div 10 1000 FREQUENCY (kHz) 1s/div ______________________________________________________________________________________ +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs PIN NAME MAX5520 MAX5521 1 1 CS 2 2 SCLK 3 3 DIN 4 -- REFIN FUNCTION Active-Low Digital-Input Chip Select Serial-Interface Clock Serial-Interface Data Input Reference Input -- 4 REFOUT 5, 6, 7, 11 5, 6, 7, 11 N.C. No Connection. Leave N.C. inputs unconnected (floating) or connected to GND. Reference Output 8 8 VDD Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a 0.1F capacitor. 9 9 GND Ground 10 10 OUT Analog Voltage Output 12 12 FB EP Exposed Paddle EP Feedback Input Exposed Paddle. Connect EP to GND. MAX5520 Functional Diagram VDD REFIN POWERDOWN CONTROL DAC REGISTER INPUT REGISTER SCLK DIN CS CONTROL LOGIC AND SHIFT REGISTER 10-BIT DAC OUT MAX5520 FB GND ______________________________________________________________________________________ 11 MAX5520/MAX5521 Pin Description +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5520/MAX5521 MAX5521 Functional Diagram VDD POWERDOWN CONTROL 2-BIT PROGRAMMABLE REFERENCE INPUT REGISTER SCLK DIN CS REF BUF DAC REGISTER CONTROL LOGIC AND SHIFT REGISTER REFOUT 10-BIT DAC OUT MAX5521 FB GND Detailed Description The MAX5520/MAX5521 single, 10-bit, ultra-low-power, voltage-output DACs offer Rail-to-Rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and require only 6A (max) supply current. These devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18A. The MAX5521 includes an internal reference that saves additional board space and can source up to 8mA, making it functional as a system reference. The 16MHz, 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE protocols. When V DD is applied, all DAC outputs are driven to zero scale with virtually no output glitch. The MAX5520/MAX5521 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an outputamplifier inverting input is available). These devices come in a 4mm x 4mm thin QFN package. Digital Interface The MAX5520/MAX5521 use a 3-wire serial interface compatible with SPI, QSPI, and MICROWIRE protocols (Figures 1 and 2). The MAX5520/MAX5521 include a single, 16-bit, input shift register. Data loads into the shift register through the serial interface. CS must remain low until all 16 bits are clocked in. Data loads MSB first, D9-D0. The 16 bits consist of 4 control bits (C3-C0), 10 data bits (D9-D0), and 2 sub-bits (see Table 1). D9-D0 are the DAC data bits and S1 and S0 are the sub-bits. The sub-bits must be set to zero for proper operation. The control bits C3-C0 control the MAX5520/MAX5521, as outlined in Table 2. Each DAC channel includes two registers: an input register and a DAC register. The input register holds input data. The DAC register contains the data updated to the DAC output. The double-buffered register configuration allows any of the following: * Loading the input registers without updating the DAC registers * Updating the DAC registers from the input registers * Updating all the input and DAC registers simultaneously 12 ______________________________________________________________________________________ +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs CONTROL DATA BITS MSB C3 LSB C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 Sub-bits S1 and S0 must be set to zero for proper operation. tCH SCLK tCL tDS C3 DIN tCS0 C2 C1 S0 tDH tCSH tCSS CS tCSW tCS1 Figure 1. Timing Diagram SCLK DIN 1 C3 2 C2 3 C1 CONTROL BITS 4 C0 5 D9 6 D8 7 D7 8 D6 9 D5 10 D4 DATA BITS 11 D3 12 D2 13 D1 14 D0 15 S1 16 S0 SUB-BITS COMMAND EXECUTED CS Figure 2. Register Loading Diagram ______________________________________________________________________________________ 13 MAX5520/MAX5521 Table 1. Serial Write Data Format MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Table 2. Serial-Interface Programming Commands INPUT DATA SUB-BITS C3 CONTROL BITS C2 C1 C0 D9-D0 S1-S0 0 0 0 0 XXXXXXXXXX 00 No operation; command is ignored. 0 0 0 1 10-bit data 00 Load input register from shift register; DAC register unchanged; DAC output unchanged. 0 0 1 0 -- -- Command reserved; do not use. 0 0 1 1 -- -- Command reserved; do not use. 0 1 0 0 -- -- Command reserved; do not use. 0 1 0 1 -- -- Command reserved; do not use. 0 1 1 0 -- -- Command reserved; do not use. 0 1 1 1 -- -- Command reserved; do not use. 00 Load DAC register from input register; DAC output updated; MAX5520 enters normal operation if in shutdown; MAX5521 enters normal operation if in standby or shutdown. 1 0 0 0 10-bit data FUNCTION 1 0 0 1 10-bit data 00 Load input register and DAC register from shift register; DAC output updated; MAX5520 enters normal operation if in shutdown; MAX5521 enters normal operation if in standby or shutdown. 1 0 1 0 -- -- Command reserved; do not use. 1 0 1 1 -- -- Command reserved; do not use. 1 1 0 0 D9, D8, XXXXXXXX 00 MAX5520 enters shutdown; MAX5521 enters standby*. For the MAX5521, D9 and D8 configure the internal reference voltage (Table 3). 00 MAX5520/MAX5521 enter normal operation; DAC output reflects existing contents of DAC register. For the MAX5521, D9 and D8 configure the internal reference voltage (Table 3). 00 MAX5520/MAX5521 enter shutdown; DAC output set to high impedance. For the MAX5521, D9 and D8 configure the internal reference voltage (Table 3). 00 Load input register and DAC register from shift register; DAC output updated; MAX5520 enters normal operation if in shutdown; MAX5521 enters normal operation if in standby or shutdown. 1 1 0 1 D9, D8, XXXXXXXX 1 1 1 0 D9, D8, XXXXXXXX 1 1 1 1 10-bit data X = Don't care. *Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown. 14 ______________________________________________________________________________________ +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Shutdown Mode The MAX5520/MAX5521 feature a software-programmable shutdown mode that reduces the typical supply current and the reference input current to 0.18A (max). Writing an input control word with control bits C[3:0] = 1110 places the device in shutdown mode (Table 2). In shutdown, the MAX5520 reference input and DAC output buffers go high impedance. Placing the MAX5521 into shutdown turns off the internal reference, and the DAC output buffers go high impedance. The serial interface remains active for all devices. Table 2 shows several commands that bring the MAX5520/MAX5521 back to normal operation. The power-up time from shutdown is required before the DAC outputs are valid. Note: For the MAX5521, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation before entering standby mode. Table 3. Reference Output Voltage Programming D9 D8 REFERENCE VOLTAGE (V) 0 0 1.214 0 1 1.940 1 0 2.425 1 1 3.885 Standby Mode (MAX5521 Only) The MAX5521 features a software-programmable standby mode that reduces the typical supply current to 6A. Standby mode powers down all circuitry except the internal voltage reference. Place the device in standby mode by writing an input control word with control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC output buffers go high impedance. If the MAX5521 is coming out of standby, the power-up time from standby is required before the DAC outputs are valid. For the MAX5521, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation before entering standby mode. To enter standby from shutdown, issue the command to return to normal operation, followed immediately by the command to go into standby. Table 2 shows several commands that bring the MAX5521 back to normal operation. When transitioning from standby mode to normal operation, only the DAC power-up time is required before the DAC outputs are valid. Reference Input The MAX5520 accepts a reference with a voltage range extending from 0 to VDD. The output voltage (VOUT) is represented by a digitally programmable voltage source as: VOUT = (VREF x N / 1024) x gain where N is the numeric value of the DAC's binary input code (0 to 1023), VREF is the reference voltage and gain is the externally set voltage gain for the MAX5520/ MAX5521. In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5G (typ). Reference Output The MAX5521 internal voltage reference is software configurable to one of four voltages. Upon power-up, the default reference voltage is 1.214V. Configure the reference voltage using the D8 and D9 data bits (Table 3) when the control bits are as follows: C[3:0] = 1100, 1101, or 1110 (Table 2). VDD must be kept at a minimum of 200mV above VREF for proper operation. ______________________________________________________________________________________ 15 MAX5520/MAX5521 Power Modes The MAX5520/MAX5521 feature two power modes to conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode, the device is completely powered down, including the internal voltage reference in the MAX5521. The MAX5521 also offers a standby mode where all circuitry is powered down except the internal voltage reference. Standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. Standby mode also helps reduce the wake-up delay by not requiring the reference to power up when returning to normal operation. MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Applications Information 1-Cell and 2-Cell Circuit See Figure 3 for an illustration of how to power the MAX5520/MAX5521 with either one lithium-ion battery or two alkaline batteries. The low current consumption of the devices makes the MAX5520/MAX5521 ideal for battery-powered applications. Programmable Current Source See the circuit in Figure 4 for an illustration of how to configure the MAX5520 as a programmable current source for driving an LED. The MAX5520 drives a standard NPN transistor to program the current source. The current source (I LED ) is defined in the equation in Figure 4. Voltage Biasing a Current-Output Transducer See the circuit in Figure 5 for an illustration of how to configure the MAX5520 to bias a current-output transducer. In Figure 5, the output voltage of the MAX5520 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor R. Self-Biased Two-Electrode Potentiostat Application See the circuit in Figure 6 for an illustration of how to use the MAX5520 to bias a two-electrode potentiostat on the input of an ADC. Bipolar Output The MAX5520 output can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT = VREF x [(NA - 512) / 512] where NA represents the numeric value of the DAC's binary input code. Table 5 shows digital codes (offset binary) and the corresponding output voltage for the circuit in Figure 4. Configurable Output Gain The MAX5520/MAX5521 have a force-sense output, which provides a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5520/MAX5521 is specified in a unity-gain configuration (op-amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. Another advantage of the force-sense DAC is that it allows many useful circuits to be created with only a few simple external components. An example of a custom fixed gain using the force-sense output of the MAX5520/MAX5521 is shown in Figure 9. In this example R1 and R2 set the gain for VOUT. VOUT = [(VREFIN x NA) / 1024] x [1 + (R2 / R1)] where NA represents the numeric value of the DAC input code. Unipolar Output Figure 7 shows the MAX5520 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes. VDD 1.8V VALKALINE 3.3V 2.2V VLITHIUM 3.3V 536k +1.25V REFIN DAC VOUT 0.1F MAX6006 (1A, 1.25V SHUNT REFERENCE) 0.01F VOUT (1.22mV / LSB) V x NDAC VOUT = REFIN 1024 MAX5520 GND NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell 16 ______________________________________________________________________________________ +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5520/MAX5521 V+ REF LED ILED OUT DAC TO ADC DAC REFIN VOUT IF 2N3904 RF FB MAX5520 WE MAX5521 ILED = TO ADC FB R VREFIN x NDAC 1024 x R SENSOR CE NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. Figure 4. Programmable Current Source Driving an LED REFOUT BAND GAP TO ADC CL Figure 6. Self-Biased Two-Electrode Potentiostat Application DAC REFIN VOUT VOUT VOUT = VBIAS + (IT x R) MAX5520 REFIN FB TRANSDUCER VBIAS DAC OUT R IT MAX5520 V x NDAC VBIAS = REFIN 1024 FB V x NA VOUT = REFIN 1024 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. NA IS THE DAC INPUT CODE (0 TO 1023 DECIMAL). Figure 5. Transimpedance Configuration for a Voltage-Biased Current-Output Transducer Figure 7. Unipolar Output Circuit Table 4. Unipolar Code Table (Gain = +1) Table 5. Bipolar Code Table (Gain = +1) DAC CONTENTS MSB LSB ANALOG OUTPUT DAC CONTENTS MSB LSB ANALOG OUTPUT 1111 1111 1100 +VREF (1023/21024) 1111 1111 1100 +VREF (511/512) 1000 0000 0100 +VREF (513/1024) 1000 0000 0100 +VREF (1/512) 1000 0000 0000 +VREF (512/1024) = +VREF/2 1000 0000 0000 0V 0111 1111 1100 +VREF (511/1024) 0111 1111 1100 -VREF (1/512) 0000 0001 0100 +VREF (1/1024) 0000 0000 0100 -VREF (511/512) 0000 0000 0000 0V 0000 0000 0000 -VREF (512/512) = -VREF ______________________________________________________________________________________ 17 MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs Power Supply and Bypassing Considerations Bypass the power supply with a 0.1F capacitor to GND. Minimize lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. For the thin QFN package, connect the exposed paddle to ground. 10k Layout Considerations Digital and AC transient signals coupling to GND can create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines. 10k MAX5520 V+ REFIN VOUT DAC OUT VOUT DAC OUT REFIN R2 V- MAX5520 FB FB R1 Figure 8. Bipolar Output Circuit 18 Figure 9. Separate Force-Sense Outputs Create Unity and Greater-than-Unity DAC Gains Using the Same Reference ______________________________________________________________________________________ +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5520/MAX5521 1.8V VDD 5.5V REFIN DAC VOUT VOUT H CS1 MAX5520 FB MAX5401 SOT-POT 100k W SCLK VOUT = VREFIN x NDAC 255 - NPOT 1+ 1024 255 ( ) NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE. 5PPM/C RATIOMETRIC TEMPCO DIN CS2 L Figure 10. Software-Configurable Output Gain Chip Information TRANSISTOR COUNT: 10,688 PROCESS: BiCMOS ______________________________________________________________________________________ 19 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX5520/MAX5521 +1.8V to +5.5V, Ultra-Low-Power, 10-Bit, Voltage-Output DACs PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 B 1 2 PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 B 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.