UbE D il - B5Babb2 OO0b3bb 5 ESCYP CY7p134 TU6-23 AL S ! SEMICONDUCTOR CYPRESS SEMICONDUCTOR PRELIMINARY CY7B135 CY7B1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features 0.8-micron BICMOS for high performance High-speed access 20 ns (commercial) 25 ns (military) Automatic power-down Fully asynchronous operation 7B1342 includes semaphores 7B134 available in 48-pin DIB 48-pin LEC 7B135/7B1342 available in 52-pin LCC/PLCC Functional Description The CY7B134, CY7B135, and CY7B1342 are high-speed BiCMOS 4K x 8 dual-port static RAMs. The CY7B1342 includes semaphores that provide a means to allo- cate portions of the dual-port RAM or any shared resource. Two ports are provided permittingindependent, asynchronous ac- cess for reads and writes to any location in memory. Application areas include inter- processor/multiprocessoesigns,commu- nicationsstatus buffering, and dual-portvi- deo/graphicsmemory. Each port has independent control pins: chip enable (CE), read or write enable (R/ W), and output enable (OF). The CY7B134/135 are suited for those systems that do not require on-chip arbitration or areintolerant ofwaitstates, Therefore, the user must be aware that simultaneous ac- cess to a location is possible. Semaphores are offered on the CY7B1342 to assist in arbitrating between ports. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (sema- phore) at any time. Control of a sema- phore indicates that a shared resource is in use, An automatic power-down feature is controlledindependently oneach portbya chip enable (CE) pin or SEM pin (CY7B1342 only). The CY7B134 is available in 48-pin DIP and 48-pin LCC. The CY7B135 and CY7B1342 are available in 52-pin LCC/ PLCC. Logic Block Diagram RAW AWR ee GER Ce OER Ain Aur Ato Aton "On. @ ico COLUMN COLUMN coL}. Vor | SEL HO iO SEL} Cu, ___=} WOor A, > be __. ROW MEMORY ROW eR 3 SELECT ARRAY SELECT 3 A _> jx Aca An < Ava e s SEMAPHORE At r ARBITRATION je Aor CEL (7B1342 only) Ta ce, t OF, RA, >} - FWa ____ (7B1942 only) | | (781342 only) SEM 3M, 1342-1 Selection Guide Maximum Operating Current(mA) Maximum Standby Current(mA) 7B135-20 7B134220 2-104 7B13525 7B134225 7B13535 7B134235CYPRESS SEMICONDUCTOR YEE > = e58%6be OOOb3b? 7 EaCYP -46-23- CY7B134 = _-T-46-23-12 CV7BIS4 = PRELIMINARY CY7B1342 == SS PRESS | | Pin Configurations SRAMs mI 1342-2 LCC Top View Jee PRE SE ig aig 2 Fey 8 FEE SF els 6 8 4.3 21448 47 46 45 44 49 76 a! [ea Pt a0 = ce a ewe ree SS 3 2:41:52 1 50 49 48 47 Brrrepeeze2 SRBLRBYBBSAR S RRBGSBSARSRaSE BS 1342-4 1342-5 | Pin Definitions | Left Port Right Port Description AgL-11L Aor-11R Address Lines CEy, CER Chip Enable OE, OER Output Enable RW, R/We Read/Write Enable - SEM, SEMR SemaphoreEnable. When asserted LOW, allowsaccess to eight semaphores, The three least (CY7B1342 (CY7B1342 significantbits of the address lines will determine which semaphore to write or read. The | only) only) I/Qp pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into | the respective location. : | 2-1054BE D RM 258%bb2 0006366 9 EaCyP T-46-23-] CY7B134 = 2 CY7B135 a PRELIMINARY CY7B1342 Saas SEMICONDUCTOR Maximum Ratings (Abovewhich the useful life may be impaired. Foruserguidelines, Static Discharge Voltage ...........2...20+ eseoee > 2001V nottested.) (per MIL-STD-883, Method 3015) Storage Temperature ...........65 sees 65Cto +150C = Latch-UpCurrent ............. 20005 vaveseseee >200mA Ambient Temperaturewith . Operating Range Power Applied .........+ seseereeeseee = 55Cto +125C 7 " Ambient Supply Voltage to Ground Potential Vy, (Pin 48 to Pin 24) oo... cc cseseneerenseses O5V to +7.0V = 0C to +70C * DC Voltage Applied to Outputs = in High Z State ....... seeseee 0,5Vto +7,0V 40C to c x DC Input Voltage] ..... seseveceeresees = 3,0V to +7.0V 55C to +125C + Electrical Characteristics Overthe Operating Rangel formation, 7B13420 | 7B134~25 | 7B134-35 7B135-20 | 7B135-25 | 7B13535 7B134220 | 7B134225 | 7B1342-35 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max, | Units Vou Output HIGH Voltage Voc = Min., lon = 4.0 mA 24 2.4 2.4 Vv VoL. Output LOW Voltage Vec = Min., or, = 4.0 mA 0.4 0.4 0.4 Vv Vin Input HIGH Voltage 2.2 2.2 2.2 v Vit Input LOW Voltage 0.8 0.8 0.8 v Ix Input Load Current GND < Vi < Vcc 10 } +10 | 10 | +10 | -10 ] +10 | pA Toz. Output LeakageCurrent | Outputs Disabled, 10 | +10 | 10 | +10 | -10 | +10] pA GND <= Vo = Vcc Tec OperatingCurrent Vcc = Max., Com'l 240 220 210 | mA Jour =OmA Mil 280 230 Ispi Standby Current CE, and CEr > Vin, Com! 80 75 | 70 | mA (Both Ports TTL Levels) | f= faxl4l Mil 20 1 75 Ispo Standby Current CE, and CEr > Vin, Com! 150 140 130 | mA (One Port TTL Level) f= fmaxl4l Mi 180 160 Isp3 Standby Current Both Ports. Com! 15 15 15 | mA (Both Ports CMOS Levels) e and CEp > wee 0.29, Ty =. Voc 0. i orVin<avt=o | Mil 30 30 Ispa Standby Current One Port _ Com't 130 120 110 | mA (One Port CMOS Level) CE, or CEr > Vcc 0.2V, Vin = Voc 0.2V or - Vin < 0.2, Active Mil 150 130 Port Outputs, f = faxl4l Capacitancel5) Parameters Description Test Conditions Maxi Units Cin InputCapacitance Ta = 25C, f= 1 MHz, 10 pF Cout Output Capacitance Voc = 5.0V 10 pF Notes: 1. Pulse width < 20.ns, 5. Tested initially and after any design or process changes that may affect 2. Tais the instant on case temperature. these parameters. 3, Seethe last page of this specification for Group Asubgrouptestingine 6. Forall packages except DIP and cerDIP (D26, P25), which have maxi- mums of Ciy = 15 pE Cour = 15 pF. 4. fax = I/trc= Allinputs cycling at f = 1/tac (except output enable). f= 0 meas no address or control Jines change. This applies only to in- puts at CMOS level standby Igp3. 2-106CYPRESS SEMICONDUCTOR 4BE D 2e54%bb2 0006369 O Ewcyp | (a) Normal Load (Load 1) CY7B134 , CY7B135 PRELIMINARY CY7B1342 T-46-23-12 a ouTPUuT a OUTPUT A Al = 3470. me Ts nl Z = = Vi = 1.4V = VK = (b) Thevenin Equivalent (Load 1) (c) Three-State Delay (Load 3) 1942-6 1342-7 1942-8 ALLINPUT PULSES 1342-9 Switching Characteristics Over the Operating Rangel-8] 7B13420 7BI3425 7B13435 7B135~20 7B135-25 7B13535 7B134220 7B134225 7B1342~35 Parameters Description Min. | Max. | Min. | Max. | Min. | Max. Units READ CYCLE tre Read Cycle Time 20 25 35 ns taa Address to Data Valid 20 25 35 ns toHa Output Hold From Address Change 3 3 3 ns tace CE LOW to Data Valid 20 25 35 ns tpor OE LOW to Data Valid 13 15 20 ns ttzone! OE Low to LowZ 3 3 3 ns tyzoEl! OE HIGH to High Z 13 15 20 Tis trzcE! CE LOW to Low Z, 3 3 3 ns tzcko) CEHIGH to High Z 13 15 20 Tis teu CE LOW to Power Up 0 0 0 ns tpp CE HIGH to Power Down 20 25 35 ns WRITE CYCLE two Write Cycle Time 20 25 35 ns tscE CE LOW to Write End 15 20 30 ns taw Address Set-Up to Write End 15 20 30 nS tHa Address Hold From Write End 2 2 2 ns tsa Address Setup to Write Start 0 0 0 ns tpwE Write Pulse Width 15 20 25 ns tsp Data Set-up to Write End 13 15 15 ns typ Data Hold From Write End 0 0 0 ns tazweel R/W LOW to High Z B 15 20 TIS trzWwEel R/W HIGH to Low Z. 3 3 3 ns 2-107CYPRESS SEMICONDUCTOR ULE D MM 258%bbe 0006370 ? racyp - T-46-23-12 CYbiss = oe = ee PRELIMINARY CY7B1342 SS SEMICONDUCTOR = Switching Characteristics Over the Operating Range!-l (continued) . 7B134-20 | 78134-25 7B13435 . 7B13520 7B13525 7B13535 : 7B1342-20 7B134225 7B1342-35 Parameters Description Min. | Max. | Min. { Max. | Min. | Max. Units : WRITE CYCLE (continued) twope Write Pulse to Data Delay 40 50 60 ns tpppu Write Data Valid to Read Data Valid 30 30 35 ns SEMAPHORETIMING!!1) tsop SEM Flag Update Pulse (OE or SEM) 10 10 15 ns tswRD SEM Flag Write to Read Time 5 ns tsps SEM Fiag Contention Window ns Notes: : 8. Nd See the last page of this specification for Group A subgroup testing in- formation, Test conditions assume signal transition time of 3 ns orless, timing ref- erence levels of1,5V, input pulse levels of 0 to 3,0V, and output loading of the specified IoL/Ioy and 30 pF load capacitance Test conditions used are Load 3. 10. For information on port-to-port delay through RAM cells from writ- ing port to reading port, refer to Read Timing with Port-toPort Delay waveform. 11, Semaphore timing applies only to CY7B1342. 12. R/Wis HIGH for read cycle. 13. Device is continuously selected, CE = Vy, and OE = Vy. 14, Address valid prior to or coincident with CE transition LOW. Switching Waveforms Read Cycte No. 112,13] Either Port Address Access Lo: tac ! ADDRESS x DATA OUT Read Cycle No, 2[!2.14] SEMU] or CE faa tous PREVIOUS DATA VALID K XX X KX DATA VALID 1342-10 Either Port CE/OE Access GE DATA OUT leo DATA VALID Isa 2-108 1342-11CYPRESS SEMICONDUCTOR zs SEMICONDUCTOR HEE D MM 2549662 0006371 9 racyp T-46-23-12 CY7B134 CY7B135 PRELIMINARY CY7B1342 Switching Waveforms Read Timing with Port-to-Port Delayl!5] twe ADDRESS, MATCH x Ba | ewe YY sp ste HD DATAwa ., VALID ADDRESS, x MATCH topp DATAgun. > vauw twon 1342~12 Write Cycle No, 1: OF Tri-States Data I/Os (Either Port)[!6.17,18] two ADDRESS SEMI19! OR CE RW DATA DATA VALID OE Wf ie SN >| tHz0e zoe DATAgur S33-S SS HIGH IMPEDANCE 4 444427 ZF 7 1342-13 Note: 15, CEL = CEp =LOW: RAV, = HIGH 16. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 17, R/W must be HIGH during all address transactions. 18. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tpwr or (t:zwe + tsp) to allow the /O drivers to turn off and data to be placed on the bus for the required tsp. EOE is HIGH during a RAV controlled write cycle (as in this ex- ample), this requirement does not apply and the write pulse canbe as_ short as the specified tpwe. 19, SEM only applies to CY7B1342 2109 SRAMs aCYPRESS SEMICONDUCTOR 4BE D MM 2569662 0006372 O Eacyp CY7B134 , CY7B135 PRELIMINARY CY7B1342 ee Switching Waveforms (continued) Write Cycle No. 2: R/W Tri-States Data I/Os (Either Port)[!7.20] T-46-23-12 two ! - ADDRESS x x sce tha an onct CW ALLL tsa taw 1 RAV PWE . \ \ Fa . r< tsp <>| th DATA z DATA VALID >+___ tuzwe > tawe * DATAgyt -SSS_Y-SS_NS_S_ NN ON NSCS ON HIGH IMPEDANCE KIT ITT. ZLLZLL LLL LLL DL LLL CoE 1342-14 Semaphore Read After Write Timing, Either Side (CY7B1342 only)[24) }+ tr, > t ona > : [ Ao~Aa XKXK VALID ADDRESS KXXKXS K VALID ADDRESS KXXK XK tace | / DATAgyy VALID + t tay 1.4| SEM ta -_-_ e- tsce N \ y, tsop tsp Oo DATANVALID tsa tewe al 'Ho RW J . Y jt tsynp - tpoe >I ALLL LLLLLLLLL LE >, +- WRITE CYCLE _ Notes: READ CYCLE 1342-15 20. Data /O pins enter high-impedance when OE is held LOW during 21. eS HIGH for the duration of the above timing (both write and read write. cycle), 2-110CYPRESS SEMICONDUCTOR 4YBE D ES 258%bbe 0006373 2 EXCyP CY7B134 CY7B135 a : PRELIMINARY CY7B1342 SEMICONDUCTOR Switching Waveforms (continued) , T-46 -23-12 Timing Diagram of Semaphore Contention (CY7B1342 only)[22,23.24] , . E] Agu-Aat MATCH X a = < RM, w SEM, tsps AonAor MATCH x AAW; H SEM, xz 1342-16 Notes: eo 22. 1Oor = 1/Oo. = LOW (request semaphore); CEp = CE, =HIGH 24. If isps is violated, it is gauranteed that only one side will gain access to 23, Semaphores are reset (available to both ports) at cycle start. thesemaphore. 2-111UGE D Mi 2565662 OO0b374 4 EMCyYP CY7B134 = CYPRESS SEMICONDUCTOR CY7B135 a T-46-23-19 PRELIMINARY CY7B1342 = SEMICONDUCTOR on Architecture When reading a semaphore, all eight data lines output the sema- The CY7B184 and CY7B135 consist of an array of 4K words of 8 bitseach of dual-port RAM cells, 1/O and addresslines, andcontrol signals (CE, OE, R/W). Two semaphore control pins exist for the CY7B1342 (SEM). Functional Description Write Operation Data must be set up for a duration of tsp before the rising edge of R/W in order to guarantee a valid write, Since there is no on-chip arbitration, the user must be sure that a specificlocation willnotbe - accessedsimultaneously by both ports or erroneous data could re- sult, A write operation is controlled by either the OEpin (see Write Cycle No. 1 timing diagram) or the R/W pin (see Write Cycle No. 2timing diagram), Data can be written tyzo after the OE is deas- serted or tyzwe after the falling edge of R/W. Required inputs for write operations aresummarized in Table 1. Ifa location is being written to by one port and the opposite port attempts to read the same location, a port-to-port flowthrough delayis metbefore the data is valid on the output. Data will be valid onthe portwishing to read the location tppp after the data is pres- ented on the writing port. Read Operation Whenreading the device, the user must assert both the OE and CE pins, Data will be available tacg after CE or tpog after OE are as- serted. If the user of the CY7B1342 wishes to access a semaphore, the SEM pin must be asserted instead of the CE pin. Requiredin- puts for read operations are summarized in Table 1. Semaphore Operation The CY7B1342 provides eight semaphore latches which are sepa- rate from the dual port memory locations. Semaphores are used to reserve resources which are shared between the two ports. The state of the semaphore indicates that a resource is in use. Forexam- ple, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location, The left port then veri- fies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tsop before at- tempting to read the semaphore, The semaphore value will be available tswrp + tpog after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes con- trol over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, aone is written to cancel its request. Semaphoresare accessed by asserting SEM LOW. The SEM pin functionsas a chip enable for the semaphore latches. CE must re- main HIGH during SEM LOW. Ao.2 represents the semaphore address, OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/Og is used. If a 0 is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing a zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immedi- ately own the semaphore. Table 2shows sample semaphore opera- tions. phore value. The read value is latched in an output register to pre- vent the semaphore from changing state during a write from the other port. If both ports request a semaphore control by writing a 0 to a semaphore within tsps of each other, it is guaranteed that only one side will gain access to the semaphore. Table 1, Non-contending Read/Write Inputs Outputs CE | R/W | OF | SEM | 1/09 ~ YO7 Operation Hi xX |X H |HighZ Power-Down H| aH | L | Lb [Dataoue | soabaran X |X 1H X | HighZ 1/O Lines Disabled H {sv ][ xX L_ {| Dataln Write to Semaphore LY]HYL H |DataOut | Read L L |X H_ | DataIn Write LEX |X L IllegalCondition Table 2. Semaphore Operation Example . VO | 1/0 Function Left | Right Status No Action 1 1 Semaphorefree Left port writes 0 1 Left port obtains semaphore semaphore Right port writes 0 0 1 | Rightsideis denied tosemaphore access Left port writes 1 to 1 0 Right port is granted semaphore access to Semaphore Left port writes 0 to 1 0 No change. Left port semaphore is denied access Right port writes 1 0 1 Left port obtains tosemaphore semaphore Left port writes 1 to 1 1 No port accessing semaphore semaphoreaddress Right port writes 0 1 0 Right port obtains tosemaphore semaphore Right port writes 1 1 1 No port accessing tosemaphore semaphore Left port writes 0 to 0 1 Left port obtains semaphore semaphore Left port writes 1 to 1 1 No port accessing semaphore semaphore 2-112WBE D EM 25859662 0006375 & ESCYP CY7B134 2-113 CYPRESS SEMICONDUCTOR CY7B135 Sees Cprss 23-12 PRELIMINARY CY7B1342 SS SEMICONDUCTOR T-46-2 Ordering Information . MILITARY SPECIFICATIONS Speed Package | Operating Group A Subgroup Testing (ns) Ordering Code Type Range DC Characteristics 20 CY7B134-20PC P25 | Commercial Parameters Subgroups CY7B134-20DC D26 Vou L233 CY7B134-20LC L68 VoL 12,3 25 CY7B134-25PC P25 Commercial Vit 1,2,3 CY7B134-25DC D26 Vir, Max. 1,2,3 CY7B134-25LC L68 ix 1,2,3 CY7B134-25PI P25 | Industrial loz 1,2,3- CY7B134-25D1 D26 , Tos 1,2,3 CY7B13425DMB D26 | Military Ice 1,2,3 CY7B13425LMB L68 Ispi 1,2,3 34 CY7B134-35PC P25 | Commercial Ispa 1, 2,3 CY7B134-35DC D26 Isp3 1,2,3 CY7B134-35LC L68 L Isp4 1,2,3 CY7B134-35P1 P25 | industrial Switching Characteristics CY7B134-35DI D26 Parameters Subgroups CY7B134-35DMB D26 | Military READ CYCLE CY7B134-35LMB L68 tre 7, 8,9, 10, 11 Speed Package | Operating TAA 7,89, 10, UL (ns) Ordering Code Type Range toHA 7,8, 9, 10, 11 20. | CY7B135-20LC L69 [Commercial tAcE 7,8, 9, 10, 11 CY7B135-205C 769 poz 7,8, 9, 10, 11 25 | CY7B135-25LC 169 |Commercial| | WRITECYCLE CY7B135-253C 169 twe 7, 8, 9, 10, 11 CY7B135-25]1 169 | Industrial tscr 7,8,9, 10, 11 CY7B135-25LMB 169 | Military baw 7,8,9, 10, 11 35 | CY7BI35-35LC 169 [Commercial] |tHA 7, 8,9, 10, i CY7BI35.351C 765 tsa 7, 8,9, 10, 11 CY7B135-3511 769 Industral ; ; z z = CY7B135-35LMB 169 | Military tap 769,10,11 Speed Package | Operating SEMAPHORE CYCLE (ns) Ordering Code Type Range tsop 7,8, 9, 10, 11 20. | CY7B1342-20LC 169 | Commercial tswrp 7,8,9,10, 11 | CY7B1342-20JC J69 tsps 7,8, 9, 10, 11 | 25 CY7B1342-25LC L69 Commercial | Document #: 38-00161 | CY7B1342-253C 169 CY7B1342-2551 369 | Industrial CY7B134225LMB L69 | Military 35 CY7B1342-35LC 169 | Commercial CY7B1342-353C J69 CY7B1342-35)1 69 | Industrial CY7B1342-35LMB L69 | Military SRAMs a