1A CY2081A Three-PLL Clock Generator Features * Factory-EPROM configurable for quick availability and prototyping. * General purpose clock synthesizer for all applications such as: modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes, data/telecommunications, etc. * Three independent configurable clock outputs * Outputs ranging from 500 kHz to 100 MHz (5V) and up to 80 MHz for 3.3V operation * Configurable output control pin (pin 8) can be used as an output enable, power-down, suspend or select line. * Phase-locked loop oscillator input derived from external crystal (10 MHz to 25 MHz) or external reference clock (1 MHz to 30 MHz) * 3.3V or 5V operation (factory configured) * 8-pin 150-mil packaging achieves minimum footprint for space-critical applications * Sophisticated internal loop filter requires no external components or manufacturing tweaks as commonly required with external filters Functional Description The CY2081A is a general-purpose clock synthesizer designed for use in applications such as modems, disk drives, CD-ROM drives, Video CD players, games, set-top boxes and data/telecommunications. This devices offers three configurable clock outputs in an 8-pin 150-mil SOIC package and can be configured to operate off either a 3.3V or 5V power supply. The on-chip reference oscillator is designed for 10 MHz to 25 MHz crystals. Alternatively, a reference clock between 1 MHz and 30 MHz can be used. The CY2081A also features an output control pin (pin 8) which can be configured as an output enable, power down, frequency select, or suspend input. This gives the user the ability to three-state the output, power down the device, change the CLKA output frequency during operation, or suspend any of the outputs. Asserting the PD input will result in all the PLLs and the outputs being shut down. The PLLs will have to re-lock when the PD input is deasserted. The CY2081A outputs three clocks: CLKA, CLKB, and CLKC, whose frequencies can possess any value within the specified range. Additionally, the reference frequency can be obtained on any output. Custom configurations with user-defined features and frequencies can be obtained by filling out the custom configuration form located at the back of this data sheet and contacting your local Cypress representative. The CY2081A can replace multiple Metal Can Oscillators (MCO) in a synchronous system, providing cost and board space savings to manufacturers. Hence, this device is ideally suited for applications that require multiple, accurate, and stable clocks synthesized from low-cost generators in small packages. A hard disk drive is an example of such an application. In this case, CLKA drives the PLL in the Read Controller, while CLKB and CLKC drive the MCU and associated sequencers. Consider using the CY2291, CY2292, or CY2907 for applications that require more than three output clocks. Logic Block Diagram Pin Configuration SOIC Top View CLKA GND XTALIN XTALOUT 1 8 2 7 3 6 4 5 OE/PD/FS/SUSPEND VDD CLKC CLKB 2081-1 XTALIN Reference Oscillator CLKA PLL 1 XTALOUT PLL 2 EPROMConfigurable Multiplexer and Divide Logic CLKB CLKC PLL 3 OE/PD/FS/SUSPEND 2081-2 Cypress Semiconductor Corporation Document #: 38-07251 Rev. ** * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised September 27, 2001 CY2081A Pin Summary Name Number Description CLKA 1 Configurable clock output GND 2 Ground XTALIN[1] 3 Reference Crystal Input or External Reference Clock Input 4 Reference Crystal Feedback CLKB 5 Configurable clock output CLKC 6 Configurable clock output VDD 7 Voltage Supply XTALOUT [1, 2] OE / PD / FS / SUSPEND 8 Output control pin; either active-HIGH Output Enable, active-LOW power down, CLKA Frequency Select, or active-LOW Suspend input Maximum Ratings Storage Temperature ................................. -65C to +150C Max. Soldering Temperature (10 sec.) .........................260C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature...................................................150C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Supply Voltage ............................................... -0.5V to +7.0V DC Input Voltage......................................-0.5V to VDD+0.5V Operating Conditions[3] Parameter Description Min. Max. Unit 4.5 (3.0) 5.5 (3.6) V 0 70 C VDD Supply Voltage TA Operating Temperature, Ambient CL Max. Load Capacitance per output 25 (15) pF fREF External Reference Crystal 10.0 25.0 MHz fREF External Reference Clock[4, 5] 1.0 30.0 MHz Electrical Characteristics VDD = 5V (3.3V) 10%, TA = 0C to +70C Parameter Description Conditions VOH HIGH-Level Output Voltage IOH = -4.0 mA VOL LOW-Level Output Voltage IOL = 4.0 mA [6] VIH HIGH-Level Input Voltage VIL LOW-Level Output Voltage[6] Except Crystal Pins Except Crystal Pins IIH Input HIGH Current VIN = VDD - 0.5V IIL Input LOW Current VIN = 0.5V IOZ Output Leakage Current Three State Outputs IDD VDD Supply Current[7] VDD = VDD max. 5V (3.3V) operation, CL = 25 pF (15 pF) IDDS VDD Power Supply Current in Powerdown Mode Powerdown Active, 5V Operation Min. Typ. Max. 2.4 Unit V 0.4 2.0 V V 0.8 V <100 150 A <100 150 A 250 A 40 (24) 60 (40) mA 100 200 A Notes: 1. For best accuracy, use a parallel-resonant crystal, CL=17 pF. 2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to an external crystal). 3. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses. 4. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2. 5. Please refer to application note "Crystal Oscillator Topics" for information on AC-coupling the external input reference clock. 6. Xtal inputs have CMOS thresholds. 7. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. Document #: 38-07251 Rev. ** Page 2 of 7 CY2081A Switching Characteristics[8] Parameter Name Description Min. Typ. Max. Unit t1 Output Period Clock output range, 5V operation 10 [100 MHz] 2000 [500 KHz] ns t1 Output Period Clock output range, 3.3V operation 12.5 [80 MHz] 2000 [500 KHz] ns t1A Clock Jitter[9] Peak-to-peak period jitter,% of clock period (fOUT 4 MHz) <0.5 1 % t1B Clock Jitter[9] Peak-to-peak period jitter (4 MHz fOUT 16 MHz) <0.7 1 ns t1C Clock Jitter[9] Peak-to-peak period jitter (16 MHz < fOUT 50 MHz) <400 500 ps t1D Clock Jitter[9] Peak-to-peak period jitter (fOUT > 50 MHz) <250 350 ps Output Duty Cycle[10] Duty cycle for outputs, defined as t2 / t1[11] fOUT > 66.67 MHz 40% 50% 60% Duty cycle for outputs, defined as t2 / t1[11] fOUT 66.67 MHz 45% 50% 55% t3 Rise time Output clock rise time[12] at CL=25 pF (15 pF at 3.3V operation) 3 5 ns t4 Fall time Output clock fall time[12] at CL=25 pF (15 pF at 3.3V operation) 2.5 4 ns t5 Frequency Slew Rate Rate of change of frequency of CLKA 5 40 MHz/ ms t6 Power Up Stabilization Time < 25 50 ms 1 Output clock stable time after power up Switching Waveforms All Outputs Duty Cycle and Rise/Fall Time t1 t2 OUTPUT 2.4V 0.4V t3 3.3V 2.4V 0.4V 0V t4 2081-3 Notes: 8. Guaranteed by design, not 100% tested. 9. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application note: "Jitter in PLL-Based Systems." 10. Reference Output duty cycle depends on XTALIN duty cycle. 11. Measured at 1.4V. 12. Measured between 0.4V and 2.4V. Document #: 38-07251 Rev. ** Page 3 of 7 CY2081A Test Circuit VDD 7 0.1 F OUTPUTS CLK output CLOAD 2 2081-4 GND Ordering Information Ordering Code Package Name Package Type Operating Range CY2081ASC-XXX S8 8-Pin (150-Mil) SOIC 5.0V, Commercial[13] CY2081ASL-XXX S8 8-Pin (150-Mil) SOIC 3.3V, Commercial[13] Note: 13. 0C to +70C Document #: 38-07251 Rev. ** Page 4 of 7 CY2081A Package Diagrams 8-Lead (150-Mil) SOIC S8 Document #: 38-07251 Rev. ** Page 5 of 7 CY2081A CY2081A CONFIGURATION REQUEST FORM Customer Phone # Engineer Fax # FAE/Sales Date 3.3V 1. OPERATING VOLTAGE (circle one) 2. INPUT REFERENCE FREQUENCY (Circle one) Crystal 5.0V External Clock Default reference = 14.318 MHz. If a different reference is desired, specify the frequency in the box to the right (must be between 10 MHz and 25 MHz for crystal, 1 MHz and 30 MHz for external clock): 3. OUTPUT CONTROL PIN (PIN 8) CONFIGURATION (Circle one) OE (Default) PD SUSPEND FS If the Suspend option is desired, please circle what outputs must be suspended CLKA CLKB CLKC 4. OUTPUT CONFIGURATION Fill in the desired frequencies, specifying kHz or MHz, for each output. Please adhere to the notes at the right. Contact your local Cypress representative for assistance. After configuration, please fax the form to your local Cypress representative. Notes: CLKA (FS=0) CLKA (FS=1) CLKB CLKC * * * If pin 8 is OE, PD or SUSPEND, fill in only one value for CLKA Buffered reference clock is available on all outputs. CLKA, CLKB and CLKC, outputs can range from 500 kHz to 100 MHz (80 MHz at 3.3V) 5. FOR CYPRESS USE ONLY Customer Configuration Marking Date Quantity Document #: 38-07251 Rev. ** Page 6 of 7 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2081A Document Title: CY2081A Three-PLL Clock Generator Document Number: 38-07251 REV. ECN NO. Issue Date Orig. of Change ** 110516 02/06/02 SZV Document #: 38-07251 Rev. ** Description of Change Change from Spec number: 38-01038 to 38-07251 Page 7 of 7