Never stop thinking.
Data Sheet, V1.2, Dec. 2002
Microcontrollers
TC1765
32-Bit Single-Chip Microcontroller
Edition 2002-12
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2002.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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(www.infineon.com).
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Due to technical requirements components may contain dangerous substances. For information on the types in
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Infineon Technologies Components may only be used in life-support devices or systems with the express written
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of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
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be endangered.
Never stop thinking.
Data Sheet, V1.2, Dec. 2002
Microcontrollers
TC1765
32-Bit Single-Chip Microcontroller
TC1765 Data Sheet
Preliminary
Revision History: 2002-12 V1.2
Previous Version: V1.1, 2002-10, V1.0, 2002-05
Page Subjects (major changes since last revision)
Changes from V1.1 to V1.2
58, 59 Overshoot conditions (notes 2) and 3)) for digital supply voltages added
60 Class A pins: input low voltage VILmin (CMOS) improved; pull-up/pull-down
current spec corrected and completed;
61 Class A pins: pull-up/pull-down current spec corrected and completed;
62 Note 7) inserted
69 Note 3) added to “Sum of IDDS”
80 t30min corrected
83 Package outlines updated (no more “Preliminary” in drawing)
Changes from V1.0 to V1.1
All In general: Data Sheet status changed from “Advance Information” to
“Preliminary”
22 The SSC RXFIFO and TXFIFO are 4-stage FIFOs (not 8-stage)
61 Input hysteresis corrected
62 Footnote 10) added
66 Footnote 8): word “numeric” added
69 Missing power supply currents now specified
74 Last paragraph modified because of Figure 29 correction
75 Figure 29 corrected and improved
81 t55 added (min. value) and corrected (max. value)
82 t61min and t62min corrected
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Your feedback will help us to continuously improve the quality of this document.
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Data Sheet 1 V1.2, 2002-12
TC176532-Bit Single-Chip Microcontroller
TriCore Family
Preliminary
• High Performance 32-bit TriCore CPU with 4-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU/System Clock
• Dual Issue super-scalar implementation
– Instruction triple issue
• Circular Buffer and bit-reverse addressing modes for DSP algorithms
• Flexible multi-master interrupt system
• Very fast interrupt response time
• Hardware controlled context switch for task switch and interrupts
• 48 Kbytes of on-chip SRAM for data and time critical code
• 8-channel DMA Controller for FPI Bus transactions
• Built-in calibration support
• On-chip Flexible Peripheral Interface Bus (FPI Bus) for interconnections of functional
units
• External Bus Interface Unit (EBU) with dedicated pins used for
– Communication with external data memories and peripheral units
– Instruction fetches from external Burst Flash program memories
• On-Chip Peripheral Units
– General Purpose Timer Array (GPTA) with a powerful set of digital signal filtering
and timer functionality to realize autonomous and complex I/O management
– Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/counters
– Two Asynchronous/Synchronous Serial Channels (ASC0, ASC1) with baudrate
generator, parity, framing and overrun error detection
– Two High Speed Synchronous Serial Channels (SSC0, SSC1) with programmable
data length and shift direction
– TwinCAN Module with two interconnected CAN nodes for high efficiency data
handling via FIFO buffering and gateway data transfer
– Two Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, or 12-bit
resolution and 24 analog inputs
– Watchdog Timer and System Timer
• 77 digital general purpose I/O lines and one 24-bit analog port
• On-chip Debug Support
• Power Management System
• Clock Generation Unit with PLL
• Two derivatives with upward compatible pin configuration
– TC1765N
– TC1765T (with additional 16-bit OCDS Level 2 trace port)
• Ambient temperature under bias: -40 °C to +125 °C
• P-LBGA-260 package
TC1765
Data Sheet 2 V1.2, 2002-12
Preliminary
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the
required product. This ordering code identifies: the derivative itself, i.e. its function set,
the temperature range, and the package and the type of delivery.
The TC1765 is available with the following ordering code:
Type Ordering Code Package Description
SAK-TC1765N-L40EB Q67121-C2326 P-LBGA-260 32-Bit Single-Chip
Microcontroller
40 MHz, -40 °C to +125 °C
SAK-TC1765T-L40EB Q67121-C2348 P-LBGA-260 32-Bit Single-Chip
Microcontroller
40 MHz, -40 °C to +125 °C
(with OCDS2 trace port)
TC1765
Data Sheet 3 V1.2, 2002-12
Preliminary
Block Diagram
Figure 1 TC1765 Block Diagram
TracePort
(TC1765T only)
16
ASC1
MCB04989
Twin
CAN
SSC0GPTA
4
EBU
(External
Bus
Unit)
32
24
Data
[31:0]
Address
[23:0]
Port 0
16
Port 1
Analog Input Connection
AN
[23:0]
24
OSC
FPI Bus
ECOUT
XTAL2
XTAL1
TP
JTAG &
Cerberus
SCU
Power-
Watchdog-
Reset
Sys. Cntrl.
JTAG IO
DMU
(Data Memory Unit)
32 KB SRAM
TriCore
CPU
max. 40 MHz
Trace &
OCDS Interrupt
V
SS
V
DD
128 64
PMU
(Program Memory Unit)
8 KB Boot ROM
16 KB Scratch Pad RAM
1 KB Instruction Cache
16 16
EBU
Control
10
Chip
Select
5
SSC1ASC0GPTU
ADC0
32
2
Port 2
16
Port 3
16
Port 4
Port 5
3216
5
DMA
Controller
ADC1
5
16
STM BCU PLL
8
8
OCDS
Control
ECIN
5
3
F
P
I
B
u
s
32
16
3
5
Control
V
DDRAM
CPUCLK
V
DDSBRAM
Analog
Power
Supply
10
10 23
V
DDP
5
V
SSOSC
V
DDOSC
32
32
73216
16
TC1765
Data Sheet 4 V1.2, 2002-12
Preliminary
Logic Symbol
Figure 2 TC1765 Logic Symbol
MCA04973
Alternate Functions
BYPASS
NMI
PORST
HDRST
TESTMODE
General
Control
V
SSM
V
DDM
ADC Analog
Power Supply
V
SSOSC
V
DDOSC
XTAL2
XTAL1
Oscillator
CPUCLK
TMS
TDO
TDI
TCK
JTAG / OCDS
TP [15:0]
BRKOUT
BRKIN
OCDSE
TRST
(TC1765T only)
V
SS
V
DD
10
23
Digital Circuitry
Power Supply
V
DDP
5
V
DDRAM
V
DDSBRAM
TC1765T
TC1765N
V
AREF1
V
AGND1
V
DDA1
V
SSA1
ADC1 Analog
Power Supply
V
AREF0
V
AGND0
V
DDA0
V
SSA0
ADC0 Analog
Power Supply
AN[23:0] ADC
Analog Inputs
Port 0
16-Bit
Port 1
16-Bit
Port 2
16-Bit
Port 4
8-Bit
Port 5
5-Bit
Port 3
16-Bit
GPTA
GPTA /
CFG
ASC1
SSC1
D[31:0]
A[23:0]
Chip
Select External
Bus Interface
5
10 Control
ECIN
ECOUT
GPTU / ASC0 /
SSC0 / CAN /
ADC0 / ADC1
TC1765
Data Sheet 5 V1.2, 2002-12
Preliminary
Pin Configuration
Figure 3 TC1765 Pinning for P-LBGA-260 Package (top view)
MCP05009
AN
18
A
B
C
D
F
G
H
J
K
L
M
N
P
R
T
U
V
E
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
123456789101112131415161718
123456789101112131415161718
AN
4AN
0
AN
7
AN
2
AN
5
AN
6
AN
3AN
1
AN
14
AN
15
AN
21
AN
22
AN
9
AN
10
AN
13
AN
12
AN
11
AN
8
AN
16
AN
19
AN
23
AN
20
V
AGND1
V
AREF1
V
SSA1
V
DDA1
V
DD
RAM
D30
D31
D29
D28
D27 D26
D25
D24
D23 D22
D21D20
D19D18D17
D16
V
DD
V
DD
D15
D14
D13
D12
D11
EC
IN
EC
OUT
V
DD
D9
D10
D8
D5D4
D7
D6
V
DDM
V
SSM
D2
D3 D1
D0RD RD/
WR
ADV BC0
BC1
BC2
BC3
BAA
CODE
WAIT/
IN D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A14 A13
A15 A16
A17
A18
A19
A20
A21
A22
A23 CS0
CS1
CS2
CS3
CSEMU/
CSOVL
TP.0 TP.1
TP.11TP.10
TP.8
TP.12
TP.9
TP.3TP.2
TP.7
TP.13
TP.6
TP.5TP.4
TP.14 TP.15
OCD
SE
BRK
OUT
TDO
TCK
CPU
CLK
TDI
TRST
TMS
BRK
IN
TEST
MODE
PO
RST
NMI
XTAL
2
XTAL
1
HD
RST
BY
PASS P1.0P1.4
P1.8
P1.9
P1.7
P1.6
P1.5
P1.3
P1.2 P1.1
P1.15
P1.14
P1.12
P1.11
P1.10
P1.13
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.10
P2.7
P2.8
P2.9P2.11
P2.12 P2.13P2.14
P2.15P3.0P3.1
P3.2P3.3P3.4 P3.5
P3.6P3.7
P3.8P3.9
P3.10
P3.11
P3.12
P3.13
P3.14P3.15
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6P4.7
P5.0
P5.1 P5.2
P5.3
P5.4P0.14
P0.15
P0.12
P0.13
P0.10
P0.11
P0.8
P0.9
P0.6
P0.7
P0.4 P0.5
P0.2
P0.3
P0.0
P0.1
V
SS
OSC
V
DD
OSC
V
DD
SBRAM
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
AGND0
V
AREF0
V
SSA0
V
DDA0
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDP
V
DDP
V
DDP
V
DDP
V
DDP
V
DD
V
DD
N.C. N.C.
The Trace port is only available in the TC1765T.
AN
17
TC1765
Data Sheet 6 V1.2, 2002-12
Preliminary
Table 1 Pin Definitions and Functions
Symbol Pin In
Out
Functions
D[31:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
T3
R4
P4
R2
R1
R3
N4
P3
M4
N3
L4
M3
N2
M2
L3
M1
L1
K1
K2
K3
J1
J2
H2
H1
J4
H3
G2
G1
F1
E1
F2
H4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EBU Data Bus Lines1)2)
The EBU Data Bus Lines D[31:0] serve as external data bus.
Data bus line 0
Data bus line 1
Data bus line 2
Data bus line 3
Data bus line 4
Data bus line 5
Data bus line 6
Data bus line 7
Data bus line 8
Data bus line 9
Data bus line 10
Data bus line 11
Data bus line 12
Data bus line 13
Data bus line 14
Data bus line 15
Data bus line 16
Data bus line 17
Data bus line 18
Data bus line 19
Data bus line 20
Data bus line 21
Data bus line 22
Data bus line 23
Data bus line 24
Data bus line 25
Data bus line 26
Data bus line 27
Data bus line 28
Data bus line 29
Data bus line 30
Data bus line 31
TC1765
Data Sheet 7 V1.2, 2002-12
Preliminary
A[23:0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
T5
V4
U5
R6
V5
R7
T6
U6
R8
V6
U7
T7
V8
U14
U8
T8
T9
V14
U9
R9
V13
T11
V10
U10
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
EBU Address Bus Lines3)4)
The EBU Address Bus Lines A[23:0] serve as address bus.
Address bus line 0
Address bus line 1
Address bus line 2
Address bus line 3
Address bus line 4
Address bus line 5
Address bus line 6
Address bus line 7
Address bus line 8
Address bus line 9
Address bus line 10
Address bus line 11
Address bus line 12
Address bus line 13
Address bus line 14
Address bus line 15
Address bus line 16
Address bus line 17
Address bus line 18
Address bus line 19
Address bus line 20
Address bus line 21
Address bus line 22
Address bus line 23
CS0
CS1
CS2
CS3
U12
V12
T10
R10
O
O
O
O
Chip Select Lines3)5)
Chip select output line 0
Chip select output line 1
Chip select output line 2
Chip select output line 3
CSEMU/
CSOVL
V11 O Chip Select for Emulator Region / Chip Select for
Emulator Overlay Memory3)5)
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 8 V1.2, 2002-12
Preliminary
BC0
BC1
BC2
BC3
RD
RD/WR
ADV
WAIT/IND
BAA
CODE
U2
V1
U3
V2
T1
T2
U1
R5
U4
V3
O
O
O
O
O
O
O
I
O
O
EBU Control Lines1)5)
The EBU control lines are required for controlling external
memory or peripheral devices.
Byte control line 0
Byte control line 1
Byte control line 2
Byte control line 3
Read control line
Write control line
Address valid output
Wait input / End of burst input
Burst address advance output
Code fetch status output
The CODE signal has the same timing as the chip select
signals.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 9 V1.2, 2002-12
Preliminary
AN[23:0]
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
A7
D6
B6
D5
A6
B5
C5
A5
A3
C4
C3
B3
D3
D4
E4
E3
A2
A1
B2
B1
C2
F4
F3
D2
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC Analog Input Port
The ADC Analog Input Port provides 24 analog input lines for
the A/D converters ADC0 and ADC1.
Analog input 0
Analog input 1
Analog input 2
Analog input 3
Analog input 4
Analog input 5
Analog input 6
Analog input 7
Analog input 8
Analog input 9
Analog input 10
Analog input 11
Analog input 12
Analog input 13
Analog input 14
Analog input 15
Analog input 16
Analog input 17
Analog input 18
Analog input 19
Analog input 20
Analog input 21
Analog input 22
Analog input 23
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 10 V1.2, 2002-12
Preliminary
P0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
A10
D7
B8
C7
A11
A12
D8
B9
A13
B10
A14
C9
C10
D10
A15
B11
I/O
I/O
I
I/O
I
I
I/O
I
I
I/O
I
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I/O
I/O
I
O
I
O
Port 06)
Port 0 is a 16-bit bi-directional general purpose I/O port that
is also used as input/output for ASC0, SSC0, CAN, GPTU,
ADC0, ADC1, and the DMA Controller.
GPT0 GPTU I/O line 0 /
AD0EXTIN0 ADC0 external trigger input 0
GPT1 GPTU I/O line 1
AD0EXTIN1 ADC0 external trigger input 1
DMREQ0A DMA request input 0A
GPT2 GPTU I/O line 2
AD1EXTIN0 ADC1 external trigger input 0
DMREQ1A DMA request input 1A
GPT3 GPTU I/O line 3
AD1EXTIN1 ADC1 external trigger input 1
GPT4 GPTU I/O line 4 /
AD0EMUX0 ADC0 external multiplexer control 0
GPT5 GPTU I/O line 5
AD0EMUX1 ADC0 external multiplexer control 1
GPT6 GPTU I/O line 6
AD0EMUX2 ADC0 external multiplexer control 2
RXD0 ASC0 receiver input/output
TXD0 ASC0 transmitter output
SCLK0 SSC0 clock input/output
MRST0 SSC0 master receive input /
SSC0 slave transmit output
MTSR0 SSC0 master transmit output /
SSC0 slave receive input
RXDCAN0 CAN receiver input 0
TXDCAN0 CAN transmitter output 0
RXDCAN1 CAN receiver input 1
TXDCAN1 CAN transmitter output 1
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 11 V1.2, 2002-12
Preliminary
P1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14
P1.15
N18
R16
R15
M17
N16
P15
M18
L18
P16
U16
M16
L16
K17
K18
L15
K16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 16)
Port 1 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN0 / OUT0 line of GPTA
IN1 / OUT1 line of GPTA
IN2 / OUT2 line of GPTA
IN3 / OUT3 line of GPTA
IN4 / OUT4 line of GPTA
IN5 / OUT5 line of GPTA
IN6 / OUT6 line of GPTA
IN7 / OUT7 line of GPTA
IN8 / OUT8 line of GPTA
IN09 / OUT9 line of GPTA
IN10 / OUT10 line of GPTA
IN11 / OUT11 line of GPTA
IN12 / OUT12 line of GPTA
IN13 / OUT13 line of GPTA
IN14 / OUT14 line of GPTA
IN15 / OUT15 line of GPTA
P2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
J18
T15
N15
J17
H18
J16
T16
M15
J15
H16
G18
H15
G15
G17
G16
F18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 26)
Port 2 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN16 / OUT16 line of GPTA
IN17 / OUT17 line of GPTA
IN18 / OUT18 line of GPTA
IN19 / OUT19 line of GPTA
IN20 / OUT20 line of GPTA
IN21 / OUT21 line of GPTA
IN22 / OUT22 line of GPTA
IN23 / OUT23 line of GPTA
IN24 / OUT24 line of GPTA
IN25 / OUT25 line of GPTA
IN26 / OUT26 line of GPTA
IN27 / OUT27 line of GPTA
IN28 / OUT28 line of GPTA
IN29 / OUT29 line of GPTA
IN30 / OUT30 line of GPTA
IN31 / OUT31 line of GPTA
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 12 V1.2, 2002-12
Preliminary
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
F16
F15
E18
E16
E15
E17
D18
D17
C18
C17
B18
A18
C14
D15
B17
B16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 36)
Port 3 is a 16-bit bidirectional general purpose I/O port which
also serves as input or output for the GPTA.
IN32 / OUT32 line of GPTA
IN33 / OUT33 line of GPTA
IN34 / OUT34 line of GPTA
IN35 / OUT35 line of GPTA
IN36 / OUT36 line of GPTA
IN37 / OUT37 line of GPTA
IN38 / OUT38 line of GPTA
IN39 / OUT39 line of GPTA
IN40 / OUT40 line of GPTA
IN41 / OUT41 line of GPTA
IN42 / OUT42 line of GPTA
IN43 / OUT43 line of GPTA
IN44 / OUT44 line of GPTA
IN45 / OUT45 line of GPTA
IN46 / OUT46 line of GPTA
IN47 / OUT47 line of GPTA
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
D14
C13
A17
B15
C16
D13
C15
C12
I/O
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
Port 46)
Port 4 is an 8-bit bidirectional general purpose I/O port which
also serves as input/output for the GPTA or external request
input for the DMA controller. During hardware reset the port 4
lines are also used as start-up configuration selection inputs
and PLL clock selection inputs.
IN48 / OUT48 line of GPTA
IN49 / OUT49 line of GPTA /
DMREQ0B DMA request input 0B
IN50 / OUT50 line of GPTA /
DMREQ1B DMA request input 1B
IN51 / OUT51 line of GPTA
IN52 / OUT52 line of GPTA / CFG[0]
IN53 / OUT53 line of GPTA / CFG[1]
IN54 / OUT54 line of GPTA / CFG[2]
IN55 / OUT55 line of GPTA / GPTA emergency shut down
CFG[2:0]: Start-up Configuration Selection Inputs
These pins are sampled during power-on reset (PORST =0).
The configuration inputs define the boot options of the
TC1765 after a hardware reset operation.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 13 V1.2, 2002-12
Preliminary
P5
P5.0
P5.1
P5.2
P5.3
P5.4
D12
B13
B14
C11
A16
I/O
I/O
I
O
I
I/O
I/O
I/O
Port 56)
Port 5 is a 5-bit bidirectional general purpose I/O port which
also serves as input or output for ASC1 and SSC1.
RXD1 ASC1 receiver input/output
DMREQ0C DMA request input 0C
TXD1 ASC1 transmitter output
DMREQ1C DMA request input 1C
SCLK1 SSC1 clock input/output
MRST1 SSC1 master receive input /
SSC1 slave transmit output
MTSR1 SSC1 master transmit output /
SSC1 slave receive input
TP
TP.0
TP.1
TP.2
TP.3
TP.4
TP.5
TP.6
TP.7
TP.8
TP.9
TP.10
TP.11
TP.12
TP.13
TP.14
TP.15
G7
G8
H7
H8
L7
L8
M7
M8
M11
M12
L11
L12
H11
H12
G11
G12
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
OCDS-2 Trace Port3)
TP is the OCDS Level 2 Trace Port. The Trace port is only
available in the TC1765T. The TP outputs are tristated during
reset and deep sleep mode.
Trace output 0
Trace output 1
Trace output 2
Trace output 3
Trace output 4
Trace output 5
Trace output 6
Trace output 7
Trace output 8
Trace output 9
Trace output 10
Trace output 11
Trace output 12
Trace output 13
Trace output 14
Trace output 15
TRST7) R14 I JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG module.
A high level enables the JTAG module.
TCK7) T13 I JTAG Module Clock Input
TDI8) T14 I JTAG Module Serial Data Input
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 14 V1.2, 2002-12
Preliminary
TDO R12 O JTAG Module Serial Data Output3)
TMS8) V15 I JTAG Module State Machine Control Input
OCDSE8) R11 I OCDS Enable Input
A low level on this pin during power-on reset (PORST =0)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
BRKIN8) U15 I OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
BRKOUT T12 O OCDS Break Output3)
A low level on this pin indicates that a programmable OCDS
event has occurred.
NMI8) U17 I Non-Maskable Interrupt Input
A high-to-low transition on this pin causes an NMI-Trap
request to the CPU.
HDRST8) P18 I/O Hardware Reset Input / Reset Indication Output6)
Assertion of this open-drain bidirectional pin causes a
synchronous reset of the chip through external circuitry.
The internal reset circuitry drives this pin in response to a
power-on, hardware, watchdog and power-down wake-up
reset for a specific period of time. For a software reset, it is
programmable whether this pin is activated or not.
PORST T17 I Power-on Reset Input
A low level on PORST causes an asynchronous reset of the
entire chip. During power-up of the TC1765, this pin must be
held active (low).
BYPASS N17 I PLL Bypass Control Input
This pin is sampled during power-on reset (PORST = 0). If
BYPASS is at high level, direct drive mode operation of the
clock circuitry is selected and the PLL is bypassed.
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 15 V1.2, 2002-12
Preliminary
XTAL1
XTAL2
U18
T18
I
O
Oscillator/PLL/Clock Generator Input/Output Pins
XTAL1 is the input to the oscillator amplifier and input to the
internal clock generator. XTAL2 is the output of the oscillator
amplifier circuit. For clocking the device from an external
source, XTAL1 is driven with the clock signal while XTAL2 is
left unconnected. For crystal oscillator operation XTAL1 and
XTAL2 are connected to the crystal with the appropriate
recommended oscillator circuitry.
ECOUT P1 O EBU Clock Output3)
ECIN N1 – EBU Clock Input
The ECIN pin is used to latch the data from external
components into the EBU. This pin has to be connected to the
ECOUT pin. Additional delay elements might be used to
adapt to long delays at the address and data lines.
CPUCLK R13 O CPU Clock Output3)
General purpose clock output (can be disabled if not used). In
addition, the OCDS-2 trace output data are synchronous to
this clock.
TEST
MODE8) V16 I Test Mode Select Input
For normal operation of the TC1765 this pin should be
connected to VDD.
VDDOSC R18 – Main Oscillator Power Supply (2.5 V)9)
VSSOSC R17 – Main Oscillator Ground
VDD J3,
P2,
T4,
V7,
U11,
U13,
L2,
F17,
D11,
V9
–Core and EBU Power Supply (2.5 V)9)
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 16 V1.2, 2002-12
Preliminary
VDDP L17,
H17,
D16,
B12,
C8
–Port 0 to 5 and Dedicated Pins Power Supply (3.3 - 5 V)10)
VDDRAM G3 – Power Supply for PMU Memories (2.5 V)9)
VDDSBRAM P17 – Power Supply for DMU Memory (2.5 V)9)
Used for normal and stand-by operating mode.
VSS D9,
K4,
K15,
G9,
G10,
H9,
H10,
J7,
J8,
J9,
J10,
J11,
J12,
K7,
K8,
K9,
K10,
K11,
K12,
L9,
L10,
M9,
M10
–Ground
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 17 V1.2, 2002-12
Preliminary
VDDM B4 – ADC Analog Part Power Supply (5 V)10)
VSSM A4 – ADC Analog Part Ground for VDDM
VDDA0 A9 – ADC0 Analog Part Power Supply (2.5 V)9)
VSSA0 B7 – ADC0 Analog Part Ground for VDDA0
VDDA1 G4 – ADC1 Analog Part Power Supply (2.5 V)9)
VSSA1 D1 – ADC1 Analog Part Ground for VDDA1
VAREF0 A8 – ADC0 Reference Voltage10)
VAGND0 C6 – ADC0 Reference Ground
VAREF1 C1 – ADC1 Reference Voltage10)
VAGND1 E2 – ADC1 Reference Ground10)
N.C. V17,
V18
–Not Connected; reserved for future expansions
1) These pins have a drive capability of 600 µA when used as outputs.
2) These pins can be connected with internal pull-up devices by setting bit SCU_CON.EBUDPEN.
3) These outputs have a drive capability of 600 µA.
4) These pins can be connected with internal pull-up devices by setting bit SCU_CON.EBUAPEN.
5) These pins can be connected with internal pull-up devices by setting bit SCU_CON.EBUCPEN.
6) These pins have a drive capability of 2.4 mA when used as outputs.
7) These pins have an internal pull-down device connected.
8) These pins have an internal pull-up device connected.
9) The voltage on power supply pins marked with 10) has to be raised earlier or at least at the same time (= time
window of 1 µs) than on power supply pins marked with 9) (details see power supply section on Page 54).
10) See note 9).
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
TC1765
Data Sheet 18 V1.2, 2002-12
Preliminary
Parallel Ports
The TC1765 has 77 digital input/output port lines organized into four parallel 16-bit ports
(Port 0 to Port 3), one 8-bit port (Port 4), and one 5-bit port (Port 5). Additionally,
24 analog input port lines are available. The External Bus Unit (EBU) is provided with
dedicated data, address, and control lines. A 16-bit Trace Port is available only in the
TC1765T.
The digital parallel ports Port 0 to Port 5 can be all used as general purpose I/O lines or
they can perform input/output functions for the on-chip peripheral units. The on-chip
External Bus Interface Unit allows to communicate with external memories, external
peripherals, or external debugging devices. An overview on the port-to-peripheral unit
assignment is shown in Figure 4.
Note: For further details on the three pin classes of the TC1765 I/O pins see also Table 8
on Page 56):
Figure 4 Parallel Ports of the TC1765
TC1765N
TC1765T
Parallel
Ports
MCA04981
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
GPIO Alternate Functions
GPTU / ASC0 / SSC0 /
CAN / ADC0 / ADC1
GPTA
GPTA
GPTA
GPTA / CFG
ASC1 / SSC1
External Bus Interface
TP[15:0]
OCDS Trace Port
(TC1765T only)
Address Bus A[23:0]
Data Bus D[31:0]
AN[23:0]
Control Lines
TC1765
Data Sheet 19 V1.2, 2002-12
Preliminary
Serial Interfaces
The TC1765 includes five serial peripheral interface units:
– Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1)
– Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1)
– One TwinCAN Interface
Asynchronous/Synchronous Serial Interfaces
Figure 5 shows a global view of the functional blocks of the two Asynchronous/
Synchronous Serial interfaces ASC0 and ASC1.
Figure 5 General Block Diagram of the ASC Interfaces
MCB05050
ASC0
Module
(Kernel)
Port 0
Control
RXD0
TXD0
ASC1
Module
(Kernel)
RXD1
TXD1
P0.7 /
RXD0
P0.8 /
TXD0
P5.0 /
RXD1
P5.1 /
TXD1
Port 5
Control
Clock
Control
Address
Decoder
Interrupt
Control
f
ASC1
EIR
TBIR
TIR
RIR
Clock
Control
Address
Decoder
Interrupt
Control
f
ASC0
To DMA
EIR
TBIR
RIR
TIR
To DMA
TC1765
Data Sheet 20 V1.2, 2002-12
Preliminary
Each ASC module, ASC0 and ASC1, communicates with the external world via two I/O
lines. The RXD line is the receive data input signal (in Synchronous Mode also output).
TXD is the transmit output signal. Clock control, address decoding, and interrupt service
request control are managed outside the ASC module kernel.
The Asynchronous/Synchronous Serial Interfaces provide serial communication
between the TC1765 and other microcontrollers, microprocessors, or external
peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In Asynchronous
Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
selected. Parity, framing, and overrun error detection are provided to increase the
reliability of data transfers. Transmission and reception of data are double-buffered. For
multiprocessor communication, a mechanism is included to distinguish address bytes
from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator
provides the ASC with a separate serial clock signal that can be very accurately adjusted
by a prescaler implemented as a fractional divider.
Features:
• Full-duplex asynchronous operating modes
– 8-bit or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baud rate from 2.5 Mbit/s to 0.6 Bit/s (@ 40 MHz clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baud rate from 5 Mbit/s to 406.9 Bit/s (@ 40 MHz clock)
• Double buffered transmitter/receiver
• Interrupt generation
– On a transmitter buffer empty condition
– On a transmit last bit of a frame condition
– On a receiver buffer full condition
– On an error condition (frame, parity, overrun error)
TC1765
Data Sheet 21 V1.2, 2002-12
Preliminary
High-Speed Synchronous Serial Interfaces
Figure 6 shows a global view of the functional blocks of the two High-Speed
Synchronous Serial interfaces SSC0 and SSC1.
Figure 6 General Block Diagram of the SSC Interfaces
Each of the SSC modules has three I/O lines, located at Port 0 and Port 5. Each of the
SSC modules is further supplied by separate clock control, interrupt control, address
decoding, and port control logic.
The SSC supports full-duplex and half-duplex serial synchronous communication up to
20 Mbit/s (@ 40 MHz module clock) with receive and transmit FIFO support. The serial
clock signal can be generated by the SSC itself (master mode) or can be received from
an external master (slave mode). Data width, shift direction, clock polarity, and phase are
programmable. This allows communication with SPI-compatible devices. Transmission
MCB05051
Clock
Control
Address
Decoder
Interrupt
Control
f
SSC0
SSC0
Module
(Kernel)
Clock
Control
Address
Decoder
Interrupt
Control
f
SSC1
SSC1
Module
(Kernel)
RXD
TXD
Master
RXD
TXD
Slave
Slave
Master
SCLK
RXD
TXD
Master
RXD
TXD
Slave
Slave
Master
SCLK
Port 0
Control P0.10 /
MRST0
P0.11 /
MTSR0
P0.9 /
SCLK0
Port 5
Control
P5.4 /
MTSR1
P5.3 /
MRST1
P5.2 /
SCLK1
EIR
RIR
To DMA
EIR
TIR
RIR
To DMA
TIR
TC1765
Data Sheet 22 V1.2, 2002-12
Preliminary
and reception of data are double-buffered. A 16-bit baud rate generator provides the
SSC with a separate serial clock signal.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Flexible data format
– Programmable number of data bits: 2-bit to 16 bit
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Baud rate generation from 20 Mbit/s to 305.18 Bit/s (@ 40 MHz module clock)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
• Three-pin interface
– Flexible SSC pin configuration
• 4-stage receive FIFO (RXFIFO) and 4-stage transmit FIFO (TXFIFO)
– Independent control of RXFIFO and TXFIFO
– 2 to 16 bit FIFO data width
– Programmable receive/transmit interrupt trigger level
– Receive and transmit FIFO filling level indication
– Overrun error generation
– Underflow error generation
TC1765
Data Sheet 23 V1.2, 2002-12
Preliminary
TwinCAN Interface
Figure 7 shows a global view of the functional blocks of the TwinCAN module.
Figure 7 General Block Diagram of the TwinCAN Module
The TwinCAN module has four I/O lines located at Port 0. The TwinCAN module is
further supplied by a clock control, interrupt control, address decoding, and port control
logic.
The TwinCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames are handled in accordance to CAN specification V2.0 part B (active).
Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit
identifiers as well as with extended frames with 29-bit identifiers.
Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic
handling and to minimize the CPU load. The flexible combination of Full-CAN
functionality and the FIFO architecture reduces the efforts to fulfill the real-time
requirements of complex embedded control applications. Improved CAN bus monitoring
functionality as well as the increased number of message objects permit precise and
convenient CAN bus traffic handling.
Depending on the application, each of the thirty-two message objects can be individually
assigned to one of the two CAN nodes. Gateway functionality allows automatic data
exchange between two separate CAN bus systems, which decreases CPU load and
improves the real time behavior of the entire system.
TwinCAN Module Kernel
Message
Buffers
MCB05059
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR2
f
CAN
SR3
SR0 Port
Control
P0.13 /
TXDCAN0
P0.12 /
RXDCAN0
SR7
SR6
SR5
P0.15 /
TXDCAN1
P0.14 /
RXDCAN1
Bitstream
Processor
SR4
TXDC0
RXDC0
TXDC1
RXDC1
Error
Handling
Control
Timing
Control
Interrupt
Control
TC1765
Data Sheet 24 V1.2, 2002-12
Preliminary
The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are
programmable up to a data rate of 1 Mbit/s. A pair of receive and transmit pins connect
each CAN node to a bus transceiver.
Features:
• CAN functionality conforms to CAN specification V2.0 B active.
• Dedicated control registers are provided for each CAN node.
• A data transfer rate up to 1 Mbit/s is supported.
• Flexible and powerful message transfer control and error handling capabilities are
implemented.
• Full-CAN functionality: 32 message objects can be individually
– Assigned to one of the two CAN nodes
– Configured as transmit or receive object
– Participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm
– Set up to handle frames with 11-bit or 29-bit identifiers
– Provided with programmable acceptance mask register for filtering
– Monitored via a frame counter
– Configured to Remote Monitoring Mode
• Up to eight individually programmable interrupt nodes can be used.
• CAN Analyzer Mode for bus monitoring is implemented.
TC1765
Data Sheet 25 V1.2, 2002-12
Preliminary
Timer Units
The TC1765 includes two timer units:
– General Purpose Timer Unit (GPTU)
– General Purpose Timer Array (GPTA)
General Purpose Timer Unit
Figure 8 shows a global view of the General Purpose Timer Unit (GPTU) module.
Figure 8 General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as
event timing, event counting, and event recording. The GPTU communicates with the
external world via eight inputs and eight outputs located at Port 0.
The I/O has three timers (T0, T1, and T2) can operate independently from each other,
or can be combined.
General Features:
• All timers are 32-bit precision timers with a maximum input frequency of fGPTU.
• Events generated in T0 or T1 can be used to trigger actions in T2.
• Timer overflow or underflow in T2 can be used to clock either T0 or T1.
• T0 and T1 can be concatenated to form one 64-bit timer.
MCB05052
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR2
f
GPTU
SR3
SR0
GPTU
Module
(Kernel)
Port
Control
P0.1 / GPT1
SR7
SR6
SR5
SR4
IN1
IN2
IN3
IN0
IN7
IN6
IN5
IN4
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
IO1
Not Connected
IO7
IO0 P0.0 / GPT0
IO2 P0.2 / GPT2
IO3 P0.3 / GPT3
P0.4 / GPT4
IO4
IO5 P0.5 / GPT5
IO6 P0.6 / GPT6
TC1765
Data Sheet 26 V1.2, 2002-12
Preliminary
Features of T0 and T1:
• Each timer has a dedicated 32-bit reload register with automatic reload on overflow.
• Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload
registers.
• Overflow signals can be selected to generate service requests, pin output signals, and
T2 trigger events.
• Two input pins can define a count option.
Features of T2:
• Count up or down is selectable
• Operating modes:
–Timer
– Counter
– Quadrature counter (incremental/phase encoded counter interface)
• Options:
– External start/stop, one-shot operation, timer clear on external event
– Count direction control through software or an external event
– Two 32-bit reload/capture registers
• Reload modes:
– Reload on overflow or underflow
– Reload on external event: positive transition, negative transition, or both transitions
• Capture modes:
– Capture on external event: positive transition, negative transition, or both
transitions
– Capture and clear timer on external event: positive transition, negative transition, or
both transitions
• Can be split into two 16-bit counter/timers
• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0
and T1 overflow events can also be assigned to these functions.
• Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle
output pins.
• T2 events are freely assignable to the service request nodes.
TC1765
Data Sheet 27 V1.2, 2002-12
Preliminary
General Purpose Timer Array
Figure 9 shows a global block diagram of the General Purpose Timer Array (GPTA).
Figure 9 GPTA Module Block Diagram
The GPTA module has 56 input signals and 56 output signals which are connected with
56 Port 1, Port 2, Port 3, and Port 4 pins.
The General Purpose Timer Array (GPTA) provides important digital signal filtering and
timer support whose combination enables autonomous and complex functionalities. This
architecture allows easy implementation and easy validation of any kind of timer
functions.
MCB05053
Port
Control
IO54
IO55
P4.0
P4.1
P4.6
P4.7
GPTA Module Kernel
Clock Generation Unit
Filter &
Prescaler
Cells
Phase
Discriminator
Logic
Duty Cycle
Measurement Digital Phase
Locked Loop
Interrupt Control Unit
IO Sharing Unit with Emergency Shut-Off
Signal Generation Unit
Global
Timers
Global Timer
Cells Local Timer
Cells
OUT54
OUT55
IO48
IO49
IO46
IO47
P3.0
P3.1
P3.14
P3.15
IO32
IO33
IO30
IO31
P2.0
P2.1
P2.14
P2.15
IO16
IO17
IO14
IO15
P1.0
P1.1
P1.14
P1.15
IO0
IO1
IN0
IN1
OUT0
OUT1
IN55
IN54
AS0
AS1
AS55
Clock
Control
Address
Decoder
A/D
Converter
PTIN01
PTIN10
f
GPTA
PTIN11
PTIN00
Interrupt
Control
SR01
SR52
SR53
SR00
To DMA LTC54
GTC30
AS54
TC1765
Data Sheet 28 V1.2, 2002-12
Preliminary
The General Purpose Timer Array (GPTA) provides a set of hardware modules required
for high speed digital signal processing:
• Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation.
• Phase Discrimination Logic units (PDL) decode the direction information output by a
rotation tracking system.
• Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities.
• A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA
module clock ticks during an input signal’s period.
• Global Timer units (GT) driven by various clock sources are implemented to operate
as a time base for the associated “Global Timer Cells”.
• Global Timer Cells (GTC) can be programmed to capture the contents of a Global
Timer on an event that occurred at an external port pin or at an internal FPC output.
A GTC may be also used to control an external port pin with the result of an internal
compare operation. GTCs can be logically concatenated to provide a common
external port pin with a complex signal waveform.
• Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also
logically tied together to drive a common external port pin with a complex signal
waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or
triggered by
– A prescaled GPTA module clock,
– An FPC, PDL, DCM, PLL, or GTC output signal line,
– An external port pin.
Some input lines driven by processor I/O pads may be shared by a LTC and a GTC cell
to trigger their programmed operation simultaneously.
The following list summarizes all blocks supported:
Clock Generation Unit:
• Filter and Prescaler Cell (FPC):
– Six independent units
– Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce
Filter)
–fGPTA down-scaling capability
–fGPTA/2 maximum input signal frequency in Filter Mode
• Phase Discriminator Logic (PDL):
– Two independent units
– Two operating modes (2 and 3 sensor signals)
–fGPTA/4 maximum input signal frequency in 2-sensor mode, fGPTA/6 maximum input
signal frequency in 3-sensor mode
• Duty Cycle Measurement (DCM):
– Four independent units
– 0 - 100% margin and time-out handling
TC1765
Data Sheet 29 V1.2, 2002-12
Preliminary
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
• Digital Phase Locked Loop (PLL):
– One unit
– Arbitrary multiplication factor between 1 and 65535
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
Signal Generation Unit:
• Global Timers (GT):
– Two independent units
– Two operating modes (Free Running Timer and Reload Timer)
– 24-bit data width
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
• Global Timer Cell (GTC):
– 32 independent units
– Two operating modes (Capture, Compare and Capture after Compare)
– 24-bit data width
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
• Local Timer Cell (LTC):
– 64 independent units
– Three operating modes (Timer, Capture and Compare)
– 16-bit data width
–fGPTA maximum resolution
–fGPTA/2 maximum input signal frequency
Interrupt Control Unit:
• 111 interrupt sources generating 54 service requests
I/O Sharing Unit:
• Interconnecting input and output lines from FPC, GTC, LTC and ports
• Emergency function
TC1765
Data Sheet 30 V1.2, 2002-12
Preliminary
Analog-to-Digital Converters
The two on-chip ADC modules of the TC1765 are analog to digital converters with 8-bit,
10-bit or 12-bit resolution including sample & hold functionality. The A/D converters
operate by the method of the successive approximation. A multiplexer selects between
up to 16 analog input channels for each ADC module. The 24 analog inputs are switched
to the analog input channels of the ADC modules by a fixed scheme. Conversion
requests are generated either under software control or by hardware (GPTA). An
automatic self-calibration adjusts the ADC modules to changing temperatures or
process variations.
Features:
• 8-bit, 10-bit, 12-bit A/D Conversion
• Successive approximation conversion method
• Fast conversion times: e.g. 10-bit conversion (without sample time): 2.05 µs
• Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution
• Integrated sample and hold functionality
• 24 analog input pins / 16 analog input channels of each ADC module
• Fix assignment of 24 analog input pins to the 32 ADC0/ADC1 input channels
• Dedicated control and status registers for each analog channel
• Flexible conversion request mechanisms
• Selectable reference voltages for each channel
• Programmable sample and conversion timing schemes
• Limit checking
• Flexible ADC module service request control unit
• Synchronization of the two on-chip A/D Converters
• Automatic control of an external analog input multiplexer for ADC0
• Equidistant samples initiated by timer
• Two trigger inputs, connected with the General Purpose Timer Array (GPTA)
• Two external trigger input pins of each ADC for generating conversion requests
• Power reduction and clock control feature
Figure 10 shows a global view of the ADC module kernel with the module specific
interface connections.
The ADC modules communicate with the external world via five (ADC0) or two (ADC0)
digital I/O lines and sixteen analog inputs. Clock control, address decoding, digital I/O
port control, and service request generation is managed outside the ADC module kernel.
The end of a conversion is indicated for each channel n (n = 0-15) by a pulse on the
output signals SRCHn. These signals can be used to trigger a DMA transfer to read the
conversion result automatically. Two trigger inputs and a synchronization bridge are
used for internal control purposes.
TC1765
Data Sheet 31 V1.2, 2002-12
Preliminary
Figure 10 General Block Diagram of the ADC Interface
MCB05054
Clock
Control
Address
Decoder
f
ADC
GPTA
PTIN00
SR[3:0]
PTIN01
ADC0
Module
Kernel
Synchronization Bridge
ADC1
Module
Kernel
PTIN10
PTIN11
Port 0
Control
P0.0 /
AD0EXTIN0
P0.1 /
AD0EXTIN1
P0.4 /
AD0EMUX0
P0.5 /
AD0EMUX1
P0.6 /
AD0EMUX2
AN0
AN1
AN22
AN23
AIN15
AIN0
AIN1
AIN13
AIN15
Port 0
Control
P0.2 /
AD1EXTIN0
P0.3 /
AD1EXTIN1
Analog Pad to ADC0/ADC1 Input Channel
Connection
V
AGND1
V
SSA1
V
DDA1
V
DDM1
V
AREF1
V
SSM1
V
AGND1
V
SSA1
V
DDA1
V
DDM1
V
AREF1
V
SSM1
Interrupt
Control
SRCH[15:0]
To DMA
Address
Decoder
SR[3:0]
Interrupt
Control
SRCH[15:0]
To DMA
AIN14
AIN1
AIN0
TC1765
Data Sheet 32 V1.2, 2002-12
Preliminary
On-Chip Memories
The memory system of the TC1765 provides the following memories:
• Program Memory Unit (PMU) with
– 8 Kbytes Boot ROM (BROM)
– 16 Kbytes Code Scratch-Pad RAM (SPRAM)
– 1 Kbyte Instruction Cache (ICACHE)
• Data Memory Unit (DMU) with
– 32 Kbytes Data Memory (SRAM)
– Can be used for standby operation during power-down states using a separate
power supply
TC1765
Data Sheet 33 V1.2, 2002-12
Preliminary
Address Map
Table 2 defines the segment oriented address blocks of the TC1765 with its address
range, size, and PMU/DMU access view. Table 3 shows the block address map of
segment 15 which includes the on-chip peripheral units.
Table 2 TC1765 Block Address Map
Seg-
ment
Address
Range
Size Description DMU
Acc.
PMU
Acc.1)
0 - 7 0000 0000H -
7FFF FFFFH
2 GB Reserved – –
8 8000 0000H -
8FFF FFFFH
256 MB Reserved via
FPI
PMU
local
cached
9 9000 0000H -
9FFF FFFFH
256 MB Reserved DMU
local
via FPI
10 A000 0000H -
AFFF FFFFH
256 MB External Memory Space via
FPI
via
EBU or
FPI
11 B000 0000H -
BDFF FFFFH
224 MB External Memory Space
mappable into Segment 10
via
FPI
via
EBU or
FPI
non-cached
BE00 0000H -
BEFF FFFFH
16 MB External Emulator Space via
FPI
BF00 0000H -
BFFF DFFFH
-16 MB Reserved
PMU
local
BFFF E000H -
BFFF FFFFH
8 KB Boot ROM
4 Kbytes general purpose
4 Kbytes factory test support
12 C000 0000H -
C000 3FFFH
16 KB Local Code Scratch-Pad RAM
(SPRAM)
via
FPI
PMU
local
C000 4000H -
C7FF FEFFH
–Reserved
C7FF FF00H -
C7FF FFFFH
256 B PMU Control Registers
C800 0000H -
CFFF FFFFH
–Reserved
TC1765
Data Sheet 34 V1.2, 2002-12
Preliminary
13 D000 0000H -
D000 7FFFH
32 KB Local Data Memory (SRAM)
DMU
local via FPI
non-cached
D000 8000H -
D7FF FEFFH
–Reserved
D7FF FF00H -
D7FF FFFFH
256 B DMU Registers
D800 0000H -
DFFF FFFFH
256 MB Reserved
14 E000 0000H -
EFFF FFFFH
256 MB External Peripheral and
Data Memory Space
via
FPI
not
possi-
ble
15 F000 0000H -
F000 3BFFH
-16 KB On-Chip Peripherals & Ports
via
FPI
not
possi-
ble
non-cached
F000 3C00H -
F000 3DFFH
512 B DMA Registers
F000 3E00H -
F00F FFFFH
–Reserved
F010 0000H -
F010 0BFFH
12 ×
256 B
CAN Module
F010 0C00H -
FFFE FEFFH
–Reserved
FFFE FF00H -
FFFE FFFFH
256 B CPU Slave Interface Registers
(CPS)
FFFF 0000H -
FFFF FFFFH
64 KB Core SFRs + GPRs
1) The PMU can access external memory directly (“via EBU”, only instruction accesses) or via the FPI Bus (“via
FPI”). If both paths are possible as defined in this column, selection is done via SCU_CON.EXTIF.
Table 2 TC1765 Block Address Map (cont’d)
Seg-
ment
Address
Range
Size Description DMU
Acc.
PMU
Acc.1)
TC1765
Data Sheet 35 V1.2, 2002-12
Preliminary
Table 3 Block Address Map of Segment 15
Symbol Description Address Range Size
SCU System Control Unit F000 0000H - F000 00FFH256 Bytes
– Reserved F000 0100H - F000 01FFH–
BCU Bus Control Unit F000 0200H - F000 02FFH256 Bytes
STM System Timer F000 0300H - F000 03FFH256 Bytes
OCDS On-Chip Debug Support F000 0400H - F000 04FFH256 Bytes
EBU External Bus Unit F000 0500H - F000 05FFH256 Bytes
– Reserved F000 0600H - F000 06FFH–
GPTU General Purpose Timer Unit F000 0700H - F000 07FFH256 Bytes
ASC0 Async./Sync. Serial Interface 0 F000 0800H - F000 08FFH256 Bytes
ASC1 Async./Sync. Serial Interface 1 F000 0900H - F000 09FFH256 Bytes
SSC0 High-Speed Synchronous
Serial Interface 0
F000 0A00H - F000-0AFFH256 Bytes
SSC1 High-Speed Synchronous
Serial Interface 1
F000 0B00H - F000-0BFFH256 Bytes
– Reserved F000 0C00H - F000 17FFH–
GPTA General Purpose Timer Array F000 1800H - F000 1FFFH8×256 Bytes
– Reserved F000 2000H - F000 21FFH–
ADC0 Analog-to-Digital Converter 0 F000 2200H - F000 23FFH2×256 Bytes
ADC1 Analog-to-Digital Converter 1 F000 2400H - F000 25FFH2×256 Bytes
– Reserved F000 2600H - F000 27FFH–
P0 Port 0 F000 2800H - F000 28FFH256 Bytes
P1 Port 1 F000 2900H - F000 29FFH256 Bytes
P2 Port 2 F000 2A00H - F000 2AFFH256 Bytes
P3 Port 3 F000 2B00H - F000 2BFFH256 Bytes
P4 Port 4 F000 2C00H - F000 2CFFH256 Bytes
P5 Port 5 F000 2D00H - F000 2DFFH256 Bytes
– Reserved F000 2E00H - F000 3BFFH–
DMA DMA Controller F000 3C00H - F000 3DFFH2×256 Bytes
– Reserved F000 3E00H - F00F FFFFH–
CAN1) Controller Area Network
Module
F010 0000H - F010 0BFFH12 ×256 Bytes
TC1765
Data Sheet 36 V1.2, 2002-12
Preliminary
– Reserved F010 0C00H - FFFE FEFFH–
CPU Slave Interface Registers
(CPS)
FFFE FF00H - FFFE FFFFH256 Bytes
Reserved FFFF 0000H - FFFF BFFFH–
Memory Protection Registers FFFF C000H - FFFF EFFFH12 Kbytes
Reserved FFFF F000H - FFFF FCFFH–
Core Debug Registers (OCDS) FFFF FD00H - FFFF FDFFH256 Bytes
Core Special Function
Registers (CSFRs)
FFFF FE00H - FFFF FEFFH256 Bytes
General Purpose Registers
(GPRs)
FFFF FF00H - FFFF FFFFH256 Bytes
1) Access to unused address regions within this peripheral unit don’t generate a bus error.
Table 3 Block Address Map of Segment 15 (cont’d)
Symbol Description Address Range Size
TC1765
Data Sheet 37 V1.2, 2002-12
Preliminary
Memory Protection System
The TC1765 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the kinds of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1765, numbered 0 and 1,
which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU.
Because the TC1765 uses a Harvard-style memory architecture, each Memory
Protection Register Set is broken down into a Data Protection Register Set and a Code
Protection Register Set. Each Data Protection Register Set can specify up to four
address ranges to receive particular protection modes. Each Code Protection Register
Set can specify up to two address ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Mode Register) which determines the memory access modes which apply to the
specified range.
TC1765
Data Sheet 38 V1.2, 2002-12
Preliminary
On-Chip FPI Bus
The FPI Bus interconnects the functional units of the TC1765, such as the CPU and on-
chip peripheral components. The FPI Bus also interconnects the TC1765 to external
components by way of the External Bus Controller Unit (EBU). The FPI Bus is designed
to be quick to acquire by on-chip functional units, and quick to transfer data. The low
setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition,
which is required for time-critical applications. The FPI Bus is designed to sustain high
transfer rates. For example, a peak transfer rate of up to 160 Mbyte/s can be achieved
with a 40 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration
cycle allow the FPI Bus to operate at close to its peak bandwidth.
Features:
• Supports multiple bus masters
• Supports demultiplexed address/data operation
• Address and data buses are 32 bits wide
• Data transfer types include 8-, 16-, and 32-bit sizes
• Single- and multiple-data transfers per bus acquisition cycle
• Designed to minimize EMI and power consumption
TC1765
Data Sheet 39 V1.2, 2002-12
Preliminary
External Bus Unit
The External Bus Unit (EBU) of the TC1765 is the interface between external memories
and peripheral units and the internal memories and peripheral units. The basic structure
of the EBU is shown in Figure 11.
Figure 11 EBU Structure and Interfaces
The EBU consists of two parts and is used for the following two operations:
• FBU (FPI Bus Unit):
– Communication with external memories or peripheral units via the FPI Bus
– Non-burst instruction fetches
• BIFU (Burst Instruction Fetch Unit):
– Instruction fetches from the PMU to external Burst Flash program memories with
16-bit and 32-bit data width
The EBU controls all transactions required for these two operations and in particular
handles the arbitration between these two tasks.
The types of external devices/Bus modes controlled by the FBU are:
– INTEL style peripherals (separate RD and WR signals)
– MOTOROLA style peripherals (OE and R/W)
–ROMs, EPROMs
– Static RAMs
– Peripherals with demultiplexed A/D bus
– Burst Mode Flash Memories
– 8-, 16- and 32-bit data bus width
MCA04983
TriCore
CPU
PMU
with on-chip
Progam Memory
DMU
with on-chip
Data Memory
EBU
Control
Lines
Chip Select
Lines
A[23:0]
D[31:0]
FPI Bus
Burst Mode
Instruction
Fetches
To Peripheral
Units and DMA
5
ECOUT
ECIN
BIFU
FBU
10
TC1765
Data Sheet 40 V1.2, 2002-12
Preliminary
DMA Controller
The Direct Memory Access (DMA) Controller executes DMA transactions from a source
address location to a destination address location, without intervention of the CPU. One
DMA transaction is controlled by one DMA channel.
Each of the two blocks in the DMA controller, block 0 and block 1 (see Figure 12),
provides four DMA channels with sixteen DMA request inputs. The request assignment
unit in each sub-block assigns one DMA request input to each DMA channel. The control
unit includes a third request unit dedicated especially for request control through I/O
pins. This unit connects two of eight request inputs with two request outputs which can
be then wired externally of the DMA controller module to the request inputs of the two
DMA controller blocks. Request assignment unit 2 evaluates pulses or levels by its edge
detect and level select logic.
Features:
• 8 independent DMA channels (4 per DMA block)
– 4 DMA selectable request inputs per DMA channel
– Fixed priority of DMA channels within a DMA block
– Software and hardware DMA request generation
• Support of FPI Bus to FPI Bus DMA transactions
• Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated
• Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Source and destination transfer individually programmable in steps from 0 to
255 bytes
– Support of circular buffer addressing mode
• Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit
• Register set for each DMA channel
– Source and destination start address register
– Source and destination end address register
– Channel control and status register
– Offset and transfer count register
• Bus bandwidth allocation
• Flexible interrupt generation
Figure 12 shows the TC1765 specific implementation details and interconnections of
the DMA module. The DMA module is further supplied by a separate clock control,
address decoding, interrupt control, port control logic.
TC1765
Data Sheet 41 V1.2, 2002-12
Preliminary
Figure 12 DMA Module Block Diagram with Interconnections
MCB04965
Clock
Control
Address
Decoder
Interrupt
Control
SR1
SR6
SR0
Control
Unit
SR7
16
16
Sub-Block 0
Request
Assign.
Unit 0
DMA
Channels
00-03
Sub-Block 1
Request
Assign.
Unit 1
DMA
Channels
10-13
4
4
Request
Assign.
Unit 2
DMA Controller
P0.1 /
DMREQ0A
P4.1 /
DMREQ0B
P5.0 /
DMREQ0C
GPTA3
(GTC30)
ASC0
ASC1
SSC0
SSC1
ADC0
ADC1
GPTA3
(LTC54)
P0.2 /
DMREQ1A
P4.2 /
DMREQ1B
P5.1 /
DMREQ1C
REQO0
REQO1
DMA
Request
Wiring
Matrix
f
DMA
TC1765
Data Sheet 42 V1.2, 2002-12
Preliminary
System Timer
The TC1765’s System Timer (STM) is designed for global system timing applications
requiring both high precision and long range. The STM has the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Driven by clock fSTM (identical to the system clock fSYS)
• Counting starts automatically after a reset operation (except a hardware reset)
The STM is an upward counter, running with the system clock frequency (fSTM =fSYS).
It is enabled per default after reset, and immediately starts counting up. Other than via
reset, it is no possible to affect the contents of the timer during normal operation of the
application, it can only be read, but not written to. Depending on the implementation of
the clock control of the STM, the timer can optionally be disabled or suspended for
power-saving and debugging purposes via a clock control register.
The maximum clock period is 256 ×1 / fSTM. At fSTM = 40 MHz, for example, the STM
counts 57.1 years before overflowing. Thus, it is capable of continuously timing the entire
expected product life-time of a system without overflowing.
Figure 13 Block Diagram of the System Timer Module
STM Module
00
H
CAP
TIM6
TIM5
TIM4
TIM3
TIM2
TIM1
TIM0
00
H
55 47 39 31 23 15 7
56-Bit System Timer
Address
Decoder
Clock
Control
Enable /
Disable
PORST
f
STM
MCA04795
TC1765
Data Sheet 43 V1.2, 2002-12
Preliminary
Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failure. The WDT helps to abort an accidental
malfunction of the TC1765 in a user-specified time period. When enabled, the WDT will
cause the TC1765 system to be reset if the WDT is not serviced within a user-
programmable time period. The CPU must service the WDT within this time interval to
prevent the WDT from causing a TC1765 system reset. Hence, routine service of the
WDT confirms that the system is functioning properly.
In addition to this standard “Watchdog” function, the WDT incorporates the EndInit
feature and monitors its modifications. A system-wide line is connected to the ENDINIT
bit implemented in a WDT control register, serving as an additional write-protection for
critical registers (besides Supervisor Mode protection).
A further enhancement in the TC1765’s Watchdog Timer is its reset prewarning
operation. Instead of immediately resetting the device on the detection of an error, as
known from standard Watchdogs, the WDT first issues an Non-maskable Interrupt (NMI)
to the CPU before finally resetting the device at a specified time period later. This gives
the CPU a chance to save system state to memory for later examination of the cause of
the malfunction, an important aid in debugging.
Features:
• 16-bit Watchdog counter
• Selectable input frequency: fSYS/256 or fSYS/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated password access mechanism with fixed and user-definable password
fields
• Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and limited.
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
• Double Reset Detection: If a Watchdog induced reset occurs twice without a proper
access to its control register in between, a severe system malfunction is assumed and
the TC1765 is held in reset until a power-on reset. This prevents the device from being
periodically reset if, for instance, connection to the external memory has been lost
such that even system initialization could not be performed.
TC1765
Data Sheet 44 V1.2, 2002-12
Preliminary
• Important debugging support is provided through the reset prewarning operation by
first issuing an NMI to the CPU before finally resetting the device after a certain period
of time.
System Control Unit
The System Control Unit (SCU) of the TC1765 handles the system control tasks. All
these system functions are tightly coupled, thus, they are conveniently handled by one
unit, the SCU. The system tasks of the SCU are:
• Reset Control
– Generation of all internal reset signals
– Generation of external HDRST reset signal
• PLL Control
– PLL_CLC Clock Control Register
• Power Management Control
– Enabling of several power-down modes
– Control of the PLL in power-down modes
• Watchdog Timer
• Trace Control and Trace Status indication
• Pull-up/pull-down I/O control
• Device Identification
TC1765
Data Sheet 45 V1.2, 2002-12
Preliminary
Interrupt System
An interrupt request is serviced by the CPU. Interrupt requests are also called “Service
Requests” because they are serviced by a “Service Provider”, the CPU.
Each peripheral unit in the TC1765 typically generates service requests. Additionally, the
Bus Control Unit, the Debug Unit, the DMA controller, and even the CPU itself can
generate service requests. Several peripheral units are able to generate in parallel to a
service request DMA requests to the DMA Controller.
As shown in Figure 14, each TC1765 unit that can generate service requests is
connected to one or multiple Service Request Nodes (SRN). Each SRN contains a
Service Request Control Register mod_SRCx, where “mod” is the identifier of the
service requesting unit and “x” an optional index. The Interrupt arbitration bus connects
the SRNs with the Interrupt Control Unit, which handles interrupt arbitration among
competing interrupt service requests.
Units which can generate service requests are:
– General Purpose Timer Unit (GPTU) with 8 SRNs
– General Purpose Timer Array (GPTA) with 54 SRNs
– Two High-Speed Synchronous Serial Interfaces (SSC0/SSC1) with 3 SRNs each
– Two Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) with 4 SRNs each
– TwinCAN controller with 8 SRNs
– Two Analog/Digital Converters (ADC0/ADC1) with 4 SRNs each
– Bus Control Unit (BCU) with 1 SRN
– DMA Controller Processor (DMA) with 8 SRNs
– Central Processing Unit (CPU) with 4 SRNs
– Debug Unit (OCDS) with 1 SRN
– Central Processing Unit (CPU) with 4 SRNs (software activated)
External interrupt inputs in TC1765 are available using the input pins connected to the
General Purpose Timer Unit (GPTU). Each of the seven GPTU I/O pins can be used as
an external interrupt input, using the Service Request Nodes of the GPTU module.
Additionally, such an external interrupt input can also trigger a timer function.
TC1765
Data Sheet 46 V1.2, 2002-12
Preliminary
Figure 14 Block Diagram of the TC1765 Interrupt System
MCB04993
54 SRNs
8 SRNs
8
GPTU
54
GPTA
3 SRNs
3
SSC0
3 SRNs
3
SSC1
4 SRNs
4
ASC0
4 SRNs
4
ASC1
8 SRNs
8
CAN
8 SRNs
8
DMA
4 SRNs
4
ADC0
4 SRNs
4
ADC1
11 SRNBCU
Service
Request
Nodes
Service
Requestors
8
54
3
3
4
4
8
8
4
4
1
Interrupt
Arbitration Bus
1
Debug
Unit
44 SRNs 4
Int. Req.
PIPN
CPU
CCPN
Int. Ack.
Software
Interrupts
1
Interrupt
Control
Unit
ICU
DMA
Request Bus
2
2
2
2
6
6
1 SRN
1
TC1765
Data Sheet 47 V1.2, 2002-12
Preliminary
Boot Options
The TC1765 booting schemes provides a number of different boot options for the start
of code execution. Table 4 shows the boot options available in the TC1765.
Table 4 TC1765 Boot Selections
OCDSE BRKIN CFG[2:0] Type of Boot Boot Source PC Start
Value
11000
BStart from Boot ROM
Entry Point 1
Boot ROM BFFF FFFCH
001BStart from Boot ROM
Entry Point 2
010BStart from Boot ROM
Entry Point 3
011BStart from Boot ROM
Entry Point 4
100BExternal memory as
master directly
PMU - EBU
External
Memory
A000 0000H
101BExternal memory via
PMU - FPI Bus - EBU
110BReserved; don’t use these combinations.
111B
01100
B
or
101B
Go to halt with EBU
enabled as master
––
all other
combina-
tions
Go to halt with EBU
disabled
0 0 – Go to external emulator
space
– BE00 0000H
1 0 – Tri-state chip
(deep sleep)
––
TC1765
Data Sheet 48 V1.2, 2002-12
Preliminary
Power Management System
The TC1765 power management system allows software to configure the various
processing units so that they automatically adjust to draw the minimum necessary power
for the application.
There are four power management modes:
•Run Mode
• Idle Mode
• Sleep Mode
• Deep Sleep Mode
Table 5 describes the features of the power management modes.
Table 5 Power Management Mode Summary
Mode Description
Run The system is fully operational. All clocks and peripherals are enabled,
as determined by software.
Idle The CPU clock is disabled, waiting for a condition to return it to Run
Mode. Idle Mode can be entered by software when the processor has no
active tasks to perform. All peripherals remain powered and clocked.
Processor memory is accessible to peripherals. A reset, Watchdog Timer
event, a falling edge on the NMI pin, or any enabled interrupt event will
return the system to Run Mode.
Sleep The system clock continues to be distributed only to those peripherals
programmed to operate in Sleep Mode. Interrupts from operating
peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset
event will return the system to Run Mode. Entering this state requires an
orderly shut-down controlled by the Power Management State Machine.
Deep Sleep The system clock is shut off; only an external signal will restart the
system. Entering this state requires an orderly shut-down controlled by
the Power Management State Machine (PMSM).
TC1765
Data Sheet 49 V1.2, 2002-12
Preliminary
On-Chip Debug Support
The On-Chip Debug Support (OCDS) of the TC1765 consists of four building blocks:
• OCDS module in the TriCore CPU
– On-chip breakpoint hardware
– Support of an external break signal
•Trace module
– Outputs 16 bits each fSYS system clock cycle at TP[15:0] with pipeline status
information, PC bus information, and breakpoint qualification information
• DMA Controller Trace
– Indication of address counter updates
• Debugger Interface Cerberus
– Provided for debug purposes of emulation tool vendors
– Accessible through a JTAG standard interface with dedicated JTAG port pins
Figure 15 shows a basic block diagram of the building blocks.
.
Figure 15 OCDS Basic Block Diagram
SCU
Trace
Control
&
Status
MCB04995
Cerberus &
JTAG
TRST
TCK
TMS
TDI
TDO
JTAG
I/O Lines
TriCore
CPU
BRKIN
BRKOUT
TP[15:0]
(TC1765T only)
OCDSE
FPI Bus
OCDS/TCU
DMA
Controller
16
16
16
Trace
TC1765
Data Sheet 50 V1.2, 2002-12
Preliminary
Clock Generation Unit
The Clock Generation Unit (CGU) in the TC1765, shown in Figure 16, consists of an
oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it looses its lock on the external clock.
In general, the CGU is controlled through the System Control Unit (SCU) module of the
TC1765.
Figure 16 Clock Generation Unit Block Diagram
MCA04974
Oscillator
Circuit
XTAL1
XTAL2
&
f
OSC
Phase
Detect. VCO
N
Divider
PLL
f
VCO
f
SYS
System_
CLK
Lock
Detector
OSC_OK Deep
Sleep
BYPASS
1
0
MUX
Clock Generation Unit
CGU
System Control Unit
SCU
K
Divider
Register PLL_CLC
KDIVLOCK PLLBYP
TC1765
Data Sheet 51 V1.2, 2002-12
Preliminary
PLL Operation
The fVCO clock of the PLL has a frequency which is a multiple of the externally applied
clock fOSC. The factor for this is controlled through the fix divider value N (N = 10) applied
to the divider in the feedback path. The K-Divider is defined by bit field KDIV. Table 6
lists the possible values for KDIV and the resulting division factor.
The VCO output frequency and the resulting system clock is determined by:
Table 6 Output Frequencies fSYS Derived from Various Output Factors
K-Factor fSYS Duty
Cycle
[%]
Selected
Factor
KDIV fVCO =
150 MHz
fVCO =
160 MHz
fVCO =
200 MHz
2 000B751)
1) These combinations cannot be used because the maximum system clock of 40 MHz is exceeded.
801) 1001) 50
4 010B37.5 40 501) 50
52)
2) These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle).
011B30 32 40 40
6 100B24.5 26.67 33.33 50
8 101B18.75 20 25 50
92) 110B16.67 17.78 22.22 44
10 111B15 16 20 50
16 001B9.38 10 12.5 50
fVCO = 10 × fOSC fSYS = fVCO / K = ×fOSC
10
K
TC1765
Data Sheet 52 V1.2, 2002-12
Preliminary
Recommended Oscillator Circuits
The oscillator circuit, designed to work with both, an external crystal oscillator or an
external stable clock source, basically consists of an inverting amplifier with XTAL1 as
input and XTAL2 as output. When using a crystal, a proper external oscillator circuitry
must be used, connected to both pins, XTAL1 and XTAL2. The on-chip oscillator
frequency can be within the range of 4 MHz to 16 MHz. When using an external clock
signal it must be connected to XTAL1. XTAL2 is left open (unconnected). For direct drive
operation without PLL, the frequency of an external clock must not exceed 40 MHz.
Figure 17 shows the recommended external oscillator circuitries for both operating
modes, external crystal mode and external input clock mode.
Figure 17 Oscillator Circuitries
For the oscillator of the TC1765 the following external passive components are
recommended:
– Crystal: max. 16 MHz
–C1, C2: 10 pF
A block capacitor between VDDOSC and VSSOSC is recommended, too.
–C1, C2: 12 pF
Note: For crystal operation, it is strongly recommended to measure the negative
resistance in the final target system (layout) to determine the optimum parameters
for the oscillator operation. Please refer to the minimum and maximum values of
the negative resistance specified by the crystal supplier.
MCB04996
TC1765
Oscillator
V
DDOSC
V
SSOSC
C
1
4-16
MHz
C
2
XTAL1
XTAL2
TC1765
Oscillator
V
DDOSC
V
SSOSC
XTAL1
XTAL2
External
Clock Signal
TC1765
Data Sheet 53 V1.2, 2002-12
Preliminary
Power Supply
Figure 18 shows the TC1765’s power supply concept, where certain logic modules are
individually supplied with power. This concept improves the EMI behavior by reduction
of the noise cross coupling. Also the operation margin is improved in sensitive modules
like the A/D converter by noise reduction.
Figure 18 TC1765 Power Supply Concept
TC1765
MCD05227
CPU &
Control &
Peripherals
EBU, TP
V
DDP
(3.3 - 5 V)
V
SS
V
DDSBRAM
(2.5 V)
V
SS
V
DDRAM
(2.5 V)
V
SS
ADC0
Control Logic
ADC1
Control Logic
V
DDA0
(2.5 V)
V
SSA0
V
DDM
(5 V)
V
SSM
V
DDA1
(2.5 V)
V
SSA1
DMU PMU
GPIO Ports
(P0-P5) &
dedicated
Pins
V
DD
(2.5 V)
V
SS
V
DDOSC
(2.5 V)
V
SSOSC
OSC
TC1765
Data Sheet 54 V1.2, 2002-12
Preliminary
Ports Power Supply
The TC1765’s port power supply concept is shown in Figure 19. The External Bus Unit
(EBU) I/O lines are in the core and EBU VDD power supply group for 2.5 V nominal
operating voltage. The general purpose input/outputs (GPIOs) provide 3.3 to 5 V nominal
voltage input/output acceptance and drive characteristics.
Figure 19 Ports Power Supply Concept
Power-up Sequence
During Power-up the reset pin PORST has to be held active until both power supply
voltages have reached at least their minimum values.
During the Power-up time (rising of the supply voltages from 0 to their regular operating
values) it has to be ensured, that the difference between VDDP and VDD never drops
below -0.5 V.
Power Loss
If VDDP is dropping below VDD, external circuitry in the power supply has to ensure, that
VDD is also limited to the same level.
If VDDI is dropping below the operating range, VDDP may stay active.
Powering Down
During powering down (falling of the supply voltages from their regular operating values
to zero), it has to be ensured, that the difference between VDDP and VDD never drops
below -0.5 V.
MCA05226
V
SS
EBU I/O Lines
(Pads)
&
Schmitt Trigger
Ports 0 to 5
(Pads)
&
Schmitt Trigger
V
DD
(2.5 V)
V
DDP
(3.3 - 5 V)
Port Logic
TC1765
Data Sheet 55 V1.2, 2002-12
Preliminary
Identification Register Values
Table 7 TC1765 Identification Registers
Short Name Address Value
PMU_ID C7FF FF08H0006 C003H
DMU_ID D7FF FF08H0007 C003H
SCU_ID F000 0008H0003 C003H
MANID F000 0070H0000 1820H
CHIPID F000 0074H0000 8601H
RTID F000 0078H0000 0000H
BCU_ID F000 0208H0000 6A05H
STM_ID F000 0308H0000 C002H
JPD_ID F000 0408H0000 6301H
EBU_ID F000 0508H0005 C004H
GPTU_ID F000 0708H0001 C002H
ASC0_ID F000 0808H0000 4401H
ASC1_ID F000 0908H0000 4401H
SSC0_ID F000 0A08H0000 4525H
SSC1_ID F000 0B08H0000 4525H
GPTA_ID F000 1808H0002 C002H
ADC0_ID F000 2208H0000 3103H
DMA_ID F000 3F08H0018 C001H
CAN_ID F010 0008H0000 4110H
CPU_ID FFFE FF08H0000 0202H
TC1765
Data Sheet 56 V1.2, 2002-12
Preliminary
Parameter Interpretation
The parameters listed on the following pages partly represent the characteristics of the
TC1765 and partly its demands on the system. To aid in interpreting the parameters
right, when evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the TC1765 will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to
the TC1765.
Pin Classes
The TC1765 has three classes of digital I/O pins:
–Class A pins, which are 3.0 to 5.25 V voltage pins
–Class B pins, which are 2.5 V nominal voltage pins (input tolerant for 3.3 V)
–Class C pins, which are 2.5 V nominal voltage pins only
Table 8 shows the assignments of all digital I/O pins to pin classes and to VDD power
supply pins.
Table 8 Assignments of Digital Pins to Pin Classes and Power Supply Pins
Pins Pin Classes Power Supply
Port 0 to Port 5,
BYPASS, HDRST
Class A
(3.0 to 5.25 V)
VDDP VSS
D[31:0], A[23:0], CS[3:0],
CSEMU/CSOVL, BC[3:0],
RD, RD/WR, ADV,
WAIT/IND, BAA, CODE,
TRST, TCK, TDI, TDO, TMS,
ODCSE, BRKIN, BRKOUT,
NMI, PORST,
ECOUT, ECIN, CPUCLK,
TESTMODE, TP[15:0]
Class B
(nominal 2.5 V)
VDD
XTAL1, XTAL2 Class C
(nominal 2.5 V)
VDDOSC VSSOSC
No pins assigned (nominal 2.5 V) VDDRAM
VDDSBRAM
VSS
TC1765
Data Sheet 57 V1.2, 2002-12
Preliminary
Absolute Maximum Ratings
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Parameter Symbol Limit Values Unit Notes
min. max.
Ambient temperature TA-40 125 °C under bias
Storage temperature TA-65 150 °C–
Junction temperature TJ–150°C under bias
Voltage on VDDP with respect to
VSS
VDD -0.5 6.2 V see Table 8
Voltage on VDD, VDDOSC,
VDDRAM and VDDSBRAM with
respect to VSS
VDD -0.5 3.25 V –
Voltage on any Class A input pin
with respect to VSS
VIN -0.5 VDD + 0.5 V –
Voltage on any Class B input pin
with respect to VSS
VIN -0.5 3.7 V –
Voltage on any Class C input pin
with respect to VSS
VIN -0.5 VDDOSC
+ 0.5
V–
Input current on any pin during
overload condition
IIN -10 10 mA –
Absolute sum of all input currents
during overload condition
ΣIIN – |100| mA –
TC1765
Data Sheet 58 V1.2, 2002-12
Preliminary
Package Parameters (P-LBGA-260)
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1765. All parameters specified in the following table refer to these
operating conditions, unless otherwise noticed.
Parameter Symbol Limit Values Unit Notes
min. max.
Power dissipation PDISS –0.9W–
Thermal resistance RTHA – 24.8 K/W Chip to ambient
Parameter Symbol Limit Values Unit Notes
min. max.
Digital supply voltage1) VDDP 3.0 5.252) VClass A pins
VDD
VDDOSC
VDDRAM
2.3 2.753) V Class B and
Class C pins4)
VDDSBRAM 2.25 2.75 V 4)5)
Digital ground voltage VSS 0V–
Ambient temperature under
bias
TA-40 +125 °C–
Analog supply voltages VDDA 2.25 2.75 V –
VDDM 4.5 5.25 V –
Analog reference voltage VAREF 4VDDM +
0.05
V6)
Analog ground voltage VAGND VSSA -
0.05
VSSA +
0.05
V7)
Analog input voltage VAIN VAGND VAREF V–
CPU clock fSYS –40MHz–
Overload current IOV -10 10 mA 8)9)10)
Short circuit current ISC -10 10 mA 5)6)11)
Absolute sum of overload +
short circuit currents Σ|IOV| +
|ISC|
–|50|mA
9)
External load capacitance CL–50pF–
TC1765
Data Sheet 59 V1.2, 2002-12
Preliminary
1) Digital supply voltages applied to the TC1765 must be static regulated voltages which allow a typical voltage
swing of ±10%.
2) Voltage overshoot to 6.5 V is permissible, provided that the pulse duration is less than 100 µs and the
cumulated summary of the pulses does not exceed 1 hour.
3) Voltage overshoot to 4 V is permissible, provided that the pulse duration is less than 100 µs and the cumulated
summary of the pulses does not exceed 1 hour.
4) In order to minimize the danger of latch-up conditions, these 2.5 V VDD power supply pins should be kept at
the same voltage level during normal operating mode. This condition is typically achieved by generating the
2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a
separate stand-by power supply VDDSBRAM is used.
5) The minimum voltage at pin VDDSBRAM during TC1765 power down mode is 1.8 V in order to keep the contents
of SBRAM valid. The core power supply VDD must be below the standby power supply VDD < VDDSBRAM +
0.3 V.
6) The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range.
7) The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range.
8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload
currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits.
9) Not 100% tested, guaranteed by design and characterization.
10) Applicable for analog inputs.
11) Applicable for digital inputs.
TC1765
Data Sheet 60 V1.2, 2002-12
Preliminary
DC Characteristics
Input/Output DC-Characteristics
VSS = 0 V; TA = -40 °C to +125 °C;
Parameter1) Symbol Limit Values Unit Test Conditions
min. max.
Class A Pins (VDDP = 3.0 to 5.25 V)
Output low voltage2) VOL CC – 0.45 V IOL = 2.4 mA3)
IOL = 600 µA4)
VDDP = 4.5 to 5.25 V
0.2 ×
VDDP
VIOL = 2.4 mA
IOL = 600 µA4)
VDDP = 3.0 to 4.49 V
Output high voltage2) VOH CC 0.7 ×
VDDP
–VIOH = -2.4 mA
IOH = -600 µA4)
VDDP = 4.5 to 5.25 V
VIOH = -2.4 mA
IOH = -600 µA4)
VDDP = 3.0 to 4.49 V
Input low voltage5) VIL SR -0.5 0.8 V VDDP = 4.5 to 5.25 V
(TTL)
0.45 ×
VDDP
VVDDP = 4.5 to 5.25 V
(CMOS)
0.2 ×
VDDP
VVDDP = 3.0 to 4.49 V
(CMOS)
Input high voltage5) VIH SR 2.0 VDDP
+0.5
VVDDP = 4.5 to 5.25 V
(TTL)
0.73 ×
VDDP
VVDDP = 3.0 to 5.25 V
(CMOS)
Pull-up current6)7) |IPUH| CC – 10 µAVOUT = VDDP - 0.02 V
|IPUL| CC 120 600 µAVOUT = 0.5 × VDDP
Pull-down current8)7) |IPDL| CC – 10 µAVOUT = 0.02 V
|IPDH| CC 120 700 µAVOUT = 0.5 × VDDP
TC1765
Data Sheet 61 V1.2, 2002-12
Preliminary
Class B Pins (VDDP05 = 2.30 to 2.75 V)
Output low voltage VOL CC – 0.2 ×
VDD
VIOL = 2.4 mA
0.45 V IOL = 600 µA
Output high voltage VOH CC 0.7 × VDD –VIOH = -2.4 mA
0.9 × VDD –VIOH = -600 µA
Input high voltage VIH SR 0.7 × VDD 3.7 V –
Input low voltage VIL SR -0.5 0.2 ×
VDD
V–
Pull-up current6)7) |IPUH| CC – 10 µAVOUT = VDD - 0.02 V
|IPUL| CC 50 250 µAVOUT = 0.5 × VDD
Pull-down current8)7) |IPDL| CC – 10 µAVOUT = 0.02 V
|IPDH| CC 40 300 µAVOUT = 0.5 × VDD
Class A and B Pins
Input Hysteresis HYS CC 0.030 ×
VDDx9) –VCMOS only
10)
VDDx limits see11)
Input leakage current
(Digital I/O)
IOZ2 CC – ±500 nA 0 V < VIN < VDDx9)
Peak short-circuit
current
Peak back-drive
current
(per digital pin)
Peak time & period
time12)13)
ISCBDpeak
SR
–±20 mA 14)10)
Constant short-circuit
current
Constant back-drive
current
(per digital pin)
ISCBDcons
SR
–±10 mA 14)10)
Input/Output DC-Characteristics (cont’d)
VSS = 0 V; TA = -40 °C to +125 °C;
Parameter1) Symbol Limit Values Unit Test Conditions
min. max.
TC1765
Data Sheet 62 V1.2, 2002-12
Preliminary
Pin capacitance10)
(Digital I/O)
CIO CC – 10 pF f = 1 MHz
TA = 25 °C
Class C Pins (VDDOSC = 2.30 to 2.75 V), see Page 68
1) All Class A pins of the TC1765 are equipped with Low-Noise output drivers, which significantly improve the
device’s EMI performance. These Low-Noise drivers deliver their maximum current only until the respective
target output level is reached. After that the output current is reduced. This results in an increased impedance
of the driver, which attenuates electrical noise from the connected PCB tracks. The current, which is specified
in column “Test Conditions”, is delivered in any case.
2) This specification is not valid for outputs of GPIO lines, which are switched to open drain mode. In open drain
mode the output will float and the voltage results from the external circuitry.
3) Output drivers in high current mode.
4) Condition for output driver in dynamic current mode & low current mode – guaranteed by design
characterization.
5) Input characteristics can be switched between TTL and CMOS via register Px_PICON except for dedicated
pins which have CMOS input characteristics.
6) The maximum current can be drawn while the respective signal line remains inactive.
7) The two pull-up/pull-down current test conditions for VOUT cover the curves as shown in Figure 20 and
Figure 21. All pull-up/pull-down currents are given as absolute values.
8) The minimum current must be drawn in order to drive the respective signal line active.
9) In case of Class B pins VDDx = VDD. In case of Class A pins VDDx = VDDP.
10) Guaranteed by design characterization.
11) The test condition for Class A pins is: VDDP = 4.5 to 5.25 V; for Class B pins: VDD = 2.3 to 2.75 V;
12) The max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 mA and the peak
period equivalent of 10 mA constant-short-circuit current resp. 10 mA constant-back-drive current. The integral
of ISCBDpeak over the peak period is thus limited to 10 mA (provided: ISCBDpeak ≤ 20 mA).
13) To be defined for Class B pads.
14) Short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the
specified operating range (i.e. VSCBD > VDDP + 0.5 V or VSCBD < VSS - 0.5 V) or a short circuit condition occurs
on the respective pin. The absolute sum of input ISCBD and IOV currents on all port pins must not exceed
100 mA at any time. The supply voltage (VDDP and VSS) must remain within the specified limits. Under short-
circuit conditions the corresponding pin is not ready for use. In case of Class B pins VDDx = VDD. In case of
Class A pins VDDx = VDDP.
Input/Output DC-Characteristics (cont’d)
VSS = 0 V; TA = -40 °C to +125 °C;
Parameter1) Symbol Limit Values Unit Test Conditions
min. max.
TC1765
Data Sheet 63 V1.2, 2002-12
Preliminary
Pull-Up/Pull-Down Characteristics
Figure 20 Pull-Up/Pull-Down Characteristics of Class A Pins
MCD05139
0
0
µA
I
V
V123456
Pull-up
0
0
µA
I
V
V123456
Pull-down
Best Case
Nominal
100
200
300
400
500
600
700
100
200
300
400
500
600
700
Worst Case
Nominal
Best Case
Worst Case
TC1765
Data Sheet 64 V1.2, 2002-12
Preliminary
Figure 21 Pull-Up/Pull-Down Characteristics of Class B Pins
Note: The pull-up/pull-down characteristics as shown in Figure 20 and Figure 21 are
guaranteed by design characterization.
MCD05140
0
0
50
100
150
200
250
µA
I
V
V0.5 1 1.5 2 2.5 3
Pull-up
0
0
50
100
150
200
250
µA
I
V
V0.5 1 1.5 2 2.5 3
Pull-down
Best Case
Nominal
Worst Case
Worst Case
Nominal
Best Case
TC1765
Data Sheet 65 V1.2, 2002-12
Preliminary
AD Converter Characteristics
VSS = 0 V; TA= -40 °C to +125 °C;
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
Analog supply voltages VDDAx SR 2.25 2.5 2.75 V 1)
VDDM SR 4.5 5 5.25 V –
Analog ground voltage VSSAx SR -0.1 – 0.1 V 1)
Analog reference
voltage
VAREFx SR 4 – VDDM + 0.05 V 1)2)
Analog reference
ground
VAGNDx SR VSSAx -
0.05
–VSSAx + 0.05 V 1)3)
Analog input voltage
range
VAIN SR VAGNDx –VAREFx V1)
Internal ADC clock fANA 0.5 – 5 MHz –
Power-up calibration
time
tPUC CC – – 3328 × (3 +
CON.CPS)
×tBC
µs–
Sample time tSCC (3 + CON.CPS) ×
(CHCONn.STC + 2) × tBC
µs4)
6 × tBC –– µs
Conversion time tCCC tS + (30 + CON.CPS × 4)
×tBC + 2 × tDIV
µs for 8-bit conv.4)
tS + (36 + CON.CPS × 4)
×tBC + 2 × tDIV
µs for 10-bit conv.4)
ts + (42 + CON.CPS × 4)
×tBC + 2 × tDIV
µs for 12-bit conv.4)
Total unadjusted error TUE5) CC – – ±1 LSB for 8-bit conv.
––±2 LSB for 10-bit conv.
––±6 LSB for 12-bit conv.
Overload current6) IAOV17) CC -2 – +5 mA –
-2 0 mA kA=1.0 × 10-3
0+5mAkA=1.0 × 10-4
IAOV28) CC -4 – +10 mA –
-4 0 mA kA=1.0 × 10-3
0+10mAkA=1.0 × 10-4
Overload coupling factor
9) kACC – – 1.0 × 10-3 – see IAOV1 and
IAOV2
1.0 × 10-4 –
TC1765
Data Sheet 66 V1.2, 2002-12
Preliminary
Input leakage current at
analog inputs
IOZ1 CC – – ±200 nA 0 V< VIN < VDDA1)
Input leakage current at
VAGND and VAREF
IOZ2 CC – – ±500 nA 0 V< VIN < VDDA1)
Switched cap. at
positive reference
voltage input
CAREFSW
CC
–1520 pF
10)
Switched cap. at
negative reference
voltage input
CAGNDSW
CC
–1520 pF
10)
Total capacitance at
analog voltage input
CAINTOTCC
–1215 pF–
Switched cap. at analog
voltage input
CAINSW CC – – 10 pF 11)
ON resistance of the
transmission gates in
the analog voltage path
RAIN CC – – 0.7 kΩ–
1) Suffix x = 0 refers to ADC0 and suffix x = 1 refers to ADC1.
2) The value of VAREF is permitted to be within the range of VSSA - 0.05 V < VAREF < VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAREF is out of the specified range.
3) The value of VAGND is permitted to be within the range of VSSA - 0.05 V < VAGND < VDDM + 0.05 V. The value
specified for the total unadjusted error (TUE) is not guaranteed while the VAGND is out of the specified range.
4) Definitions for CPS, STC, tBC and tDIV see Figure 23.
5) TUE is tested at VAREF = 5 V, VAGND = 0 V and VDDM = 4.9 V.
6) Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the
specified operating range (i.e. VAOV > VDDM + 0.5 V or VAOV < VSSM - 0.5 V) or a short circuit condition occurs
on the respective ADC pin. The absolute sum of input currents on all port pins must not exceed 10 mA at any
time. The supply voltage (VDD, VDDA0, VDDA1 and VSS, VSSA0, VSSA1) must remain within the specified limits.
Under short-circuit conditions the corresponding pin is not ready for use.
7) Applies for one analog input pin.
8) Applies for two numeric adjacent analog input pins.
AD Converter Characteristics (cont’d)
VSS = 0 V; TA= -40 °C to +125 °C;
Parameter Symbol Limit Values Unit Test
Conditions
min. typ. max.
TC1765
Data Sheet 67 V1.2, 2002-12
Preliminary
Figure 22 Equivalent Circuitry of Analog Input
Note: This equivalent circuitry for an analog input is also valid for the reference inputs
VAREF and VAGND.
9) The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to
the resulting leakage current (Ileak) into an adjacent pin: |Ileak| = kA × |IOV|.
Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent
analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN × |Ileak|.
See also section 7.1.6 “Error Through Overload Conditions” in the TC1765 Peripheral Units User’s Manual for
further explanations.
10) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this smaller capacitances are successively switched to the reference voltage. Alternatively,
the redistributed charge could be specified.
11) The switched capacitance at the analog voltage input must be charged within the sampling time. Alternatively,
the redistributed charge could be specified.
MCS04879
R
AIN, Source
=
V
AIN
C
AIN, Block
R
AIN, On
C
AINTOT
-
C
AINSW
C
AINSW
A/D Converter
TC1765
Data Sheet 68 V1.2, 2002-12
Preliminary
Figure 23 ADC Clock Circuit
Note: The frequency of fADC is the system clock frequency (fSYS) divided by the value of
bit field ADCx_CLC.RMC.
Oscillator Pins (Class C Pins)
TA = -40 °C to +125 °C; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
Parameter Symbol Limit values Unit Test Conditions
min. max.
Input low voltage at
XTAL1
VILX SR -0.5 0.3 ×
VDDOSC
V–
Input high voltage at
XTAL1
VIHX RR 0.7 ×
VDDOSC
VDDOSC
+0.5
V–
Input current at XTAL1 IIX1 CC – ±20 µA0 V < VIN < VDDOSC
Input leakage current
XTAL11)
1) Only applicable in deep sleep mode.
IOZ CC – ±200 nA 0 V < VIN < VDDOSC
MCA04657
Programmable
Clock Divider
(1:1) to (1:128)
4:1
3:1
f
BC
f
DIV
Peripheral
Clock Divider
(1:1) to (1:8)
f
ADC
f
ANA
Programmable
Counter
Sample
Time
t
S
CON.PCD CON.CTC CON.CPS CHCONn.STC
f
TIMER
Control/Status Logic
Interrupt Logic
External Trigger Logic
External Multiplexer Logic
Request Generation Logic
A/D Converter Module
Arbiter
(1:20) Control Unit
(Timer)
TC1765
Data Sheet 69 V1.2, 2002-12
Preliminary
Power Supply Current
TA = -40 °C to +125 °C;
Parameter Symbol Limit Values Unit Test Conditions
min. typ.1)
1) Parameters in this column are tested at 25 °C, 40 MHz system clock (if applicable) and nominal VDD voltages.
max.
Active mode supply current IDD CC – – 200 mA PORST = VIL2)3)
2) These parameters are tested at VDDmax and 40 MHz system clock (bypass mode) with all outputs
disconnected and all inputs at VIL or VIH.
3) These power supply currents are defined as the sum of all currents at the VDD power supply lines:
VDD + VDDP + VDDRAM + VDDSBRAM + VDDOSC + VDDM + VDDA0 + VDDA1
– 260 290 mA Sum of IDDS4)3)
4) These power consumption characteristics are measured while running a typical application pattern. The power
consumption of modules can increase or decrease using other application programs. The PLL is inactive
during this measurement.
–7 10mAIDD at VDDP4)
–201– mAIDD at VDD
(Core and EBU)4)
–31– mAIDD at VDDRAM4)
–21
4) 1205)
5) This parameter has been evaluated at design characterization using an atypical test pattern that makes
extensive usage of the DMU memory.
mA IDD at VDDSBRAM
–0.1– mAIDD at VDDAx4)
Idle mode supply current IID CC – 123 – mA PORST = VIH2)6)7)
6) All peripherals are enabled and in idle state.
7) Guaranteed by design characterization.
Sleep mode supply current ISL CC – 50 – mA PORST = VIH2)7)
Deep sleep mode supply
current
IDS CC – 5 900 µAPORST = VIH8)
8) This is the sum of all 2.5 V power supply currents.
–1 4.4mAPORST = VIH9)
9) This is the sum of all 5 V power supply currents.
Stand-by pin power supply
current
ISB CC – 1 250 µAIDD at VDDSBRAM10)
10) TC1765 in deep sleep mode.
– 1 200 µA11)
11) All other VDD pins are at 0 V; TJ = 150 °C; VDDSBRAM = 2.0 V.
TC1765
Data Sheet 70 V1.2, 2002-12
Preliminary
AC Characteristics
Output Rise/Fall Times
Class A drivers (GPIO Ports 0 to 5): VDDP = 3.0 to 5.25 V; VSS = 0 V
Class B drivers (Bus interface): VDD = 2.30 to 2.75 V; VSS = 0 V
TA = -40 °C to +125 °C, unless otherwise noted; fSYS = 40 MHz
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Class A Pins
Nominal output rise/
fall time1)
1) Measured from 10% output level to 90% output level and vice versa.
tRFAnom
CC
–5–ns
TA = 25 °C, CL = 50 pF,
VDDP = 5.0 V
Px_POCON.PDCy = 0
Px_POCON.PECy = 0
Maximal output rise/
fall time1) tRFAmax
CC
––12ns
CL = 50 pF
Px_POCON.PDCy = 0
Px_POCON.PECy = 0
Slow output rise/fall
time1) tRFAslow
CC
––55ns
CL = 100 pF
Px_POCON.PDCy = 0
Px_POCON.PECy = 1
Class B Pins
Output rise/fall time1) tRFBmax
CC
––4nsfor ECOUT
CL = 50 pF
– – 7 ns for all Class B pins
except ECOUT
CL = 50 pF
TC1765
Data Sheet 71 V1.2, 2002-12
Preliminary
Testing Waveforms
TA = -40 °C to +125 °C; Frequency: max. 40 MHz;
Class A Pins: VDDP813 = 3.0 to 5.25 V; VSS = 0 V;
Figure 24 Testing Waveforms for Class A Pins
Class B and Class C Pins: VDD = 2.30 to 2.75 V; VSS = 0 V;
VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V;
Figure 25 Testing Waveforms for Class B and Class C Pins
Figure 26 Tri-State Testing Waveforms for Class B Pins
MCT04880
VIHmin
VILmax
VOHmin
VOLmax
VOHmin
VOLmax
Test Points
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0.
Timing measurements are made at VOHmin for a logic 1 and VOLmax for a logic 0.
Input and Output Low/High max./min. voltages are defined at Page 60.
MCT04881
V
IHmin
V
ILmax
V
DD
/ 2 Test Points V
DD
/ 2
AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0.
Timing measurements are made at VDD/2 for a logic 1 and for a logic 0.
Input Low/High max./min. voltages are defined at Page 61 and Page 68.
MCT05074
VLoad + 0.1 V VOH - 0.1 V
Timing
Reference
Points
VLoad - 0.1 V VOL - 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL
level occurs (IOH/IOL = 15 mA).
TC1765
Data Sheet 72 V1.2, 2002-12
Preliminary
Input Clock Timing
VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; TA = -40 °C to +125 °C;
Figure 27 Input Clock Timing
Parameter Symbol Limit Values Unit
min. max.
Oscillator clock frequency direct drive fOSC SR
(= 1/tOSC)
416MHz
with PLL 10 16 MHz
Input clock frequency driving
at XTAL1
direct drive 1/tOSCDD
SR
–40 MHz
with PLL 10 30 MHz
Input clock high time t1SR 7 –ns
Input clock low time t2SR 7 –ns
Input clock rise time t3SR –4ns
Input clock fall time t4SR –4ns
MCT04882
0.5
V
DDOSC
Input Clock
at XTAL1
t
OSC
t
1
t
2
V
IHX
V
ILX
t
4
t
3
TC1765
Data Sheet 73 V1.2, 2002-12
Preliminary
ECOUT and CPUCLK Timing
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF;
Figure 28 ECOUT/CPUCLK Output Clock Timing
Parameter Symbol Limit Values Unit
min. typ. max.
Clock period tCPUCLK
tECOUT
CC
25 ––ns
Clock high time t5CC 7.5 ––ns
Clock low time t6CC 7.5 ––ns
Clock rise time t7CC ––4ns
Clock fall time t8CC ––4ns
Clock duty cycle t5/(t5 + t6)DC CC 45 50 55 %
0.9
V
DD
MCT05228
0.5
V
DDP05
ECOUT
CPUCLK
t
CLKOUT
t
5
t
6
0.1
V
DD
t
8
t
7
TC1765
Data Sheet 74 V1.2, 2002-12
Preliminary
PLL Parameters
Note: All PLL characteristics defined on this and the next page are guaranteed by design
characterization.
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C;
Phase Locked Loop Operation
When PLL operation is enabled and configured (see Figure 16 and Page 51), the PLL
clock fVCO (and with it the system clock fSYS) is constantly adjusted to the selected
frequency. The relation between fVCO and fSYS is defined by: fVCO =K×fSYS. The PLL
causes a jitter of fSYS and CPUCLK/ECOUT, which is directly derived from fSYS and
which has its frequency.
The following two formulas define the (absolute) approximate maximum value of jitter DN
in ns dependent on the K-factor, the system clock frequency fSYS in MHz, and the
number P of consecutive fSYS periods.
[1]
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a value
of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum
accumulated jitter remains at a constant value. Further, a lower system clock frequency
fSYS results in a higher maximum jitter.
Figure 29 gives an example for typical jitter curves with K=4@40MHz,
K= 6 @33 MHz, and K = 8@20/25 MHz.
Parameter Symbol Limit Values Unit
min. max.
Accumulated jitter DNsee Figure 29 –
VCO frequency range fVCO 150 200 MHz
PLL base frequency fPLLBASE 40 130 MHz
PLL lock-in time tL–200 µs
for P < 23.5
K DN [ns] = ±3.9
fSYS [MHz] ×P+ 1.2
for P > 23.5
K DN [ns] = ±91.7
fSYS [MHz] × K+ 1.2
TC1765
Data Sheet 75 V1.2, 2002-12
Preliminary
Figure 29 Approximated Maximum Accumulated PLL Jitter for Typical System
Clock Frequencies fSYS
Note: For safe clock generation and PLL operation the definitions and restrictions as
defined at pages 50, 51, and 72 must be regarded.
MCD05141_mod
0
±1.0
P
ns
D
N
±1.2
±1.4
±1.6
±2.0
123456
±1.8
7
D
N
P
K
= Max. jitter
= Number of consecutive
f
SYS
periods
= K-divider of PLL
f
SYS
= 20 MHz (
K
= 8)
f
SYS
= 25 MHz (
K
= 8)
f
SYS
= 33 MHz (
K
= 6)
f
SYS
= 40 MHz (
K
= 4)
TC1765
Data Sheet 76 V1.2, 2002-12
Preliminary
EBU Demultiplexed Timing
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF;
Parameter Symbol Limit Values Unit
min. max.
Output delay from ECOUT t10 CC 0 9 ns
Output delay from ECOUT t11 CC -2 4 ns
Data setup to ECOUT t12 SR 9 –ns
Data hold from ECOUT 1)
1) Valid for EBU_BUSCONx.26 = 0.
t13 SR 1 –ns
Data valid after ECOUT 1) t15 CC 2 –ns
Data setup to ECIN 2)
2) Valid for EBU_BUSCONx.26 = 1 (early sample feature).
t31 SR see Page 80 –ns
Data hold from ECIN 2) t32 SR see Page 80 –ns
TC1765
Data Sheet 78 V1.2, 2002-12
Preliminary
Figure 31 EBU Demultiplexed Write Timing
Data Valid
MCT05230
ECOUT
ADV
CSx
RD
RD/WR
D[31:0]
BC[3:0]
t
10
t
11
t
11
t
10
t
11
t
10
t
11
t
10
t
11
t
11
t
10
t
15
t
10
Address Valid
1)
CODE remains at high level during a demultiplexed write cycle
A[23:0]
CODE
1)
SVM
TC1765
Data Sheet 79 V1.2, 2002-12
Preliminary
WAIT Timing (FPI Bus to External Memory)
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF;
Figure 32 WAIT Timing (from FPI Bus to external Memory)
Parameter Symbol Limit Values Unit
min. max.
WAIT setup to ECOUT t50 SR 141)
1) Guaranteed by design characterization.
–ns
WAIT hold from ECOUT t51 SR 141) –ns
WAIT setup to ECOUT t52 SR 11 –ns
WAIT hold from ECOUT t53 SR 2 –ns
MCT05231
ECOUT
t
50
t
51
t
50
t
51
WAIT
Synchronous Mode
ECOUT
t
52
t
53
t
52
t
53
WAIT
Asynchronous Mode
TC1765
Data Sheet 80 V1.2, 2002-12
Preliminary
EBU Burst Mode Timing
VSS = 0 V, VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF;
Figure 33 Burst Mode Timing (Instruction Read)
Parameter Symbol Limit Values Unit
min. max.
Output delay from ECIN t30 CC 2 14 ns
Data setup to ECIN t31 SR 41)
1) Guaranteed by design characterization.
–ns
Data hold from ECIN t32 SR 11) –ns
Address Valid
ValidValid
MCT05232
ECIN
t
30
t
30
t
30
t
30
t
30
t
30
t
30
t
32
t
31
t
32
t
31
A[23:2]
CS0
CODE
RD
BAA
ADV
D[31:0]
Note: WAIT must be 1 during a Burst Mode Read Cycle.
t
30
t
30
TC1765
Data Sheet 81 V1.2, 2002-12
Preliminary
Trace Port Timing (TC1765T only)
This timing is applicable for TP[15:0] when CPU or DMA trace mode is enabled
(SCU_CON.ETEN = 1).
VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF;
Figure 34 Trace Port Timing
Parameter Symbol Limit Values Unit
min. max.
TP[15:0] and BRKOUT high/low from
CPUCLK
t55 CC 0 8 ns
MCT05233
CPUCLK
t
55
TP[15:0]
BRKOUT Old State New State
TC1765
Data Sheet 82 V1.2, 2002-12
Preliminary
SSC Master Mode Timing
VSS = 0 V; VDDP = 4.5 to 5.25 V; TA = -40 °C to +125 °C; CL = 50 pF;
Figure 35 SSC Master Mode Timing
Parameter Symbol Limit Values Unit
min. max.
SCLK / MTSR low/high from ECOUT 1)
1) This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic
(POCON.PECx = 0 and POCON.PDCx = 0) of the corresponding SSC output lines.
t60 CC –7ns
MRST setup to SLCK rising/falling edge t61 SR 182)
2) Guaranteed by design characterization.
–ns
MRST hold from SLCK rising/falling edge t62 SR 102) –ns
State n
MCT05234
ECOUT
SCLK
t
60
MTSR
t
60
t
61
t
62
Data Valid
State n-1 State n+1
t
ECOUT
t
60
MRST
Note: The timing diagram assumes the highest possible baudrate operation.
(
f
SSC
=
f
ECOUT
, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000
H
)
TC1765
Data Sheet 83 V1.2, 2002-12
Preliminary
Package Outlines
P-LBGA-260-2
Plastic Low Profile Pitch Ball Grid Array
GPA09421
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
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