LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 LMV851/LMV852/LMV854 8 MHz Low Power CMOS, EMI Hardened Operational Amplifiers Check for Samples: LMV851, LMV852, LMV854 FEATURES DESCRIPTION * Texas Instrument's LMV851/LMV852/LMV854 are CMOS input, low power op amp ICs, providing a low input bias current, a wide temperature range of -40C to +125C and exceptional performance, making them robust general purpose parts. Additionally, the LMV851/LMV852/LMV854 are EMI hardened to minimize any interference so they are ideal for EMI sensitive applications. The unity gain stable LMV851/LMV852/LMV854 feature 8 MHz of bandwidth while consuming only 0.4 mA of current per channel. These parts also maintain stability for capacitive loads as large as 200 pF. The LMV851/LMV852/LMV854 provide superior performance and economy in terms of power and space usage. This family of parts has a maximum input offset voltage of 1 mV, a rail-to-rail output stage and an input common-mode voltage range that includes ground. Over an operating supply range from 2.7V to 5.5V the LMV851/LMV852/LMV854 provide a CMRR of 92 dB, and a PSRR of 93 dB. The LMV851/LMV852/LMV854 are offered in the space saving 5-Pin SC70 package, the 8-Pin VSSOP and the 14-Pin TSSOP package. 1 2 * * * * * * * * * * * Unless Otherwise Noted, Typical Values at TA = 25C, VSUPPLY = 3.3V Supply Voltage 2.7V to 5.5V Supply Current (Per Channel) 0.4 mA Input Offset Voltage 1 mV max Input Bias Current 0.1 pA GBW 8 MHz EMIRR at 1.8 GHz 87 dB Input Noise Voltage at 1 kHz 11 nV/Hz Slew Rate 4.5 V/s Output Voltage Swing Rail-to-Rail Output Current Drive 30 mA Operating Ambient Temperature Range -40C to 125C APPLICATIONS * * * * * * Photodiode Preamp Piezoelectric Sensors Portable/Battery-Powered Electronic Equipment Filters/Buffers PDAs/Phone Accessories Medical Diagnosis Equipment Typical Application V R1 + NO RF RELATED DISTURBANCES PRESSURE SENSOR + - + R2 ADC + EMI HARDENED EMI HARDENED INTERFERING RF SOURCES Figure 1. Sensor Amplifiers Close to RF Sources 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2013, Texas Instruments Incorporated LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) Human Body Model 2 kV Charge-Device Model 1 kV Machine Model 200V VINDifferential Supply Voltage Supply Voltage (V+ - V-) 6V V+ - Voltage at Input/Output Pins +0.4V V -0.4V -65C to +150C Storage Temperature Range Junction Temperature (3) +150C Soldering Information Infrared or Convection (20 sec) (1) +260C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC board. (2) (3) Operating Ratings Temperature Range (1) (2) -40C to +125C Supply Voltage (V - V-) + 2.7V to 5.5V Package Thermal Resistance (JA (2)) 5-Pin SC70 313 C/W 8-Pin VSSOP 217 C/W 14-Pin TSSOP 135 C/W (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables. The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC board. 3.3V Electrical Characteristics (1) Unless otherwise specified, all limits are specified for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, and RL = 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Test Conditions VOS Input Offset Voltage TCVOS Input Offset Voltage Drift IB (1) (2) (3) (4) (5) 2 Input Bias Current Min (5) (5) (2) Typ (3) Max (2) 0.26 See (4) 1 1.2 0.4 See (4) 2 0.1 10 500 Units mV V/C pA Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting distribution This parameter is specified by design and/or characterization and is not tested in production. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 3.3V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are specified for TA = 25C, V+ = 3.3V, V- = 0V, VCM = V+/2, and RL = 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter IOS Test Conditions Min (2) Input Offset Current CMRR + -0.2V < VCM < V - 1.2V Common Mode Rejection Ratio + 2.7V V 5.5V, VOUT = 1V PSRR Power Supply Rejection Ratio EMIRR EMI Rejection Ratio, IN+ and IN- (6) CMVR Input Common-Mode Voltage Range AVOL Large Signal Voltage Gain VO (7) Output Swing High, (measured from V+) Output Swing Low, (measured from V-) IO Output Short Circuit Current IS Supply Current (8) Typ (3) Max (2) Units 1 pA 76 75 92 See (4) dB 75 74 93 dB (4) VRFpeak = 100 mVP (-20 dBVP), f = 400 MHz 64 VRFpeak = 100 mVP (-20 dBVP), f = 900 MHz 78 VRFpeak = 100 mVP (-20 dBVP), f = 1800 MHz 87 VRFpeak = 100 mVP (-20 dBVP), f = 2400 MHz 90 CMRR 76 dB -0.2 RL = 2 k, VOUT = 0.15V to 1.65V, VOUT = 3.15V to 1.65V 100 97 114 RL = 10 k, VOUT = 0.1V to 1.65V, VOUT = 3.2V to 1.65V 100 97 115 dB 2.1 dB RL = 2 k to V+/2 31 35 43 RL = 10 k to V+/2 7 10 12 RL = 2 k to V+/2 26 32 43 RL = 10 k to V+/2 6 11 14 Sourcing, VOUT = VCM, VIN = 100 mV 25 20 28 Sinking, VOUT = VCM, VIN = -100 mV 28 20 31 V mV mV mA LMV851 0.42 0.50 0.58 LMV852 0.79 0.90 1.06 LMV854 1.54 1.67 1.99 AV = +1, VOUT = 1 VPP, 10% to 90% mA SR Slew Rate 4.5 V/s GBW Gain Bandwidth Product 8 MHz m Phase Margin 62 deg en Input-Referred Voltage Noise f = 1 kHz 11 f = 10 kHz 10 nV/Hz in Input-Referred Current Noise f = 1 kHz 0.005 pA/Hz ROUT Closed Loop Output Impedance f = 6 MHz 400 CIN Common-Mode Input Capacitance 11 Differential-Mode Input Capacitance 6 THD+N (6) (7) (8) Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, BW = >500 kHz 0.006 pF % The EMI Rejection Ratio is defined as EMIRR = 20log ( VRFpeak/VOS). The specified limits represent the lower of the measured values for each output range condition. Number specified is the slower of positive and negative slew rates. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 3 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 5V Electrical Characteristics www.ti.com (1) Unless otherwise specified, all limits are specified for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, and RL = 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Test Conditions Min (2) Typ (3) Max (2) Input Offset Voltage TCVOS Input Offset Voltage Drift IB Input Bias Current IOS Input Offset Current 1 pA CMRR Common Mode Rejection Ratio -0.2V VCM V+ -1.2V 77 76 94 See (4) dB PSRR Power Supply Rejection Ratio 2.7V V+ 5.5V, VOUT = 1V 75 74 93 See (4) dB EMIRR EMI Rejection Ratio, IN+ and IN- (5) (5) (6) CMVR Input Common-Mode Voltage Range AVOL Large Signal Voltage Gain VO (7) Output Swing High, (measured from V+) Output Swing Low, (measured from V-) IO IS (1) (2) (3) (4) (5) (6) (7) 4 Output Short Circuit Current Supply Current 0.26 See (4) 1 1.2 0.4 See (4) 2 0.1 10 500 Units VOS VRFpeak = 100 mVP (-20 dBVP), f = 400 MHz 64 VRFpeak = 100 mVP (-20 dBVP), f = 900 MHz 76 VRFpeak = 100 mVP (-20 dBVP), f = 1800 MHz 84 VRFpeak = 100 mVP (-20 dBVP), f = 2400 MHz 89 CMRR 77 dB -0.2 RL = 2 k, VOUT = 0.15V to 2.5V, VOUT = 4.85V to 2.5V 105 102 118 RL = 10 k, VOUT = 0.1V to 2.5V, VOUT = 4.9V to 2.5V 105 102 120 34 39 47 RL = 10 k to V+/2 7 11 13 RL = 2 k to V+/2 31 38 50 RL = 10 k to V+/2 7 12 15 65 Sinking, VOUT = VCM, VIN = -100 mV 58 44 62 pA V dB RL = 2 k to V+/2 60 48 V/C dB 3.8 Sourcing, VOUT = VCM, VIN = 100 mV mV mV mV mA LMV851 0.43 0.52 0.60 LMV852 0.82 0.93 1.09 LMV854 1.59 1.73 2.05 mA Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device. Limits are 100% production tested at 25C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting distribution This parameter is specified by design and/or characterization and is not tested in production. The EMI Rejection Ratio is defined as EMIRR = 20log ( VRFpeak/VOS). The specified limits represent the lower of the measured values for each output range condition. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are specified for TA = 25C, V+ = 5V, V- = 0V, VCM = V+/2, and RL = 10 k to V+/2. Boldface limits apply at the temperature extremes. Parameter Test Conditions (8) SR Slew Rate GBW m en Input-Referred Voltage Noise Min AV = +1, VOUT = 2 VPP, 10% to 90% (2) Typ (3) Max (2) Units 4.5 V/s Gain Bandwidth Product 8 MHz Phase Margin 64 deg f = 1 kHz 11 f = 10 kHz 10 nV/Hz in Input-Referred Current Noise f = 1 kHz 0.005 pA/Hz ROUT Closed Loop Output Impedance f = 6 MHz 400 CIN Common-Mode Input Capacitance 11 Differential-Mode Input Capacitance 6 THD+N (8) Total Harmonic Distortion + Noise f = 1 kHz, AV = 1, BW = >500 kHz 0.003 pF % Number specified is the slower of positive and negative slew rates. Connection Diagrams Top View Top View Figure 2. 5-Pin SC70 Package See Package Number DCK0005A Figure 3. 8-Pin VSSOP Package See Package Number DGK0008A Top View Figure 4. 14-Pin TSSOP Package See Package Number PW0014A Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 5 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. VOS vs. VCM at 3.3V 0.3 0.3 0.2 0.3 0.2 125C 85C 0.2 0.1 0.1 0.1 0.1 VOS mV) VOS (mV) 0.3 125C 85C 0.2 VOS vs. VCM at 5.0V 0 0 25C -40C -0.1 -0.1 -0.2 0 0 25C -0.1 -40C -0.1 -0.2 -0.3 -0.2 -0.2 -0.3 VS = 5.0V VS = 3.3V -0.3 -0.3 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -0.5 0.5 1.5 Figure 6. VOS vs. Supply Voltage VOS vs. Temperature 200 0.3 0.2 150 200 100 150 100 50 50 00 -50 -50 -100 85C 125C VOS (V) VOS (mV) 0.2 0.1 0.1 00 -40C 25C 100 125 3.3V 5.0V -200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 VSUPPLY (V) 12 0 25 50 75 TEMPERATURE (C) Figure 7. Figure 8. VOS vs. VOUT Input Bias Current vs. VCM at 25C 5 VS = 5.0V, RL = 2k TA = 25C 4 9 6 3 IBIAS (pA) VOS (V) 5.5 -150 -0.3 0 -3 -6 35 24 3 2 11 0 0-1 -2 -1 -3 -4 -2-5 5V 3.3V -3 -9 -4 -5 1 2 3 4 5 -1 VOUT (V) Submit Documentation Feedback 0 1 2 3 4 5 6 VCM (V) Figure 9. 6 4.5 -150 -100 -200 -0.2 -0.3 -12 0 3.5 Figure 5. 0.3 -0.1 -0.1 -0.2 2.5 VCM (V) VCM (V) Figure 10. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. Input Bias Current vs. VCM at 85C 500 50 TA = 85C 30 50 40 20 30 20 10 10 00 -10 -20 -10 -30 -40 -20 -50 -30 5.0V 3.3V 300 500 400 200 300 200 100 100 00 -100 -200 -100 -300 -400 -200 -500 -300 5.0V 3.3V -400 -40 -500 -50 -1 0 1 2 3 4 5 -1 6 0 2 3 4 5 VCM (V) Figure 11. Figure 12. Supply Current vs. Supply Voltage Single LMV851 Supply Current vs. Supply Voltage Dual LMV852 1.2 0.6 0.6 SUPPLY CURRENT (mA) 0.7 85C 125C 0.5 0.5 0.4 0.4 25C 0.3 0.3 0.2 -40C 1.1 1.2 1.0 1.1 1.0 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.5 0.6 0.4 125C 6 85C 25C -40C 0.5 0.2 0.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 6.0 3.0 2.2 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 13. Figure 14. Supply Current vs. Supply Voltage Quad LMV854 Supply Current vs. Temperature Single LMV851 0.7 0.7 85C SUPPLY CURRENT (mA) 125C 2.0 2.2 SUPPLY CURRENT (mA) 1 VCM (V) 0.7 SUPPLY CURRENT (mA) TA = 125C 400 IBIAS (pA) IBIAS (pA) 40 Input Bias Current vs. VCM at 125C 2.0 1.8 1.8 1.6 1.6 1.4 1.4 1.2 25C 1.0 1.2 -40C 0.8 1.0 0.8 0.6 0.6 5.0V 0.5 0.5 0.4 0.4 3.3V 0.3 0.3 0.2 0.2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 SUPPLY VOLTAGE (V) Figure 15. 0 25 50 75 100 125 TEMPERATURE (C) Figure 16. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 7 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. Supply Current vs. Temperature Dual LMV852 Supply Current vs. Temperature Quad LMV854 1.2 2.2 1.2 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 2.2 2.0 1.0 1.0 5.0V 0.8 0.8 3.3V 0.6 0.6 0.4 5.0V 1.6 1.6 1.4 1.4 1.2 3.3V 1.0 1.2 0.8 1.0 0.8 0.4 -50 -25 0 25 50 75 TEMPERATURE (C) 100 -50 125 0 75 Sinking Current vs. Supply Voltage Sourcing Current vs. Supply Voltage 100 90 90 100 80 90 80 70 70 60 60 50 50 40 30 40 20 10 30 100 80 90 80 70 70 60 60 50 50 40 30 40 20 10 30 -40C 25C 85C 100 125 125C 25C -40C 125C 85C 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 10 6.0 2.5 3.0 4.0 4.5 5.0 5.5 Figure 19. Figure 20. Output Swing High vs. Supply Voltage RL = 2 k Output Swing High vs. Supply Voltage RL = 10 k 50 45 RL = 10 k: VOUT FROM RAIL HIGH (mV) 85C 40 35 30 25C 25 -40C 3.0 3.5 4.0 4.5 5.0 5.5 6.0 12 125C 85C 10 8 6 25C -40C 4 2 2.5 3.0 SUPPLY VOLTAGE (V) 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Figure 21. Submit Documentation Feedback 6.0 14 125C RL = 2 k: 20 2.5 3.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) VOUT FROM RAIL HIGH (mV) 50 Figure 18. 20 8 25 Figure 17. 100 10 -25 TEMPERATURE (C) ISOURCE (mA) ISINK (mA) 2.0 1.8 1.8 Figure 22. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. Output Swing Low vs. Supply Voltage RL = 2 k Output Swing Low vs. Supply Voltage RL = 10 k 12 45 RL = 2 k: RL = 10 k: 125C VOUT FROM RAIL LOW (mV) 85C 35 30 25 25C 20 -40C 15 10 2.5 3.0 3.5 4.0 5.0 4.5 5.5 125C 10 85C 8 6 4 25C -40C 2 0 2.5 6.0 3.0 3.5 Output Voltage Swing vs. Load Current at 5.0V 2.0 SINK 1.6 -1.2 VS = 3.3V 125C -1.6 SOURCE 5 10 20 25 30 35 125C 40 SOURCE 0 10 20 30 40 50 60 70 ILOAD (mA) Figure 25. Figure 26. Open Loop Frequency Response vs. Temperature Open Loop Frequency Response vs. Load Conditions 25C, 85C, 125C 100 60 100 80 GAIN 80 60 60 -40C 40 40 30 30 40 40 20 20 20 0 25C 85C 125C 20 10 100 CL = 5 pF -40C 100k 1M -20 0 -20 10M 100 PHASE 20 pF 5 pF 50 80 GAIN 100 pF 40 GAIN (dB) GAIN (dB) -1.2 VS = 5.0V -40C ILOAD (mA) PHASE 10k 125C -2.0 15 60 50 0 1.2 2.0 1.6 0.8 1.2 0.8 0.4 0.4 00 -0.4 -0.8 -0.4 -1.2 -1.6 -0.8 -2.0 -1.6 PHASE () VOUT FROM RAIL (V) -40C VOUT FROM RAIL (V) 125C 1.2 2.0 1.6 0.8 1.2 0.8 0.4 0.4 00 -0.4 -0.8 -0.4 -1.2 -1.6 -0.8 -2.0 50 6.0 5.5 Output Voltage Swing vs. Load Current at 3.3V SINK 60 5.0 Figure 24. 1.6 0 4.5 Figure 23. 2.0 -2.0 4.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 60 50 pF 30 40 20 20 CL = 5 pF = 20 pF 10 = 50 pF = 100 pF 0 10k 100k FREQUENCY (Hz) 5 pF PHASE () VOUT FROM RAIL LOW (mV) 40 0 100 pF 1M -20 10M FREQUENCY (Hz) Figure 27. Figure 28. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 9 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. Phase Margin vs. Capacitive Load PSRR vs. Frequency 70 120 60 100 3.3V 50 5.0V PSRR (dB) PHASE() 80 40 30 5.0V -PSRR 60 3.3V 5.0V 40 20 +PSRR 20 10 3.3V 0 1 10 100 0 100 1000 1k CLOAD (pF) CMRR vs. Frequency Channel Separation vs. Frequency 140 140 CHANNEL SEPARATION (dB) CMRR (dB) 80 80 DC CMRR 60 60 40 40 120 120 100 100 80 80 60 VS = 3.3V, 5.0V VS = 3.3V, 5.0V 60 20 10k 100k FREQUENCY (Hz) 1M 1k 10M 10k 100k 1M 10M FREQUENCY (Hz) Figure 32. Large Signal Step Response with Gain = 1 Large Signal Step Response with Gain = 10 200 mV/DIV Figure 31. 200 mV/DIV 10 10M FREQUENCY (Hz) AC CMRR 1k 1M Figure 30. 100 100 100k Figure 29. 100 20 10k f = 250 kHz AV = +1 f = 250 kHz VIN = 1 VPP VIN = 100 mVPP AV = +10 400 ns/DIV 400 ns/DIV Figure 33. Figure 34. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. Small Signal Step Response with Gain = 10 20 mV/DIV 20 mV/DIV Small Signal Step Response with Gain = 1 f = 250 kHz f = 250 kHz AV = +1 AV = +10 VIN = 100 mVPP VIN = 10 mVPP 400 ns/DIV 400 ns/DIV Figure 35. Figure 36. Slew Rate vs. Supply Voltage Overshoot vs. Capacitive Load 5.0 40 4.8 4.8 4.6 4.6 4.4 4.4 RISING EDGE 4.2 4.2 4.0 AV = +1 CL = 5 pF 4.0 2.5 3.0 3.5 f = 250 kHz 35 AV = +1 VIN =200 mVPP 30 FALLING EDGE OVERSHOOT (%) SLEWRATE (V/s) 5.0 25 20 5.0V 15 10 5 4.0 4.5 5.0 5.5 3.3V 0 10 6.0 100 SUPPLY VOLTAGE (Hz) 1000 CLOAD (pF) Figure 37. Figure 38. Input Voltage Noise vs. Frequency THD+N vs. Frequency 1 100 BW = >500 kHz THD + N (%) NOISE (nV/vHz) AV = 10x 10 0.1 VS = 3.3V, VIN = 220 mVPP VS = 5.0V, VIN = 400 mVPP AV = 1x 0.01 VS = 3.3V, VIN = 2.2VPP VS = 5.0V, VIN = 4.0VPP 1 VS = 3.3V, 5.0V 10 100 1k 10k 100k FREQUENCY (Hz) 1M 0.001 10 Figure 39. 100 1k 10k 100k FREQUENCY (Hz) Figure 40. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 11 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. THD+N vs. Amplitude ROUT vs. Frequency 1k 10 AV = 10x AV = 100x ROUT (:) THD + N (%) 100 VS = 3.3V 1 AV = 1x 0.1 10 1 AV = 10x 0.01 0.1 f = 1 kHz BW = >500 kHz 0.001 1m 10m 100m AV = 1x VS = 5.0V 1 0.01 100 10 1k 10k 100k 1M 10M FREQUENCY (Hz) VOUT (VPP) Figure 41. Figure 42. EMIRR IN+ vs. Power at 400 MHz EMIRR IN+ vs. Power at 900 MHz 100 100 90 90 125C EMIRR V_PEAK (dB) EMIRR V_PEAK (dB) 85C 125C 85C 80 70 60 25C 50 -40C 40 80 70 60 -40C 50 40 30 30 fRF = 400 MHz 20 -40 -30 -20 -10 0 fRF = 900 MHz 20 -40 -30 -20 10 RF INPUT PEAK VOLTAGE (dBVp) 0 EMIRR IN+ vs. Power at 1800 MHz EMIRR IN+ vs. Power at 2400 MHz 100 125C 85C 125C 85C 90 EMIRR V_PEAK (dB) 80 70 25C -40C 60 10 RF INPUT PEAK VOLTAGE (dBVp) Figure 44. 90 50 40 80 70 25C -40C 60 50 40 30 30 fRF = 1800 MHz 20 -40 -30 -20 -10 0 RF INPUT PEAK VOLTAGE (dBVp) 10 fRF = 2400 MHz 20 -40 -30 -20 Submit Documentation Feedback -10 0 10 RF INPUT PEAK VOLTAGE (dBVp) Figure 45. 12 -10 Figure 43. 100 EMIRR V_PEAK (dB) 25C Figure 46. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 Typical Performance Characteristics (continued) At TA = 25C, RL = 10 k, VS = 3.3V, unless otherwise specified. EMIRR IN+ vs. Frequency at 3.3V EMIRR IN+ vs. Frequency at 5.0V 100 100 90 125C 80 70 EMIRR V_PEAK (dB) EMIRR V_PEAK (dB) 90 85C 60 50 25C 40 20 10 VS = 3.3V VPEAK = -20 dBVp 100 85C 70 60 50 25C 40 -40C 30 125C 80 1000 10000 -40C 30 20 10 FREQUENCY (MHz) Figure 47. VS = 5.0V VPEAK = -20 dBVp 100 1000 10000 FREQUENCY (MHz) Figure 48. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 13 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION INTRODUCTION The LMV851/LMV852/LMV854 are operational amplifiers with very good specifications, such as low offset, low noise and a rail-to-rail output. These specifications make the LMV851/LMV852/LMV854 great choices to use in areas such as medical and instrumentation. The low supply current is perfect for battery powered equipment. The small packages, SC-70 package for the LMV851, the VSSOP package for the dual LMV852 and the TSSOP package for the quad LMV854, make any of these parts a perfect choice for portable electronics. Additionally, the EMI hardening makes the LMV851/LMV852 or LMV854 a must for almost all op amp applications. Most applications are exposed to Radio Frequency (RF) signals such as the signals transmitted by mobile phones or wireless computer peripherals. The LMV851/LMV852/LMV854 will effectively reduce disturbances caused by RF signals to a level that will be hardly noticeable. This again reduces the need for additional filtering and shielding. Using this EMI resistant series of op amps will thus reduce the number of components and space needed for applications that are affected by EMI, and will help applications, not yet identified as possible EMI sensitive, to be more robust for EMI. INPUT CHARACTERISTICS The input common mode voltage range of the LMV851/LMV852/LMV854 includes ground, and can even sense well below ground. The CMRR level does not degrade for input levels up to 1.2V below the supply voltage. For a supply voltage of 5V, the maximum voltage that should be applied to the input for best CMRR performance is thus 3.8V. When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The output is rail-to-rail and therefore will introduce no limitations to the signal range. The typical offset is only 0.26 mV, and the TCVOS is 0.4 V/C, specifications close to precision op amps. CMRR MEASUREMENT The CMRR measurement results may need some clarification. This is because different setups are used to measure the AC CMRR and the DC CMRR. The DC CMRR is derived from VOS versus VCM. This value is stated in the tables, and is tested during production testing. The AC CMRR is measured with the test circuit shown in Figure 49. R2 1 k: V+ R1 1 k: - - VIN Buffer LMV85x + R11 1 k: V+ BUFFER - R2 V 995: VOUT + V- BUFFER P1 10: Figure 49. AC CMRR Measurement Setup 14 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network. Now the closed-loop output impedance of the buffer is a part of the balance. But as the closed-loop output impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger measured bandwidth of the AC CMRR. One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So, mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends to be higher than the actual DC CMRR based on DC measurements. The CMRR curve in Figure 50 shows a combination of the AC CMRR and the DC CMRR. 100 AC CMRR 100 CMRR (dB) 80 80 DC CMRR 60 60 40 40 20 VS = 3.3V, 5.0V 20 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 50. CMRR Curve OUTPUT CHARACTERISTICS As already mentioned the output is rail to rail. When loading the output with a 10 k resistor the maximum swing of the output is typically 7 mV from the positive and negative rail The LMV851/LMV852/LMV854 can be connected as non-inverting unity gain amplifiers. This configuration is the most sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier along with the amplifier's output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp might start oscillating. The LMV851/LMV852/LMV854 can directly drive capacitive loads up to 200 pF without any stability issues. In order to drive heavier capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 51. By using this isolation resistor, the capacitive load is isolated from the amplifier's output, and hence, the pole caused by CL is no longer in the feedback loop. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. VIN RISO VOUT + CL Figure 51. Isolating Capacitive Load Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 15 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com EMIRR With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those devices and other equipment becomes a bigger challenge. The LMV851/LMV852/LMV854 are EMI hardened op amps which are specifically designed to overcome electromagnetic interference. Along with EMI hardened op amps, the EMIRR parameter is introduced to unambiguously specify the EMI performance of an op amp. This section presents an overview of EMIRR. A detailed description on this specification for EMI hardened op amps can be found in Application Note AN-1698(SNOA497). The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As a result the op amp itself will hardly receive any disturbances. The RF signals interfering with the op amp are dominantly received by the PCB and wiring connected to the op amp. As a result the RF signals on the pins of the op amp can be represented by voltages and currents. This representation significantly simplifies the unambiguous measurement and specification of the EMI performance of an op amp. RF signals interfere with op amps via the non-linearity of the op amp circuitry. This non-linearity results in the detection of the so called out-of-band signals. The obtained effect is that the amplitude modulation of the out-ofband signal is down-converted into the base band. This base band can easily overlap with the band of the op amp circuit. As an example Figure 52 depicts a typical output signal of a unity-gain connected op amp in the presence of an interfering RF signal. Clearly the output voltage varies in the rhythm of the on-off keying of the RF carrier. RF RF SIGNAL VOUT OPAMP (AV = 1) NO RF VOS + VDETECTED VOS Figure 52. Offset Voltage Variation Due to an Interfering RF Signal EMIRR Definition To identify EMI hardened op amps, a parameter is needed that quantitatively describes the EMI performance of op amps. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness. Therefore the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred offset voltage shift of an op amp as a result of an applied RF carrier (interference) with a certain frequency and level. The definition of EMIRR is given by: VRF_PEAK* EMIRRV RF_PEAK = 20 log 'VOS (c) (1) In which VRF_PEAK is the amplitude of the applied un-modulated RF signal (V) and VOS is the resulting inputreferred offset voltage shift (V). The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR is determined should be specified. The standard level for the RF signal is 100 mVP. Application Note AN-1698(SNOA497) addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of the EMIRR parameter is straightforward. When two op amps have an EMIRR which differ by 20 dB, the resulting error signals when used in identical configurations, differs by 20 dB as well. So, the higher the EMIRR, the more robust the op amp. Coupling an RF Signal to the IN+ Pin Each of the op amp pins can be tested separately on EMIRR. In this section the measurements on the IN+ pin (which, based on symmetry considerations, also apply to the IN- pin) are discussed. In Application Note AN1698(SNOA497) the other pins of the op amp are treated as well. For testing the IN+ pin the op amp is connected in the unity gain configuration. Applying the RF signal is straightforward as it can be connected directly to the IN+ pin. As a result the RF signal path has a minimum of components that might affect the RF signal level at the pin. The circuit diagram is shown in Figure 53. The PCB trace from RFIN to the IN+ pin should 16 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 be a 50 stripline in order to match the RF impedance of the cabling and the RF generator. On the PCB a 50 termination is used. This 50 resistor is also used to set the bias level of the IN+ pin to ground level. For determining the EMIRR, two measurements are needed: one is measuring the DC output level when the RF signal is off; and the other is measuring the DC output level when the RF signal is switched on. The difference of the two DC levels is the output voltage shift as a result of the RF signal. As the op amp is in the unity gain configuration, the input referred offset voltage shift corresponds one-to-one to the measured output voltage shift. C2 10 F + VDD C3 100 pF RFin + R1 50: Out C4 100 pF C1 22 pF + VSS C5 10 F Figure 53. Circuit for Coupling the RF Signal to IN+ Cell Phone Call The effect of electromagnetic interference is demonstrated in a setup where a cell phone interferes with a pressure sensor application (Figure 55). This application needs two op amps and therefore a dual op amp is used. The experiment is performed on two different dual op amps: a typical standard op amp and the LMV852, EMI hardened dual op amp. The op amps are placed in a single supply configuration. The cell phone is placed on a fixed position a couple of centimeters from the op amps. VOUT (0.5V/DIV) When the cell phone is called, the PCB and wiring connected to the op amps receive the RF signal. Subsequently, the op amps detect the RF voltages and currents that end up at their pins. The resulting effect on the output of the second op amp is shown in Figure 54. Typical Opamp LMV852 TIME (0.5s/DIV) Figure 54. Comparing EMI Robustness Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 17 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com The difference between the two types of dual op amps is clearly visible. The typical standard dual op amp has an output shift (disturbed signal) larger than 1V as a result of the RF signal transmitted by the cell phone. The LMV852, EMI hardened op amp does not show any significant disturbances. DECOUPLING AND LAYOUT Care must be given when creating a board layout for the op amp. For decoupling the supply lines it is suggested that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between V+ and V-. For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor between ground and V-. Even with the LMV851/LMV852/LMV854 inherent hardening against EMI, it is still recommended to keep the input traces short and as far as possible from RF sources. Then the RF signals entering the chip are as low as possible, and the remaining EMI can be, almost, completely eliminated in the chip by the EMI reducing features of the LMV851/LMV852/LMV854. PRESSURE SENSOR APPLICATION The LMV851/LMV852/LMV854 can be used for pressure sensor applications. Because of their low power the LMV851/LMV852/LMV854 are ideal for portable applications, such as blood pressure measurement devices, or portable barometers. This example describes a universal pressure sensor that can be used as a starting point for different types of sensors and applications. Pressure Sensor Characteristics The pressure sensor used in this example functions as a Wheatstone bridge. The value of the resistors in the bridge change when pressure is applied to the sensor. This change of the resistor values will result in a differential output voltage, depending on the sensitivity of the sensor and the applied pressure. The difference between the output at full scale pressure and the output at zero pressure is defined as the span of the pressure sensor. A typical value for the span is 100 mV. A typical value for the resistors in the bridge is 5 k. Loading of the resistor bridge could result in incorrect output voltages of the sensor. Therefore the selection of the circuit configuration, which connects to the sensor, should take into account a minimum loading of the sensor. Pressure Sensor Example The configuration shown in Figure 55 is simple, and is very useful for the read out of pressure sensors. With two op amps in this application, the dual LMV852 fits very well. The op amp configured as a buffer and connected at the negative output of the pressure sensor prevents the loading of the bridge by resistor R2. The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. Given the differential output voltage VS of the pressure sensor, the output signal of this op amp configuration, VOUT, equals: VOUT = VDD 2 - VS R1 * 1 + 2 x R2 2 (c) (2) To align the pressure range with the full range of an ADC, the power supply voltage and the span of the pressure sensor are needed. For this example a power supply of 5V is used and the span of the sensor is 100 mV. When a 100 resistor is used for R2, and a 2.4 k resistor is used for R1, the maximum voltage at the output is 4.95V and the minimum voltage is 0.05V. This signal is covering almost the full input range of the ADC. Further processing can take place in the microprocessor following the ADC. 18 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 R1 2.4 k: VDD VDD PRESSURE SENSOR + LMV852 - + R2 100: ADC LMV852 + VOUT VS Figure 55. Pressure Sensor Application THERMOCOUPLE AMPLIFIER The following circuit is a typical example for a thermocouple amplifier application using an LMV851/LMV852, or LMV854. A thermocouple converts a temperature into a voltage. This signal is then amplified by the LMV851/LMV852, or LMV854. An ADC can convert the amplified signal to a digital signal. For further processing the digital signal can be processed by a microprocessor and used to display or log the temperature. The temperature data can for instance be used in a fabrication process. Characteristics of a Thermocouple A thermocouple is a junction of two different metals. These metals produce a small voltage that increases with temperature. The thermocouple used in this application is a K-type thermocouple. A K-type thermocouple is a junction between Nickel-Chromium and Nickel-Aluminum. This is one of the most commonly used thermocouples. There are several reasons for using the K-type thermocouple, these include: temperature range, the linearity, the sensitivity, and the cost. A K-type thermocouple has a wide temperature range. The range of this thermocouple is from approximately -200C to approximately 1200C, as can be seen in Figure 56. This covers the generally used temperature ranges. Over the main part of the temperature range the output voltage depends linearly on the temperature. This is important for easily converting the measured signal levels to a temperature reading. The K-type thermocouple has good sensitivity when compared to many other types; the sensitivity is about 41 uV/C. Lower sensitivity requires more gain and makes the application more sensitive to noise. In addition, a K-type thermocouple is not expensive, many other thermocouples consist of more expensive materials or are more difficult to produce. Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 19 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com THERMOCOUPLE VOLTAGE (mV) 50 40 30 20 10 0 -10 -200 0 200 400 600 800 1000 1200 TEMPERATURE (C) Figure 56. K-Type Thermocouple Response Thermocouple Example For this example, suppose the range of interest is 0C to 500C, and the resolution needed is 0.5C. The power supply for both the LMV851/LMV852, or LMV854 and the ADC is 3.3V. The temperature range of 0C to 500C results in a voltage range from 0 mV to 20.6 mV produced by the thermocouple. This is indicated in Figure 56 by the dotted lines. To obtain the highest resolution, the full ADC range of 0 to 3.3V is used. The gain needed for the full range can be calculated as follows: AV = 3.3V / 0.0206V = 160 (3) If RG is 2 k, then the value for RF can be calculated for a gain of 160. Since AV = RF / RG, RF can be calculated as follows: RF = AV x RG = 160 x 2 k = 320 k (4) To get a resolution of 0.5C, the LSB of the ADC should be smaller then 0.5C / 500C = 1/1000. A 10-bit ADC would be sufficient as this gives 1024 steps. A 10-bit ADC such as the two channel 10-bit ADC102S021 can be used. Unwanted Thermocouple Effect At the point where the thermocouple wires are connected to the circuit, usually copper wires or traces, an unwanted thermocouple effect will occur. At this connection, this could be the connector on a PCB, the thermocouple wiring forms a second thermocouple with the connector. This second thermocouple disturbs the measurements from the intended thermocouple. Using an isothermal block as a reference enables correction for this unwanted thermocouple effect. An isothermal block is a good heat conductor. This means that the two thermocouple connections both have the same temperature. The temperature of the isothermal block can be measured, and thereby the temperature of the thermocouple connections. This is usually called the cold junction reference temperature. In the example, an LM35 is used to measure this temperature. This semiconductor temperature sensor can accurately measure temperatures from -55C to 150C. The two channel ADC in this example also converts the signal from the LM35 to a digital signal. Now the microprocessor can compensate the amplified thermocouple signal, for the unwanted thermocouple effect. 20 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 LMV851, LMV852, LMV854 www.ti.com SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 Cold Junction Temperature RG LM35 RF T Metal A Copper Metal B Thermocouple - RG LMV851 + Copper Amplified Thermocouple Output RF Cold Junction Reference Figure 57. Thermocouple Read Out Circuit Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 Submit Documentation Feedback 21 LMV851, LMV852, LMV854 SNOSAW1A - OCTOBER 2007 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Original (March 2013) to Revision D 22 Submit Documentation Feedback Page Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMV851 LMV852 LMV854 PACKAGE OPTION ADDENDUM www.ti.com 24-Dec-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV851MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98 LMV851MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98 LMV851MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A98 LMV852MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 AB5A LMV852MME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 AB5A LMV852MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM & no Sb/Br) -40 to 125 AB5A LMV854MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV854 MT LMV854MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV854 MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Dec-2016 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMV851MG/NOPB SC70 DCK 5 LMV851MGE/NOPB SC70 DCK LMV851MGX/NOPB SC70 DCK LMV852MM/NOPB VSSOP LMV852MM/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 DGK 8 1000 178.0 13.4 5.3 3.4 1.4 8.0 12.0 Q1 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV852MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV852MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV852MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV854MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV851MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV851MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0 LMV851MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LMV852MM/NOPB VSSOP DGK 8 1000 202.0 201.0 28.0 LMV852MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMV852MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LMV852MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LMV852MMX/NOPB VSSOP DGK 8 3500 364.0 364.0 27.0 LMV854MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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