T11 941 LD6805 series SO Low-dropout regulators, high PSRR, 150 mA Rev. 4 -- 7 June 2013 Product data sheet 1. Product profile 1.1 General description The LD6805 series is a small-size Low DropOut regulator (LDO) family with ultra high Power Supply Rejection Ratio (PSRR) of 75 dB. The voltage drop is 250 mV at 150 mA current rating. Operating voltages can range from 2.3 V to 5.5 V. Each device has a fixed output voltage VO(nom) between 1.2 V and 3.6 V. The LD6805K/xxH devices show a high-ohmic state (3-state) at the output pin when set to disabled mode. The LD6805K/xxP devices contain a pull-down switching transistor to provide a low-ohmic output state (auto discharge function) in disabled mode. The LD6805 series devices are available in a DFN1010C-4 (SOT1194-1) plastic package with a size of 1 1 0.55 mm. The devices are ideal for use in portable applications requiring component miniaturization. 1.2 Features and benefits High PSRR Overcurrent protection Auto discharge or high-ohmic output state when disabled Low quiescent current (0.1 A) in shutdown mode High-level ElectroStatic Discharge (ESD) protection (6 kV Human Body Model (HBM)) DFN1010C-4 (SOT1194-1) plastic package with a size of 1 1 0.55 mm Pb-free, Restriction of Hazardous Substances (RoHS) compliant, free of halogen and antimony (dark green compliant) 1.3 Applications Smartphones Mobile handsets Digital still cameras Tablet PCs Mobile internet devices Portable media players 1.4 Quick reference data IO = 150 mA PSRR = 75 dB at 1 kHz RMS noise Vn(o)RMS = 40 V at 10 Hz to 100 kHz tstartup(reg) = 150 s VI = 2.3 V to 5.5 V VO = 1.2 V to 3.6 V Dropout voltage Vdo = 250 mV at IO = 150 mA Quiescent current Iq = 35 A at 0 mA LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 2. Pinning information 2.1 Pinning LD6805 IN 4 3 EN OUT 1 2 GND 001aan948 Transparent top view Fig 1. Pin configuration for DFN1010C-4 (SOT1194-1) 2.2 Pin description Table 1. Pin description for DFN1010C-4 (SOT1194-1) Symbol Pin Description OUT 1 regulator output voltage GND 2 supply ground EN 3 device enable input; active HIGH IN 4 regulator input voltage i.c. TAB internal connected[1] [1] The TAB is GND level (it is placed on the reverse side of the IC). It is recommended to connect the TAB to GND. Leaving it unconnected is also allowed but it may result in lower thermal performance. 3. Ordering information Table 2. Ordering information Type number LD6805 series Package Name Description Version DFN1010C-4 plastic thermal enhanced ultra thin small outline package; no leads; 4 terminals; body 1 1 0.55 mm SOT1194-1 Further ordering options see Section 3.1 "Ordering options". LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 2 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 3.1 Ordering options Further information on output voltage is available on request; see Section 20 "Contact information". An explanation of high-ohmic and pull-down type is in Section 4 "Block diagram". Table 3. Type number Nominal output voltage VO(nom) Type number Nominal output voltage VO(nom) LD6805K/12H 1.2 V LD6805K/22H 2.2 V LD6805K/13H 1.3 V LD6805K/23H 2.3 V LD6805K/14H 1.4 V LD6805K/25H 2.5 V LD6805K/15H 1.5 V LD6805K/28H 2.8 V LD6805K/16H 1.6 V LD6805K/29H 2.9 V LD6805K/18H 1.8 V LD6805K/30H 3.0 V LD6805K/185H 1.85 V LD6805K/31H 3.1 V LD6805K/20H 2.0 V LD6805K/33H 3.3 V LD6805K/21H 2.1 V LD6805K/36H 3.6 V Table 4. LD6805_SER Product data sheet Type number extension of high-ohmic output Type number extension of pull-down output Type number Nominal output voltage VO(nom) Type number Nominal output voltage VO(nom) LD6805K/12P 1.2 V LD6805K/23P 2.3 V LD6805K/13P 1.3 V LD6805K/25P 2.5 V LD6805K/14P 1.4 V LD6805K/26P 2.6 V LD6805K/15P 1.5 V LD6805K/28P 2.8 V LD6805K/16P 1.6 V LD6805K/29P 2.9 V LD6805K/18P 1.8 V LD6805K/30P 3.0 V LD6805K/20P 2.0 V LD6805K/31P 3.1 V LD6805K/21P 2.1 V LD6805K/33P 3.3 V LD6805K/22P 2.2 V LD6805K/36P 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 3 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 4. Block diagram ,1 287 5 9UHIHUHQFH *(1(5$725 (1 29(5&855(17 3527(&7,21 5 (1$%/(6+87 '2:1&,5&8,7 *1' Fig 2. DDD Block diagram of LD6805K/xxP (auto discharge function) ,1 287 5 (1 9UHIHUHQFH *(1(5$725 29(5&855(17 3527(&7,21 (1$%/(6+87 '2:1&,5&8,7 5 *1' DDD Fig 3. LD6805_SER Product data sheet Block diagram of LD6805K/xxH All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 4 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit 4 ms transient 0.5 +6 V 0.5 +6 V 0.5 +6 V - 400 mW VI input voltage VEN voltage on pin EN VO output voltage Ptot total power dissipation [1] Tstg storage temperature 55 +150 C Tj junction temperature 40 +125 C Tamb ambient temperature VESD electrostatic discharge voltage 40 +85 C human body model level 6 [2] - 6 kV machine model class 3 [3] - 400 V [1] The (absolute) maximum power dissipation depends on the junction temperature Tj. Higher power dissipation is allowed with lower ambient temperatures. The conditions to determine the specified values are Tamb = 25 C and the use of a two-layer Printed-Circuit Board (PCB). [2] According to IEC 61340-3-1. [3] According to JESD22-A115C. 6. Recommended operating conditions Table 6. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Tamb ambient temperature 40 Tj junction temperature - input voltage 2.3 voltage on pin EN Typ Max Unit - +85 C - +125 C - 5.5 V 0 - VI V 0.5 - VI + 0.3 V 0.7 1.0 - F Pin IN VI Pin EN VEN Pin OUT output voltage VO CL(ext) [1] LD6805_SER Product data sheet [1] external load capacitance See Section 10.1 "Capacitor values". All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 5 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 7. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Rth(j-a) Conditions [1][2] thermal resistance from junction to ambient Typ Unit 250 K/W [1] The overall Rth(j-a) can vary depending on the board layout. To minimize the effective Rth(j-a), all pins must have a solid connection to larger Cu layer areas for example to the power and ground layer. In multilayer PCB applications, the second layer is used to create a large heat spreader area directly below the LDO. If this layer is either ground or power, it is connected with several vias to the top layer connecting to the device ground or supply. Avoid the use of solder-stop varnish under the chip. [2] Use the measurement data given for a rough estimation of the Rth(j-a) in your application. The actual Rth(j-a) value can vary in applications using different layer stacks and layouts. 8. Characteristics Table 8. Electrical characteristics At recommended input voltages and Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - 250 - mV Tamb = +25 C 2 0.5 +2 % 30 C Tamb +85 C 3 - +3 % Tamb = +25 C 3 0.5 +3 % 30 C Tamb +85 C 4 - +4 % VI = (VO(nom) + 0.5 V) to 5.5 V 0.1 - +0.1 %/V 1 mA IO 150 mA - 0.0025 0.01 %/mA - - 150 mA VO(nom) > 1.8 V; VO = 0.95 VO(nom) 200 - - mA VO(nom) < 1.8 V; VO = 0.9 VO(nom) 200 - - mA - 300 - mA Output voltage Vdo dropout voltage IO = 150 mA; VI < VO(nom) VO output voltage variation VO 1.8 V; IO = 1 mA VO < 1.8 V; IO = 1 mA Line regulation error VO/(VOxVI) relative output voltage variation with input voltage Load regulation error VO/(VOxIO) relative output voltage variation with output current Output current IO output current IOM peak output current Isc short-circuit current VI = (VO(nom) + 0.5 V) to 5.5 V pin OUT Regulator quiescent current Iq quiescent current LD6805_SER Product data sheet VEN = 1.1 V; IO = 0 mA - 35 - A VEN = 1.1 V; 1 mA IO 150 mA - 150 - A VEN 0.4 V - 0.1 1 A All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 6 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA Table 8. Electrical characteristics ...continued At recommended input voltages and Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Ripple rejection and output noise PSRR power supply rejection ratio VI = VO(nom) + 1.0 V; IO = 50 mA; fripple = 1 kHz - 75 - dB Vn(o)(RMS) RMS output noise voltage fripple = 10 Hz to 100 kHz; CL(ext) = 1 F - 40 - V Enable input and timing VIL LOW-level input voltage pin EN 0 - 0.4 V VIH HIGH-level input voltage pin EN 1.1 - 5.5 V tstartup(reg) regulator start-up time VI = 5.5 V; VO = 0.95 VO(nom); IO = 150 mA; CL(ext) = 1 F - 150 - s VI = 5.5 V; VO = 0.05 VO(nom); CL(ext) = 1 F - 300 - s - 100 - LD6805K/xxP; auto discharge function tsd(reg) regulator shutdown time Rpd pull-down resistance LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 7 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 9. Dynamic behavior 9.1 Power Supply Rejection Ratio (PSRR) PSRR stands for the capability of the regulator to suppress unwanted signals on the input voltage like noise or ripples. V O ripple PSRR dB = - 20 log ---------------------- for all frequencies V I ripple 80 018aaa171 (2) PSRR (dB) 60 (3) (4) (1) 40 20 0 102 103 104 f (Hz) 105 (1) IO = 1 mA (2) IO = 50 mA (3) IO = 100 mA (4) IO = 200 mA Fig 4. LD6805_SER Product data sheet PSRR for LD6805K/18x All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 8 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 9.2 Dropout The dropout voltage is defined as the smallest input to output voltage difference at a specified load current when the regulator operates within its linear region. This means that the input voltage is below the nominal output voltage value and the pass transistor works as a plain resistor. A small dropout voltage guarantees lower power consumption and efficiency maximization. 018aaa172 400 Vdo (mV) 300 (1) (2) 200 (3) 100 0 0 40 80 120 160 200 IO (mA) (1) Tamb = +85 C (2) Tamb = +25 C (3) Tamb = 40 C Fig 5. LD6805_SER Product data sheet Dropout voltage as a function of output current for LD6805K/25x All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 9 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 9.3 Accuracy The LD6805 series guarantees high accuracy of the nominal output voltage. 018aaa173 2.52 VO (V) 2.51 (1) (2) 2.50 (3) (4) 2.49 2.48 -60 -20 20 60 100 140 Tamb (C) (1) IO = 1 mA (2) IO = 100 mA (3) IO = 150 mA (4) IO = 200 mA Fig 6. LD6805_SER Product data sheet Accuracy for LD6805K/25x All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 10 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 10. Application information 10.1 Capacitor values The LD6805 series requires external capacitors at the output to guarantee a stable regulator behavior. Do not under-run the specified minimum Equivalent Series Resistance (ESR). The absolute value of the total capacitance attached to the output pin OUT influences the shutdown time (tsd(reg)) of the LD6805 series. Also an input capacitor is recommended to keep the input voltage stable. Table 9. External load capacitor Symbol Parameter Conditions Cext(IN) external capacitance on pin IN [1] CL(ext) external load capacitance [1] ESR equivalent series resistance [1] Min Typ Max Unit 0.7 1.0 0.7 1.0 - F 5 - 500 m F The minimum value of capacitance for stability and correct operation is 0.7 F. The specified capacitor tolerance is 30 % or better over the temperature and operating conditions range. The recommended capacitor type is X7R to meet the full device temperature specification of 40 C to +125 C. IN IN OUT EN GND 1F OUT 1F 001aan647 Fig 7. Application diagram 11. Test information 11.1 Quality information This product has been qualified in accordance with NX1-00023 NXP Semiconductors Quality and Reliability Specification and is suitable for use in consumer applications. LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 11 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 12. Marking 7(50,1$/ ,1'(;0$5.(5 0$5.,1*&2'( 9(1'25&2'( DDD Fig 8. Table 10. Product data sheet Marking of high-ohmic output Type number Nominal output voltage VO(nom) Marking code Type number Nominal output voltage VO(nom) Marking code LD6805K/12H 1.2 V AH LD6805K/22H 2.2 V KH LD6805K/13H 1.3 V BH LD6805K/23H 2.3 V LH LD6805K/14H 1.4 V CH LD6805K/25H 2.5 V NH LD6805K/15H 1.5 V DH LD6805K/28H 2.8 V QH LD6805K/16H 1.6 V EH LD6805K/29H 2.9 V RH LD6805K/18H 1.8 V GH LD6805K/30H 3.0 V SH LD6805K/185H 1.85 V 5H LD6805K/31H 3.1 V TH LD6805K/20H 2.0 V IH LD6805K/33H 3.3 V VH LD6805K/21H 2.1 V JH LD6805K/36H 3.6 V YH Table 11. LD6805_SER Marking DFN1010C-4 (SOT1194-1) Marking of pull-down output Type number Nominal output voltage VO(nom) Marking code Type number Nominal output voltage VO(nom) Marking code LD6805K/12P 1.2 V AP LD6805K/23P 2.3 V LP LD6805K/13P 1.3 V BP LD6805K/25P 2.5 V NP LD6805K/14P 1.4 V CP LD6805K/25P 2.5 V NP LD6805K/15P 1.5 V DP LD6805K/26P 2.6 V OP LD6805K/16P 1.6 V EP LD6805K/29P 2.9 V RP LD6805K/18P 1.8 V GP LD6805K/30P 3.0 V SP LD6805K/20P 2.0 V IP LD6805K/31P 3.1 V TP LD6805K/21P 2.1 V JP LD6805K/33P 3.3 V VP LD6805K/22P 2.2 V KP LD6805K/36P 3.6 V YP All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 12 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 13. Package outline Plastic thermal enhanced ultra thin small outline package; no leads; 4 terminals; body 1 x 1 x 0.55 mm SOT1194-1 X A B D A E A1 A3 terminal 1 index area detail X e 1 2 C C A B C v w b y1 C y E D h h k terminal 1 index area L 4 3 0 1 mm scale Dimensions Unit(1) mm A A1 A3 b D Dh E Eh e max 0.55 0.05 0.152 0.30 1.05 0.53 1.05 0.53 nom 0.25 1.00 0.48 1.00 0.48 0.65 min 0.00 0.05 0.20 0.95 0.43 0.95 0.43 k L v 0.1 0.2 0.30 0.25 0.20 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1194-1 --- --- --- Fig 9. sot1194-1_po European projection Issue date 11-05-30 12-05-22 Package outline DFN1010C-4 (SOT1194-1) LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 13 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 14. Packing information 14.1 Packing methods Table 12. Packing methods Type number Package Description Orientation 12NC [1] ending Packing quantity LD6805K DFN1010C-4 (SOT1194-1) 2 mm pitch, 8 mm tape and reel Q1 10000 [1] 115 For further information about orientation, see Section 14.2. 14.2 Carrier tape information 4 4 4 4 GLUHFWLRQRIIHHG DDD Fig 10. Carrier tape Table 13. LD6805_SER Product data sheet Orientations Orientation Meaning Pin 1 location Q1 quadrant 1 upper left Q2 quadrant 2 upper right Q3 quadrant 3 lower left Q4 quadrant 4 lower right All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 14 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 15. Soldering Footprint information for reflow soldering of HXSON4 package SOT1194-1 1.2 1.15 0.65 0.25 0.48 45 1.55 0.5 1.2 1.3 0.025 0.48 r= 0.05 solder land solder land plus solder paste solder paste deposit solder resist occupied area Dimensions in mm 0.2 r= 0.05 Remark: Stencil of 75 m is recommended. sot1194-1_fr Fig 11. Soldering footprint DFN1010C-4 (SOT1194-1) LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 15 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 16 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 16.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 12) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 15. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 12. LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 17 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 17. References LD6805_SER Product data sheet [1] IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices [2] IEC 61340-3-1 -- Methods for simulation of electrostatic effects - Human body model (HBM) electrostatic discharge test waveforms [3] JESD22-A115C -- Electrostatic discharge (ESD) Sensitivity Testing Machine Model (MM) [4] NX2-00001 -- NXP Semiconductors Quality and Reliability Specification [5] AN10365 -- Surface-mount reflow soldering description All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 18 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 18. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes LD6805_SER v.4 20130607 Product data sheet - LD6805_SER v.3 Modifications: * * * Added type number LD6805K/26P Section 1.2 "Features and benefits": updated Section 9.1 "Power Supply Rejection Ratio (PSRR)": corrected equation LD6805_SER v.3 20130503 Product data sheet - LD6805_SER v.2 LD6805_SER v.2 20120625 Product data sheet - LD6805_SER v.1 LD6805_SER v.1 20110922 Objective data sheet - - LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 19 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. LD6805_SER Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 20 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LD6805_SER Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 -- 7 June 2013 (c) NXP B.V. 2013. All rights reserved. 21 of 22 LD6805 series NXP Semiconductors Low-dropout regulators, high PSRR, 150 mA 21. Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 3.1 4 5 6 7 8 9 9.1 9.2 9.3 10 10.1 11 11.1 12 13 14 14.1 14.2 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Dynamic behavior . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supply Rejection Ratio (PSRR). . . . . . . 8 Dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 11 Capacitor values . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Quality information . . . . . . . . . . . . . . . . . . . . . 11 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Packing information . . . . . . . . . . . . . . . . . . . . 14 Packing methods . . . . . . . . . . . . . . . . . . . . . . 14 Carrier tape information . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering of SMD packages . . . . . . . . . . . . . . 16 Introduction to soldering . . . . . . . . . . . . . . . . . 16 Wave and reflow soldering . . . . . . . . . . . . . . . 16 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 June 2013 Document identifier: LD6805_SER