© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 4
1Publication Order Number:
NCS7101/D
NCS7101, NCV7101
1.8 Volt Rail-to-Rail
Operational Amplifier
The NCS7101 operational amplifier provides rail−to−rail operation
on both the input and output. The output can swing within 50 mV of
each rail. This rail−to−rail operation enables the user to make full use
of the entire supply voltage range available. It is designed to work at
very low supply voltages (1.8 V and ground), yet can operate with a
supply of up to 10 V and ground. The NCS7101 is available in the
space saving SOT−23−5 package with two industry standard pinouts.
Features
•Low Voltage, Single Supply Operation (1.8 V and Ground to 10 V
and Ground)
•1.0 pA Input Bias Current
•Unity Gain Bandwidth of 1.0 MHz at 5.0 V,
0.9 MHz at 1.8 V
•Output Voltage Swings Within 50 mV of Both Rails @ 1.8 V
•No Phase Reversal on the Output for Over−Driven Input Signals
•Input Offset Trimmed to 1.0 mV
•Low Supply Current (ID = 1.0 mA)
•Works Down to Two Discharged NiCd Battery Cells
•ESD Protected Inputs Up to 2.0 kV
•These Devices are Pb−Free and are RoHS Compliant
•AEC−Q100 Qualified and PPAP Capable
•*NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
Typical Applications
•Dual NiCd/NiMH Cell Powered Systems
•Portable Communication Devices
•Low Voltage Active Filters
•Power Supply Monitor and Control
•Interface to DSP
Figure 1. Typical Application
1.8 V
to
10 V
This device contains 68 active transistors.
-
+
Rail to Rail Input Rail to Rail Output
Device Package Shipping†
ORDERING INFORMATION
NCS7101SN1T1G
3000 Tape & Reel
(7 inch Reel)
CASE 483
SOT−23−5
SN SUFFIX
PIN CONNECTIONS
1
VOUT
VCC
Non−Inverting
Input
2
3
5
4
VEE
Inverting
Input
Style 1 Pin Out (SN1T1)
LOW VOLTAGE
RAIL−TO−RAIL
OPERATIONAL AMPLIFIER
+−
1
VOUT
VEE
Non−Inverting
Input
2
3
5
4
VCC
Inverting
Input
Style 2 Pin Out (SN2T1)
+−
MARKING DIAGRAM
x = C for SN1
D for SN2
A = Assembly Location
Y = Year
W = Work Week
G= Pb−Free Package
NCS7101SN2T1G
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NCV7101SN1T1G*
SOT−23−5
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
5
1
5
AAx AYWG
G
(Note: Microdot may be in either location)
NCV7101SN2T1G*
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MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) VS10 V
Input Differential Voltage Range (Note 1) VIDR VEE − 300 mV to 10 V V
Input Common Mode Voltage Range (Note 1) VICR VEE − 300 mV to 10 V V
Output Short Circuit Duration (Note 2) tSC Indefinite sec
Junction Temperature TJ150 °C
Power Dissipation and Thermal Characteristics − SOT−23−5 Package
Thermal Resistance, Junction−to−Air
Power Dissipation @ TA = 70°C
RqJA
PD
220
364
°C/W
mW
Storage Temperature Range Tstg −65 to +150 °C
Operating Ambient Temperature Range NCS7101
NCV7101
TA−40 to +85
−40 to +125
°C
ESD Protection at any Pin Human Body Model (Note 3) VESD 2000 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Either or both inputs should not exceed the range of VEE − 300 mV to VEE + 10 V.
2. Maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded.
TJ = TA + (PDRqJA)
3. ESD data available upon request.
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DC ELECTRICAL CHARACTERISTICS
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0, RL to GND, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Input Offset Voltage
VCC = 0.9 V, VEE = −0.9 V
TA = 25°C
TA = TLow to THigh
VCC = 2.5 V, VEE = −2.5 V
TA = 25°C
TA = TLow to THigh
VCC = 5.0 V, VEE = −5.0 V
TA = 25°C
TA = TLow to THigh
VIO
−7.0
−9.0
−7.0
−9.0
−7.0
−9.0
0.6
−
0.6
−
0.6
−
7.0
9.0
7.0
9.0
7.0
9.0
mV
Input Offset Voltage Temperature Coefficient (RS = 50)
TA = −40°C to 125°C
DVIO/DT−8.0 −mV/°C
Input Bias Current (VCC = 1.8 V to 10 V) |IIB|−1.0 −pA
Common Mode Input Voltage Range VICR VEE −VCC V
Large Signal Voltage Gain
VCC = 5.0 V, VEE = −5.0 V
RL = 10 kW
RL = 2.0 kW
AVOL
16
16
50
30
−
−
kV/V
Output Voltage Swing, High (VID = "0.2 V)
VCC = 0.9 V, VEE = −0.9 V (TA = 25°C)
RL = 10 k
RL = 2.0 k
TA = TLow to THigh
RL = 10 k
RL = 2.0 k
VCC = 2.5 V, VEE = −2.5 V (TA = 25°C)
RL = 600
RL = 2.0 k
TA = TLow to THigh
RL = 600
RL = 2.0 k
VCC = 5.0 V, VEE = −5.0 V (TA = 25°C)
RL = 600
RL = 2.0 k
TA = TLow to THigh
RL = 600
RL = 2.0 k
VOH
0.85
0.80
0.85
0.79
2.10
2.35
2.00
2.40
4.40
4.80
4.40
4.80
0.88
0.82
−
−
2.21
2.44
−
−
4.60
4.88
−
−
−
−
−
−
−
−
−
−
−
−
−
−
V
Output Voltage Swing, Low (VID = "0.2 V)
VCC = 0.9 V, VEE = −0.9 V (TA = 25°C)
RL = 10 k
RL = 2.0 k
TA = TLow to THigh
RL = 10 k
RL = 2.0 k
VCC = 2.5 V, VEE = −2.5 V (TA = 25°C)
RL = 600
RL = 2.0 k
TA = TLow to THigh
RL = 600
RL = 2.0 k
VCC = 5.0 V, VEE = −5.0 V (TA = 25°C)
RL = 600
RL = 2.0 k
TA = TLow to THigh
RL = 600
RL = 2.0 k
VOL
−
−
−
−
−
−
−
−
−
−
−
−
−0.88
−0.82
−
−
−2.22
−2.38
−
−
−4.66
−4.88
−
−
−0.85
−0.80
−0.85
−0.78
−2.10
−2.35
−2.00
−2.30
−4.40
−4.80
−4.35
−4.80
V
Common Mode Rejection Ratio
Vin = 0 to 10 V
Vin = 0 to 5.0 V
CMRR
65
60
−
−
−
−
dB
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DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0, RL to GND, TA = 25°C, unless otherwise noted.)
Characteristics UnitMaxTypMinSymbol
Power Supply Rejection Ratio
VCC/VEE = 10 V/Ground, DVS = 2.5 V
PSRR 65 − − dB
Output Short Circuit Current (Vin Diff = "1.0 V)
VCC = +0.9 V, VEE = −0.9 V
Source
Sink
VCC = +2.5 V, VEE = −2.5 V
Source
Sink
VCC = 5.0 V, VEE = −5.0 V
Source
Sink
ISC
−
−
20
−60
50
−140
3.0
−3.0
25
−25
72
−72
−
−
60
−20
140
−50
mA
Power Supply Current (VO = 0 V)
VCC = +0.9 V, VEE = −0.9 V
TA = 25°C
TA = −40°C to 85°C
TA = −40°C to 125°C
VCC = +2.5 V, VEE = −2.5 V
TA = 25°C
TA = −40°C to 85°C
TA = −40°C to 125°C
VCC = 5.0 V, VEE = −5.0 V
TA = 25°C
TA = −40°C to 85°C
TA = −40°C to 125°C
ID
−
−
−
−
−
−
−
−
−
0.97
−
−
1.05
−
−
1.13
−
−
1.20
1.30
1.60
1.30
1.40
1.70
1.40
1.50
1.80
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.5 V, VEE = −2.5 V, VCM = VO = 0, RL to GND, TA = 25°C, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Slew Rate (VO = −2.0 to 2.0 V, RL = 2.0 kW, AV = 1.0) SR 0.7 1.2 3.0 V/ms
Gain Bandwidth Product (VCC = 10 V) GBW 0.5 1.0 3.0 MHz
Gain Margin (RL = 10 k, CL = 5.0 pF) Am −6.5 −dB
Phase Margin (RL = 10 k, CL = 5.0 pF) φm−60 −Deg
Power Bandwidth (VO = 4.0 Vpp, RL = 2.0 kW, THD v 1.0%) BWP−130 −kHz
Total Harmonic Distortion (VO = 4.0 Vpp, RL = 2.0 kW, AV = 1.0)
f = 1.0 kHz
f = 10 kHz
THD
−
−
0.02
0.2
−
−
%
Differential Input Resistance (VCM = 0 V) Rin −u1.0 −tera W
Differential Input Capacitance (VCM = 0 V) Cin −2.0 −pF
Equivalent Input Noise Voltage (Freq = 1.0 kHz) en−140 −nV/√Hz
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t, time (1.0 ms/Div)t, time (500 ns/Div)
TA, AMBIENT TEMPERATURE (°C)
Figure 2. Output Saturation Voltage versus
Load Resistance
Figure 3. Output Saturation Voltage versus
Load Current
Figure 4. Input Bias Current versus
Temperature
Figure 5. Gain and Phase versus Frequency
Figure 6. Transient Response Figure 7. Slew Rate
0
100 1.0 k 10 k 100 k 1.0 M
RL, LOAD RESISTANCE (W)
400
800
1200
−1200
−800
−400
0
High State Output
Sourcing Current
Low State Output
Sinking Current
VS = ±2.5 V
RL = to GND
TA = 25°C
0
0 2.0 8.0 10 12
IL, LOAD CURRENT (mA)
0.4
0.8
1.2
−1.2
−0.8
−0.4
0
High State Output
Sourcing Current
Low State Output
Sinking Current
VS = ±2.5 V
RL = to GND
TA = 25°C
4.0 6.0
Vsat, OUTPUT SATURATION VOLTAGE (V)
IIB, INPUT CURRENT (pA)
1000
10
0.1
0
0 25 50 75 100 125
1.0
VS = ±2.5 V
RL = ∞
CL = 0
AV = 1.0
500 mV/div
50 mV/div
VEE
VCC
Vsat, OUTPUT SATURATION VOLTAGE (mV)
VEE
VCC
100
VS = ±2.5 V
VO = 4.0 VPP
RL = 10 k
CL = 10 pF
AV = 1.0
TA = 25°C
VS = ±2.5 V
VO = 4.0 VPP
RL = 10 k
CL = 10 pF
AV = 1.0
TA = 25°C
f, FREQUENCY (Hz)
AVOL, GAIN (dB)
100
60
20
0
10 100
40
VS = ±5.0 V
RL = 100 k
TA = 25°C
80
1.0 1.0 k 10 k 100 k 1.0 M 10 M
f, EXCESS PHASE (°)
−180
−140
−100
−60
−20
0
PHASE
GAIN
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2.0
8.0
10 k
6.0
100 k1.0 k 1.0 M
4.0
0
RL = 10 k
AV = 1.0
TA = 25°C
14
Figure 8. Output Voltage versus Frequency
Vout, OUTPUT VOLTAGE (VPP)
f, FREQUENCY (Hz)
10
12
VS = ±5.0 V
VS = ±2.5 V
VS = ±0.9 V
Figure 9. Common Mode Rejection versus
Frequency
Figure 10. Power Supply Rejection versus
Frequency
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 10 M
CMR, COMMON MODE REJECTION (dB)
−10
0
10
100
100 k 1.0 M
20
30
40
50
60
70
80
90
VS = ±2.5 V
RL = ∞
TA = 25°C
AV = 1.0
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 10 M
PSR, POWER SUPPLY REJECTION (dB)
−10
0
10
100
100 k 1.0 M
20
30
40
50
60
70
80
90
VS = ±2.5 V
RL = ∞
TA = 25°C
AV = 1.0
PSR+
PSR−
0
VS, SUPPLY VOLTAGE (V)
Figure 11. Output Short Circuit Sinking
Current versus Supply Voltage
|ISC|, OUTPUT SHORT CIRCUIT CURRENT (mA)
140
120
100
80
60
40
20
0
−40°C
85°C
25°C
Output Pulsed Test
at 3% Duty Cycle
±1.0 ±2.0 ±3.0 ±4.0 ±5.0
Figure 12. Output Short Circuit Sourcing
Current versus Supply Voltage
0
VS, SUPPLY VOLTAGE (V)
|ISC|, OUTPUT SHORT CIRCUIT CURRENT (mA)
140
120
100
80
60
40
20
0
−40°C
85°C
25°C
Output Pulsed Test
at 3% Duty Cycle
±1.0 ±2.0 ±3.0 ±4.0 ±5.0
VS, SUPPLY VOLTAGE (V)
Figure 13. Supply Current versus Supply
Voltage with No Load
0±1.0 ±2.0 ±3.0 ±4.0 ±5.0
RL = ∞
AV = 1.0
Vin = 0 V
|ID|, SUPPLY CURRENT (mA)
1.2
1.0
0.8
0.6
0.4
0.2
0
−40°C
85°C
25°C
1.4
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3.0
−50 −25 0 25 50 75 100
2.0
1.0
0
125
TA, AMBIENT TEMPERATURE (°C)
VS = ±2.5 V
RL = 10 k
CL = 5.3 pF
TA, AMBIENT TEMPERATURE (°C)
1.6
−50 −25 0 25 50 75 100
1.2
0.8
0.4
0
125
RL = 10 k
CL = 10 pF
AV = 1.0
TA = 25°C
+Slew Rate, VS = ±0.9 V
−Slew Rate, VS = ±2.5 V
−Slew Rate, VS = ±0.9 V
10
1.0
0.01
0.1
0.001
f, FREQUENCY (Hz)
10 1.0 k100 100 k10 k
VS = ±2.5 V
Vout = 4.0 VPP
RL = 10 k
TA = 25°C
Figure 14. Total Harmonic Distortion versus
Frequency with 5.0 V Supply
Figure 15. Total Harmonic Distortion versus
Frequency with 10 V Supply
Figure 16. Total Harmonic Distortion versus
Frequency with 5.0 V Supply
Figure 17. Total Harmonic Distortion versus
Frequency with 10 V Supply
f, FREQUENCY (Hz)
0.01
0.001
0.1
1.0
10
10 1.0 k100 100 k10 k
VS = ±5.0 V
Vout = 8.0 VPP
RL = 10 k
TA = 25°C
Figure 18. Slew Rate versus Temperature (Avg.) Figure 19. Gain Bandwidth Product versus
Temperature
+Slew Rate, VS = ±2.5 V
THD, TOTAL HARMONIC DISTORTION (%)
GBW, GAIN BANDWIDTH PRODUCT (MHz)
SR, SLEW RATE (V/ms)
AV = 1.0
AV = 10
AV = 100
AV = 1000
AV = 1.0
AV = 10
AV = 100
AV = 1000
AV = 1.0
AV = 10
AV = 100
AV = 1000
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k
THD, TOTAL HARMONIC DISTORTION (%)
0.001
0.01
0.1
1.0
10
VS = ±2.5 V
Vout = 4.0 VPP
RL = 2 k
TA = 25°CAV = 1.0
AV = 10
AV = 100
AV = 1000
f, FREQUENCY (Hz)
10 100 1.0 k 10 k 100 k
THD, TOTAL HARMONIC DISTORTION (%)
0.001
0.01
0.1
1.0
10
VS = ±5.0 V
Vout = 8.0 VPP
RL = 2 k
TA = 25°C
THD, TOTAL HARMONIC DISTORTION (%)
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Figure 20. Voltage Gain and Phase versus
Frequency
80
0
60
40
20
80
0
60
40
20
Phase Margin
Gain Margin
−50 −25 0 25 50 75 100 125
VS = ±2.5 V
RL = 10 k
CL = 10 pF
TA, AMBIENT TEMPERATURE (°C)
Figure 21. Gain and Phase Margin versus
Temperature
Am, GAIN MARGIN (dB)
Φm, PHASE MARGIN (°)
70
50
30
10
70
50
30
10
Φm, PHASE MARGIN (°)
10 100 1.0 k 1.0M
Phase Margin
Gain Margin
10 k
−40
−20
0
20
40
80
60
100
VS = ±2.5 V
RL = 10 k
CL = 5.0 pF
TA = 25°C
−40
−20
0
20
40
80
60
100
Rt, DIFFERENTIAL SOURCE RESISTANCE (W)
Figure 22. Gain and Phase Margin versus
Differential Source Resistance
Am, GAIN MARGIN (dB)
100 k
Figure 23. Gain and Phase Margin versus
Output Load Capacitance
Figure 24. Output Voltage Swing versus
Supply Voltage
0 2.0
VCC − VEE, SUPPLY VOLTAGE (V)
8.0
0
6.0
4.0
2.0
RL = 10 k
AV = 100
TA = 25°C
Split Supplies
Vout, OUTPUT VOLTAGE (VPP)
4.0 6.0 8.0 10
10
12
−30
30
10
−10
−300
−60
−140
−220
10 k 100 k 1.0 M 10 M 100 M
f, FREQUENCY (Hz)
AV, GAIN (dB)
40
20
0
−20
−20
−100
−180
−260
50 20
Φ, EXCESS PHASE (°)
Φm, PHASE MARGIN (°)
1.0 10 1000
Phase Margin
Gain Margin
100
20
40
70
60 VS = ±2.5 V
RL = 10 k
AV = 100
TA = 25°C
0
10
20
30
40
60
50
70
CL, CAPACITIVE LOAD (pF)
AV, GAIN MARGIN (dB)
50
30
0
10
RL = 10 k
AV = 100
TA = 25°C
VS = ±0.9 V
VS = ±2.5 V
Figure 25. Gain and Phase Margin versus
Supply Voltage
40
±2.0±1.0
60
80
0
70
±3.0 ±4.0 ±5.0
VS, SUPPLY VOLTAGE (V)
Am, GAIN MARGIN (dB)
AV = 100
RL = 10 k
CL = 0
TA = 25°C
Phase Margin
Gain Margin
50
30
10
20
0
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90
VS, SUPPLY VOLTAGE (V)
±2.0 ±4.0±3.0±1.0 ±5.00
70
100
60
80
110
120
RL = 10 k
CL = 0
TA = 25°C
Figure 26. Open Loop Voltage Gain versus
Supply Voltage (Split Supplies)
AVOL, OPEN LOOP GAIN (dB)
Figure 27. Input Offset Voltage versus Common
Mode Input Voltage Range, VS = +2.5 V
0
−3.0 −1.0−2.0
−15
5
−20
−10
10
20
15
−5
0 1.0 2.0 3.0
VCM, COMMON VOLTAGE RANGE (V)
VIO, INPUT OFFSET VOLTAGE (mV)
VS = ±2.5 V
RL = ∞
CL = 0
AV = 1.0
TA = 25°C
Figure 28. Input Offset Voltage versus Common
Mode Input Voltage Range, VS = +0.9 V
0
−0.6 −0.2−0.4
10
20
15
0 0.2 0.4 1.0
VCM, COMMON MODE INPUT VOLTAGE (V)
VIO, INPUT OFFSET VOLTAGE (mV)
VS = ±0.9 V
RL = ∞
CL = 0
AV = 1.0
TA = 25°C
−0.8−1.0 0.6 0.8
5
−20
−15
−10
−5
Figure 29. Common−Mode Input Voltage Range
versus Power Supply Voltage
0
±2.0
6.0
4.0
±3.0 ±4.0
VS, SUPPLY VOLTAGE (V)
VCM, COMMON MODE INPUT
VOLTAGE RANGE (V)
DVIO = 5.0 mV
RL = ∞
CL = 0
AV = 1.0
TA = 25°C
±1.0±0.5 ±5.0
2.0
−6.0
−4.0
−2.0
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APPLICATION INFORMATION AND OPERATING DESCRIPTION
GENERAL INFORMATION
The NCS7101 is a rail−to−rail input, rail−to−rail output
operational amplifier that features guaranteed 1.8 volt
operation. This feature is achieved with the use of a modified
analog CMOS process that allows the implementation of
depletion MOSFET devices. The amplifier has a 1.0 MHz
gain bandwidth product, 1.2 V/ms slew rate and is
operational over a power supply range less than 1.8 V to as
high as 10 V.
Inputs
The input topology of this device series is unconventional
when compared to most low voltage operational amplifiers.
It consists of an N−channel depletion mode differential
transistor pair that drives a folded cascode stage and current
mirror. This configuration extends the input common mode
voltage range to encompass the VEE and VCC power supply
rails, even when powered from a combined total of less than
1.8 volts. Figures 27 and 28 show the input common mode
voltage range versus power supply voltage.
The differential input stage is laser trimmed in order to
minimize offset voltage. The N−channel depletion mode
MOSFET input stage exhibits an extremely low input bias
current of less than 40 pA. The input bias current versus
temperature is shown in Figure 4. Either one or both inputs
can be biased as low as VEE minus 300 mV to as high as 10 V
without causing damage to the device. If the input common
mode voltage range is exceeded, the output will not display
a phase reversal but it may latch in the appropriate high or
low state. The device can then be reset by removing and
reapplying power. If the maximum input positive or
negative voltage ratings are to be exceeded, a series resistor
must be used to limit the input current to less than 2.0 mA.
The ultra low input bias current of the NCS7101 allows
the use of extremely high value source and feedback resistor
without reducing the amplifier’s gain accuracy. These high
value resistors, in conjunction with the device input and
printed circuit board parasitic capacitances Cin, will add an
additional pole to the single pole amplifier shown in
Figure 30. If low enough in frequency, this additional pole
can reduce the phase margin and significantly increase the
output settling time. The effects of Cin, can be canceled by
placing a zero into the feedback loop. This is accomplished
with the addition of capacitor Cfb. An approximate value for
Cfb can be calculated by:
Cfb +Rin Cin
Rfb
Figure 30. Input Capacitance Pole Cancellation
+
-Output
Rfb
Cin
Rin
Cfb
Cin = Input and printed circuit board capacitance
Input
Output
The output stage consists of complementary P and N
channel devices connected to provide rail−to−rail output
drive. With a 2.0 k load, the output can swing within 100 mV
of either rail. It is also capable of supplying over 95 mA
when powered from 10 V and 3.0 mA when powered from
1.8 V.
When connected as a unity gain follower, the NCS7101
can directly drive capacitive loads in excess of 390 pF at
room temperature without oscillating but with significantly
reduced phase margin. The unity gain follower
configuration exhibits the highest bandwidth and is most
prone to oscillations when driving a high value capacitive
load. The capacitive load in combination with the
amplifier’s output impedance, creates a phase lag that can
result in an under−damped pulse response or a continuous
oscillation. Figure 32 shows the effect of driving a large
capacitive load in a voltage follower type of setup. When
driving capacitive loads exceeding 390 pF, it is
recommended to place a low value isolation resistor
between the output of the op amp and the load, as shown in
Figure 31. The series resistor isolates the capacitive load
from the output and enhances the phase margin. Refer to
Figure 33. Larger values of R will result in a cleaner output
waveform but excessively large values will degrade the
large signal rise and fall time and reduce the output’s
amplitude. Depending upon the capacitor characteristics,
the isolation resistor value will typically be between 50 to
500 ohms. The output drive capability for resistive and
capacitive loads is shown in Figures 2, 3, and 23.
Figure 31. Capacitance Load Isolation
+
-
Output
R
Isolation resistor R = 50 to 500
CL
Input
Note that the lowest phase margin is observed at cold
temperature and low supply voltage.
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Figure 32. Small Signal Transient Response with Large Capacitive Load
Figure 33. Small Signal Transient Response with Large
Capacitive Load and Isolation Resistor.
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The non−inverting input threshold levels are set so that
the capacitor voltage oscillates between 1/3 and 2/3 of
VCC. This requires the resistors R1a, R1b and R2 to be of
equal value. The following formula can be used to ap-
proximate the output frequency.
RT
470 k
R2
470 k
R1b
470 k
R1a
470 k
CT
1.0 nF
VCC
fO = 1.5 kHz
0.67 VCC
-
+
0.9 V
fO+1
1.39 RTCT
VCC
0.33 VCC
0
Output Voltage
Timing Capacitor
Voltage
Figure 34. Square Wave Oscillator
R1b
470 k
VCC
D2
1N4148
fO
-
+
VCC
R2
470 k
D1
1N4148
10 k
10 k
1.0 M
cw
R1a
470 k
CT
1.0 nF
0.67 VCC
VCC
0.33 VCC
0
Output Voltage
Timing Capacitor
Voltage
0.67 VCC
VCC
0.33 VCC
0
Output Voltage
Timing Capacitor
Voltage
The timing capacitor CT will charge through diode D2 and discharge
through diode D1, allowing a variable duty cycle. The pulse width of the
signal can be programmed by adjusting the value of the trimpot. The ca-
pacitor voltage will oscillate between 1/3 and 2/3 of VCC, since all the
resistors at the non−inverting input are of equal value.
Clock−wise, Low Duty Cycle
Counter−Clock−wise, High Duty Cycle
Figure 35. Variable Duty Cycle Pulse Generator
cww
R1
1.0 M
R2
1.0 M
R3
1.0 k
Cin
10 mF
2.5 V
10,000 mF
+
-
Ceff. +R1
R3Cin
−2.5 V
≈
Figure 36. Positive Capacitance Multiplier
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fL
+1
2pR1C1[200 Hz
fH+1
2pRfCf[4.0 kHz
Af+1)
Rf
R2+11
Af
fLfH
R1
10 k
Rf
100 k
R2
10 k
Cf
400 pF
0.9 V
−0.9 V
C1
80 nF
VO
+
-
Vin
Figure 37. Voice Band Filter
Rsense
VCC
+
-
Vsupply
Vin
Isink+
Vin
Rsense
Figure 38. High Compliance Current Sink
IsVO
1.00 A 67.93 mV
0.50 A 78.67 mV
3.3 k
R3
1.0 k
RL
Is
5.0 V
R4
2.4 k
VL
For best performance, use low
tolerance resistors.
+
-
1.0 W
Rsense
R5
1.0 k
R1
1.0 k
Figure 39. High Side Current Sense
R2
VO
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k R2
R2
VCC
+
-iL+VS
R1
Figure 40. Current Source
k R1
R1
, Note that iL is independent of RL
VO
RL
VS
iL
R1
VCC
+
-
Figure 41. Current to Voltage Converter
VO = −iS R1
VO
iS
R1
VCC
+
-
Figure 42. Voltage to Current Converter
VOiR1 +iL+VR1
R1+VS
R1
RL
iR1
iL
VS
i = 0
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R2
VCC
+
-
VO+V2ƪR4
R3)R4ƫƪR2
R1)1ƫ*V1R2
R1
Figure 43. Differential Amplifier
R1
R3
VO
R4
V2
V1
If R1 = R3, and R2 = R4, the equation simplifies to:
VO+(V2*V1)R2
R1
R4
VCC
+
-
VO+*R2ƪV1
R1)V2
R2)V3
R3ƫ
Figure 44. Summing Amplifier
R2
R3VO
R5
V2
V1
To minimize input offset current take:
R5 = R1 // R2 // R3 // R4
R1
V2
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PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
DIM MIN MAX
MILLIMETERS
A3.00 BSC
B1.50 BSC
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
L1.25 1.55
M0 10
S2.50 3.00
123
54 S
A
G
L
B
D
H
C
J
__
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
T
SEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NCS7101/D
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