PH
VIN
GND
BOOT
VSENSE
COMP
SS
CSS
D1
VIN
VOUT
EN
TPS54231
CI
CBOOT
LO
CO
Ren1
RO2
C1
C2
R3
Ren2
RO1
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10
Efficiency-%
I -LoadCurrent- A
L
V =3.3V
O
V =12V
I
V =18V
I
V =24V
I
V =28V
I
V =5V
I
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
2A, 28V INPUT, STEP DOWN DC/DC CONVERTER WITH ECO-MODE™
Check for Samples: TPS54231
1FEATURES APPLICATIONS
2• 3.5 V to 28 V Input Voltage Range • Consumer Applications such as Set-Top
Boxes, CPE Equipment, LCD Displays,
• Adjustable Output Voltage Down to 0.8 V Peripherals, and Battery Chargers
• Integrated 80 mΩHigh Side MOSFET Supports • Industrial and Car Audio Power Supplies
up to 2 A Continuous Output Current • 5V, 12V and 24V Distributed Power Systems
• High Efficiency at Light Loads with a Pulse
Skipping Eco-mode™ DESCRIPTION
• Fixed 570 kHz Switching Frequency The TPS54231 is a 2 V, 2 A non-synchronous buck
• Typical 1 μA Shutdown Quiescent Current converter that integrates a low RDS(on) high side
• Adjustable Slow Start Limits Inrush Currents MOSFET. To increase efficiency at light loads, a
pulse skipping Eco-mode™ feature is automatically
• Programmable UVLO Threshold activated. Furthermore, the 1 μA shutdown supply
• Overvoltage Transient Protection current allows the device to be used in battery
• Cycle-by-Cycle Current Limit, Frequency Fold powered applications. Current mode control with
Back and Thermal Shutdown Protection internal slope compensation simplifies the external
compensation calculations and reduces component
• Available in Easy-to-Use SOIC8 Package count while allowing the use of ceramic output
• Supported by SwitcherPro™ Software Tool capacitors. A resistor divider programs the hysteresis
(http://focus.ti.com/docs/toolsw/folders/print/s of the input under-voltage lockout. An overvoltage
witcherpro.html)transient protection circuit limits voltage overshoots
during startup and transient conditions. A cycle by
cycle current limit scheme, frequency fold back and
thermal shutdown protect the device and the load in
the event of an overload condition. The TPS54231 is
available in an 8-pin SOIC package that has been
internally optimized to improve thermal performance.
SIMPLIFIED SCHEMATIC EFFICIENCY
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Eco-mode, SwitcherPro, PowerPAD, SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
For additional design needs, see:
TPS54231 TPS54232 TPS54233 TPS54331 TPS54332
IO(Max) 2A 2A 2A 3A 3.5A
Input Voltage Range 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V
Switching Freq. (Typ) 570kHz 1000kHz 285kHz 570kHz 1000kHz
Switch Current Limit (Min) 2.3A 2.3A 2.3A 3.5A 4.2A
Pin/Package 8SOIC 8SOIC 8SOIC 8SOIC 8SO PowerPAD™
ORDERING INFORMATION(1)
TJPACKAGE SWITCHING FREQUENCY PART NUMBER(2)
–40°C to 150°C 8 pin SOIC 570 kHz TPS54231D
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The D package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54231DR). See applications section of
data sheet for layout information.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
VIN –0.3 to 30
EN –0.3 to 6
BOOT 38
Input Voltage V
VSENSE –0.3 to 3
COMP –0.3 to 3
SS –0.3 to 3
BOOT-PH 8
Output Voltage PH –0.6 to 30 V
PH (10 ns transient from ground to negative peak) –5
EN 100 μA
BOOT 100 mA
Source Current VSENSE 10 μA
PH 6 A
VIN 6 A
Sink Current COMP 100 μA
SS 200
Electrostatic Human body model (HBM) 2 kV
Discharge Charged device model (CDM) 500 V
Operating Junction Temperature, TJ–40 to 150 °C
Storage Temperature, Tstg –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2Copyright © 2008–2012, Texas Instruments Incorporated
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
PACKAGE DISSIPATION RATINGS(1) (2) (3)
THERMAL IMPEDANCE PSEUDO THERMAL IMPEDANCE
PACKAGE JUNCTION TO AMBIENT JUNCTION TO TOP
SOIC8 100°C/W 5°C/W
(1) Maximum power dissipation may be limited by overcurrent protection
(2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
(3) Test board conditions:
(a) 2 inches x 1.5 inches, 2 layers, thickness: 0.062 inch
(b) 2-ounce copper traces located on the top and bottom of the PCB
(c) 6 thermal vias located under the device package
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
Operating Input Voltage on (VIN pin) 3.5 28 V
Operating junction temperature, TJ–40 150 °C
ELECTRICAL CHARACTERISTICS
TJ= –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted)
DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold Rising and Falling 3.5 V
Shutdown supply current EN = 0V, VIN = 12V, –40°C to 85°C 1 4 μA
Operating – non switching supply current VSENSE = 0.85 V 75 110 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising and Falling 1.25 1.35 V
Input current Enable threshold – 50 mV -1 μA
Input current Enable threshold + 50 mV -4 μA
VOLTAGE REFERENCE
Voltage reference 0.772 0.8 0.828 V
HIGH-SIDE MOSFET
BOOT-PH = 3 V, VIN = 3.5 V 115 200
On resistance mΩ
BOOT-PH = 6 V, VIN = 12 V 80 150
ERROR AMPLIFIER
Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 92 μmhos
Error amplifier DC gain(1) VSENSE = 0.8 V 800 V/V
Error amplifier unity gain bandwidth(1) 5 pF capacitance from COMP to GND pins 2.7 MHz
Error amplifier source/sink current V(COMP) = 1 V, 100 mV overdrive ±7 μA
Switch current to COMP transconductance VIN = 12 V 9 A/V
SWITCHING FREQUENCY
TPS54231 Switching Frequency VIN = 12 V 400 570 740 kHz
Minimum controllable on time VIN = 12 V, 25°C 105 130 ns
Maximum controllable duty ratio(1) BOOT-PH = 6 V 90% 93%
PULSE SKIPPING ECO-MODE™
Pulse skipping Eco-mode™ switch current threshold 100 mA
CURRENT LIMIT
Current limit threshold VIN = 12 V 2.3 3.5 5.3 A
(1) Specified by design
Copyright © 2008–2012, Texas Instruments Incorporated 3
1
2
3
45
6
7
8
BOOT
VIN
EN
SS
PH
GND
COMP
VSENSE
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TJ= –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted)
DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
Thermal Shutdown 165 °C
SLOW START (SS PIN)
Charge current V(SS) = 0.4 V 2 μA
SS to VSENSE matching V(SS) = 0.4 V 10 mV
DEVICE INFORMATION
PIN ASSIGNMENTS
PIN FUNCTIONS
PIN DESCRIPTION
NAME NO.
BOOT 1 A 0.1 μF bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor falls below the
minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed.
VIN 2 Input supply voltage, 3.5 V to 28 V.
EN 3 Enable pin. Pull below 1.25 V to disable. Float to enable. Programming the input undervoltage lockout with two
resistors is recommended.
SS 4 Slow start pin. An external capacitor connected to this pin sets the output rise time.
VSENSE 5 Inverting node of the gm error amplifier.
COMP 6 Error amplifier output, and input to the PWM comparator. Connect frequency compensation components to this pin.
GND 7 Ground.
PH 8 The source of the internal high-side power MOSFET.
4Copyright © 2008–2012, Texas Instruments Incorporated
550
555
560
565
570
575
580
585
590
-50 -25 0 25 50 75 100 125 150
fsw-OscillatorFrequency-kHz
T -JunctionTemperature-°C
J
VIN=12V
0
1
2
3
4
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J
T =25°C
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60
65
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
Rdson-OnResistance-mW
VIN=12V
Error
Amplifier
RQ
S
Boot
Charge
Boot
UVLO
Current
Sense
Oscillator
Frequency
Shift
Gate
Drive
Logic
Slope
Compensation
PWM
Latch
PWM
Comparator
ECO-MODE
MinimumClamp
™
Maximum
Clamp
Voltage
Reference
Discharge
Logic
VSENSE
COMP
PH
BOOT
VIN
GND
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
S
1.25V
0.8V
80mW
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2.1V
9 A/V
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VSENSE
1 Am3 Am
gm=92 A/V
DCgain=800V/V
BW=2.7MHz
m
2kW
2 Am
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
FUNCTIONAL BLOCK DIAGRAM
spacer
spacer TYPICAL CHARACTERIZATION CURVES
ON RESISTANCE SHUTDOWN QUIESCENT CURRENT SWITCHING FREQUENCY
vs vs vs
JUNCTION TEMPERATURE INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
Copyright © 2008–2012, Texas Instruments Incorporated 5
1.90
2
2.10
-50 -25 0 25 50 75 100 125 150
I -SlowStartChargeCurrent- A
SS m
T -JunctionTemperature-°C
J
100
110
120
130
140
-50 -25 0 25 50 75 100 125 150
Tonmin-MinimumControllableOnTime-ns
T -JunctionTemperature-°C
J
VIN=12V
5.50
5.75
6
6.25
6.50
6.75
7
7.25
7.50
-50 -25 0 25 50 75 100 125 150
MinimumControllableDutyRatio-%
T -JunctionTemperature-°C
J
VIN=12V
0.7760
0.7820
0.7880
0.7940
0.8000
0.8060
0.8120
0.8180
0.8240
-50 -25 0 25 50 75 100 125 150
Vref-VoltageReference-V
T -JunctionTemperature-°C
J
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
TYPICAL CHARACTERIZATION CURVES (continued)
MINIMUM CONTROLLABLE ON MINIMUM CONTROLLABLE DUTY
VOLTAGE REFERENCE TIME RATIO
vs vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 4. Figure 5. Figure 6.
SS CHARGE CURRENT CURRENT LIMIT THRESHOLD
vs vs
JUNCTION TEMPERATURE INPUT VOLTAGE
Figure 7. Figure 8.
6Copyright © 2008–2012, Texas Instruments Incorporated
3 8 13 18 23 28
0
5
10
15
20
25
30
V -OutputVoltage-V
O
V -InputVoltage-V
I
I =2 A
O
I =1 A
O
3 8 13 18 23 28
V -OutputVoltage-V
O
V -InputVolatage-V
I
0.75
0.85
0.95
1.05
1.15
1.25
I =2 A
O
I =1 A
O
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
SUPPLEMENTAL APPLICATION CURVES
TYPICAL MINIMUM OUTPUT VOLTAGE TYPICAL MAXIMUM OUTPUT VOLTAGE
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 9. Figure 10.
OVERVIEW
The TPS54231 is a 28 V, 2 A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To
improve performance during line and load transients, the device implements a constant frequency, current mode
control which reduces output capacitance and simplifies external frequency compensation design. The
TPS54231 has a pre-set switching frequency of 570 kHz.
The TPS54231 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pull-up
current source that can be used to adjust the input voltage under-voltage lockout (UVLO) with two external
resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to
operate. The operating current is 75 μA typically when not switching and under no load. When the device is
disabled, the supply current is 1 μA typically.
The integrated 80 mΩhigh-side MOSFET allows for high efficiency power supply designs with continuous output
currents up to 2 A.
The TPS54231 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference
voltage.
By adding an external capacitor, the slow start time of the TPS54231 can be adjustable which enables flexible
output filter selection.
To improve the efficiency at light load conditions, the TPS54231 enters a special pulse skipping Eco-modeTM
when the peak inductor current drops below 100 mA typically.
The frequency foldback reduces the switching frequency during startup and over current conditions to help
control the inductor current. The thermal shut down gives the additional protection under fault conditions.
DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54231 uses a fixed frequency, peak current mode control. The internal switching frequency of the
TPS54231 is fixed at 570kHz.
Copyright © 2008–2012, Texas Instruments Incorporated 7
EN
START EN
V
Ren2 = V - V + 1 A
Ren1 m
START STOP
V - V
Ren1 =
3 Am
EN
1.25V
VIN
+
-
Ren1
Ren2
1 Am3 Am
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
ECO-MODETM
The TPS54231 is designed to operate in pulse skipping Eco-modeTM at light load currents to boost light load
efficiency. When the peak inductor current is lower than 100 mA typically, the COMP pin voltage falls to 0.5 V
typically and the device enters Eco-modeTM . When the device is in Eco-modeTM, the COMP pin voltage is
clamped at 0.5 V internally which prevents the high side integrated MOSFET from switching. The peak inductor
current must rise above 100 mA for the COMP pin voltage to rise above 0.5 V and exit Eco-modeTM. Since the
integrated current comparator catches the peak inductor current only, the average load current entering Eco-
modeTM varies with the applications and external output filters.
VOLTAGE REFERENCE (Vref)
The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by
scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8 V.
BOOTSTRAP VOLTAGE (BOOT)
The TPS54231 has an integrated boot regulator and requires a 0.1 μF ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R
grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve
drop out, the TPS54231 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is
greater than 2.1 V typically.
ENABLE AND ADJUSTABLE INPUT UNDER-VOLTAGE LOCKOUT (VIN UVLO)
The EN pin has an internal pull-up current source that provides the default condition of the TPS54231 operating
when the EN pin floats.
The TPS54231 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended
to use an external VIN UVLO to add Hysteresis unless VIN is greater than (VOUT + 2 V). To adjust the VIN UVLO
with Hysteresis, use the external circuitry connected to the EN pin as shown in Figure 11. Once the EN pin
voltage exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate
the resistor values needed for the desired VIN UVLO threshold voltages. The VSTART is the input start threshold
voltage, the VSTOP is the input stop threshold voltage and the VEN is the enable threshold voltage of 1.25 V. The
VSTOP should always be greater than 3.5 V.
Figure 11. Adjustable Input Undervoltage Lockout
(1)
(2)
8Copyright © 2008–2012, Texas Instruments Incorporated
( ) ( ) ( )
( )
SS ref
SS
SS
C nF V V
T ms =
I A
´
m
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
PROGRAMMABLE SLOW START USING SS PIN
It is highly recommended to program the slow start time externally because no slow start time is implemented
internally. The TPS54231 effectively uses the lower voltage of the internal voltage reference or the SS pin
voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output
accordingly. A capacitor (CSS) on the SS pin to ground implements a slow start time. The TPS54231 has an
internal pull-up current source of 2 μA that charges the external slow start capacitor. The equation for the slow
start time (10% to 90%) is shown in Equation 3 . The Vref is 0.8V and the ISS current is 2 μA.
(3)
The slow start time should be set between 1ms to 10ms to ensure good start-up behavior. The slow start
capacitor should be no more than 27 nF.
If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below
1.25 V, or a thermal shutdown event occurs, the TPS54231 stops switching.
ERROR AMPLIFIER
The TPS54231 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The
transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation
components are connected between the COMP pin and ground.
SLOPE COMPENSATION
In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the
TPS54231 adds a built-in slope compensation which is a compensating ramp to the switch current signal.
CURRENT MODE COMPENSATION DESIGN
To simplify design efforts using the TPS54231, the typical designs for common applications are listed in Table 1.
For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended
when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the
nominal value when the applied voltage increases. Advanced users may refer to the Step by Step Design
Procedure in the Application Information section for the detailed guidelines or use SwitcherPro™ Software tool
(http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html).
Table 1. Typical Designs (Referring to Simplified Schematic on page 1)
VIN VOUT Fsw LoCoRO1 RO2 C2C1R3
(V) (V) (kHz) (μH) (kΩ) (kΩ) (pF) (pF) (kΩ)
12 5 570 15 Ceramic 33 μF 10 1.91 47 1800 21
12 3.3 570 10 Ceramic 47μF 10 3.24 47 4700 21
12 1.8 570 6.8 Ceramic 100 μF 10 8.06 47 4700 21
12 0.9 570 4.7 Ceramic 100 μFx2 10 80.6 47 4700 21
12 5 570 15 Aluminum 330 μF/160 mΩ10 1.91 47 220 40.2
12 3.3 570 10 Aluminum 470 μF/160 mΩ10 3.24 47 220 21
12 1.8 570 6.8 SP 100 μF/15 mΩ10 8.06 47 4700 40.2
12 0.9 570 4.7 SP 220 μF/12 mΩ10 80.6 47 4700 40.2
OVERCURRENT PROTECTION AND FREQUENCY SHIFT
The TPS54231 implements current mode control that uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared;
when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output
current.
Copyright © 2008–2012, Texas Instruments Incorporated 9
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
The TPS54231 provides robust protection during short circuits. There is potential for overcurrent runaway in the
output inductor during a short circuit at the output. The TPS54231 solves this issue by increasing the off time
during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2,
and 1 as the voltage ramps from 0 V to 0.8 V on VSENSE pin. The relationship between the switching frequency
and the VSENSE pin voltage is shown in Table 2.
Table 2. Switching Frequency Conditions
SWITCHING FREQUENCY VSENSE PIN VOLTAGE
570 kHz VSENSE ≥0.6 V
570 kHz / 2 0.6 V > VSENSE ≥0.4 V
570 kHz / 4 0.4 V > VSENSE ≥0.2 V
570 kHz / 8 0.2 V > VSENSE
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54231 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an
overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin
voltage goes above 109% × Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls
below 107% × Vref, the high-side MOSFET will be enabled again.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 165°C, the device reinitiates the power up sequence.
10 Copyright © 2008–2012, Texas Instruments Incorporated
C1
4.7 Fm
C2
4.7 Fm
C3
0.01 Fm
R1
332kW
R2
68.1kW
C5
0.015 Fm
C4
0.1 Fm
C7
47pF
R3
29.4kW
C6
1000pF
C8
47 Fm
C9
47 FmR5
10.2kW
R6
3.24kW
L1
10 Hm
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
APPLICATION INFORMATION
Figure 12. Typical Application Schematic
STEP BY STEP DESIGN PROCEDURE
The following design procedure can be used to select component values for the TPS54231. Alternately, the
SwitcherPro™Software may be used to generate a complete design. The SwitcherPro™ Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
For this design example, use the following as the input parameters
Table 3. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 7 V to 28 V
Output voltage 3.3 V
Input ripple voltage 300 mV
Output ripple voltage 30 mV
Output current rating 2 A
Operating Frequency 570 kHz
SWITCHING FREQUENCY
The switching frequency for the TPS54231 is fixed at 570 kHz.
Copyright © 2008–2012, Texas Instruments Incorporated 11
2
OUT(MAX)
CIN
I
I =
( )
OUT(MAX)
IN OUT(MAX) MAX
BULK SW
I 0.25
V = + I ESR
Cf
´
D ´
´
OUT REF
R5
V = V +1
R6
é ù
´ê ú
ë û
REF
OUT REF
R5 V
R6 =
V V
´
-
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
OUTPUT VOLTAGE SET POINT
The output voltage of the TPS54231 is externally adjustable using a resistor divider network. In the application
circuit of Figure 12, this divider network is comprised of R5 and R6. The relationship of the output voltage to the
resistor divider is given by Equation 4 and Equation 5:
(4)
(5)
Choose R5 to be approximately 10 kΩ. Slightly increasing or decreasing R5 can result in closer output voltage
matching when using standard value resistors. In this design, R4 = 10.2 kΩand R = 3.24 kΩ, resulting in a 3.31
V output voltage. The zero ohm resistor R4 is provided as a convenient place to break the control loop for
stability testing.
INPUT CAPACITORS
The TPS54231 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.
The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be
used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of
circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54231 circuit is not located
within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated
to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple
voltage is acceptable. For this design two 4.7 μF capacitors are used for the input decoupling capacitor. They are
X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ, and the current
rating is 3 A. Additionally, a small 0.01 μF capacitor is included for high frequency filtering.
This input ripple voltage can be approximated by Equation 6
(6)
Where IOUT(MAX) is the maximum load current, fSW is the switching frequency, CBULK is the bulk capacitor value
and ESRMAX is the maximum series resistance of the bulk capacitor.
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 7
(7)
In this case, the input ripple voltage would be 113 mV and the RMS ripple current would be 1 A. It is also
important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the
layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in
Design Parameters and is larger than the calculated value. This measured value is still below the specified input
limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus ΔVIN/2. The chosen
bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both
providing ample margin. It is important that the maximum ratings for voltage and current are not exceeded under
any circumstance.
OUTPUT FILTER COMPONENTS
Two components need to be selected for the output filter, L1 and C2. Since the TPS54231 is an externally
compensated device, a wide range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 8
12 Copyright © 2008–2012, Texas Instruments Incorporated
ú
û
ù
ê
ë
é+
´´
-
=E S R
OSW
L P PO P P R
CF
D
IV
4
)5.0(
)2/(1 max_min_ COOO FRC ´´´= p
LPP
L(PK) OUT(MAX)
I
I = I + 2
2 2
OUT(MAX) LPP
L(RMS)
1
I = I + × I
12
( )
( )
OUT IN(MAX) - OUT
LPP IN MAX OUT SW
V × V V
I = V × L F 0.8´ ´
( )
OUT(MAX) IN(MAX) OUT
MIN
IN(MAX) IND OUT SW
V V V
L = V K I F
´ -
´ ´ ´
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
(8)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
This value is at the discretion of the designer; however, the following guidelines may be used. For designs using
low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher
ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 8.5 μH. For this
design, a large value was chosen: 10 μH.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The peak-to-peak inductor current is calculated using Equation 9
(9)
The RMS inductor current can be found from Equation 10
(10)
and the peak inductor current can be determined with Equation 11
(11)
For this design, the RMS inductor current is 2.008 A and the peak inductor current is 2.32 A. The chosen
inductor is a Coilcraft MSS1038-103NL 10 μH. It has a saturation current rating of 3.04 A and an RMS current
rating of 2.90 A, meeting these requirements. Smaller or larger inductor values can be used depending on the
amount of ripple current the designer wishes to allow so long as the other design requirements are met. Larger
value inductors will have lower ac current and result in lower output voltage ripple, while smaller inductor values
will increase ac current and output voltage ripple. In general, inductor values for use with the TPS54231 are in
the range of 6.8 μH to 47μH.
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor current it determines the amount of output ripple voltage. The actual value of the
output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired
closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is
desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With high
switching frequencies such as the 570-kHz frequency of this design, internal circuit limitations of the TPS54231
limit the practical maximum crossover frequency to about 25 kHz. In general, the closed loop crossover
frequency should be higher than the corner frequency determined by the load impedance and the output
capacitor. This limits the minimum capacitor value for the output filter to:
(12)
Where ROis the output load impedance (VO/IO) and fCO is the desired crossover frequency. For a desired
maximum crossover of 25 kHz the minimum value for the output capacitor is around 3.6μF. This may not satisfy
the output ripple voltage requirement. The output ripple voltage can be estimated by Equation 13:
(13)
Where:
D = Duty cycle (VOUT/VIN)
CO= Output Capacitance
Copyright © 2008–2012, Texas Instruments Incorporated 13
( )
SENSE CO O
Gain = 20 log 2 R F C + 3- ´ ´ ´ ´p
( )
P1 Z P
F = 1/ 2 R Cp´ ´ ´
( )
Z1 Z Z
F = 1/ 2 R Cp´ ´ ´
( )
PO OA Z
F = 1/ 2 R Cp´ ´ ´
ggm REF
DC
O
V V
G = V
´
( ) LPP
OUT RMS
1
I = × I
12
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
RESR = Equivalent series resistance of the output capacitors
The peak-to-peak output voltage ripple consists of two terms. The first term is due to the ac ripple current (ILPP)
charging and discharging the output capacitance in each switching cycle and the second term is due to the ac
ripple current in the ESR of the output capacitor. These two terms maybe out of phase and may add or subtract
depending on the duty cycle. The required capacitance and ESR of the output filter capacitor must be chosen to
meet the allowable output ripple voltage requirement as specified in the initial design parameters.
The maximum RMS ripple current in the output capacitor is given by Equation 14
(14)
For this design example, two 47-μF ceramic output capacitors are chosen for C8 and C9. These are TDK
C3216X5R0J476M, rated at 6.3 V with a maximum ESR of 2 mΩand a ripple current rating in excess of 3 A. The
calculated total RMS ripple current is 184 mA ( 92 mA each) and the maximum total ESR required is 56 mΩ.
These output capacitors exceed the requirements by a wide margin and will result in a reliable, high-performance
design. it is important to note that the actual capacitance in circuit may be less than the catalog value when the
output is operating at the desired output of 3.3 V The selected output capacitor must be rated for a voltage
greater than the desired output voltage plus ½ the ripple voltage. Any derating amount must also be included.
Other capacitor types work well with the TPS54231, depending on the needs of the application.
COMPENSATION COMPONENTS
The external compensation used with the TPS54231 allows for a wide range of output filter configurations. A
large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R
dielectric output capacitors, but other types are supported.
A Type II compensation scheme is recommended for the TPS54231. The compensation components are chosen
to set the desired closed loop cross over frequency and phase margin for output filter components. The type II
compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency
zero / pole pair. The required compensation components are a resistor RZ) in series with a capacitor RZ) from
COMP to ground and a capacitor CP) in parallel with RZand CZfrom COMP to ground.
The dc gain is approximated by Equation 15:
(15)
Where:
Vggm = 800
VREF = 0.8 V
The low-frequency pole is determined by Equation 16:
(16)
The mid-frequency zero is determined by Equation 17:
(17)
And, the mid-frequency pole is given by Equation 18:
(18)
The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency
should be less than 1/8 of the minimum operating frequency, but for the TPS54231it is recommended that the
maximum closed loop crossover frequency be not greater than 25 kHz. Next, the required gain and phase boost
of the crossover network needs to be calculated. By definition, the gain of the compensation network must be the
inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much
higher than the closed loop crossover frequency, the gain of the modulator and output filter can be approximated
by Equation 19:
(19)
14 Copyright © 2008–2012, Texas Instruments Incorporated
zP
PRF
C
´´´
=
1
2
1
p
zZ
ZRF
C
´´´
=
1
2
1
p
CO O O OA
Z
COMP ggm REF
2 × × F × V × C × R × 0.91
R = GM × V × V
p
kFF COP ´=
1
k
F
FCO
Z=
1
÷
ø
ö
ç
è
æ+= deg45
2
tan PB
k
( )
90 degPB = PM + PL-
( ) ( ) 10
CO ESR O CO O O
PL = tan 2 F R C tan 2 F R C´ ´ ´ ´ - ´ ´ ´ ´ -a ap p
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
Where:
RSENSE = 1Ω/9
FCO = Closed-loop crossover frequency
CO= Output capacitance
The phase loss is given by Equation 20:
(20)
Where:
RESR = Equivalent series resistance of the output capacitor
RO= VO/IO
Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement
can be determined. The required phase boost is given by Equation 21:
(21)
Where PM = the desired phase margin and PL = the phase loss calculated in Equation 20.
A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop
frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined
by Equation 22 and the resultant zero and pole frequencies are given by Equation 23 and Equation 24
(22)
(23)
(24)
The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the
modulator and output filter. Due to the relationships of the pole and zero frequencies, the value of RZcan be
derived directly by Equation 25 :
(25)
Where:
VO= Output voltage
CO= Output capacitance
FCO = Desired crossover frequency
ROA = 8.696 MΩ
GMCOMP = 9 A/V
Vggm = 800
VREF = 0.8 V
With RZknown, CZand CPcan be calculated using Equation 26 and Equation 27:
(26)
(27)
Copyright © 2008–2012, Texas Instruments Incorporated 15
1
Cp = = 50 pF
2 107800 29400p´ ´ ´
1
Cz = = 934 pF
2 5798 29400p´ ´ ´
-6 6
3
2 25000 3.3 41 10 8.696 10 × 0.91
Rz = = 29.2 × 10
9 800 0.8
p´ ´ ´ ´ ´ ´ ´ W
´ ´
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance
is less than the rated value when the capacitors have a dc bias voltage applied. This is the case in a dc/dc
converter. The actual output capacitance may be as low as 41 μF. The combined ESR is approximately 0.002 Ω.
The desired cross over frequency is 25 kHz.
Using Equation 19 and Equation 20, the output stage gain and phase loss are equivalent as:
Gain = 5.9 dB
and
PL = –93.8 degrees
For 60 degrees of phase margin, Equation 21 requires 63.9 degrees of phase boost.
Equation 22,Equation 23, and Equation 24 are used to find the zero and pole frequencies of:
FZ1 = 5798 Hz
And
FP1 = 107.8 kHz
RZ, is calculated using Equation 25:
(28)
With Rz set to the standard value of 29.4 kΩ, the values of Czand CPcan be calculated using Equation 26 and
Equation 27.
(29)
(30)
Using standard values for R3, C6, and C7 in the application schematic of Figure 12:
R3 = 29.4 kΩ
C6 = 1000 pF
C7 = 47 pF
The measured overall loop response for the circuit is given in Figure 19. Note that the actual closed loop
crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual
values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall
the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of
line and load variability.
BOOTSTRAP CAPACITOR
Every TPS54231 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The
bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a high-
quality ceramic type with X7R or X5R grade dielectric for temperature stability.
CATCH DIODE
The TPS54231 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak
to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note that
the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B240A is chosen, with a reverse voltage
of 40 V, forward current of 2 A, and a forward voltage drop of 0.5 V.
16 Copyright © 2008–2012, Texas Instruments Incorporated
( )
( ) ( )
Omin IN max Omin DS(on)min D O min L D
V = 0.096 × V I × R + V I × R V- - -
( )
( ) ( )
Omax IN min O max DS(on) max D O max L D
V = 0.91 × V I × R + V I × R V- - -
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
OUTPUT VOLTAGE LIMITATIONS
Due to the internal design of the TPS54231, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91%
and is given by Equation 31:
(31)
Where:
VIN min = Minimum input voltage
IO max = Maximum load current
VD= Catch diode forward voltage
RL= Output inductor series resistance
The equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 130 ns at 25°C
junction temperature. The approximate minimum output voltage for a given input voltage and minimum load
current is given by Equation 32:
(32)
Where:
VIN max = Maximum input voltage
IO min = Minimum load current
VD= Catch diode forward voltage
RL= Output inductor series resistance
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to assure proper functionality.
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or
pulse skipping Eco-modeTM.
The device power dissipation includes:
1) Conduction loss: Pcon = Iout2x RDS(on) x VOUT/VIN
2) Switching loss: Psw = 0.5 x 10-9 x VIN2x IOUT x Fsw
3) Gate charge loss: Pgc = 22.8 x 10-9 x Fsw
4) Quiescent current loss: Pq = 0.075 x 10-3 x VIN
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
Fsw is the switching frequency (Hz).
So
Ptot = Pcon + Psw + Pgc + Pq
For given TA, TJ= TA+ Rth x Ptot.
For given TJMAX = 150°C, TAMAX = TJMAX– Rth x Ptot.
Copyright © 2008–2012, Texas Instruments Incorporated 17
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
Where:
Ptot is the total device power dissipation (W).
TAis the ambient temperature (°C).
TJis the junction temperature (°C) .
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
PCB LAYOUT
The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. The typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the
optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 13 for
a PCB layout example. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source
of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the
ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be
routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching
node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB
conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side
ground area must provide adequate heat dissipating area. The TPS54231 uses a fused lead frame so that the
GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of
internal or back side ground plane available, and the top side ground area can be connected to these areas
using multiple vias under or adjacent to the device to help dissipate heat. The additional external components
can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate
layout schemes, however this layout has been shown to produce good results and is intended as a guideline.
18 Copyright © 2008–2012, Texas Instruments Incorporated
BOOT
VSENSE
PH
VIN GND
EN
Vout
PH
Vin
TOPSIDE
GROUND
AREA
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
CATCH
DIODE
SignalVIA
RouteBOOT CAPACITOR
traceonotherlayertoprovide
widepathfortopsideground
RESISTOR
DIVIDER
Feedback Trace
COMP
SS
COMPENSATION
NETWORK
ThermalVIA
SLOWSTART
CAPACITOR
UVLO
RESISTOR
DIVIDER
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
Figure 13. TPS54231 Board Layout
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 12is 0.68 in2. This area
does not include test points or connectors.
ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS
As EMI becomes a rising concern in more and more applications, the internal design of the TPS54231 takes
measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the Step by Step Design Procedure above to prevent potential EMI issues.
APPLICATION CURVES
Copyright © 2008–2012, Texas Instruments Incorporated 19
-30
-20
-10
0
10
20
30
40
50
60
10 100 1k 10k 100k 1M
f-Frequency-Hz
Gain-dB
-90
-40
10
60
110
160
Phase-deg.
Gain
Phase
Vout
LoadCurrent
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
I -OutputCurrent- A
O
V =15V
IN V =24V
IN
V =28V
IN
V =7V
IN
OutputRegulation-%
-0.1
-0.05
0
0.05
0.1
0.15
510 15 20 25 30
V -InputVoltage-V
I
OutputRegulation-%
I =0 A
O
I =1 A
O
I =2 A
O
0
10
20
30
40
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
I -OutputCurrent- A
O
Efficiency-%
V =15V
IN
V =24V
IN
V =28V
IN
V =7V
IN
0
10
20
30
40
50
60
70
80
90
100
Efficiency-%
0 0.02
I -OutputCurrent- A
O
0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
V =15V
IN
V =24V
IN
V =28V
IN
V =7V
IN
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
Figure 14. TPS54231 Efficiency Figure 15. TPS54231 Low Current Efficiency
Figure 16. TPS54231 Load Regulation Figure 17. TPS54231 Line Regulation
Figure 18. TPS54231 Transient Response Figure 19. TPS54231 Loop Response
20 Copyright © 2008–2012, Texas Instruments Incorporated
Vout
PH
Vin
Vout
Vout
PI
Vin
PI
TPS54231
www.ti.com
SLUS851C –OCTOBER 2008–REVISED JULY 2012
Figure 20. TPS54231 Output Ripple Figure 21. TPS54231 Input Ripple
Figure 22. TPS54231 Start Up Figure 23. TPS54231 Start-up Relative to Enable
Figure 24. Eco-mode™
Copyright © 2008–2012, Texas Instruments Incorporated 21
TPS54231
SLUS851C –OCTOBER 2008–REVISED JULY 2012
www.ti.com
REVISION HISTORY
NOTE: Page numbers and equation reference numbers of current version may differ from previous versions.
Changes from Original (October 2008) to Revision A Page
• Added a new table to the Description - For additional design needs ................................................................................... 2
• Changed the ABSOLUTE MAXIMUM RATINGS table, Input Voltage - EN pin max value From: 5V to 6V ........................ 2
• Changed Equation 9 for calculating ILPP ............................................................................................................................. 13
• Added new Equation 10 for calculating IL(RMS) .................................................................................................................... 13
• Changed Equation 11 for calculating IL(PK) .......................................................................................................................... 13
• Added peak-to-peak output voltage ripple descriptive text following Equation 13 ............................................................. 13
• Changed Equation 14 for calculating IOUT(RMS) .................................................................................................................... 14
• Changed Equation 16 for calculating FPO ........................................................................................................................... 14
• Changed Equation 25 for calculating RZ............................................................................................................................. 15
• Changed Equation 28 for calculating RZ............................................................................................................................. 16
• Changed Equation 29 and Equation 30 for calculating CZand CP, respectively. ............................................................... 16
Changes from Revision A (March 2010) to Revision B Page
• Removed SWIFT™ from the data sheet title ........................................................................................................................ 1
• Deleted Features Item: For SWIFT™ Documentation, See the TI Website at http://www.ti.com/swift ................................ 1
Changes from Revision B (February 2012) to Revision C Page
• Added 5.3 to the MAX column of the ELEC CHAR table, section CURRENT LIMIT ........................................................... 3
• Deleted Maximum Power Dissipation versus Junction Temperature graph ......................................................................... 7
22 Copyright © 2008–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS54231D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS54231DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS54231DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS54231DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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