NB10594001 - TE CONNECTIVITY

To our custo mers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corpor ation took over all the business of both

companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid

Renesas Electronics document. W e appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please

confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to

additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights

of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights

of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by

you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control

laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas

Electronics products or the technology described in this document for any purpose relating to military applications or use by

the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and

technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Ren esas E lectronics assumes no liability whatsoever for any da mages

incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified acco rding to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as

indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular

application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior

written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for

which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way

liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an

application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written

consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise

expressly specified in a Renesas Electronics data sheets or data books, et c.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electro nic app liances; machine tool s; p ersonal electron ic equipment; and indu strial robots .

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equ i pment; submersible repeaters; nu clear reactor control systems; medical equipment or

systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare

interven tion (e.g. excision, et c.), and any oth er applications or purposes that pose a direct th reat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,

Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a

Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire

control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because

the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system

manufactured by you.

10. Please contact a Renesas Electronics sales office for det ai ls as to enviro nmental matters such as the en vi ronmental

compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable

laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS

Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with

applicable laws and regulations.

11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this

document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

Rev.3.02 Apr 10, 2008 Page 1 of 131

REJ03B0177-0302

DESCRIPTION

The 38D2 Group is the 8-bit microcomputer based on the 740

Family core technology.

The 38D2 Group is pin-compatible with the 38C2 Group.

The 38D2 Group has an LCD drive control circuit, an A/D

converter, a serial interface, and a ROM correction function and

on-chip oscillator as additional functions.

The QzROM version and the flash memory version are available.

The flash memory version does not have a selection function for

the oscillation start mode. Only the on-chip oscillator starts

oscillating.

The various microcomputers include variations of memory size,

and packaging. For details, refer to the section on part

numbering.

FEATURES

• Basic machine-language instructions ................................. 71

• The minimum instruction execution time ................... 0.32 μs

(at 12.5 MHz oscillation frequency)

• Memory size (QzROM version)

ROM ........................................................ 16 K to 60 K bytes

RAM ........................................................... 640 to 2048 bytes

• Memory size (Flash memory version)

ROM ...................................................................... 60 K bytes

RAM ...................................................................... 2048 bytes

• Programmable input/output ports .. 51 (common to SEG: 24)

• Interrupts ............................................. 18 sources, 16 vectors

• Timers ..................................................... 8-bit × 4, 16-bit × 2

• Serial interface .......8-bit × 2 (UART or Clock-synchronized)

• PWM .......... 10-bit × 2, 16-bit × 1 (common to IGBT output)

• A/D converter .......................................... 10-bit × 8 channels

(A/D converter can be operated in low-speed mode.)

• Watchdog timer ......................................................... 8-bit × 1

• ROM correction function ....................... 32 bytes × 2 vectors

• LED direct drive port ............................................................ 8

(average current: 15 mA, peak current: 30 mA, total current: 90 mA)

• LCD drive control circuit

Bias ............................................................................ 1/2, 1/3

Duty .............................................................................. 2, 3, 4

Common output .................................................................... 4

Segment output ................................................................... 24

• Main clock generating circuit ............................................... 1

(connect to external ceramic resonator or on-chip oscillator)

• Sub-clock generating circuit ..................................................1

(connect to external quartz-crystal oscillator)

• Power source voltage (QzROM version)

[In frequency/2 mode]

f(XIN) ≤ 12.5 MHz.............................................. 4.5 to 5.5 V

f(XIN) ≤ 8 MHz................................................... 4.0 to 5.5 V

f(XIN) ≤ 4 MHz................................................... 2.0 to 5.5 V

f(XIN) ≤ 2 MHz................................................... 1.8 to 5.5 V

[In frequency/4 mode]

f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V

f(XIN) ≤ 8 MHz................................................... 2.0 to 5.5 V

f(XIN) ≤ 4 MHz................................................... 1.8 to 5.5 V

[In frequency/8 mode]

f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V

f(XIN) ≤ 8 MHz................................................... 2.0 to 5.5 V

f(XIN) ≤ 4 MHz................................................... 1.8 to 5.5 V

[In low-speed mode].............................................. 1.8 to 5.5 V

Note. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the fre-

quency/2 mode.

• Power source voltage (Flash memory version)

[In frequency/2 mode]

f(XIN) ≤ 12.5 MHz.............................................. 4.5 to 5.5 V

f(XIN) ≤ 8 MHz................................................... 4.0 to 5.5 V

f(XIN) ≤ 4 MHz................................................... 2.7 to 5.5 V

[In frequency/4 mode]

f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V

f(XIN) ≤ 8 MHz................................................... 2.7 to 5.5 V

[In frequency/8 mode]

f(XIN) ≤ 16 MHz................................................. 4.5 to 5.5 V

f(XIN) ≤ 8 MHz................................................... 2.7 to 5.5 V

[In low-speed mode].............................................. 2.7 to 5.5 V

Note. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the fre-

quency/2 mode.

• Power dissipation (QzROM version)

• In frequency/2 mode ..................................... Typ. 32 mW

(VCC = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)

• In low-speed mode ........................................ Typ. 18 μW

(VCC = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)

• Power dissipation (Flash memory version)

• In frequency/2 mode ..................................... Typ. 20 mW

(VCC = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)

• In low-speed mode ...................................... Typ. 1.1 mW

(VCC = 2.7 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)

• Operating temperature range ............................... −20 to 85°C

Flash Memory Mode

• Program/Erase voltage ............................. VCC = 2.7 to 5.5 V

• Program method ....................... Programming in unit of byte

• Erase method .................................................... Block erasing

• Program/Erase control by software command

APPLICATION

Household products, Consumer electronics, etc.

38D2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0177-0302

Rev.3.02

Apr 10, 2008

Rev.3.02 Apr 10, 2008 Page 2 of 131

REJ03B0177-0302

38D2 Group

Fig. 1 Pin configuration (LQFP Package)

Package type : PLQP0064GA-A(64P6U-A)/PLQP0064KB-A(64P6Q-A)

P06/SEG6

P07/SEG7

P10/SEG8

P11/SEG9

P12/SEG10

P13/SEG11

P14/SEG12

P15/SEG13

P16/SEG14

P17/SEG15

6 7 8 9 10111213141516

45 44 43 42 41 40 39 38 37 36 35 34 33

P24/SEG20

P25/SEG21

COM2

COM1

COM0

P27/SEG23/VL2

P26/SEG22/VL1

COM3

P03/SEG3/(KW7)

/SEG

P05/SEG5

P51/INT1

P56/SCLK1/(KW2)

P55/TXD1/(KW1)

P54/RXD1/(KW0)

P53/T4OUT/PWM1

P20/SEG16

P21/SEG17

P22/SEG18

P23/SEG19

48 47 46

12345

M38D2XGXFP/HP

M38D29FFFP/HP

P36/T2OUT/CKOUT/(LED6)

P52/T3OUT/PWM0

VREF

VL3

P47/RTP1/AN7

P46/RTP0/AN6

P32/TXD2/(LED2)

P31/SCLK2/(LED1)

P33/RXD2/(LED3)

P50/INT0

AVSS

P02/SEG2/(KW6)

P01/SEG1/(KW5)

P00/SEG0/(KW4)

P57/SRDY1/(KW3)

P35/TXOUT1/(LED5)

P34/INT2/(LED4)

P30/SRDY2/(LED0)

P60/CNTR1

P37/CNTR0/TXOUT2/(LED7)

XOUT

P43/AN3

P42/ADKEY/AN2

P44/AN4

P45/AN5

VSS

P41/OOUT1/AN1

P40/OOUT0/AN0

OSCSEL (Note 1)

P62/XCOUT

P61/XCIN

VCC

XIN

RESET

PIN CONFIGURATION

(TOP VIEW)

Note 1:CNVSS in flash

memory version

Rev.3.02 Apr 10, 2008 Page 3 of 131

REJ03B0177-0302

38D2 Group

NOTE:

1. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

Table 1 Performance overview

Parameter Function

Number of basic instructions 71

Instruction execution time 0.32 μs (Minimum instruction, Oscillation frequency 12.5 MHz)

Oscillation frequency 16 MHz (Maximum)(1)

Memory sizes

(QzROM version)

ROM 16 K to 60 K bytes

RAM 640 to 2048 bytes

Memory sizes

(Flash memory version)

ROM 60 K bytes

RAM 2048 bytes

I/O port P0-P5, P60-P628-bit × 6, 3-bit × 1 (24 pins sharing SEG)

Interrupt 18 sources, 16 vectors (includes key input interrupt)

Timer 8-bit × 4, 16-bit × 2

Serial Interface 8-bit × 2 (UART or Clock-synchronized)

PWM 10-bit × 2, 16-bit × 1 (common to IGBT output)

A/D converter 10-bit × 8 (operated in low-speed mode)

Watchdog timer 8-bit × 1

ROM correction function 32 bytes × 2 vectors

LED direct drive port

8 (average current: 15 mA, peak current: 30 mA, total current: 90 mA)

LCD drive control

circuit

Bias 1/2, 1/3

Duty 2, 3, 4

Common output 4

Segment output 24

Main clock generating circuits Built-in (connect to external ceramic resonator or on-chip oscillator)

Sub-clock generating circuits Built-in (connect to external quartz-crystal oscillator)

Power source voltage

(QzROM version)

In frequency/2 mode

(1)

f(XIN) ≤ 12.5 MHz 4.5 to 5.5 V

f(XIN) ≤ 8 MHz 4.0 to 5.5 V

f(XIN) ≤ 4 MHz 2.0 to 5.5 V

f(XIN) ≤ 2 MHz 1.8 to 5.5 V

In frequency/4 mode f(XIN) ≤ 16 MHz 4.5 to 5.5 V

f(XIN) ≤ 8 MHz 2.0 to 5.5 V

f(XIN) ≤ 4 MHz 1.8 to 5.5 V

In frequency/8 mode f(XIN) ≤ 16 MHz 4.5 to 5.5 V

f(XIN) ≤ 8 MHz 2.0 to 5.5 V

f(XIN) ≤ 4 MHz 1.8 to 5.5 V

In low-speed mode 1.8 to 5.5 V

Power source voltage

(Flash memory version)

In frequency/2 mode

(1)

f(XIN) ≤ 12.5 MHz 4.5 to 5.5 V

f(XIN) ≤ 8 MHz 4.0 to 5.5 V

f(XIN) ≤ 4 MHz 2.7 to 5.5 V

In frequency/4 mode f(XIN) ≤ 16 MHz 4.5 to 5.5 V

f(XIN) ≤ 8 MHz 2.7 to 5.5 V

In frequency/8 mode f(XIN) ≤ 16 MHz 4.5 to 5.5 V

f(XIN) ≤ 8 MHz 2.7 to 5.5 V

In low-speed mode 2.7 to 5.5 V

Power dissipation

(QzROM version)

In frequency/2 mode Std. 32 mW (Vcc = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)

In low-speed mode Std. 18 μW (Vcc = 2.5 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)

Power dissipation

(Flash memory version)

In frequency/2 mode Std. 20 mW (Vcc = 5 V, f(XIN) = 12.5 MHz, Ta = 25°C)

In low-speed mode Std. 1.1 mW (Vcc = 2.7 V, f(XIN) = stop, f(XCIN) = 32 kHz, Ta = 25°C)

Input/Output

characteristics

Input/Output withstand voltage VCC

Output current 10 mA

Operating temperature range -20 to 85°C

Device structure CMOS silicon gate

Package 64-pin plastic molded LQFP

Rev.3.02 Apr 10, 2008 Page 4 of 131

REJ03B0177-0302

38D2 Group

Fig. 2 Functional block diagram

Timer

Port P0 (8)

Port P1 (8)

Port P2 (8)

Internal peripheral function

A/D converter

10-bits × 8-channels

Serial I/O

Serial I/O1

(UART or Clock synchronous)

Serial I/O2

(UART or Clock synchronous)

LCD drive control circuit

4 COM × 24 SEG

Timer X (16 bits)

PWM (16 bits)

IGBT output

Timer Y (16 bits)

Timer 1 (8 bits)

Timer 2 (8 bits)

Timer 3 (8 bits)

PWM0 (10 bits)

Timer 4 (8 bits)

PWM1 (10 bits)

System clock φ generation

XIN–XOUT

(Main clock)

XCIN–XCOUT

(Sub-clock)

Memory

ROM

RAM for LCD display

(12 bytes)

RAM

CPU core

Port P4 (8)Port P5 (8)Port P6 (3)

Port P3 (8)

Watchdog timer

On-chip

oscillator

ROM correction

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

FUNCTIONAL BLOCK DIAGRAM

Rev.3.02 Apr 10, 2008 Page 5 of 131

REJ03B0177-0302

38D2 Group

PIN DESCRIPTION

Table 2 Pin description (1)

Pin Name Function Function except a port function

VCC, VSS Power source • Apply 1.8 to 5.5 V to VCC, and 0 V to VSS.

RESET Reset input • Reset input pin for active “L”.

XIN Clock input • Input and output pins for the main clock generating circuit.

• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to

set the oscillation frequency. When an external clock is used, connect the clock source to

XIN, and leave XOUT pin open.

• Feedback resistor is built in between XIN pin and XOUT pin.

XOUT Clock output

VL3 LCD power

source

• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage.

• Input 0 − VL3 voltage to LCD.

COM0−

COM3

Common output • LCD common output pins.

•COM

2 and COM3 are not used at 1/2 duty ratio.

•COM

3 is not used at 1/3 duty ratio.

P00/SEG0/(KW4)−

P03/SEG3/(KW7)

I/O port P0 • 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in a bit unit.

• LCD segment

output pins

• Key input interrupt

input pins

P04/SEG4−

P07/SEG7

P10/SEG8−

P17/SEG15

I/O port P1 • 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in a bit unit.

P20/SEG16−

P25/SEG21

I/O port P2 • 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in a bit unit.

P26/SEG22/VL1

P27/SEG23/VL2

• LCD power source

pins

P30/SRDY2/(LED0)

P31/SCLK2/(LED1)

P32/TxD2/(LED2)

P33/RxD2/(LED3)

I/O port P3 • 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in 4-bit unit.

• Serial I/O2 function pins

P34/INT2/(LED4)• External interrupt pin

P35/TXOUT1/(LED5)

P36/T2OUT/CKOUT/

(LED6)

• Timer X, Timer 2 output pins

P37/CNTR0/TXOUT2/

(LED7)

• Timer X function pin

P40/OOUT0/AN0

P41/OOUT1/AN1

I/O port P4 • 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in 4-bit unit.

• A/D convertor

input pins

• Oscillation

external output

pins

P42/AN2/ADKEY •ADKEY

P43/AN3−P45/AN5

P46/RTP0/AN6

P47/RTP1/AN7

• Real time port

function pins

P50/INT0

P51/INT1

I/O port P5 • 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in 4-bit unit

• External input pins

P52/T3OUT/PWM0

P53/T4OUT/PWM1

• Timer 3, Timer 4 output pins

• PWM output pins

P54/RxD1/(KW0)

P55/TxD1/(KW1)

P56/SCLK1/(KW2)

P57/SRDY1/(KW3)

• Serial I/O1 function pins

• Key input interrupt input pins

Rev.3.02 Apr 10, 2008 Page 6 of 131

REJ03B0177-0302

38D2 Group

Table 3 Pin description (2)

Pin Name Function Function except a port function

P60/CNTR1I/O port P6 • .3-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be

individually programmed as either input or output.

• Pull-up control is enabled in 3-bit unit

• Timer Y function pins

P61/XCIN

P62/XCOUT

• Sub clock generating circuit I/O pins

(oscillator connected)

OSCSEL

(Only QzROM

version)

Oscillation start

selection pin

• Whether oscillation starts by an oscillator between the XIN and XOUT pins or an on-chip

oscillator is selected.

•V

PP power source input pin in the QzROM writing mode.

CNVSS

(Only flash memory

version)

CNVSS • Pin for controlling the operating mode of the chip. Connect to VSS.

VREF Analog reference

voltage

• Reference voltage input pin for A/D converter.

AVSS Analog power

source

• Analog power source input pin for A/D converter. Connect to VSS.

Rev.3.02 Apr 10, 2008 Page 7 of 131

REJ03B0177-0302

38D2 Group

PART NUMBERING

Fig. 3 Part numbering

Product M38D2 4 G 6 - XXX FP

Package type

FP: PLQP0064GA-A package

HP: PLQP0064KB-A package

ROM number

Omitted in the shipped in blank version.

ROM memory size

1 : 4096 bytes 9 : 36864 bytes

2 : 8192 bytes A : 40960 bytes

3 : 12288 bytes B : 45056 bytes

4 : 16384 bytes C : 49152 bytes

5 : 20480 bytes D : 53248 bytes

6 : 24576 bytes E : 57344 bytes

7 : 28672 bytes F : 61440 bytes

8 : 32768 bytes

The first 128 bytes and the last 2 bytes of ROM

are reserved areas ; they cannot be used.

Memory type

G : QzROM version

F : Flash memory version

RAM size

0 : 192 bytes

1 : 256 bytes

2 : 384 bytes

3 : 512 bytes

4 : 640 bytes

5 : 768 bytes

6 : 896 bytes

7 : 1024 bytes

8 : 1536 bytes

9 : 2048 bytes

Rev.3.02 Apr 10, 2008 Page 8 of 131

REJ03B0177-0302

38D2 Group

GROUP EXPANSION

Renesas plans to expand the 38D2 Group as follows.

Memory Size

• ROM size ................................................... 16 K to 60 K bytes

• RAM size .................................................... 640 to 2048 bytes

• ROM size ................................................................ 60 K bytes

• RAM size ............................................................... 2048 bytes

Packages

• PLQP0064GA-A ...............0.8 mm-pitch plastic molded LQFP

• PLQP0064KB-A ...............0.5 mm-pitch plastic molded LQFP

Fig. 4 Memory expansion plan

32K

28K

24K

20K

16K

12K

256 384 512 640 768 896 1,024

192

40K

48K

1,536 2,048

56K

60K

ROM size

(bytes)

RAM size (bytes)

M38D24G4

M38D24G6

Products under development or planning : the development schedule and specification may be revised without notice.

M38D28G8

Memory Expansion Plan Under development

M38D29GF/FF

M38D29GC

Rev.3.02 Apr 10, 2008 Page 9 of 131

REJ03B0177-0302

38D2 Group

Currently supported products are listed below .

Table 4 As of August 2007

Part No. ROM size (bytes)

ROM size for User in ( )

RAM size

(bytes) Package Remarks

M38D29GF-XXXFP

61440

(61310) 2048

PLQP0064GA-A

M38D29GF-XXXHP PLQP0064KB-A

M38D29GFFP PLQP0064GA-A Blank

M38D29GFHP PLQP0064KB-A Blank

M38D29GC-XXXFP

49152

(49022) 2048

PLQP0064GA-A

M38D29GC-XXXHP PLQP0064KB-A

M38D29GCFP PLQP0064GA-A Blank

M38D29GCHP PLQP0064KB-A Blank

M38D28G8-XXXFP

32768

(32638) 1536

PLQP0064GA-A

M38D28G8-XXXHP PLQP0064KB-A

M38D28G8FP PLQP0064GA-A Blank

M38D28G8HP PLQP0064KB-A Blank

M38D24G6-XXXFP

24576

(24446) 640

PLQP0064GA-A

M38D24G6-XXXHP PLQP0064KB-A

M38D24G6FP PLQP0064GA-A Blank

M38D24G6HP PLQP0064KB-A Blank

M38D24G4-XXXFP

16384

(16254) 640

PLQP0064GA-A

M38D24G4-XXXHP PLQP0064KB-A

M38D24G4FP PLQP0064GA-A Blank

M38D24G4HP PLQP0064KB-A Blank

M38D29FFFP 61440 2048 PLQP0064GA-A Flash memory version

M38D29FFHP PLQP0064KB-A

Support products

Rev.3.02 Apr 10, 2008 Page 10 of 131

REJ03B0177-0302

38D2 Group

NOTE:

1. For detailed specifications, confirm the descriptions in the Datasheet.

Notes on Differences between QzROM and Flash Mem-

ory Versions

(1) The memory map, the writing modes and programming

circuits vary because of the differences in their internal

memories.

(2) The oscillation parameters of XIN-XOUT and XCIN-XCOUT

may vary.

(3) The QzROM version and the flash memory version MCUs

differ in their manufacturing processes, built-in ROM, and

layout patterns. Because of these differences, characteristic

values, operation margins, A/D conversion accuracy, noise

immunity, and noise radiation may vary within the specified

range of electrical characteristics.

(4) When switching from the flash memory version to the

QzROM version, implement system evaluations equivalent

to those implemented in the flash memory version.

(5) The both operations except the electrical characteristics are

same at the emulator (emulator MCU board: M38D29T-

RLFS).

Table 5 Differences between QzROM and flash memory versions

QzROM version Flash memory version

Oscillation circuit at reset and at returning from stop mode

Main clock XIN or on-chip oscillator selectable

by OSCSEL pin On-chip oscillator

Termination of OSCEL/CNVSS pin OSCSEL = “H” OSCSEL = “L” CNVSS = “L”

Main clock oscillation at reset and at returning from

stop mode Oscillation on Stop Stop

On-chip oscillator oscillation at reset and at returning

from stop mode Stop Oscillation on Oscillation on

System clock φ oscillation at reset and at returning

from stop mode f(XIN)/8 f(OCO)/32 f(OCO)/32

Mounting of main clock oscillation circuit Required Optional Optional

On-chip oscillator oscillation in low speed-mode Stop

Stop by setting the on-chip

oscillator stop bit because it

is not stopped.

Writing “1” to on-chip oscillator stop bit in on-chip

oscillator mode On-chip oscillator is stopped On-chip oscillator is not

stopped

Reset input “L” pulse width 2 μs or more 2 ms or more

Absolute maximum rating: OSCSEL/CNVSS pin −0.3 to 8.0 −0.3 to VCC + 0.3

Minimum operating power source voltage 1.8 V 2.7 V

A/D converter minimum operating power source voltage 2.0 V 2.7 V

Rev.3.02 Apr 10, 2008 Page 11 of 131

REJ03B0177-0302

38D2 Group

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The 38D2 Group uses the standard 740 Family instruction set.

Refer to the 740 Family Software Manual for details on the

instruction set.

Machine-resident 740 Family instructions are as follows:

The FST and SLW instructions cannot be used.

The STP, WIT, MUL, and DIV instructions can be used.

The central processing unit (CPU) has six registers. Figure 5

shows the 740 Family CPU register structure.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as

arithmetic data transfer, etc., are executed mainly through the

accumulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing

modes, the value of the OPERAND is added to the contents of

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the

value of the OPERAND is added to the contents of register Y

and specifies the real address.

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine calls

and interrupts. This register indicates start address of stored area

(stack) for storing registers during subroutine calls and

interrupts.

The low-order 8 bits of the stack address are determined by the

contents of the stack pointer. The high-order 8 bits of the stack

address are determined by the stack page selection bit. If the

stack page selection bit is “0”, the high-order 8 bits becomes

“0016”. If the stack page selection bit is “1”, the high-order 8 bits

becomes “0116”.

The operations of pushing register contents onto the stack and

popping them from the stack are shown in Figure 6.

Table 6 shows the push and pop instructions of accumulator or

processor status register.

Store registers other than those described in Figure 6 with

program when the user needs them during interrupts or

subroutine calls.

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit

registers PCH and PCL. It is used to indicate the address of the

next instruction to be executed.

Fig. 5 740 Family CPU register structure

Processor status register (PS)

Carry flag

Zero flag

Interrupt disable flag

Decimal mode flag

Break flag

Index X mode flag

Overflow flag

Negative flag

b7 b0

b15

Program counter

Stack pointer

Index register Y

Index register X

Accumulator

PCLPCH

CZIDBTVN

b7 b0

Rev.3.02 Apr 10, 2008 Page 12 of 131

REJ03B0177-0302

38D2 Group

Fig. 6 Register push and pop at interrupt generation and subroutine call

Interrupt request →

On-going Routine

M(S) ← (PCH)

(S) ← (S) − 1

M(S) ← (PCL)

(S) ← (S) − 1

.....

Execute RTS

Subroutine

(S) ← (S) + 1

(PCL) ← M(S)

(S) ← (S) + 1

(PCH) ← M(S)

M(S) ← (PCH)

(S) ← (S) − 1

M(S) ← (PCL)

(S) ← (S) − 1

M(S) ← (PS)

(S) ← (S) − 1

Interrupt Service

Routine

(S) ← (S) + 1

(PS) ← M(S)

(S) ← (S) + 1

(PCL) ← M(S)

(S) ← (S) + 1

(PCH) ← M(S)

Execute JSR

Execute RTI

(1)

Push return address

on stack

Push contents of processor

status register on stack

I Flag is set from “0” to “1”

Fetch the jump vector

POP contents of

processor status

POP return

address

from stack

POP return address

from stack

Push return address

on stack

Note1: Condition for acceptance of an interrupt request here → Interrupt disable flag is “0” and

Interrupt enable bit corresponding to each interrupt source is “1”

- - - - - - - - - - - -

Table 6 Push and pop instructions of accumulator or processor status register

Push instruction to stack Pop instruction from stack

Accumulator PHA PLA

Processor status register PHP PLP

Rev.3.02 Apr 10, 2008 Page 13 of 131

REJ03B0177-0302

38D2 Group

[Processor Status Register (PS)]

The processor status register is an 8-bit register consisting of 5

flags which indicate the status of the processor after an

arithmetic operation and 3 flags which decide MCU operation.

Branch operations can be performed by testing the Carry (C)

flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag.

In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C)

The C flag contains a carry or borrow generated by the

arithmetic logic unit (ALU) immediately after an arithmetic

operation. It can also be changed by a shift or rotate

instruction.

• Bit 1: Zero flag (Z)

The Z flag is set to “1” if the result of an immediate arithmetic

operation or a data transfer is “0”, and set to “0” if the result is

anything other than “0”.

• Bit 2: Interrupt disable flag (I)

The I flag disables all interrupts except for the interrupt

generated by the BRK instruction.

Interrupts are disabled when the I flag is “1”.

• Bit 3: Decimal mode flag (D)

The D flag determines whether additions and subtractions are

executed in binary or decimal. Binary arithmetic is executed

when this flag is “0”; decimal arithmetic is executed when it is

“1”.

Decimal correction is automatic in decimal mode. Only the

ADC and SBC instructions can be used for decimal arithmetic.

• Bit 4: Break flag (B)

The B flag is used to indicate that the current interrupt was

generated by the BRK instruction. When the BRK instruction

is generated, the B flag is set to “1” automatically. When the

other interrupts are generated, the B flag is set to “0”, and the

processor status register is pushed onto the stack.

• Bit 5: Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed

between accumulator and memory. When the T flag is “1”,

direct arithmetic operations and direct data transfers are

enabled between memory locations.

• Bit 6: Overflow flag (V)

The V flag is used during the addition or subtraction of one

byte of signed data. It is set if the result exceeds +127 to -128.

When the BIT instruction is executed, bit 6 of the memory

location operated on by the BIT instruction is stored in the

overflow flag.

• Bit 7: Negative flag (N)

The N flag is set to “1” if the result of an arithmetic operation

or data transfer is negative. When the BIT instruction is

executed, bit 7 of the memory location operated on by the BIT

instruction is stored in the negative flag.

Table 7 Set and clear instructions of each bit of processor status register

C flag Z flag I flag D flag B flag T flag V flag N flag

Set instruction SEC −SEI SED −SET −−

Clear instruction CLC −CLI CLD −CLT CLV −

Rev.3.02 Apr 10, 2008 Page 14 of 131

REJ03B0177-0302

38D2 Group

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit, etc.

This register is allocated at address 003B16.

After the system is released from reset, the mode depends on the

OSCSEL pin state in the QzROM version.

When the OSCSEL pin state is GND level, only the on-chip

oscillator starts oscillation. The XIN-XOUT oscillation stops

oscillating, and XCIN and XCOUT pins function as I/O ports. The

operating mode is the on-chip oscillator mode.

When the OSCSEL pin state is Vcc level, the XIN-XOUT

oscillation divided by 8 starts oscillation. The on-chip oscillator

stops oscillating, and the XCIN and XCOUT pins function as I/O

ports. The operating mode is the frequency/8 mode.

In the flash memory version, only the on-chip oscillator starts

oscillating. The XIN-XOUT oscillation stops oscillating, and the

XCIN and XCOUT pins function as I/O ports. The operating mode

is the on-chip oscillator mode.

When the main clock or sub-clock is used, after the XIN-XOUT

oscillation and the XCIN-XCOUT oscillation are enabled, wait in

the on-chip oscillator mode etc. until the oscillation stabilizes,

and then switch the operation mode.

When the main clock is not used (XIN-XOUT oscillation and an

external clock input are not used), connect the XIN pin to VCC

through a resistor and leave XOUT open.

[CPU Mode Register 2 (CPUM2)] 001116

The CPU mode register 2 contains the control bits for the on-chip

oscillator.

The CPU mode register 2 is allocated at address 001116.

Fig. 7 Structure of CPU mode register

On-chip oscillator stop bit

0 : Oscillating

1 : Stopped

Not used (do not write “1”)

Not used (returns “0” when read)

Not used (do not write “1”)

Processor mode bits

b1 b0

0 0 : Single-chip mode

0 1 :

1 0 :

1 1 :

Stack page selection bit

0 : 0 page

1 : 1 page

Internal system clock selection bit

0 : Main clock selected (includes OCO, XIN)

1 : XCIN–XCOUT selected

Port Xc switch bit

0 : I/O port function (Oscillation stop)

1 : XCIN–XCOUT oscillating function

XIN–XOUT oscillation stop bit

0 : Oscillating

1 : Stopped

Main clock division ratio selection bit (Valid only when CM3=0)

b7 b6

0 0 : f(XIN)/2 (frequency/2 mode)

0 1 : f(XIN)/8 (frequency/8 mode)

1 0 : f(XIN)/4 (frequency/4 mode)

1 1 : On-chip oscillator

b7 b0

CPU mode register 2

CPUM2

(address 001116, QzROM version, OSCSEL=L, initial value: 0016)

( QzROM version, OSCSEL=H, initial value: 0116)

( Flash memory version, initial value: 0016)

CM8

b7 b0

CPU mode register

CPUM

(address 003B16, QzROM version, OSCSEL=L, initial value: E016)

( QzROM version, OSCSEL=H, initial value: 4016)

( Flash memory version, initial value: E016)

CM0CM1

CM2CM3CM4

CM5

CM6CM7

Not available

Notes 1: When the on-chip oscillator is selected by the watchdog timer count source selection bit 2 (bit 5 of

watchdog timer control register (address 002916)), the on-chip oscillator does not stop

even when the on-chip oscillator stop bit is set to “1”.

Also, when the low-speed mode is set, the on-chip oscillator stops regardless of the value of this bit in

the QzROM version. The on-chip oscillator does not stop in the flash memory version, so set this bit to

“1” to stop the oscillation.

In on-chip oscillator mode, even if this bit is set to “1”, the on-chip oscillator does not stop in the flash

memory version, but stops in the QzROM version.

2: In low-speed mode, the XCIN-XCOUT oscillation stops if the port XC switch bit is set to “0”.

3: In XIN mode, the XIN-XOUT oscillation does not stop even if the XIN-XOUT oscillation stop bit is set to “1”.

4: 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

(1)

(4)

(2)

(3)

Rev.3.02 Apr 10, 2008 Page 15 of 131

REJ03B0177-0302

38D2 Group

Fig. 8 Switch procedure of CPU mode register

After releasing reset

Low-speed/XIN mode ?

Start the oscillation

(bits 4 and 5 of CPUM)

Oscillator starts oscillation.

Do not change bit 3, bit 6 and bit 7

of CPUM until oscillation stabilizes.

Select internal system clock

(bit 3 of CPUM or bit 7, 6 = “01”)

Wait by on-chip oscillator operation until

establishment of oscillator clock

Switch the main clock division ratio

selection bit (bit 7, 6 = “00” or “10”)

Start with an on-chip oscillator.

Initial value of CPUM is E016.

Initial value of CPUM2 is 0016.

As for the details of condition for

transition among each mode,

refer to the state transition of

system clock.

System can operate in on-chip

oscillator mode until oscillation

stabilize.

Select internal system clock.

Do not change bit 3, bit 6 and bit

7 of CPUM at the same time.

Select main clock division ratio.

Switch to frequency/2 or frequency/4 mode here,

if necessary.

Main routine

Reset

OSCSEL ?

After releasing reset

Wait by operation until establishment

The CPU starts its operation

in the built-in XIN mode.

Initial value of CPUM is 4016.

Initial value of CPUM2 is 0116.

After releasing reset

Low-speed/XIN mode ?

Start the oscillation

(bits 4 and 5 of CPUM)

Oscillator starts oscillation.

Do not change bit 3, bit 6 and bit 7 of CPUM until

oscillation stabilizes.

Select internal system clock

(bit 3 of CPUM or bit 7, 6 = “01”)

Wait by on-chip oscillator operation until

establishment of oscillator clock

Switch the main clock division ratio

selection bit (bit 7, 6 = “00” or “10”)

Start with an on-chip oscillator.

Initial value of CPUM is E016.

Initial value of CPUM2 is 0016.

As for the details of condition for

transition among each mode,

refer to the state transition of system clock.

System can operate in on-chip oscillator mode until

oscillation stabilize.

Select internal system clock.

Do not change bit 3, bit 6 and bit 7 of CPUM at the

same time.

Select main clock division ratio.

Switch to frequency/2 or 4 mode here, if necessary.

Main routine

Reset

Rev.3.02 Apr 10, 2008 Page 16 of 131

REJ03B0177-0302

38D2 Group

MEMORY

• Special Function Register (SFR) Area

The Special Function Register area in the zero page contains

control registers such as I/O ports and timers.

• RAM

RAM is used for data storage and for stack area of subroutine

calls and interrupts.

•ROM

In the QzROM version, the first 128 Kbytes and the last 2 bytes

are reserved for device testing and the rest is the user area. Also,

1 byte of address FFDB16 is reserved.

In the flash memory version, programming and erase operations

can be performed to reserved ROM areas.

• Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

• Zero Page

Access to this area with only 2 bytes is possible in the zero page

addressing mode.

• Special Page

Access to this area with only 2 bytes is possible in the special

page addressing mode.

•

ROM Code Protect Address in QzROM Version (Address

FFDB

)

Address FFDB16 as reserved ROM area in the QzROM version

is ROM code protect address. “0016” or “FE16” is written into

this address when selecting the protect bit write by using a serial

programmer and selecting protect enabled for writing shipment

by Renesas Technology Corp. When “0016” or “FE16” is set to

the ROM code protect address, the protect function is enabled, so

that reading or writing from/to the corresponding area is disabled

by a serial programmer.

As for the QzROM product in blank, the ROM code is protected

by selecting the protect bit write at ROM writing with a serial

programmer.

The protect can be performed, dividing twice. The protect area 1

is from the beginning address of ROM to address “EFFF16”.

As for the QzROM product shipped after writing, “0016” (protect

enabled to all area), “FE16” (protect enabled to the protect area 1)

or “FF16” (protect disabled) is written into the ROM code protect

address when Renesas Technology Corp. performs writing. The

writing of “0016”, “FE16” or “FF16” can be selected as ROM

option setup (“MASK option” written in the mask file converter)

when ordering.

For the ROM code protect in the flash memory version, refer to

the “FLASH MEMORY MODE”.

<Notes>

• After a reset, the contents of RAM are undefined. Make sure to

set the initial value before use.

• When Renesas ships QzROM write products, we write ROM

option data* specified by the mask file converter MM to the

ROM code protect address. Therefore, set FF16 to the ROM

code protect address in ROM data regardless of the presence

or absence of a protect. When data other than FF16 is set, we

may ask that the ROM data be submitted again.

* ROM option data: mask option noted in MM

Fig. 9 Memory map diagram

Reserved area

SFR area

0FF016

100016

SFR area

Interrupt vector area

ROM area

Reserved ROM area

(128 bytes)

010016

000016

004016

084016

FF0016

FFDC16

FFFE16

FFFF16

Zero page

Special page

RAM area

RAM size

(bytes)

Address

XXXX16

192

256

384

512

640

768

896

1024

1536

2048

XXXX16

00FF16

013F16

01BF16

023F16

02BF16

033F16

03BF16

043F16

063F16

083F16

ROM size

(bytes)

Address

YYYY16

Address

ZZZZ16

4096

8192

12288

16384

20480

24576

28672

32768

36864

40960

45056

49152

53248

57344

61440

F00016

E00016

D00016

C00016

B00016

A00016

900016

800016

700016

600016

500016

400016

300016

200016

100016

F08016

E08016

D08016

C08016

B08016

A08016

908016

808016

708016

608016

508016

408016

308016

208016

108016

YYYY16

ZZZZ16

Reserved ROM area

RAM

ROM

Protect area 1

EFFF16

FFDB16 Reserved ROM area

(ROM code protect)

Not used

0FD016

Reserved area

(2)

Note 1: This area is available in the flash memory version only.

2: ROM correction vectors are assigned. As for the details, refer to the “ROM CORRECTION FUNCTION”.

3: In the flash memory version, programming and erase operations can be performed to reserved ROM areas.

Note that their areas are different from those in the QzROM version.

(2)

Reserved ROM area

(ID code)

FFD416 (1)

SFR area

0FEF16

0FE016

(1)

LCD display RAM area

004C16

Rev.3.02 Apr 10, 2008 Page 17 of 131

REJ03B0177-0302

38D2 Group

Fig. 10 Memory map of special function register (SFR)

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

CPU mode register 2 (CPUM2)

RRF register (RRFR)

LCD mode register (LM)

LCD power control register (VLCON)

AD control register (ADCON)

AD conversion register (low-order) (ADL)

AD conversion register (high-order) (ADH)

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Oscillation output control register (OSCOUT)

Timer X (low-order) (TXL)

Timer X (high-order) (TXH)

Timer X (extension) (TXEX)

Timer X mode register (TXM)

Timer X control register 1 (TXCON1)

Timer X control register 2 (TXCON2)

Compare register 1 (low-order) (COMP1L)

Compare register 1 (high-order) (COMP1H)

Compare register 2 (low-order) (COMP2L)

Compare register 2 (high-order) (COMP2H)

Compare register 3 (low-order) (COMP3L)

Compare register 3 (high-order) (COMP3H)

Timer Y (low-order) (TYL)

Timer Y (high-order) (TYH)

Timer Y mode register (TYM)

Timer Y control register (TYCON)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Interrupt control register 2 (ICON2)

Transmit/receive buffer register 1 (TB1/RB1)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART1 control register (UART1CON)

Baud rate generator 1 (BRG1)

Transmit/receive buffer register 2 (TB2/RB2)

Serial I/O2 status register (SIO2STS)

Serial I/O2 control register (SIO2CON)

Timer 1 (T1)

Timer 2 (T2)

Timer 3 (T3)

Timer 4 (T4)

PWM01 register (PWM01)

Timer 12 mode register (T12M)

Timer 34 mode register (T34M)

Timer 1234 mode register (T1234M)

Timer 1234 frequency division selection register (PRE1234)

Watchdog timer control register (WDTCON)

ROM correction address 1 high-order register (RCA1H)

ROM correction address 1 low-order register (RCA1L)

ROM correction address 2 high-order register (RCA2H)

ROM correction address 2 low-order register (RCA2L)

ROM correction enable register (RCR)

Reserved

0FF016

0FF116

0FF216

0FF316

0FF416

0FF516

0FF616

0FF716

0FF816

0FF916

0FFA16

0FFB16

0FFC16

0FFD16

0FFE16

0FFF16

PULL register (PULL)

UART2 control register (UART2CON)

Baud rate generator 2 (BRG2)

Clock output control register (CKOUT)

Segment output disable register 0 (SEG0)

Segment output disable register 1 (SEG1)

Segment output disable register 2 (SEG2)

Key input control register (KIC)

Note 1: The blanks are reserved. Do not write data to these areas.

2: No memory access is allowed to the blank areas within the SFRs.

3: Addresses 0FE016 to 0FEF16 are available in the flash memory version only.

0FE016

0FE116

0FE216

0FE316

0FE416

0FE516

0FE616

0FE716

0FE816

0FE916

0FEA16

0FEB16

0FEC16

0FED16

0FEE16

0FEF16

Flash memory control register 0 (FMCR0)

Flash memory control register 1 (FMCR1)

Flash memory control register 2 (FMCR2)

Reserved

(1)

Rev.3.02 Apr 10, 2008 Page 18 of 131

REJ03B0177-0302

38D2 Group

I/O PORTS

• Direction Registers

The I/O ports P0−P6 have direction registers which determine

the input/output direction of each individual pin. Each bit in a

direction register corresponds to one pin, each pin can be set to

be input port or output port.

When “0” is written to the bit of the direction register, the

corresponding pin becomes an input pin. As for ports P0−P2,

when “1” is written to the bit of the direction register and the

segment output disable register, the corresponding pin becomes

an output pin. As for ports P3−P6, when “1” is written to the bit

of the direction register, the corresponding pin becomes an

output pin.

If data is read from a pin set to output, the value of the port latch

is read, not the value of the pin itself. However, when peripheral

output (RTP1, RTP0, TXOUT1, T4OUT, T3OUT, T2OUT/CKOUT,

OOUT0, and OOUT1) is selected, the output value is read. Pins set

to input are floating. If a pin set to input is written to, only the

port output latch is written to and the pin remains floating.

• Pull-up Control

Each individual bit of ports P0−P2 can be pulled up with a

program by setting direction registers and segment output disable

registers 0 to 2 (addresses 0FF416 to 0FF616).

The pin is pulled up by setting “0” to the direction register and

“1” to the segment output disable register.

By setting the PULL register (addresses 0FF016), ports P3−P6

can control pull-up with a program.

However, the contents of PULL register do not affect ports

programmed as the output ports.

Fig. 11 Structure of ports P0 to P2

Fig. 12 Structure of PULL register and segment output

disable register

Segment output

disable register

Direction

Input port

No pull-up

Input port

Pull-up

Segment

output Port output

“0”

“0” “1”

“1”

Initial state

P00 pull-up

P01 pull-up

P02 pull-up

P03 pull-up

P04 pull-up

P05 pull-up

P06 pull-up

P07 pull-up

Segment output disable register 0

(SEG0 : address 0FF416)

b7 b0

Notes 1: The PULL register and segment output disable

ports.

2: When the VL pin input selection bit (VLSEL) of the

LCD power control register (address 001416) is “1”,

settings of P26 and P27 are invalid.

PULL register

(PULL : address 0FF016)

b7 b0

P30−P33 pull-up

P34−P37 pull-up

P40−P43 pull-up

P44−P47 pull-up

P50−P53 pull-up

P54−P57 pull-up

P60−P62 pull-up

Not used (return “0” when read)

P10 pull-up

P11 pull-up

P12 pull-up

P13 pull-up

P14 pull-up

P15 pull-up

P16 pull-up

P17 pull-up

Segment output disable register 1

(SEG1 : address 0FF516)

b7 b0

P20 pull-up

P21 pull-up

P22 pull-up

P23 pull-up

P24 pull-up

P25 pull-up

P26 pull-up

P27 pull-up

Segment output disable register 2

(SEG2 : address 0FF616)

b7 b0

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

0 : No pull-up

1 : Pull-up

Rev.3.02 Apr 10, 2008 Page 19 of 131

REJ03B0177-0302

38D2 Group

Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

Table 8 List of I/O port function

Pin Name

Input/Output

I/O format Non-port function Related SFRs

Ref. No.

P00/SEG0/(KW4)−

P03/SEG3/(KW7)

Port P0 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

LCD segment

output

Key input

(key-on wakeup)

interrupt input

Segment output disable

(1)

P04/SEG4−

P07/SEG7

(2)

P10/SEG8−

P17/SEG15

Port P1 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

Segment output disable

P20/SEG16−

P25/SEG21

Port P2 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

Segment output disable

P26/SEG22/VL1

P27/SEG23/VL2

LCD power

input

P30/SRDY2/(LED0)

P31/SCLK2/(LED1)

P32/TXD2/(LED2)

P33/RXD2/(LED3)

Port P3 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

Serial I/O2 function I/O PULL register

Serial I/O2 control

Serial I/O2 status

UART2 control register

(3)

(4)

(5)

(6)

P34/INT2/(LED4) External interrupt input PULL register

Interrupt edge selection

(7)

P35/TXOUT1/(LED5) Timer X output 1 PULL register (8)

P36/T2OUT/CKOUT

/(LED6)

Timer 2 output

Clock output Timer X mode register

Timer 12 mode register

Clock output control

(9)

/CNTR

XOUT2

/(LED7)

Timer X function input

Timer X output 2

PULL register

Timer X mode register

(10)

P40/OOUT0/AN0

P41/OOUT1/AN1

Port P4 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

Oscillation

external

output pins

PULL register

AD control register

Oscillation output

control register

(13)

P42/AN2/ADKEY A/D conversion input PULL register (11)

P43/AN3−P45/AN5AD control register (12)

P46/RTP0/AN6

P47/RTP1/AN7

Real time

port function

output

PULL register

AD control register

Timer Y mode register

(13)

P50/INT0

P51/INT1

Port P5 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

External interrupt input PULL register

Interrupt edge selection

(7)

P52/T3OUT/PWM0

P53/T4OUT/PWM1

Timer 3 output

Timer 4 output

PWM output

PULL register

Timer 34 mode register

(9)

P54/RXD1/(KW0)

P55/TXD1/(KW1)

P56/SCLK1/(KW2)

P57/SRDY1/(KW3)

Serial I/O1

function I/O

Key input

(key-on

wakeup)

interrupt input

PULL register

Serial I/O1 control

Serial I/O1 status

UART1 control register

(14)

(15)

(16)

(17)

P60/CNTR1Port P6 Input/Output,

individual bits

CMOS compatible input level

CMOS 3-state output

Timer Y function input PULL register

Timer Y mode register

(7)

P61/XCIN Sub-clock oscillation circuit PULL register (18)

P62/XCOUT CPU mode register (19)

COM0 −COM3Common Output LCD common output LCD mode register (20)

Rev.3.02 Apr 10, 2008 Page 20 of 131

REJ03B0177-0302

38D2 Group

Fig. 13 Port block diagram (1)

(1) Ports P00-P03

(6) Port P33

(5) Port P32

(3) Port P30

Data bus

Serial I/O enable bit

Transmit enable bit

Serial I/O output

P32/TxD2 P-channel output disable bit

Port latch

Direction

Pull-up control

Serial I/O ready output

Data bus Port latch

Serial I/O mode selection bit

Serial I/O enable bit

SRDY2 output enable bit

Direction

Pull-up control

Direction

Data bus

Serial I/O enable bit

Receive enable bit

Serial I/O input

Port latch

(4) Port P31

Serial I/O synchronous

clock selection bit

Data bus

Serial I/O clock output

Serial I/O clock input

Serial I/O mode selection bit

Serial I/O enable bit

Port latch

Direction

Serial I/O enable bit Pull-up control

(2) Ports P04-P07, P1, P2

Segment output disable bit

Direction

Data bus Port latch

VL2/VL3

VL1/VSS

Key input control

Key-on wakeup

interrupt input

Segment data

Segment output disable bit

Direction

Data bus Port latch

LCD power input (VL1,VL2)

only for P26, P27

VL2/VL3

VL1/VSS

Segment data

Segment output disable bit

Rev.3.02 Apr 10, 2008 Page 21 of 131

REJ03B0177-0302

38D2 Group

Fig. 14 Port block diagram (2)

(12) Ports P43-P45

Analog input pin selection bit

A-D conversion input

Data bus Port latch

Direction

Pull-up control

(14) Port P54

(7) Ports P34, P50, P51, P60

Data bus

Direction

Port latch

Pull-up control

CNTR1 interrupt input

INT0-INT2 interrupt input

(8) Port P35

Port latch

Data bus

Pulse output mode

Timer X output

Direction

Pull-up control

Direction

Data bus

Serial I/O enable bit

Receive enable bit

Port latch

Pull-up control

Serial I/O input

Key-on wakeup interrupt input Key input control

(9) Ports P36, P52, P53

Port latch

Data bus

Port/Timer output selection

Timer output/PWM output

Timer output/System clock φ output

Direction

Pull-up control

(13) Ports P40, P41, P46, P47

Data bus Port latch

Oscillation output control bit/

Real time control bit

Direction

Pull-up control

Analog input pin selection bit

A-D conversion input

Oscillation output/

Data for real time port

(10) Ports P37

Data bus

Direction

Port latch

Pull-up control

CNTR0 interrupt input

Timer output

A-D conversion input

Data bus Port latch

Direction

Pull-up control

(11) Ports P42

ADKEY enable bit

Analog input pin selection bit

Port/Timer output selection

Rev.3.02 Apr 10, 2008 Page 22 of 131

REJ03B0177-0302

38D2 Group

Fig. 15 Port block diagram (3)

(20) COM0-COM3

VL3

VL2

VL1

VSS

Gate input signal of

each gate depends

on the duty ratio

and bias values.

(17) Port P57

Serial I/O ready output

Data bus Port latch

Serial I/O mode selection bit

Serial I/O enable bit

SRDY1 output enable bit

Direction

Pull-up control

Key-on wakeup interrupt input Key input control

(19) Port P62

Data bus Port latch

Direction

Xc oscillation enabled + Pull-up control

Xc oscillation enabled

Port P61

Oscillator

Xc oscillation enabled

(18) Port P61

Data bus Port latch

Direction

Xc oscillation enabled

Sub-clock generation circuit input

Xc oscillation enabled + Pull-up control

(16) Port P56

Serial I/O synchronous clock

selection bit

Data bus

Serial I/O clock output

Serial I/O mode selection bit

Serial I/O enable bit

Port latch

Direction

Serial I/O enable bit Pull-up control

Serial I/O clock input

Key-on wakeup interrupt input Key input control

(15) Port P55

Data bus

Serial I/O enable bit

Transmit enable bit

Serial I/O output

P55/TxD1 P-channel output disable bit

Port latch

Direction

Pull-up control

Key-on wakeup interrupt input Key input control

Rev.3.02 Apr 10, 2008 Page 23 of 131

REJ03B0177-0302

38D2 Group

• Termination of unused pins

• Termination of common pins

I/O ports: Select an input port or an output port and follow

each processing method.

In addition, it is recommended that related

registers be overwritten periodically to prevent

malfunctions, etc.

Output ports: Open.

Input ports: If the input level become unstable, through current

flow to an input circuit, and the power supply

current may increase.

Especially, when expecting low consumption

current (at STP or WIT instruction execution etc.),

pull-up or pull-down input ports to prevent

through current (built-in resistor can be used).

We recommend processing unused pins through a

resistor which can secure IOH(avg) or IOL(avg).

Because, when an I/O port or a pin which have an

output function is selected as an input port, it may

operate as an output port by incorrect operation

etc.

Table 9 Termination of unused pins

Pin Termination 1 Termination 2 Termination 3

P00/SEG0/(KW4)−P07/SEG7I/O port When selecting SEG output, open. −

P10/SEG8−P17/SEG15

P20/SEG16−P27/SEG23/VL2

P30/SRDY2/(LED0),

P57/SRDY1/(KW3)

When selecting SRDY function,

perform termination of output port.

−

P31/SCLK2/(LED1),

P56/SCLK1/(KW2)

When selecting external clock input,

perform termination of input port.

When selecting internal clock output,

perform termination of output port.

P32/TXD2/(LED2),

P55/TXD1/(KW1)

When selecting TxD function, perform

termination of output port.

−

P33/RXD2/(LED3),

P54/RXD1/(KW0)

When selecting RxD function,

perform termination of input port.

−

P34/INT2/(LED4) When selecting INT function, perform

termination of input port.

−

P35/TXOUT1/(LED5) When selecting TXOUT function,

perform termination of output port.

−

P36/T2OUT/CKOUT/(LED6)

When selecting T

2OUT

function or CKOUT

function, perform termination of output port.

−

P37/CNTR0/TXOUT2/(LED7) When selecting TXOUT function,

perform termination of output port.

−

P40/OOUT0/AN0,

P41/OOUT1/AN1

When selecting AN function, these

pins can be opened. (A/D conversion

result cannot be guaranteed.)

When selecting oscillation output,

perform termination of output port.

P42/AN2/ADKEY

When selecting ADKEY function,

pull-up this pin through a resistor.

P43/AN3−P47/RTP1/AN7−

P50/INT0,

P51/INT1

When selecting INT function, perform

termination of input port.

−

P52/T3OUT/PWM0,

P53/T4OUT/PWM1

When selecting PWM, T

3OUT

, or T

4OUT

function, perform termination of output port.

−

P60/CNTR1When selecting CNTR input function,

perform termination of input port.

−

P61/XCIN,

P62/XCOUT

Do not select XCIN-XCOUT oscillation

function by program.

−

VL3 Set the VL3 connect bit to “1”

and apply a Vcc level

voltage to VL3 pin.

Set the VL3 connect bit to “0” and

leave the VL3 pin open.

−

COM0−COM3Open −−

AVss Connect to Vss −−

VREF Connect to Vcc −−

XIN When only on-chip oscillator

is used, connect to VCC

through a resistor.

−−

XOUT When external clock is input

or when only on-chip

oscillator is used, open.

−−

Rev.3.02 Apr 10, 2008 Page 24 of 131

REJ03B0177-0302

38D2 Group

INTERRUPTS

The 38D2 Group interrupts are vector interrupts with a fixed

priority scheme, and generated by 16 sources among 18 sources:

6 external, 11 internal, and 1 software.

The interrupt sources, vector addresses(1), and interrupt priority

are shown in Table 10.

Each interrupt except the BRK instruction interrupt has the

interrupt request bit and the interrupt enable bit. These bits and

the interrupt disable flag (I flag) control the acceptance of

interrupt requests. Figure 16 shows an interrupt control diagram.

An interrupt requests is accepted when all of the following

conditions are satisfied:

• Interrupt disable flag ................................ “0”

• Interrupt request bit .................................. “1”

• Interrupt enable bit ................................... “1”

Though the interrupt priority is determined by hardware, priority

processing can be performed by software using the above bits

and flag.

Notes 1:Vector addresses contain interrupt jump destination addresses.

2:Reset function in the same way as an interrupt with the highest priority.

Table 10 Interrupt vector addresses and priority

Interrupt Source

Priority

Vector Addresses(1) Interrupt Request Generating

Conditions Remarks

High Low

Reset (2) 1FFFD16 FFFC16 At reset Non-maskable

INT02FFFB16 FFFA16 At detection of either rising or falling

edge of INT0 input

External interrupt (active edge selectable)

INT13FFF916 FFF816 At detection of either rising or falling

edge of INT1 input

External interrupt (active edge selectable)

INT24FFF716 FFF616 At detection of either rising or falling

edge of INT2 input

Valid when INT2 interrupt is selected

External interrupt (active edge selectable)

Key input

(key-on wakeup)

At falling of ports P00−P03, P54−P57

input logical level AND

Valid when key input interrupt is selected

External interrupt (falling valid)

CNTR05FFF516 FFF416 At detection of either rising or falling

edge of CNTR0 input

External interrupt (active edge selectable)

Timer X 6 FFF316 FFF216 At timer X underflow

Timer 1 7 FFF116 FFF016 At timer 1 underflow Valid when timer 1 interrupt is selected

Timer 2 8 FFEF16 FFEE16 At timer 2 underflow Valid when timer 2 interrupt is selected

Timer 3 9 FFED16 FFEC16 At timer 3 underflow Valid when timer 3 interrupt is selected

Timer 4 10 FFEB16 FFEA16 At timer 4 underflow Valid when timer 4 interrupt is selected

Serial I/O1 receive 11 FFE916 FFE816 At completion of serial I/O1 data receive Valid only when serial I/O1 is selected

Serial I/O1 transmit 12 FFE716 FFE616 At completion of serial I/O1 transmit

shift or transmit buffer is empty

Valid only when serial I/O1 is selected

Serial I/O2 receive 13 FFE516 FFE416 At completion of serial I/O2 data receive Valid only when serial I/O2 is selected

Serial I/O2 transmit 14 FFE316 FFE216 At completion of serial I/O2 data

transmit shift or transmit buffer is empty

Valid only when serial I/O2 is selected

Timer Y 15 FFE116 FFE016 At timer Y underflow

CNTR1At detection of either rising or falling

edge of CNTR1 input

External interrupt (active edge selectable)

A/D conversion 16 FFDF16 FFDE16 At completion of A/D conversion Valid when A/D interrupt is selected

BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt

Rev.3.02 Apr 10, 2008 Page 25 of 131

REJ03B0177-0302

38D2 Group

Fig. 16 Interrupt control

• Interrupt Disable Flag

The interrupt disable flag is assigned to bit 2 of the processor

status register. This flag controls the acceptance of all interrupt

requests except for the BRK instruction. When this flag is set to

“1”, the acceptance of interrupt requests is disabled. When it is

set to “0”, acceptance of interrupt requests is enabled. This flag is

set to “1” with the SEI instruction and set to “0” with the CLI

instruction.

When an interrupt request is accepted, the contents of the

processor status register are pushed onto the stack while the

interrupt disable flag remains set to “0”. Subsequently, this flag

is automatically set to “1” and multiple interrupts are disabled.

To use multiple interrupts, set this flag to “0” with the CLI

instruction within the interrupt processing routine.

The contents of the processor status register are popped off the

stack with the RTI instruction.

• Interrupt Request Bits

Once an interrupt request is generated, the corresponding

interrupt request bit is set to “1” and remains “1” until the request

is accepted. When the request is accepted, this bit is

automatically set to “0”.

Each interrupt request bit can be set to “0”, but cannot be set to

“1”, by software.

• Interrupt Enable Bits

The interrupt enable bits control the acceptance of the

corresponding interrupt requests. When an interrupt enable bit is

set to “0”, the acceptance of the corresponding interrupt request

is disabled. If an interrupt request occurs in this condition, the

corresponding interrupt request bit is set to “1”, but the interrupt

request is not accepted. When an interrupt enable bit is set to “1”,

acceptance of the corresponding interrupt request is enabled.

Each interrupt enable bit can be set to “0” or “1” by software.

The interrupt enable bit for an unused interrupt should be set to

“0”.

• Interrupt Source Selection

Any of the following combinations can be selected by the

interrupt edge selection register (003A16).

•INT

2 or key input

• Timer Y or CNTR1

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

BRK instruction

Reset

Interrupt

acceptance

Rev.3.02 Apr 10, 2008 Page 26 of 131

REJ03B0177-0302

38D2 Group

Fig. 17 Structure of interrupt-related registers

INT0 interrupt request bit

INT1 interrupt request bit

INT2 interrupt request bit

Key input interrupt request bit

CNTR0 interrupt request bit

Timer X interrupt request bit

Timer 1 interrupt request bit

Timer 2 interrupt request bit

Timer 3 interrupt request bit

Interrupt request register 1

(IREQ1 : address 003C16)

INT0 interrupt enable bit

INT1 interrupt enable bit

INT2 interrupt enable bit

Key input interrupt enable bit

CNTR0 interrupt enable bit

Timer X interrupt enable bit

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

Timer 4 interrupt request bit

Serial I/O1 receive interrupt request bit

Serial I/O1 transmit interrupt request bit

Serial I/O2 receive interrupt request bit

Serial I/O2 transmit interrupt request bit

Timer Y interrupt request bit

CNTR1 interrupt request bit

AD conversion interrupt request bit

Not used (returns “0” when read)

0 : No interrupt request issued

1 : Interrupt request issued

Timer 4 interrupt enable bit

Serial I/O1 receive interrupt enable bit

Serial I/O1 transmit interrupt enable bit

Serial I/O2 receive interrupt enable bit

Serial I/O2 transmit interrupt enable bit

Timer Y interrupt enable bit

CNTR1 interrupt enable bit

AD conversion interrupt enable bit

Not used (Do not write to “1”.)

Interrupt control register 2

(ICON2 : address 003F16)

0 : Interrupts disabled

1 : Interrupts enabled

0 : INT2 interrupt

1 : Key input interrupt

Interrupt control register 1

(ICON1 : address 003E16)

Interrupt request register 2

(IREQ2 : address 003D16)

INT0 interrupt edge selection bit

INT1 interrupt edge selection bit

INT2 interrupt edge selection bit

INT2/Key input interrupt switch bit

Timer Y/CNTR1 interrupt switch bit

Not used (Do not write to “1”.)

Not used (return “0” when read)

Interrupt edge selection register

(INTEDGE : address 003A16)

0 : Falling edge active

1 : Rising edge active

0 : Timer Y interrupt

1 : CNTR1 interrupt

b7 b0 b7 b0

b7 b0

Rev.3.02 Apr 10, 2008 Page 27 of 131

REJ03B0177-0302

38D2 Group

• Interrupt Request Generation, Acceptance, and

Handling

Interrupts have the following three phases.

(i) Interrupt Request Generation

An interrupt request is generated by an interrupt source

(external interrupt signal input, timer underflow, etc.) and

the corresponding request bit is set to “1”.

(ii) Interrupt Request Acceptance

Based on the interrupt acceptance timing in each instruction

cycle, the interrupt control circuit determines acceptance

conditions (interrupt request bit, interrupt enable bit, and

interrupt disable flag) and interrupt priority levels for

accepting interrupt requests. When two or more interrupt

requests are generated simultaneously, the highest priority

interrupt is accepted. The value of interrupt request bit for

an unaccepted interrupt remains the same and acceptance is

determined at the next interrupt acceptance timing point.

(iii) Handling of Accepted Interrupt Request

The accepted interrupt request is processed.

Figure 18 shows the time up to execution in the interrupt routine,

and Figure 19 shows the interrupt sequence.

Figure 20 shows the timing of interrupt request generation,

interrupt request bit, and interrupt request acceptance.

• Interrupt Handling Execution

When interrupt handling is executed, the following operations

are performed automatically.

(1) Once the currently executing instruction is completed, an

interrupt request is accepted.

(2) The contents of the program counters and the processor

status register at this point are pushed onto the stack area in

order from 1 to 3.

1. High-order bits of program counter (PCH)

2. Low-order bits of program counter (PCL)

3. Processor status register (PS)

(3) Concurrently with the push operation, the jump address of

the corresponding interrupt (the start address of the interrupt

processing routine) is transferred from the interrupt vector to

the program counter.

(4) The interrupt request bit for the corresponding interrupt is

set to “0”. Also, the interrupt disable flag is set to “1” and

multiple interrupts are disabled.

(5) The interrupt routine is executed.

(6) When the RTI instruction is executed, the contents of the

registers pushed onto the stack area are popped off in the

order from 3 to 1. Then, the routine that was before running

interrupt processing resumes.

As described above, it is necessary to set the stack pointer and

the jump address in the vector area corresponding to each

interrupt to execute the interrupt processing routine.

Fig. 18 Time up to execution in interrupt routine

Fig. 19 Interrupt sequence

7 cycles

Interrupt request

generated

Interrupt request

acceptance

Interrupt routine

starts

Interrupt sequence

0 to 16 cycles

7 to 23 cycles

* When executing DIV instruction

Main routine Stack push and

Vector fetch

Interrupt handling

routine

SYNC

Push onto stack

Vector fetch

Address bus

Data bus

Execute interrupt

routine

PC S,SPS S-1,SPS S-2,SPS BLBHAL,AH

Not used PCHPCLPS ALAH

SYNC : CPU operation code fetch cycle

(This is an internal signal that cannot be observed from the external unit.)

BL, BH: Vector address of each interrupt

AL, AH: Jump destination address of each interrupt

SPS : “0016” or “0116”

([SPS] is a page selected by the stack page selection bit of CPU mode register.)

Rev.3.02 Apr 10, 2008 Page 28 of 131

REJ03B0177-0302

38D2 Group

<Notes>

The interrupt request bit may be set to “1” in the following cases.

• When setting the external interrupt active edge

Related bits: INT0 interrupt edge selection bit

(bit 0 of interrupt edge selection register

(address 003A16))

INT1 interrupt edge selection bit

(bit 1 of interrupt edge selection register)

INT2 interrupt edge selection bit

(bit 2 of interrupt edge selection register)

CNTR0 activate edge switch bit

(bits 6 and 7 of timer X control register 1

(address 002E16))

CNTR1 activate edge switch bit

(bits 6 of timer Y mode register

(address 003816))

• When switching the interrupt sources of an interrupt vector

address where two or more interrupt sources are assigned

Related bit: Timer Y/CNTR1 interrupt switch bit

(bit 3 of interrupt edge selection register)

If it is not necessary to generate an interrupt synchronized with

these settings, take the following sequence.

(1) Set the corresponding enable bit to “0” (disabled).

(2) Set the interrupt edge selection bit (the active edge switch

bit) or the interrupt source bit.

(3) Set the corresponding interrupt request bit to “0” after one

or more instructions have been executed.

(4) Set the corresponding interrupt enable bit to “1” (enabled).

Fig. 20 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance

(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.

(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.

The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt

requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2

separately.

T1 T2 T3 : Interrupt acceptance timing points

IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.

Note : Period 2 indicates the last φ cycle during one instruction cycle.

IR1T2

SYNC

IR2T3

Internal clock φ

Instruction cycle Push onto stack

Vector fetch Instruction cycle

Rev.3.02 Apr 10, 2008 Page 29 of 131

REJ03B0177-0302

38D2 Group

• Key Input Interrupt (Key-on Wake-Up)

A key input interrupt request is generated by detecting the falling

edge from any pin of ports P00−P03, P54−P57 that have been set

to input mode. In other words, it is generated when AND of input

level goes from “1” to “0”. An example of using a key input

interrupt is shown in Figure 21, where an interrupt request is

generated by pressing one of the keys consisted as an active-low

key matrix which inputs to ports P54−P57.

Fig. 21 Connection example when using key input interrupt

∗

∗∗∗

∗∗

∗∗ Port P54

latch

Port P54

direction register = “0”

Port P55

latch

Port P55

direction register = “0”

Port P56

latch

Port P56

direction register = “0”

Port P57

latch

Port P57

direction register = “0”

Port P00

latch

Port P00

direction register = “1”

Port P01

latch

Port P01

direction register = “1”

Port P02

latch

Port P02

direction register = “1”

Port P03

latch

Port P03

direction register = “1”

P54 input

P55 input

P56 input

P57 input

P00 output

P01 output

P02 output

P03 output

PULL register

Bit 5 = “1”

Port P0

Input reading circuit

Key input interrupt request

Port PXx

“L” level output

∗ P-channel transistor for pull-up

∗∗ CMOS output buffer

Port P5 Input

reading circuit

Key input control

Segment output

disable register 0

Bit 3 = “1”

Segment output

disable register 0

Bit 2 = “1”

Segment output

disable register 0

Bit 1 = “1”

Segment output

disable register 0

Bit 0 = “1”

Rev.3.02 Apr 10, 2008 Page 30 of 131

REJ03B0177-0302

38D2 Group

A key input interrupt is controlled by the key input control

is enabled, set “1” to the key input control register. A key input

of any pin of ports P00−P03, P54−P57 that have been set to input

mode is accepted.

Fig. 22 Structure of key input control register

P54 key input control bit

P55 key input control bit

P56 key input control bit

P57 key input control bit

P00 key input control bit

P01 key input control bit

P02 key input control bit

P03 key input control bit

b7 Key input control register

(KIC : address 0FF716)

0 : Key input interrupt disabled

1 : Key input interrupt enabled

Rev.3.02 Apr 10, 2008 Page 31 of 131

REJ03B0177-0302

38D2 Group

TIMERS

8-Bit Timer

The 38D2 Group has four built-in 8-bit timers: timer 1, timer 2,

timer 3, and timer 4.

Each timer has the 8-bit timer latch. All timers are down-

counters.

When the timer reaches “0016”, the contents of the timer latch is

reloaded into the timer with the next count pulse. In this mode,

the interrupt request bit corresponding to that timer is set to “1”.

The count can be stopped by setting the stop bit of each timer to

“1”.

Fig. 23 Timer 1-4 block diagram

Timer 1 latch (8)

Timer 1 (8)

Timer 2 latch (8)

Timer 2 (8)

Timer 3 latch (8)

Timer 3 (8)

Timer 4 latch (8)

Timer 4 (8)

Timer 1 interrupt request

Timer 2 interrupt request

Timer 3 interrupt request

Timer 4 interrupt request

XCIN

Data bus

Timer 1 count stop bit

10 bit

PWM1

circuit

1/2

Timer 4 operating

mode selection bit

T4OUT output

edge switch bit

P53

latch

Timer 4 output selection bit

P53 direction

P53/PWM1/

T4OUT

10 bit

PWM0

circuit

1/2

Timer 3 operating

mode selection bit

T3OUT output

edge switch bit

P52

latch

Timer 3 output selection bit

P52 direction

P52/PWM0/

T3OUT

“00”

“01”

“10”

“00”

“01”

“1”

“0”

“01”

“10”

“00”

“0”

“1”

“0”

“1”

“0”

Clock for

timer 1

Clock for

timer 2

Clock for

timer 3

Clock for

timer 4

Timer 1

Timer 2

Timer 3

Timer 4

Frequency division

selection bits

(2 bits for each timer)

Clock for timer 1

Clock for timer 2

Clock for timer 3

Clock for timer 4

The following values can be selected

the clock for timer;

1/1,1/2,1/16,1/256

Frequency divider

1/2

T2OUT output

edge switch bit

Timer 2 output selection bit

“0”

“1”

P36 direction

P36/T2OUT/CKOUT

P36

latch

Timer 2 output selection bit

P36 clock output

control bit System clock φ

“1”

“0”

“10”

Timer Y

output

Timer 3 write control bit

PWM01 register (2)

Timer 4 write control bit

Timer 2 write control bit

Timer 1 count

source selection

bits

Timer 2 count

source selection

bits

Timer 2 count stop bit

Timer 3 count source

selection bit

Timer 3 count stop bit

Timer 4 count source

selection bits

Timer 4 count stop bit

Timer 4 output selection bit

φ SOURCE

φ SOURCE: represents the oscillation frequency of

XIN input in the frequency/2, 4 or 8 mode,

on-chip oscillator divided by 4 in the on-chip

oscillator mode,

and sub-clock in the low-speed mode.

“11”

f(XIN)

(Note)

Rev.3.02 Apr 10, 2008 Page 32 of 131

REJ03B0177-0302

38D2 Group

• Frequency Divider For Timer

Timer 1, timer 2, timer 3 and timer 4 have the frequency divider

for the count source. The count source of the frequency divider is

switched to XIN, XCIN, or the on-chip oscillator OCO divided by

4 in the on-chip oscillator mode by the CPU mode register. The

frequency divider is controlled by each timer division ratio

selection bit. The division ratio can be selected from as follows;

1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(OCO)/4. Switch the

frequency division or count source* while the timer count is

stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

• Timer 1, Timer 2

The count source for timer 1 and timer 2 can be set using the

timer 12 mode register. XCIN may be selected as the count

source. If XCIN is selected, count operation is possible regardless

of whether or not the XIN input oscillator or the on-chip oscillator

is operating. In addition, the timer 12 mode register can be used

to output from the P36/T2OUT pin a signal to invert the polarity

every time timer 2 underflows.

At reset, all bits of the timer 12 mode register are set to “0”, timer

1 is set to “FF16”, and timer 2 is set to “0116”.

When executing the STP instruction, previously set the wait time

at return.

• Timer 3, Timer 4

The count sources of timer 3 and timer 4 can be selected by

setting the timer 34 mode register. Also, by the timer 34 mode

which polarity is inverted can be output from P52/T3OUT pin or

P53/T4OUT pin.

• Timer 3 PWM0 Mode, Timer 4 PWM1 Mode

A PWM rectangular waveform corresponding to the 10-bit

accuracy can be output from the P52/PWM0 pin and P53/PWM1

pin by setting the timer 34 mode register and PWM01 register

(refer to Figure 24).

One output pulse is the short interval. Four output pulses are the

long interval. The “n” is the value set in the timer 3 (address

002216) or the timer 4 (address 002316). The “ts” is one period of

timer 3 or timer 4 count source. “H” width of the short interval is

obtained by n × ts.

However, in the long interval, “H” width of output pulse is

extended for ts which is set by the PWM01 register (address

002416).

(1) Timer 3 PWM0 Mode, Timer 4 PWM1 Mode

• When PWM output is suspended after starting PWM output,

depending on the level of the output pulse at that time to

resume an output, the delay of the one section of the short

interval may be needed.

Stop at “H”: No output delay

Stop at “L”: Output is delayed time of 256 × ts

• In the PWM mode, the follows are performed every cycle of

the long interval (4 × 256 × ts).

• Generation of timer 3, timer 4 interrupt requests

• Update of timer 3, timer 4

(2) Write to Timer 2, Timer 3, Timer 4

When writing to the latch only, if the write timing to the reload

latch and the underflow timing are almost the same, the value is

set into the timer and the timer latch at the same time. In this

time, counting is stopped during writing to the reload latch.

Fig. 24 Waveform of PWM0 and PWM1

Output waveform of timer 3 PWM0 or timer 4 PWM1

n: Setting value of timer 3 or timer 4

ts: One period of timer 3 count source or timer 4 count source

PWM01 register (address 002416) : 2-bit value corresponding to PWM0 (bits 0, 1) or PWM1 (bits 2, 3)

256 × ts256 × ts256 × ts256 × ts

n × tsn × tsn × tsn × ts

n × tsn × tsn × ts

n × ts

PWM01 register = “002”

PWM01 register = “012”

PWM01 register = “102”

PWM01 register = “112”

(n+1) × ts

(n+1) × ts (n+1) × ts (n+1) × ts

(n+1) × ts

Short interval Short interval Short interval Short interval

Long interval

4 × 256 × ts

Interrupt request Interrupt request

Rev.3.02 Apr 10, 2008 Page 33 of 131

REJ03B0177-0302

38D2 Group

Fig. 25 Structure of timer 1 to timer 4 related registers

Timer 12 mode register

(T12M: address 002516)

Timer 34 mode register

(T34M: address 002616)

Timer 1234 mode register

(T1234M: address 002716)

Timer 1234 frequency division selection register

(PRE1234: address 002816)

PWM01 register

(PWM01: address 002416)

Timer 1 frequency division selection bits

b1b0

0 0 : 1/16 × φ SOURCE

0 1 : 1/1 × φ SOURCE

1 0 : 1/2 × φ SOURCE

1 1 : 1/256 × φ SOURCE

Timer 3 frequency division selection bits

b5b4

0 0 : 1/16 × φSOURCE

0 1 : 1/1 × φ SOURCE

1 0 : 1/2 × φ SOURCE

1 1 : 1/256 × φ SOURCE

Timer 1 count stop bit

0 : Count operation

1 : Count stop

T2OUT output edge switch bit

0 : Start at “L” output

1 : Start at “H” output

Timer 2 output selection bit (P36)

0 : I/O port

1 : Timer 2 output

Timer 2 count source selection bits

b5b4

0 0 : Underflow of timer 1

0 1 : f(XCIN)

1 0 : Frequency divider for timer 2

1 1 : Not available

Timer 1 count source selection bits

b3b2

0 0 : Frequency divider for timer 1

0 1 : f(XCIN)

1 0 : Underflow of timer Y

1 1 : Not available

Timer 2 count stop bit

0 : Count operation

1 : Count stop

PWM0 set bits

b1b0

0 0 : No extended

0 1 : Extended once in four periods

1 0 : Extended twice in four periods

1 1 : Extended three times in four periods

Not used (returns “0” when read)

PWM1 set bits

b3b2

0 0 : No extended

0 1 : Extended once in four periods

1 0 : Extended twice in four periods

1 1 : Extended three times in four periods

Timer 2 frequency division selection bits

b3b2

0 0 : 1/16 × φ SOURCE

0 1 : 1/1 × φ SOURCE

1 0 : 1/2 × φ SOURCE

1 1 : 1/256 × φ SOURCE

Timer 4 frequency division selection bits

b7b6

0 0 : 1/16 × φ SOURCE

0 1 : 1/1 × φ SOURCE

1 0 : 1/2 × φ SOURCE

1 1 : 1/256 × φ SOURCE

T3OUT output edge switch bit

0 : Start at “L” output

1 : Start at “H” output

Not used (returns “0” when read)

Timer 4 write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer 3 write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer 2 write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer 4 output selection bit (P53)

0 : I/O port

1 : Timer 4 output

Timer 3 output selection bit (P52)

0 : I/O port

1 : Timer 3 output

T4OUT output edge switch bit

0 : Start at “L” output

1 : Start at “H” output

Timer 3 count stop bit

0 : Count operation

1 : Count stop

Not used (returns “0” when read)

Timer 4 operating mode selection bit

0 : Timer mode

1 : PWM mode

Timer 3 operating mode selection bit

0 : Timer mode

1 : PWM mode

Timer 4 count source selection bits

b4b3

0 0 : Frequency divider for timer 4

0 1 : Underflow of Timer 3

1 0 : Underflow of Timer 2

1 1 : f(XIN)

Timer 3 count source selection bit

0 : Frequency divider for timer 3

1 : Underflow of Timer 2

Timer 4 count stop bit

0 : Count operation

1 : Count stop

b7 b0

b7 b0 b7 b0

b7 b0

Note1: φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the on-chip oscillator mode

•Sub-clock in the low-speed mode

(1)

Rev.3.02 Apr 10, 2008 Page 34 of 131

REJ03B0177-0302

38D2 Group

16-bit Timer

Read and write operation on 16-bit timer must be performed for

both high and low-order bytes. When reading a 16-bit timer, read

the high-order byte first. When writing to a 16-bit timer, write

the low-order byte first. The 16-bit timer cannot perform the

correct operation when reading during the write operation, or

when writing during the read operation.

Fig. 26 Timer X block diagram

Data bus

1/2

1/4

Frequency

divider

Noise filter sampling

clock selection bit

“1”

“0”

Timer X interrupt

request

Timer X (high-order)(8)Timer X (low-order)(8)

Timer X (high-order) latch (8)

Timer X (low-order) latch (8)

Equal

“000”

“001”

“010”

“011”

“101”

Pulse width

measurement

mode

Timer X count

stop bit

INT2

CNTR0 active

edge switch bits

Timer X operating

mode bits

CNTR0

interrupt request

“100”

Extend latch (2)

Timer X write

control bit

Timer 1 interrupt

D Q

Latch

Data for control of event counter window

CNTR0

INT0

0 μs

Delay time

selection bits

4/f(XIN)

“00”

“01”

“10”

“11”

8/f(XIN)

16/f(XIN)

Noise filter

(4 times same

levels judgment)

INT0

interrupt request

Count source selection bit

XcIN

“1”

“0”

Clock for timer X

XIN

Frequency divider Timer X frequency

division selection bits

Both edges

detection

“00”

“01”

“10”

“11”

Timer X output

control bit 1

Timer X output

control bit 2

Timer X operating

mode bits “010”

Delay

circuit

“000”

“001”

“011”

“100”

“101”

Timer X operating

mode bits

“010”

Compare register 3 (low-order)(8) Compare register 3 (high-order)(8)

Compare register 1 (low-order)(8) Compare register 1 (high-order)(8)

Compare register 2 (low-order)(8) Compare register 2 (high-order)(8)

Pulse output mode

Timer X output 1

selection bit

P35

latch

P35

direction

P35/TXOUT1/(LED5)

Timer X output 1

edge switch bit

“0”

“1”

IGBT output mode

PWM mode

Timer X output 2

selection bit

P37

latch

P37

direction

P37/CNTR0/TXOUT2/(LED7)

Timer X output 2

edge switch bit

“0”

“1”

Extend counter (2)

φSOURCE

φSOURCE : represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode, Internal

on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed

mode.

“0”

“1”

Delay circuit 1/2

“1”

“0”

×2

Trigger for IGBT control bit

INT1

Edge

selection

Edge

selection *

Edge

selection *

Edge

detection

Rev.3.02 Apr 10, 2008 Page 35 of 131

REJ03B0177-0302

38D2 Group

• Frequency Divider For Timer

Each timer X and timer Y have the frequency dividers for the

count source. The count source of the frequency divider is

switched to XIN, XCIN, or the on-chip oscillator OCO divided by

4 in the on-chip oscillator mode by the CPU mode register. The

division ratio of each timer can be controlled by each timer

division ratio selection bit. The division ratio can be selected

from as follows;

1/1, 1/2, 1/16, 1/256 of f(XIN), f(XCIN) or f(OCO)/4.

Switch the frequency division or count source* while the timer

count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

• Timer X

The count source for timer X can be set using the timer X mode

selected, count operation is possible regardless of whether or not

the XIN input oscillator or the on-chip oscillator is operating.

The timer X operates as down-count. When the timer contents

reach “000016”, an underflow occurs at the next count pulse and

the timer latch contents are reloaded. After that, the timer

continues countdown. When the timer underflows, the interrupt

request bit corresponding to the timer X is set to “1”.

Six operating modes can be selected for timer X by the timer X

mode register and timer X control register.

(1) Timer Mode

The count source can be selected by setting the timer X mode

setting the timer X register (extension).

(2) Pulse Output Mode

Pulses of which polarity is inverted each time the timer

underflows are output from the TXOUT1 pin. Except for that, this

mode operates just as in the timer mode.

When using this mode, set the port sharing the TXOUT1 pin to

output mode.

(3) IGBT Output Mode

After dummy output from the TXOUT1 pin, count starts with the

INT0 pin input as a trigger. In the case that the timer X output 1

active edge switch bit is “0”, when the trigger is detected or the

timer X underflows, “H” is output from the TXOUT1 pin. And

then, when the count value corresponds with the compare

After noise is cleared by noise filters, judging continuous 4-time

same levels with sampling clocks to be signals, the INT0 signal

can use 4 types of delay time by a delay circuit.

When using this mode, set the port sharing the INT0 pin to input

mode and set the port sharing the pin used as TXOUT1 or TXOUT2

function to output mode.

When the timer X output control bit 1 or 2 of the timer X control

forcibly by the interrupt signal of INT1 or INT2. And then, the

TXOUT1 output and TXOUT2 output can be set to “L” forcibly at

the same time that the timer X stops counting.

Do not write “1” to the timer X register (extension) when using

the IGBT output mode.

(4) PWM Mode

IGBT dummy output, an external trigger with the INT0 pin and

output control with pins INT1 and INT2 are not used. Except for

those, this mode operates just as in the IGBT output mode.

The period of PWM waveform is specified by the timer X set

value. In the case that the timer X output 1 active edge switch bit

is “0”, the “H” interval is specified by the compare register 1 set

value. In the case that the timer X output 2 active edge switch bit

is “0”, the “H” interval is specified by the compare registers 2

and 3 set values.

When using this mode, set the port sharing the pin used as

TXOUT1 or TXOUT2 function to output mode.

Do not write “1” to the timer X register (extension) when using

the PWM mode.

(5) Event Counter Mode

The timer counts signals input through the CNTR0 pin. In this

mode, timer X operates as the 18-bit counter by setting the timer

X register (extension). When using this mode, set the port

sharing the CNTR0 pin to input mode.

In this mode, the window control can be performed by the timer

1 underflow. When the bit 5 (data for control of event counter

window) of the timer X mode register is set to “1”, counting is

stopped at the next timer 1 underflow. When the bit is set to “0”,

counting is restarted at the next timer 1 underflow.

(6) Pulse Width Measurement Mode

In this mode, the count source is the output of frequency divider

for timer. In this mode, timer X operates as the 18-bit counter by

setting the timer X register (extension). When the bit 6 of the

CNTR0 active edge switch bits is “0”, counting is executed

during the “H” interval of CNTR0 pin input. When the bit is “1”,

counting is executed during the “L” interval of CNTR0 pin input.

When using this mode, set the port sharing the CNTR0 pin to

input mode.

Also, set to enable (“0”) the data for control of event counter

window (bit 5 of timer X mode register (address 002D16)).

Rev.3.02 Apr 10, 2008 Page 36 of 131

REJ03B0177-0302

38D2 Group

Fig. 27 Waveform of PWM/IGBT

(1) Write Order to Timer X

• In the timer mode, pulse output mode, event counter mode and

pulse width measurement mode, write to the following

registers in the order as shown below;

the timer X register (extension),

the timer X register (low-order),

the timer X register (high-order).

Do not write to only one of them.

When the above mode is set and timer X operates as the 16-bit

counter, if the timer X register (extension) is never set after

reset is released, setting the timer X register (extension) is not

required. In this case, write the timer X register (low-order)

first and the timer X register (high-order). However, once

writing to the timer X register (extension) is executed, note that

the value is retained to the reload latch.

• Write to the timer X register by the 16-bit unit. Do not read the

timer X register while write operation is performed. If the

write operation is not completed, normal operation will not be

performed.

• In the IGBT output and PWM modes, do not write “1” to the

timer X register (extension). Also, when “1” is already written

to the timer X register, be sure to write “0” to the register

before using.

Write to the following registers in the order as shown below;

the compare registers 1, 2, 3 (high- and low-order),

the timer X register (extension),

the timer X register (low-order),

the timer X register (high-order).

It is possible to use whichever order to write to the compare

registers 1, 2, 3 (high- and low-order). However, write both the

compare registers 1, 2, 3 and the timer X register at the same

time.

For the compare registers, set a value less than the setting value

in the timer X register. Also, do not set “0016”.

(2) Read Order to Timer X

• In all modes, read the following registers in the order as shown

below;

the timer X register (extension),

the timer X register (high-order),

the timer X register (low-order).

When reading the timer X register (extension) is not required,

read the timer X register (high-order) first and the timer X

Read order to the compare registers 1, 2, 3 is not specified.

• Read from the timer X register by the 16-bit unit. Do not write

to the timer X register while read operation is performed. If the

read operation is not completed, normal operation will not be

performed.

(3) Write to Timer X

• Which write control can be selected by the timer X write

control bit (b3) of the timer X mode register (address 2D16),

writing data to both the latch and the timer at the same time or

writing data only to the latch. When writing a value to the

timer X address to write to the latch only, the value is set into

the reload latch and the timer is updated at the next underflow.

After reset release, when writing a value to the timer X

address, the value is set into the timer and the timer latch at the

same time, because they are written at the same time.

When writing to the latch only, if the write timing to the high-

order reload latch and the underflow timing are almost the

same, the value is set into the timer and the timer latch at the

same time. In this time, counting is stopped during writing to

the high-order reload latch.

• Switch the frequency division or count source* while the timer

count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

Timer X count source

Timer X PWM mode

IGBT output mode

m × ts

(n+1) × ts

The following PWM waveform is output;

Duty of TXOUT1 output :{(n+1)-m}/(n+1),

Duty of TXOUT2 output :(p-q)/(n+1),

Period :(n+1) × ts

TXOUT1 output

(TXCON1 bit 5 = “0”)

TXOUT2 output

(TXCON2 bit 1 = “0”) q × ts

p × ts

n : Timer X setting value

m: Compare register 1 setting value

p : Compare register 2 setting value

q : Compare register 3 setting value

ts: One period of timer X count source

External trigger (INT0 source)

is generated. INT1 or INT2 source is generated.

Level is forcibly “L” only IGBT

output mode.

Level is “H” only IGBT

output mode.

Rev.3.02 Apr 10, 2008 Page 37 of 131

REJ03B0177-0302

38D2 Group

(4) Set of Timer X Mode Register

Set the write control bit of the timer X mode register to “1”

(write to the latch only) when setting the IGBT output and PWM

modes.

Output waveform simultaneously reflects the contents of both

registers at the next underflow after writing to the timer X

(5) Output Control Function of Timer X

• When using the output control function (INT1 and INT2) in the

IGBT output mode, set the levels of INT1 and INT2 to “H” in

the falling edge active or to “L” in the rising edge active before

switching to the IGBT output mode.

(6) Switch of CNTR0 Active Edge

• When the CNTR0 active edge switch bits are set, at the same

time, the interrupt active edge is also affected.

When the pulse width is measured, set the bit 7 of the CNTR0

active edge switch bits to “0”.

(7) When Timer X Pulse Width Measurement Mode

Used

When timer X pulse width measurement mode is used, enable the

event counter wind control data (bit 5 of timer X mode register

(address 002D16)) by setting to “0”.

If the event counter window control data (bit 5 of timer X mode

enable/disable the CNTR0 input, the input is not accepted after

the timer 1 underflow.

Fig. 28 Structure of timer X related registers

Timer X mode register

(TXM: address 002D16)

Timer X operating mode bits

b2b1b0

0 0 0 : Timer mode

0 0 1 : Pulse output mode

0 1 0 : IGBT output mode

0 1 1 : PWM mode

1 0 0 : Event counter mode

1 0 1 : Pulse width measurement mode

1 1 0 : Not available

1 1 1 : Not available

Timer X write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer X count source selection bit

0 : Frequency divider output

1 : f(XCIN)

Data for control of event counter window

0 : Event count enabled

1 : Event count disabled

Timer X count stop bit

0 : Count operation

1 : Count stop

Timer X output 1 selection bit (P35)

0 : I/O port

1 : Timer X output 1

b7 b0 b0 Timer X control register 1

(TXCON1: address 002E16)

Noise filter sampling clock selection bit

0 : f(XIN)/2

1 : f(XIN)/4

External trigger delay time selection bits

b2b1

0 0 : Not delayed

0 1 : (4/f(XIN)) μs

1 0 : (8/f(XIN)) μs

1 1 : (16/f(XIN)) μs

Timer X output control bit 1 (P51)

0 : Not used INT1 interrupt signal

1 : INT1 interrupt signal used

Timer X output control bit 2 (P34)

0 : Not used INT2 interrupt signal

1 : INT2 interrupt signal used

Timer X output 1 active edge switch bit

0 : Start at “L” output

1 : Start at “H” output

CNTR0 active edge switch bits

b7b6

0 0 : Count at rising edge in event counter mode

Falling edge active for CNTR0 interrupt

Measure “H” pulse width in pulse width measurement mode

0 1 : Count at falling edge in event counter mode

Rising edge active for CNTR0 interrupt

Measure “L” pulse width in pulse width measurement mode

1 0 : Count at both edges in event counter mode

1 1 : Both edges active for CNTR0 interrupt

Timer X control register 2

(TXCON2: address 002F16)

Timer X output 2 control bit (P37)

0 : I/O port

1 : Timer X output 2

Timer X output 2 active edge switch bit

0 : Start at “L” output

1 : Start at “H” output

Timer X dividing frequency selection bits

b3b2

0 0 : 1/16 × φ SOURCE

0 1 : 1/1 × φ SOURCE

1 0 : 1/2 × φ SOURCE

1 1 : 1/256 × φ SOURCE

Trigger for IGBT input control bit

0 : Noise filter sampling clock × 1

External trigger delay time × 1

1 : Noise filter sampling clock × 2

External trigger delay time × 1/2

Not used (returns “0” when read)

b7 b0

(1)

Note1: φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the on-chip oscillator mode

•Sub-clock in the low-speed mode

Rev.3.02 Apr 10, 2008 Page 38 of 131

REJ03B0177-0302

38D2 Group

Fig. 29 Block diagram of timer Y

• Timer Y

Timer Y is a 16-bit timer. The timer Y count source can be

selected by setting the timer Y mode register. XCIN can be

selected as the count source. When XCIN is selected as the count

source, counting can be performed regardless of XIN oscillation

or on-chip oscillator oscillation.

Four operating modes can be selected for timer Y by the timer Y

mode register. Also, the real time port can be controlled.

(1) Timer Mode

The timer Y count source can be selected by setting the timer Y

mode register.

(2) Period Measurement Mode

The interrupt request is generated at rising or falling edge of

CNTR1 pin input signal. Simultaneously, the value in timer Y

latch is reloaded in timer Y and timer Y continues counting.

Except for that, this mode operates just as in the timer mode.

The timer value just before the reloading at rising or falling of

CNTR1 pin input is retained until the timer Y is read once after

the reload.

The rising or falling timing of CNTR1 pin input is found by

CNTR1 interrupt. When using this mode, set the port sharing the

CNTR1 pin to input mode.

(3) Event Counter Mode

The timer counts signals input through the CNTR1 pin.

Except for that, this mode operates just as in the timer mode.

When using this mode, set the port sharing the CNTR1 pin to

input mode.

(4) Pulse Width HL Continuously Measurement Mode

The interrupt request is generated at both rising and falling edges

of CNTR1 pin input signal. Except for that, this mode operates

just as in the period measurement mode. When using this mode,

set the port sharing the CNTR1 pin to input mode.

(5) Real Time Port Control

When the real time port function is valid, data for the real time

port is output from ports P46 and P47 each time the timer Y

underflows.

(However, if the real time port control bits are changed from

“002” to “112” after both data for real time ports are set, data are

output independent of the timer Y operation.) When either or

both data for real time ports are changed while the real time port

function is valid, the changed data is output at the next underflow

of timer Y.

When switching the setting of the real time port control bits

between valid and invalid, write to the timer Y mode register in

byte units with the LDM or STA instruction so that both bits are

switched at the same time. Also, before using this function, set

the P46 and P47 port direction registers to output.

Data bus

Real time port

control bits

Real time port

control bits Q D

Latch

Q D

Latch

P47 direction

P47 data for real time

port

P46 direction

P46 data for real time

port

“1”

Timer Y (low-order) latch (8) Timer Y (high-order) latch (8)

“0”

CNTR1 active

edge switch bit

“10”

P47/RTP1/AN7

P46/RTP0/AN6

CNTR1

Falling edge detection

Period measurement

mode

Timer Y

interrupt request

Pulse width HL continuous

measurement mode

Timer Y operating

mode bits

CNTR1

interrupt request

Rising edge detection

Count source selection bit

XcIN

“1”

φSOURCE

Real time port control bits

Timer Y mode register

write signal

Timer Y operating mode bits

“00”, “01”, “11”

“11”

“00”

“11”

“00”

“11”

“00”

“00”, “01”, “10”

“11”

“0”

Timer Y write control bit

Timer Y count

stop bit

“00”

“11”

Timer Y mode register

write signal

Real time port control bits

Timer Y (low-order)(8) Timer Y (high-order)(8)

Frequency divider Timer Y dividing frequency selection bit

Note: In frequency/2, frequency/4, or frequency/8 mode, φSOURCE is the XIN input. In on-chip oscillator

mode, φSOURCE is the on-chip oscillator frequency divided by 4. In low-speed mode, φSOURCE is

the sub-clock frequency.

Rev.3.02 Apr 10, 2008 Page 39 of 131

REJ03B0177-0302

38D2 Group

• CNTR1 Interrupt Active Edge Selection

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit. However, in pulse width HL continuously

measurement mode, CNTR1 interrupt request is generated at

both rising and falling edges of CNTR1 pin input signal

regardless of the setting of CNTR1 active edge switch bit.

• Timer Y Read/Write Control

• When reading from/writing to timer Y, read from/write to both

the high-order and low-order bytes of timer Y. When the value

is read, read the high-order bytes first and the low-order bytes

next. When the value is written, write the low-order bytes first

and the highorder bytes next.

Write to or read from the timer X register in 16-bit units. If

reading from the timer Y register during write operation or

writing to it during read operation is performed, normal

operation will not be performed.

• Which write control can be selected by the timer Y write

control bit (b0) of the timer Y control register (address

003916), writing data to both the latch and the timer at the

same time or writing data only to the latch. When writing a

value to the timer Y address to write to the latch only, the

value is set into the reload latch and the timer is updated at the

next underflow. After reset release, when writing a value to the

timer Y address, the value is set into the timer and the timer

latch at the same time, because they are set to write at the same

time.

When writing to the latch only, if the write timing to the high-

order reload latch and the underflow timing are almost the

same, the value is set into the timer and the timer latch at the

same time. In this time, counting is stopped during writing to

the high-order reload latch.

• This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

Fig. 30 Structure of timer Y related registers

b7 b0

Timer Y control register

(TYCON: address 003916)

Timer Y write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer Y count source selection bit

0 : Frequency divider output

1 : f(XCIN)

Timer Y frequency division selection bits

b3 b2

0 0 : 1/16 × φSOURCE

0 1 : 1/1 × φSOURCE

1 0 : 1/2 × φSOURCE

1 1 : 1/256 × φSOURCE

Not used (returns “0” when read)

φ SOURCE: represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode,

Internal on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed mode.

Real time port control bits (P46, P47 )

b1 b0

0 0 : Real time port function invalid

0 1 : Do not set

1 0 : Do not set

1 1 : Real time port function valid

P46 data for real time port

P47 data for real time port

Timer Y operating mode bits

b5 b4

0 0 : Timer mode

0 1 : Period measurement mode

1 0 : Event counter mode

1 1 : Pulse width HL continuous measurement mode

CNTR1 active edge switch bit

0 : Count at rising edge in event counter mode

Measure falling period in period measurement mode

Falling edge active for CNTR1 interrupt

1 : Count at falling edge in event counter mode

Measure rising period in period measurement mode

Rising edge active for CNTR1 interrupt

Timer Y count stop bit

0 : Count operation

1 : Count stop

Timer Y mode register

(TYM: address 003816)

b0b7

Rev.3.02 Apr 10, 2008 Page 40 of 131

REJ03B0177-0302

38D2 Group

SERIAL INTERFACE

• SERIAL I/O

The 38D2 Group has two 8-bit serial I/O (serial I/O1 and serial

I/O2).

Serial I/O can be used as either clock synchronous or

asynchronous (UART) serial I/O. A dedicated timer is also

provided for baud rate generation.

(1) Clock Synchronous Serial I/O Mode

Clock synchronous serial I/O mode can be selected by setting the

serial I/O mode selection bit of the serial I/O control register to

“1”.

For clock synchronous serial I/O, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB.

Fig. 31 Block diagram of clock synchronous serial I/O

Fig. 32 Operation of clock synchronous serial I/O function

1/4

F/F

Receive buffer register

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O synchronous

clock selection bit

Baud rate generator

Frequency division ratio 1/(n+1)

BRG count source selection bit

Clock control circuitFalling-edge detector

Transmit buffer register

Data bus

Shift clock Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Data bus

Transmit shift register

Serial I/O control register

Serial I/O status register

Address 001816

[Address 001D16]

Address 001816

[Address 001D16]

Address 001916

[Address 001E16]

Address 001C16

[Address 0FF216]

Address 001A16

[Address 001F16]

P54/RXD1

[P33/RXD2]

P56/SCLK1

[P31/SCLK2]

P57/SRDY1

[P30/SRDY2]

P55/TXD1

[P32/TXD2]

[ ] : For Serial I/O2 φ SOURCE: represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode,

Internal on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed mode.

φSOURCE

D0D1D2D3D4D5D6

RBF = 1

TSC = 1

TBE = 0 TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

Write pulse to receive/transmit

buffer register

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or

after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data

is output continuously from the TxD pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal SRDY

Rev.3.02 Apr 10, 2008 Page 41 of 131

REJ03B0177-0302

38D2 Group

(2) Asynchronous Serial I/O (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

setting the serial I/O mode selection bit of the serial I/O control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but

the two buffers have the same address in memory. Since the shift

is written to the transmit buffer register, and receive data is read

from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 33 Block diagram of UART serial I/O

Fig. 34 Operation of UART serial I/O function

1/4

PE FE

1/16

Data bus

Receive buffer register

Receive shift register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Baud rate generator

Frequency division ratio 1/(n+1)

Transmit buffer register

Data bus

Transmit shift register

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

UART control register

Character length selection bit

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O synchronous clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O status register

Serial I/O control register

P54/RXD1

[P33/RXD2]

P56/SCLK1

[P31/SCLK2]

P55/TXD1

[P32/TXD2]

Address 001816

[Address 001D16]

Address 001C16 [Address 0FE216]

Address 001816

[Address 001D16]

Address 001916

[Address 001E16]

Address 001A16

[Address 001F16]

Address 001B16

[Address 0FE116]

[ ] : For Serial I/O2

φ SOURCE: represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode,

Internal on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed mode.

φSOURCE

SP detector

ST/SP/PA generator

ST detector

TSC=0

TBE=1

RBF=0

TBE=0 TBE=0

RBF=1 RBF=1

STD0D1SP D0D1

ST SP

TBE=1 TSC=1∗

STD0D1SP D0D1

ST SP

Serial input RxD

∗ Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting

of the transmit interrupt source selection bit (TIC) of the serial I/O control register.

3: The receive interrupt (RI) is set when the RBF flag becomes “1”.

4: After data is written to the transmit buffer when TSC flag = “1”, 0.5 to 1.5 cycles of the data shift cycle is necessary until

changing to TSC flag = “0”.

Transmit or receive clock

Transmit buffer register

write signal

Serial output TxD

Receive buffer register

read signal

Rev.3.02 Apr 10, 2008 Page 42 of 131

REJ03B0177-0302

38D2 Group

[Transmit Buffer Register/Receive Buffer Register

(TB1, RB1/TB2, RB2)]

The transmit buffer register and the receive buffer register are

located at the same address. The transmit buffer is write-only and

the receive buffer is read-only. If a character bit length is 7 bits,

the MSB of data stored in the receive buffer is “0”.

[Serial I/O Status Register (SIO1STS, SIO2STS)]

The read-only serial I/O status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is set to “0” when the receive

buffer register is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer

serial I/O status register sets all the error flags OE, PE, FE, and

SE (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial

I/O enable bit SIOE (bit 7 of the serial I/O control register) also

sets all the status flags to “0”, including the error flags.

All bits of the serial I/O status register are set to “0” at reset, but

if the transmit enable bit (bit 4) of the serial I/O control register

has been set to “1”, the transmit shift completion flag (bit 2) and

the transmit buffer empty flag (bit 0) become “1”.

[Serial I/O Control Register (SIO1CON, SIO2CON)]

The serial I/O control register consists of eight control bits for

the serial I/O function.

[UART Control Register (UART1CON, UART2CON)]

The UART control register consists of four control bits (bits 0 to

3) which are valid when asynchronous serial I/O is selected and

set the data format of the data transfer and one bit (bit 4) which is

always valid and sets the output structure of the P55/TXD1

[P32/TxD2] pin.

[Baud Rate Generator (BRG1, BRG2)]

The baud rate generator determines the baud rate for serial

transfer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate

generator.

When setting transmit enable bit of serial I/O to “1”, the serial

I/O transmit interrupt request bit is automatically set to “1”.

When not requiring the interrupt occurrence synchronous with

the transmission enabled, take the following sequence.

(1) Set the serial I/O transmit interrupt enable bit to “0”

(disabled).

(2) Set the transmit enable bit to “1”.

(3) Set the serial I/O transmit interrupt request bit to “0” after 1

or more instructions have been executed.

(4) Set the serial I/O transmit interrupt enable bit to “1”

(enabled).

Rev.3.02 Apr 10, 2008 Page 43 of 131

REJ03B0177-0302

38D2 Group

Fig. 35 Structure of serial I/O related registers

b7 b0

BRG count source selection bit (CSS)

0: φSOURCE

1: φSOURCE/4

Serial I/O synchronous clock selection bit (SCS)

0: BRG output divided by 4 when clock synchronous

serial I/O is selected.

BRG output divided by 16 when UART is selected.

1: External clock input when clock synchronous serial

I/O is selected.

External clock input divided by 16 when UART is selected.

SRDY output enable bit (SRDY)

0: P57 [P30] pin operates as ordinary I/O pin

1: P57 [P30] pin operates as SRDY output pin

Transmit interrupt source selection bit (TIC)

0: Interrupt when transmit buffer has emptied

1: Interrupt when transmit shift operation is completed

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Serial I/O mode selection bit (SIOM)

0: Clock asynchronous (UART) serial I/O

1: Clock synchronous serial I/O

Serial I/O enable bit (SIOE)

0: Serial I/O disabled

(pins P54 [P30] to P57 [P33] operate as ordinary I/O pins)

1: Serial I/O enabled

(pins P54 [P30] to P57 [P33] operate as serial I/O pins)

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

Transmit shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

Overrun error flag (OE)

0: No error

1: Overrun error

Parity error flag (PE)

0: No error

1: Parity error

Framing error flag (FE)

0: No error

1: Framing error

Summing error flag (SE)

0: (OE) U (PE) U (FE)=0

1: (OE) U (PE) U (FE)=1

Not used (returns “1” when read)

Serial I/O control register

(SIO1CON : address 001A16)

[SIO2CON : address 001F16]

Serial I/O status register

(SIO1STS : address 001916)

[SIO2STS : address 001E16]

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

P55/TXD1 [P32/TxD2] P-channel output disable bit (POFF)

0: CMOS output (in output mode)

1: N-channel open drain output (in output mode)

Not used (return “1” when read)

UART control register

(UART1CON : address 001B16)

[UART2CON : address 0FF116]

( ) : For Serial I/O1

[ ] : For Serial I/O2

φ SOURCE: represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode,

Internal on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed mode.

Rev.3.02 Apr 10, 2008 Page 44 of 131

REJ03B0177-0302

38D2 Group

A/D CONVERTER

The 38D2 Group has a 10-bit A/D converter. The A/D converter

performs successive approximation conversion. The 38D2 Group

has the ADKEY function which perform A/D conversion of the

“L” level analog input from the ADKEY pin automatically.

[AD Conversion Register (ADL, ADH)]

One of these registers is a high-order register, and the other is a

low-order register. The high-order 8 bits of a conversion result is

stored in the AD conversion register (high-order) (address

001716), and the low-order 2 bits of the same result are stored in

bit 7 and bit 6 of the AD conversion register (low-order) (address

001616).

During A/D conversion, do not read these registers.

Also, the connection between the resistor ladder and reference

voltage input pin (VREF) can be controlled by the VREF input

switch bit (bit 0 of address 001616). When “1” is written to this

bit, the resistor ladder is always connected to VREF. When “0” is

written to this bit, the resistor ladder is disconnected from VREF

except during the A/D conversion.

[AD Control Register (ADCON)]

This register controls A/D converter. Bits 2 to 0 are analog input

pin selection bits. Bit 3 is an AD conversion completion bit and

“0” during A/D conversion. This bit is set to “1” upon

completion of A/D conversion.

A/D conversion is started by setting “0” in this bit.

Bit 5 is the ADKEY enable bit. The ADKEY function is enabled

by setting “1” to this bit. When this function is valid, the analog

input pin selection bits are ignored. Also, when bit 5 is “1”, do

not set “0” to bit 3 by program.

[Comparison Voltage Generator]

The comparison voltage generator divides the voltage between

AV SS and VREF, and outputs the divided voltages.

[Channel Selector]

The channel selector selects one of the input ports P47/AN7−

P40/AN0 and inputs it to the comparator.

[Comparator and Control Circuit]

The comparator and control circuit compare an analog input

voltage with the comparison voltage and store the result in the

AD conversion register. When an A/D conversion is completed,

the control circuit sets the AD conversion completion bit and the

AD conversion interrupt request bit to “1”.

The comparator is constructed linked to a capacitor. The

conversion accuracy may be low because the change is lost if the

conversion speed is not enough.

Accordingly, set f(XIN) to at least 500 kHz during A/D

conversion in the XIN mode.

Also, do not execute the STP and WIT instructions during the

A/D conversion.

In the low-speed mode and on-chip oscillator mode, there is no

limit on the oscillation frequency because the on-chip oscillator

is used as the A/D conversion clock. In the low-speed mode, on-

chip oscillator starts oscillation automatically at the A/D

conversion is executed and stops oscillation automatically at the

A/D conversion is finished even though it is not oscillating.

Fig. 36 Block diagram of A/D converter

(Address 001716)(Address 001616)

ADKEY

control circuit

A/D control circuit

AVSS

b7 b0

Data bus

Channel selector

AD conversion register (H)

Resistor ladder

Comparator

A/D interrupt request

AD control register

P40/AN0

P41/AN1

P42/AN2/ADKEY

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

AD conversion register (L)

VREF

1/8

1/2

φSOURCE

Note: In frequency/2, frequency/4, or frequency/8 mode, φSOURCE is the XIN input.

In low-speed mode, or on-chip oscillator mode, φSOURCE is the on-chip

oscillator frequency divided by 4.

Rev.3.02 Apr 10, 2008 Page 45 of 131

REJ03B0177-0302

38D2 Group

Fig. 37 Structure of AD control register

ADKEY function

The ADKEY function is used to judge the analog input voltage

input from the ADKEY pin. When the A/D converter starts

operating after VIL (0.7 × Vcc-0.5) or less is input, the event of

analog voltage input can be judged with the A/D conversion

interrupt.

This function can be used with the STP and WIT state.

As for the ADKEY function in 38D2 Group, the A/D conversion

of analog input voltage immediately after starting ADKEY

function is not performed.

Therefore, the A/D conversion result immediately after an

ADKEY function is undefined. Accordingly, when the A/D

conversion result of the analog input voltage input from the

ADKEY pin is required, start the A/D conversion by program

after the analog input pin corresponding to ADKEY is selected.

• ADKEY Selection

When the ADKEY pin is used, set the ADKEY selection bit to

“1”. The ADKEY selection bit is “0”, just after the A/D

conversion is started.

• ADKEY Enable

The ADKEY function is enabled by writing “1” to the ADKEY

enable bit. Surely, in order to enable ADKEY function, set “1” to

the ADKEY enable bit, after setting the ADKEY selection bit to

“1”.

When the ADKEY enable bit of the AD control register is “1”,

the analog input pin selection bits become invalid. Please do not

write “0” in the AD conversion completion bit by the program

during ADKEY enabled state.

[ADKEY Control Circuit]

In order to obtain a more exact conversion result, by the A/D

conversion with ADKEY, execute the following;

• set the input to the ADKEY pin into a steep falling waveform,

• stabilize the input voltage within 8 clock cycles (1 μs at f(XIN)

= 8 MHz) after the input voltage is under VIL

The threshold voltage with an actual ADKEY pin is the voltage

between VIH-VIL.

In order not to make ADKEY operation perform superfluously in

a noise etc., in the state of the waiting for an input, set the voltage

of an ADKEY pin to VIH (0.9VCC) or more.

When the following operations are performed, the A/D

conversion operation cannot be guaranteed.

• When the CPU mode register is operated during A/D

conversion operation,

• When the AD conversion control register is operated during

A/D conversion operation,

• When the STP or WIT instruction is executed during A/D

conversion operation.

AD control register

(ADCON: address 001516)

Analog input pin selection bits

b2 b1 b0

0 0 0 : P40/AN0

0 0 1 : P41/AN1

0 1 0 : P42/AN2

0 1 1 : P43/AN3

1 0 0 : P44/AN4

1 0 1 : P45/AN5

1 1 0 : P46/AN6

1 1 1 : P47/AN7

AD conversion completion bit

0 : Conversion in progress

1 : Conversion completed

AD conversion clock selection bit

0 : φSOURCE/2

1 : φSOURCE/8

ADKEY enable bit

0 : Disabled

1 : Enabled

10-bit or 8-bit conversion switch bit

0 : 10-bit AD

1 : 8-bit AD

ADKEY selection bit

0 : Invalid

1 : Valid

b7 b0

*VREF input switch bit

0: ON only during A/D conversion

1: ON

Note : The bit 5 to bit 1 of address 001616 become “0” at reading.

Also, bit 0 is undefined at reading.

(low-order)

b1 b0

b7 b0

AD conversion register

high-order

(Address 001716)

b7 b2b3b6 b5 b4b9 b8 (high-order)

b7 b0

At 10bitAD

(Read address 001716 before 001616)

b5 b0b1b4 b3 b2b7 b6

b7 b0

Notes 1: φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the low-speed and the on-chip

oscillator mode

2: When the ADKEY enable bit is “1”, the analog input pin selection

bits are invalid.

Do not execute the A/D conversion by program while the ADKEY is

enabled.

Bit 0 to bit 2 of ADCON are not changed even when ADKEY is

enabled.

AD conversion register

low-order

(Address 001616)

At 8bitAD

(Read only address 001716)

(Address 001716)

(2)

(1)

Rev.3.02 Apr 10, 2008 Page 46 of 131

REJ03B0177-0302

38D2 Group

LCD DRIVE CONTROL CIRCUIT

The 38D2 Group has the built-in Liquid Crystal Display (LCD)

drive control circuit consisting of the following.

• LCD display RAM

• Segment output disable register

• LCD mode register

• Selector

• Timing controller

• Common driver

• Segment driver

• Bias control circuit

A maximum of 24 segment output pins and 4 common output

pins can be used.

Up to 96 pixels can be controlled for an LCD display. When the

LCD enable bit is set to “1” after data is set in the LCD mode

RAM, the LCD drive control circuit starts reading the display

data automatically, performs the bias control and the duty ratio

control, and displays the data on the LCD panel.

Fig. 38 Structure of LCD related registers

Table 11 Maximum number of display pixels at each duty ratio

Duty ratio Maximum number of display pixels

248 dots

or 8 segment LCD 6 digits

372 dots

or 8 segment LCD 9 digits

496 dots

or 8 segment LCD 12 digits

LCD mode register

(LM : address 001316)

b7 b0

Duty ratio selection bits

b1b0

0 0 : Not used

0 1 : 2 (use COM0, COM1)

1 0 : 3 (use COM0-COM2)

1 1 : 4 (use COM0-COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

LCD drive timing selection bit

0 : Type A

1 : Type B

LCD circuit divider division ratio selection bits

b6b5

0 0 : Clock input

0 1 : 2 division of clock input

1 0 : 4 division of clock input

1 1 : 8 division of clock input

LCDCK count source selection bit (Note 3)

0 : f(XCIN)/32

1 : φSOURCE/8192

Segment output disable register 0

(SEG0 : address 0FF416)

b7 b0

Segment output disable bit 0

0 : Segment output SEG0

1 : Output port P00

Segment output disable bit 1

0 : Segment output SEG1

1 : Output port P01

Segment output disable bit 2

0 : Segment output SEG2

1 : Output port P02

Segment output disable bit 3

0 : Segment output SEG3

1 : Output port P03

Segment output disable bit 4

0 : Segment output SEG4

1 : Output port P04

Segment output disable bit 5

0 : Segment output SEG5

1 : Output port P05

Segment output disable bit 6

0 : Segment output SEG6

1 : Output port P06

Segment output disable bit 7

0 : Segment output SEG7

1 : Output port P07

Segment output disable register 1

(SEG1 : address 0FF516)

b7 b0

Segment output disable bit 8

0 : Segment output SEG8

1 : Output port P10

Segment output disable bit 9

0 : Segment output SEG9

1 : Output port P11

Segment output disable bit 10

0 : Segment output SEG10

1 : Output port P12

Segment output disable bit 11

0 : Segment output SEG11

1 : Output port P13

Segment output disable bit 12

0 : Segment output SEG12

1 : Output port P14

Segment output disable bit 13

0 : Segment output SEG13

1 : Output port P15

Segment output disable bit 14

0 : Segment output SEG14

1 : Output port P16

Segment output disable bit 15

0 : Segment output SEG15

1 : Output port P17

Segment output disable register 2

(SEG2 : address 0FE616)

b7 b0

Segment output disable bit 16

0 : Segment output SEG16

1 : Output port P20

Segment output disable bit 17

0 : Segment output SEG17

1 : Output port P21

Segment output disable bit 18

0 : Segment output SEG18

1 : Output port P22

Segment output disable bit 19

0 : Segment output SEG19

1 : Output port P23

Segment output disable bit 20

0 : Segment output SEG20

1 : Output port P24

Segment output disable bit 21

0 : Segment output SEG21

1 : Output port P25

Segment output disable bit 22

0 : Segment output SEG22

1 : Output port P26

Segment output disable bit 23

0 : Segment output SEG23

1 : Output port P27

Notes 1: Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable

2: When the VL pin input selection bit (VLSEL) of the LCD power control register (address 003816) is “1”, settings of the segment output disable bit 22 and

segment output disable bit 23 are invalid.

3: LCDCK is a clock for an LCD timing controller.

φ SOURCE represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode.

(1)

(1)(1)

Rev.3.02 Apr 10, 2008 Page 47 of 131

REJ03B0177-0302

38D2 Group

Fig. 39 Block diagram of LCD controller/driver

Data bus

Timing controller

LCD

divider

f(XCIN)/32

φSOURCE/8192

Level

shift

Level

shift

Level

shift

Level

shift

Bias control

Selector Selector Selector Selector Selector Selector

Level

shift

Level

shift

Level

shift

Level

shift

Level

shift

Level

shift

Segment

driver

Segment

driver

Segment

driver

COM0COM1COM2COM3

VSS

P27/SEG23/VL2 VL3

P26/SEG22/VL1P03/SEG3P02/SEG2P01/SEG1P00/SEG0

Address 004016 Address 004116

P20/SEG16

“0”

“1”

LCDCK

LCDCK count source

selection bit

LCD circuit

divider division

ratio selection bits

Bias control bit

LCD enable bit

Duty ratio selection bits

LCD display RAM

Segment

driver

Segment

driver

Segment

driver

LCD power

control register

P27/

VL2

SEG23/

P26/

VL1

SEG22/

Address 004C16

Notes 1: φ SOURCE represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and sub clock in the low-speed mode.

Common

driver

Common

driver

Common

driver

Common

driver

Rev.3.02 Apr 10, 2008 Page 48 of 131

REJ03B0177-0302

38D2 Group

• Bias Control and Applied Voltage to LCD Power Input

Pins

When the voltage is applied from the LCD power input pins

(VL1−VL3), set the VL pin input selection bit (bit 5 of the LCD

power control register) and VL3 connection bit (bit 6 of LCD

power control register) to “1”, apply the voltage value shown in

Table 12 according to the bias value. In this case, SEG22 pin and

SEG23 pin cannot be used.

Select a bias value by the bias control bit (bit 2 of the LCD mode

Note: VLCD is the maximum value of supplied voltage for the

LCD panel.

• Common Pin and Duty Ratio Control

The common pins (COM0−COM3) to be used are determined by

duty ratio. Select duty ratio by the duty ratio selection bits (bits 0

and 1 of the LCD mode register). When reset is released, VCC

voltage is output from the common pin.

Note: Unused common pin outputs the unselected waveform.

• Segment Signal Output Pin

The segment signal output pins (SEG0−SEG23) are shared with

ports P0−P2. When these pins are used as the segment signal

output pins, set the direction registers of the corresponding pins

to “1”, and set the segment output disable register to “0”.

Also, these pins are set to the input port after reset, the VCC

voltage is output by the pull-up resistor.

Fig. 40 Example of circuit at each bias (at external power input)

Table 12 Bias control and applied voltage to VL1−VL3

Bias value Voltage value

1/3 bias

VL3 = VLCD

VL2 = 2/3 VLCD

VL1 = 1/3 VLCD

1/2 bias VL3 = VLCD

VL2 = VL1 = 1/2 VLCD

Table 13 Duty ratio control and common pins used

Duty

ratio

Duty ratio selection bits Common pins used

Bit 1 Bit 0

20 1COM

0, COM1

31 0COM0−COM2

41 1COM0−COM3

R4 = R5

Contrast adjust

1/2 bias

Contrast adjust

R1 = R2 = R3

1/3 bias

VL1

VL3

VL2

VL1

VL3

VL2

Rev.3.02 Apr 10, 2008 Page 49 of 131

REJ03B0177-0302

38D2 Group

• LCD Power Circuit

The LCD power circuit has the dividing resistor for LCD power

which can be connected/disconnected with the LCD power

control register.

To use the LCD, apply a voltage externally to the VL3 pin and set

the VL3 connect bit to “1”. An external voltage should be applied

even if a voltage equivalent to VCC is used for the VL3 pin. When

the LCD is not used, perform either of the following.

• Set the VL3 connect bit to “0” and leave the VL3 pin open.

•Set the V

L3 connect bit to “1” and apply a VCC level to VL3

pin.

Fig. 41 Structure of LCD power control register

Fig. 42 VL block diagram

Dividing resistor for LCD power control bit (LCDRON)

0 : Internal dividing resistor disconnected from LCD power circuit

1 : Internal dividing resistor connected to LCD power circuit

LCD power control register

(VLCON : address 001416)

b7 b0

VL pin input selection bit (VLSEL) (Note 2)

0 : Input invalid

1 : VL input function valid

Not used (Do not write to “1”.)

Dividing resistor for LCD power selection bits (RSEL) (Note 1)

b2b1

1 0 :

0 1 :

0 0 :

1 1 :

VL3 connection bit

0 : Connect LCD internal VL3 to VCC

1 : Connect LCD internal VL3 to VL3 pin

Notes 1: When voltage is applied to VL1 to VL3 by using the external resistor, write “102” to dividing resistor

for LCD power selection bits.

2: Setting to the VL pin input selection bit (VLSEL) = “1” has the most priority than setting to the port

P2 direction register (address 000516) and segment output disable register 2 (address 0FF616).

Larger resistor

Smaller resistor

Not used (Do not write to “1”.)

VL3

P27/SEG23/VL2

Bias control bit

(LCD mode register)

P26/SEG22/VL1

VL pin input

selection bit Dividing resistor for LCD

power control bit

Vcc

Dividing resistor

for LCD power

Dividing resistor for LCD

power selection bits

VL3 connection bit

LCD internal VL3

LCD internal VL2

LCD internal VL1

Rev.3.02 Apr 10, 2008 Page 50 of 131

REJ03B0177-0302

38D2 Group

• LCD Display RAM

The 12-byte area of address 004016 to 004B16 is the designated

RAM for the LCD display. When “1” is written to these

addresses, the corresponding segments of the LCD display panel

are turned on.

• LCD Drive Timing

For the LCD drive timing, type A or type B can be selected.

The LCD drive timing is selected by the timing selection bit (bit

4 of LCD mode register).

Type A is selected by setting the LCD drive timing selection bit

to “0”, type B is selected by setting the bit to “1”. Type A is

selected after reset.

The LCDCK timing frequency (LCD drive timing) is generated

internally and the frame frequency can be determined with the

following equation;

f(LCDCK) =

Frame frequency =

<Notes>

(1) When the STP instruction is executed, the following bits are

set to “0”;

• LCD enable bit (bit 3 of LCD mode register)

• Bits other than bit 6 of the LCD power control register.

And the LCD panel turns off.

To make the LCD panel turn on after returning from the stop

mode, set these bits to “1”.

(2) When the voltage is applied to VL1 to VL3 by using the

external resistor, write “102” to dividing resistor for LCD

power selection bits (RSEL) of the LCD power control

(3) When the LCD drive control circuit is used at VL3 = VCC,

apply VCC to VL3 pin and write “1” to VL3 connection bit of

the LCD power control register (address 003816).

Fig. 43 LCD display RAM map

(frequency of count source for LCDCK)

(divider division ratio for LCD)

f(LCDCK)

duty ratio

Bit

Address

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

SEG1

SEG3

SEG5

SEG7

SEG9

SEG11

SEG13

SEG15

SEG17

SEG19

SEG21

SEG23

SEG0

SEG2

SEG4

SEG6

SEG8

SEG10

SEG12

SEG14

SEG16

SEG18

SEG20

SEG22

7654 32

COM3COM2COM1COM0COM3COM2COM1COM0

Rev.3.02 Apr 10, 2008 Page 51 of 131

REJ03B0177-0302

38D2 Group

Fig. 44 LCD drive waveform (1/2 bias, type A)

Internal signal

LCDCK timing

1/4 duty Voltage level

VL3

VL2=VL1

VSS

VL3

VSS

COM0

COM1

COM2

COM3

SEG0

OFF ON OFF ON

COM3COM2COM1COM0COM3COM2COM1COM0

1/3 duty

VL3

VL2=VL1

VSS

VL3

VSS

OFF

ON ON OFF ON OFF

1/2 duty

COM0

COM1

COM2

SEG0

COM0

COM1

SEG0

VL3

VL2=VL1

VSS

VL3

VSS

OFF

ON OFF

COM0COM2COM1COM0COM2COM1COM0COM2

COM1COM0COM1COM0COM1COM0COM1COM0

LCD

Rev.3.02 Apr 10, 2008 Page 52 of 131

REJ03B0177-0302

38D2 Group

Fig. 45 LCD drive waveform (1/3 bias, type A)

Internal signal

LCDCK timing

1/4 duty

Voltage level

VL3

VSS

COM0

COM1

COM2

COM3

SEG0

OFF ON OFF ON

COM3COM2COM1COM0COM3COM2COM1COM0

1/3 duty

OFFON ON OFF ON OFF

1/2 duty

COM0

COM1

COM2

SEG0

COM0

COM1

SEG0

OFFON OFFON OFFON OFFON

VL3

VL2

VSS

VL1

VL3

VL2

VSS

VL1

VL3

VSS

VL3

VL2

VSS

VL1

VL3

VSS

COM0COM2COM1COM0COM2COM1COM0COM2

COM1COM0COM1COM0COM1COM0COM1COM0

LCD

Rev.3.02 Apr 10, 2008 Page 53 of 131

REJ03B0177-0302

38D2 Group

Fig. 46 LCD drive waveform (1/2 bias, type B)

Internal signal

LCDCK timing

1/4 duty

Voltage level

COM0

COM1

COM2

COM3

SEG0

OFF ON OFF ON

COM3COM2COM1COM0COM3COM2COM1COM0

1/3 duty

OFFON ON OFF ON OFF

1/2 duty

COM0

COM1

COM2

SEG0

COM0

COM1

SEG0

OFFON OFFON OFFON OFFON

VL3

VL2=VL1

VSS

COM0COM2COM1COM0COM2COM1COM0COM2

COM1COM0COM1COM0COM1COM0COM1COM0

1 frame 1 frame

1 frame 1 frame 1 frame 1 frame

1 frame 1 frame

VL3

VSS

VL3

VSS

VL3

VSS

VL3

VL2=VL1

VSS

VL3

VL2=VL1

VSS

LCD

Rev.3.02 Apr 10, 2008 Page 54 of 131

REJ03B0177-0302

38D2 Group

Fig. 47 LCD drive waveform (1/3 bias, type B)

Internal signal

LCDCK timing

1/4 duty

Voltage level

COM0

COM1

COM2

COM3

SEG0

OFF ON OFF ON

COM3COM2COM1COM0COM3COM2COM1COM0

1/3 duty

OFFON ON OFF ON OFF

1/2 duty

COM0

COM1

COM2

SEG0

COM0

COM1

SEG0

OFFON OFFON OFFON OFFON

VL3

VL2

VSS

VL1

VL3

VL2

VSS

VL1

VL3

VL2

VSS

VL1

COM0COM2COM1COM0COM2COM1COM0COM2

COM1COM0COM1COM0COM1COM0COM1COM0

1 frame 1 frame

1 frame 1 frame 1 frame 1 frame

1 frame 1 frame

VL3

VL2

VSS

VL1

VL3

VL2

VSS

VL1

VL3

VL2

VSS

VL1

LCD

Rev.3.02 Apr 10, 2008 Page 55 of 131

REJ03B0177-0302

38D2 Group

ROM CORRECTION FUNCTION

A part of program in ROM can be corrected.

Set the start address of the corrected ROM data (i.e. an Op code

address of the beginning instruction) to the ROM correction

address high-order and low-order registers.

When the program is being executed and the value of the

program counter matches with the set address value in the ROM

correction address registers, the program is branched to the ROM

correction vectors and then the correction program can be

executed by setting it to the ROM correction vectors.

Use the JMP instruction (3-byte instruction) to return the main

program from the correction program.

The correctable area is up to two. There are two vectors for ROM

correction.

Also, ROM correction vector can be selected from the RAM area

or ROM area by the ROM correction memory selection bit.

The ROM correction function is controlled by the ROM

correction address 1 enable bit and ROM correction address 2

enable bit.

If the ROM correction function is not used, the ROM correction

vector may be used as normal RAM/ROM. When using the

ROM correction vector as normal RAM/ROM, make sure to set

bits 1 and 0 in the ROM correction enable register to “0”

(Disable).

<Notes>

1. When using the ROM correction function, set the ROM cor-

rection address registers and then enable the ROM correc-

tion with the ROM correction enable register.

2. Do not set addresses other than the ROM area in the ROM

correction address registers.

Do not set the same ROM correction addresses in both the

ROM correction address registers 1 and ROM correction

address registers 2.

3. It is necessary to contain the process for ROM correction in

the program.

Fig. 48 ROM correction address register

Fig. 49 Memory map of M38D24G4

Fig. 50 Structure of ROM correction enable register

RAM area

RC2 = “0”

ROM area

RC2 = “1”

Vector 1 address 010016 address F10016

Vector 2 address 012016 address F12016

0FF816

ROM correction address 1 high-order register (RCA1H)

ROM correction address 1 low-order register (RCA1L)

ROM correction address 2 high-order register (RCA2H)

ROM correction address 2 low-order register (RCA2L)

0FF916

0FFA16

0FFB16

Note: Do not set address other than ROM area.

C08016

SFR area

Interrupt vector area

Reserved ROM area

010016

000016

004016

012016

FF0016

FFFF16

Zero

page

Special

page

02BF16

EFFF16

RAM

ROM

Protect

area 1

F12016

FFDB16 Reserved ROM area

C00016

F10016

ROM correction vector 1

ROM correction vector 2

ROM correction vector 1

ROM correction vector 2

ROM correction address 1 enable bit (RC0)

0 : Disable

1 : Enable

ROM correction address 2 enable bit (RC1)

0 : Disable

1 : Enable

ROM correction memory selection bit (RC2)

0 : Branch to the RAM area

1 : Branch to the ROM area

Not used (returns “0” when read)

ROM correction enable register (Address 0FFC16)

RCR

b7 b0

Note: After ROM correction address register is set,

set the ROM correction address enable bit to be enabled.

Rev.3.02 Apr 10, 2008 Page 56 of 131

REJ03B0177-0302

38D2 Group

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example,

because of a software run-away). The watchdog timer consists of

an 8-bit counter.

• Initial Value of Watchdog Timer

At reset or writing to the watchdog timer control register, each

watchdog timer is set to “FF16”. Instructions such as STA, LDM

and CLB to generate the write signals can be used.

The written data in bits 7, 6 or 5 are not valid, and the above

values are set.

Bits 7 to 5 can be rewritten only once after releasing reset.

After rewriting it is disable to write any data to this bit. This bit

becomes “0” after reset.

• Standard Operation of Watchdog Timer

The watchdog timer is in the stop state at reset and the watchdog

timer starts to count down by writing an optional value in the

watchdog timer control register. An internal reset occurs at an

underflow of the watchdog timer. Then, reset is released after the

reset release time is elapsed, the program starts from the reset

vector address.

Normally, writing to the watchdog timer control register before

an underflow of the watchdog timer is programmed. If writing to

the watchdog timer control register is not executed, the watchdog

timer does not operate.

When reading the watchdog timer control register is executed,

the contents of the high-order 5-bit counter, the count source

selection bit 2 (bit 5), the STP instruction function selection bit

(bit 6), and the count source selection bit (bit 7) are read out.

• Bit 6 of Watchdog Timer Control Register

1. When bit 6 of the watchdog timer control register is “0”, the

MCU enters the stop mode by execution of STP instruction.

Just after releasing the stop mode, the watchdog timer

restarts counting (Note 1). When executing the WIT

instruction, the watchdog timer does not stop.

2. When bit 6 is “1”, execution of STP instruction causes an

internal reset. When this bit is set to “1” once, it cannot be

rewritten to “0” by program. Bit 6 is “0” at reset.

3. The time until the underflow of the watchdog timer register

after writing to the watchdog timer control register is exe-

cuted is as follows (when the bit 7 of the watchdog timer

control register is “0”);

4. at XIN mode (f(XIN)) = 8 MHz): 32.768 ms

5. at low-speed mode (f(XCIN) = 32 KHz): 8.19s

<Notes>

1. The watchdog timer continues to count even during the wait

time set by timer 1 and timer 2 to release the stop state and

in the wait mode. Accordingly, write to the watchdog timer

control register to not underflow the watchdog timer in this

time.

2. When the on-chip oscillator is selected by the watchdog

timer count source selection bit 2, the on-chip oscillator

forcibly oscillates and it cannot be stopped. Also, in this

time, set the STP instruction function selection bit to “1” at

this time.

Select “0” (φSOURCE) the watchdog timer count source

selection bit 2 at the system which on-chip oscillator is

stopped.

Fig. 51 Block diagram of watchdog timer

Fig. 52 Structure of watchdog timer control register

1/1024

Watchdog

timer H (5)

Watchdog timer

count source

selection bit

Reset

circuit

“FF16” is set when

watchdog timer

control register is

written to.

Internal reset

Wait until reset release

Watchdog

timer L (3)

1/4

“0”

“1”

φ SOURCE

“0”

“1”

On-chip oscillator 1/4

Watchdog timer count

sourse selection bit 2

Data bus

Note1: φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the on-chip oscillator mode

•Sub-clock in the low-speed mode

(1)

STP instruction function selection bit

Undefined instruction

Reset

STP instruction

RESET

Watchdog timer H (for read-out of high-order 5 bit)

“FF16” is set to watchdog timer by writing to these bits.

Watchdog timer count source selection bit 2

0 : φSOURCE

1 : On-chip oscillator/4

Watchdog timer control register

(WDTCON : address 002916)

b7 b0

Watchdog timer count source selection bit

0 : Count source/1024

1 : Count source/4

STP instruction function selection bit

0 : Entering stop mode by execution of STP instruction

1 : Internal reset by execution of STP instruction

Notes 1: φSOURCE indicates the followings:

•XIN input in the frequency/2, 4 , or 8 mode

•On-chip oscillator divided by 4 in the on-chip

oscillator mode

•Sub-clock in the low-speed mode

2: When the on-chip oscillator is selected by the

watchdog timer count source selection bit 2,

set the STP instruction function selection bit

to “1”.

Select φ(SOURCE) as the count source at the

system which on-chip oscillator is stopped.

3: Bits 7 to 5 can be rewritten only once after reset.

After rewriting it is disable to write any data to this bit.

(1)

Rev.3.02 Apr 10, 2008 Page 57 of 131

REJ03B0177-0302

38D2 Group

CLOCK OUTPUT FUNCTION

A system clock φ can be output from I/O port P36. The triple

function of I/O port, timer 2 output function and system clock φ

output function is performed by the clock output control register

(address 0FF316) and the timer 2 output selection bit of the timer

12 mode register (address 002516).

In order to output a system clock φ from I/O port P36, set the

timer 2 output selection bit and bit 0 of the clock output control

When the clock output function is selected, a clock is output

while the direction register of port P36 is set to the output mode.

P36 is switched to the port output or the output (timer 2 output

and the clock output) except port at the cycle after the timer 2

output control bit is switched. Fig. 53 Structure of clock output control register

Fig. 54 Block diagram of clock output function

Other function registers

[RRF register (RRFR)]

The RRF register (address 001216) is the 8-bit register and does

not have the control function.

As for the value written in this register, high-order 4 bits and

low-order 4 bits interchange.

It is initialized after reset.

Fig. 55 Structure of RRF register

b7 b0

Clock output control register

(CKOUT : address 0FF316)

P36 clock output control bit

0 : Timer 2 output

1 : System clock φ output

Not used (returns “0” when read)

Not used (Do not write “1” to these bits.)

Timer 2 latch (8)

Timer 2 (8) 1/2

T2OUT output edge

switch bit

P36 clock output control bit

“0”

“1”

P36 latch

Timer 2 output selection bit

P36 direction register

P36/T2OUT/CKOUT

b7 b0

Timer 12 mode register (address 002516)

T12M

Timer 2 output selection bit

0 : I/O port

1 : Timer 2 output

System clock φ

Timer 2 output control bit

“0”

“1”

b7 b0

RRF register

DB4 data storage

DB5 data storage

DB6 data storage

DB7 data storage

DB0 data storage

DB1 data storage

DB2 data storage

DB3 data storage

(RRFR : address 001216)

Rev.3.02 Apr 10, 2008 Page 58 of 131

REJ03B0177-0302

38D2 Group

RESET CIRCUIT

To reset the microcomputer, RESET pin should be held at an “L”

level for 2 μs or more. Then the RESET pin is returned to an “H”

level (the power source voltage should be between VCC (min.)

and 5.5 V), reset is released.

After the reset is completed, the program starts from the address

contained in address FFFD16 (high-order byte) and address

FFFC16 (low-order byte). Make sure that the reset input voltage

meets VIL spec. When a power source voltage passes VCC (min.).

In the flash memory version, input to the RESET pin in the

following procedure.

• When power source is stabilized

(1) Input “L” level for 2μs or more to RESET pin.

(2) Input “H” level to RESET pin.

• At power-on

(1) Input “L” level to RESET pin.

(2) Increase the power source voltage to 2.7 V.

(3) Wait for td(P-R) until internal power source has stabilized.

(4) Input “H” level to RESET pin.

In the QzROM version, the input level applied to the OSCSEL

pin is determined when the RESET pin changes from “L” to “H”.

Fig. 56 Reset circuit example

Fig. 57 Reset sequence

VCC

Power source

voltage detection

circuit

RESET

VCC

RESET

0 V

VCC

RESET

0.2VCC or less

0 V

VCC

RESET

td(P-R) or more

5 V

2.7 V

(1)

Note 1: QzROM version: 2 μs or more

Flash memory version: td(P-R) or more

VCC (min.)

RESET

Internal

reset

Address

Data

SYNC

System clock φ

OSCSEL=L: OCO

OSCSEL=H: XIN

FFFC FFFD ADH, ADL

ADLADH

????

Reset address from

vector table

······

OSCSEL=L: OCO= about 32768 cycles

OSCSEL=H: XIN= about 8192 cycles

Notes 1: The frequency of system clock φ is f(OCO)/32 or f(XIN)/8.

2: The question marks (?) indicate an undefined state.

3: In the QzROM version, the input level applied to the OSCSEL pin is determined when the RESET pin changes from “L” to “H”.

Rev.3.02 Apr 10, 2008 Page 59 of 131

REJ03B0177-0302

38D2 Group

Fig. 58 Internal status at reset

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

001016

001116

001216

001316

001416

001516

001916

001A16

001B16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

Address

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

0FF016

0FF116

0FF316

0FF416

0FF516

0FF616

0FF716

0FF816

0FF916

0FFA16

0FFB16

0FFC16

(PS)

(PCH)

(PCL)

Port P0

Port P0 direction register

Port P1

Port P1 direction register

Port P2

Port P2 direction register

Port P3

Port P3 direction register

Port P4

Port P4 direction register

Port P5

Port P5 direction register

Port P6

Port P6 direction register

Oscillation output control register

CPU mode register 2

RRF register

LCD mode register

LCD power control register

AD control register

Serial I/O1 status register

Serial I/O1 control register

UART1 control register

Serial I/O2 status register

Serial I/O2 control register

Timer 1

Timer 2

Timer 3

Timer 4

PWM01 register

Timer 12 mode register

Timer 34 mode register

Timer 1234 mode register

Timer 1234 frequency division

selection register

Watchdog timer control register

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

(33)

(34)

(35)

Timer X (low-order)

Timer X (high-order)

Timer X (extension)

Timer X mode register

Timer X control register 1

Timer X control register 2

Compare register 1 (low-order)

Compare register 1 (high-order)

Compare register 2 (low-order)

Compare register 2 (high-order)

Compare register 3 (low-order)

Compare register 3 (high-order)

Timer Y (low-order)

Timer Y (high-order)

Timer Y mode register

Timer Y control register

Interrupt edge selection register

CPU mode register

Interrupt request register 1

Interrupt request register 2

Interrupt control register 1

Interrupt control register 2

PULL register

UART2 control register

Clock output control register

Segment output disable register 0

Segment output disable register 1

Segment output disable register 2

Key input control register

ROM correction address 1

high-order register (RCA1H)

ROM correction address 1

low-order register (RCA1L)

ROM correction address 2

high-order register (RCA2H)

ROM correction address 2

low-order register (RC2AL)

ROM correction enable register

Processor status register

Program counter

(36)

(37)

(38)

(39)

(40)

(41)

(42)

(43)

(44)

(45)

(46)

(47)

(48)

(49)

(50)

(51)

(52)

(53)

(54)

(55)

(56)

(57)

(58)

(59)

(60)

(61)

(62)

(63)

(64)

(65)

(66)

(67)

(68)

(69)

(70)

(71)

0016

0816

0016

FF16

0116

FF16

0016

Address

00000 0*0

00011 111

10000 000

11100 000

FF16

0016

FF16

0016

FF16

0016

*1*00 000

×1

FFFD16 contents

FFFC16 contents

10000 00011100 000

×××× ××

×: Not fixed

*: Depends on OSCSEL setting at the QzROM version.

In the flash memory version, the CPU mode register 2 (address 001116), is set to “0016” and the CPU mode register (address 003B16) is set to “E016”.

Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.

Rev.3.02 Apr 10, 2008 Page 60 of 131

REJ03B0177-0302

38D2 Group

CLOCK GENERATING CIRCUIT

The oscillation circuit of 38D2 Group can be formed by

connecting an oscillator, capacitor and resistor between XIN and

XOUT (XCIN and XCOUT). To supply a clock signal externally,

input it to the XIN pin and make the XOUT pin open. The clocks

that are externally generated cannot be directly input to XCIN.

Use the circuit constants in accordance with the oscillator

manufacturer's recommended values. No external resistor is

needed between XIN and XOUT since a feed-back resistor exists

on-chip. (An external feed-back resistor may be needed

depending on conditions.) However, an about 10 MΩ external

feedback resistor is needed between XCIN and XCOUT.

The 38D2 Group operation mode immediately after reset

depends on the OSCSEL pin state in the QzROM version.

When the OSCSEL pin state is GND level, the only on-chip

oscillator starts oscillating. The XIN-XOUT oscillation stops

oscillating, and XCIN and XCOUT pins function as I/O ports.

Flash memory version as same.

When the OSCSEL pin state is VCC level, the XIN-XOUT

oscillation divided by 8 starts oscillating. The on-chip oscillator

stops oscillating, and the XCIN and XCOUT pins function as I/O

ports.

Note the following in each mode.

•X

IN Mode

The XIN-XOUT oscillation does not stop even if the XIN-XOUT

oscillation stop bit is set to “1”.

• Low-Speed Mode

The XCIN-XCOUT oscillation stops if the port XC switch bit is set

to “0”.

• On-Chip Oscillator Mode

Even if the on-chip oscillator stop bit is set to “1”, the on-chip

oscillator oscillation does not stop in the flash memory version,

but stops in the QzROM version.

• Frequency Control

(1) On-chip oscillation mode

The system clock φ is the on-chip oscillator oscillation divided

by 32.

(2) XIN mode

Frequency/2 mode, frequency /4 mode, and frequency/8 mode

are collectively referred as XIN mode.

- Frequency/8 Mode

The system clock φ is the frequency of XIN divided by 8.

- Frequency/4 Mode

The system clock φ is the frequency of XIN divided by 4.

- Frequency/2 Mode

The system clock φ is half the frequency of XIN.

(3)Low-speed Mode

The system clock φ is half the frequency of sub clock.

After reset and when system returns from the stop mode, the

operation mode depends on the OSCSEL pin state in the

QzROM version and the flash memory version operation mode is

the on-chip oscillator mode.

When the RESET pin changes from “L” to “H” and when the

STP instruction is executed, determine the input level applied to

the OSCSEL pin.

Refer to the clock state transition diagram for the setting of

transition to each mode.

The XIN-OUT oscillation is controlled by the bit 5 of CPUM, and

the sub-clock oscillation is controlled by the bit 4 of CPUM and

the on-chip oscillator oscillation is controlled by the bit 0 of

CPUM2.

In the on-chip oscillator mode, the oscillation by the oscillator

can be stopped. In the low-speed mode, the power consumption

can be reduced by stopping the XIN−XOUT oscillation.

In low-speed mode, the on-chip oscillator stops in the QzROM

version regardless of the on-chip oscillator stop bit value. The

on-chip oscillator does not stop in the flash memory version, so

set the on-chip oscillator stop bit to “1” to stop the oscillation.

Set enough time for oscillation to stabilize by programming to

restart the stopped oscillation and switch the operation mode.

Also, set enough time for oscillation to stabilize by programming

to switch the timer count source.

If you switch the mode between on-chip oscillator mode, XIN

mode and low-speed mode, stabilize both XIN and XCIN

oscillations. Especially be careful immediately after power-on

and at returning from stop mode. Refer to the clock state

transition diagram for the setting of transition to each mode. Set

the frequency in the condition that f(XIN) > 3•f(XCIN).

When the XIN mode is not used (XIN-XOUT oscillation and

external clock input are not performed), connect XIN to VCC

through a resistor.

Rev.3.02 Apr 10, 2008 Page 61 of 131

REJ03B0177-0302

38D2 Group

• Oscillation Control

(1) Stop Mode

If the STP instruction is executed, the system clock φ stops at an

“H” level, and main clock and sub-clock oscillators stop.

In this time, values set previously to timer 1 latch and timer 2 latch

are loaded automatically to timer 1 and timer 2. Set the values * to

generate the wait time required for oscillation stabilization to

timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and

high-order 8 bits of timer 2) before the STP instruction.

The frequency divider for timer 1 is used for the timer 1 count

source, and the output of timer 1 is forcibly connected to timer 2. In

this time, bits 0 to 5 of the timer 12 mode register are cleared to “0”.

The values of the timer 1234 frequency divider selection register

are not changed.

Set the interrupt enable bits of the timer 1 and timer 2 to be

disabled (“0”) before executing the STP instruction.

Reference (Set values according to your oscillator and system.)

OSCSEL = “L” of the QzROM version and flash memory

version:

.......................................................................... 000516 or more

OSCSEL = “H” of the QzROM version:

..........................................................................01FF16 or more

When an external interrupt is received, the clock set according to

the OSCSEL pin state starts oscillating in the QzROM version.

The operation mode at returning is decided by the clock that set

according to the OSCSEL pin state.

Bits 3, 5, 6, and 7 of CPUM and bit 0 of CPUM2 are forcibly

changed by the OSCSEL pin state. In the flash memory version,

the on-chip oscillator starts oscillating and the operation mode at

returning is set to on-chip oscillator mode. The bit 3 of CPUM is

changed to “0”, bits 5, 6 and 7 of CPUM are changed to “1”, and

the bit 0 of CPUM2 is changed to “0” forcibly.

Oscillator restarts when reset occurs or an interrupt request is

received, but the system clock φ is not supplied to the CPU until

timer 2 underflows. This allows time for the clock circuit

oscillation to stabilize.

(2) Wait Mode

If the WIT instruction is executed, only the system clock φ stops

at an “H” state. The states of main clock, on-chip oscillator and

sub clock are the same as the state before executing the WIT

instruction, and oscillation does not stop. Since supply of system

clock φ is started immediately after the interrupt is received, the

instruction can be executed immediately.

Fig. 59 Ceramic resonator circuit example

Fig. 60 External clock input circuit

XCIN XCOUT XIN XOUT

CIN COUT

CCIN CCOUT

Rf Rd

Note : Insert a damping resistor if required.

The resistance will vary depending on the

oscillator and the oscillation drive capacity

setting.

Use the value recommended by the maker

of the oscillator.

Also, if the oscillator manufacturer's data

sheet specifies that a feedback resistor be

added external to the chip though a

feedback resistor exists on-chip, insert a

feedback resistor between XIN and XOUT

following the instruction.

XCIN XCOUT XIN XOUT

External oscillation circuit

Open

VCC

VSS

CCIN

Rf Rd

CCOUT

Rev.3.02 Apr 10, 2008 Page 62 of 131

REJ03B0177-0302

38D2 Group

Fig. 61 Clock generating circuit block diagram

System clock φ

Interrupt request

Interrupt disable flag I

Reset

WIT

instruction

STP instruction

XIN-XOUT

oscillation stop bit

CPUM BIT5

XIN XOUT

XCOUT

XCIN

Timer 1 count source

selection bits

Port Xc switch bit

CPUM BIT4

“00”

“01”

“10”

“11”

Main clock division

ratio selection bit

CPUM BIT7, 6

On-chip oscillator

Internal system clock

selection bit

CPUM BIT3

1/2 1/2

Internal system clock selection bit

“0”

“1”

STP instruction

“1”

“0”

Timer 1

Timer 2

“01”

“00”

Frequency divider

for Timer

Timer 2 count source

selection bits

“00”

“10”

(2)

1/4

1/2

“0”

“1”

“0”

CPUM2 BIT0

On-chip oscillator stop bit

Main clock

division ratio

selection bit

Notes 1: When the XCIN-XCOUT oscillation is selected as the system clock, set the port Xc

switch bit to “1”.

2: Although a feed-back resistor exists on-chip, an external

feed-back resistor may be needed depending on conditions.

3:φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the on-chip oscillator mode

•Sub-clock in the low-speed mode

However, when used as the A/D conversion clock by the A/D converter,

φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the low-speed or the on-chip oscillator mode

φSOURCE

CPUM BIT6

(1)

(3)

Rev.3.02 Apr 10, 2008 Page 63 of 131

REJ03B0177-0302

38D2 Group

Fig. 62 State transitions of system clock

Frequency/2 mode

CM4

XIN oscillation (frequency/2)

XCIN oscillation

OCO oscillation or stop

φ=f(XIN)/2

CM7=0

CM6=0

CM5=0

CM4=1

CM3=0 CM8=*

Frequency/8 mode

CM4

CM5

CM5 CM5

XIN stop

XCIN oscillation

OCO stop

φ =f(XCIN)/2

CM7=1 (invalid)

CM6=1 (invalid)

CM5=1

CM4=1

CM3=1 CM8=1

CM5

(CM7)

CM3, CM8

(6)

On-chip oscillator mode Low-speed mode

(6) CM7 (6) CM7

XIN oscillation

XCIN oscillation

OCO stop

φ =f(XCIN)/2

CM7=0 (invalid)

CM6=1 (invalid)

CM5=0

CM4=1

CM3=1 CM8=1

XIN stop

XCIN oscillation

OCO oscillation

φ =f(OCO)/32

CM7=1

CM6=1

CM5=1

CM4=1

CM3=0 CM8=0

XIN oscillation

XCIN oscillation

OCO oscillation

φ=f(OCO)/32

CM7=1

CM6=1

CM5=0

CM4=1

CM3=0 CM8=0

XIN oscillation

XCIN stop

OCO oscillation

φ=f(OCO)/32

CM7=1

CM6=1

CM5=0

CM4=0

CM3=0 CM8=0

XIN stop

XCIN stop

OCO oscillation

φ =f(OCO)/32

CM7=1

CM6=1

CM5=1

CM4=0

CM3=0 CM8=0

CM3, CM7,

CM8

(6)

CM4

XIN oscillation (frequency/8)

XCIN oscillation

OCO oscillation or stop

φ=f(XIN)/8

CM7=0

CM6=1

CM5=0

CM4=1

CM3=0 CM8=*

XIN oscillation (frequency/8)

XCIN stop

OCO oscillation or stop

φ=f(XIN)/8

CM7=0

CM6=1

CM5=0

CM4=0

CM3=0 CM8=*

CM6 CM6

Reset release

Frequency/4 mode

CM4

XIN oscillation (frequency/4)

XCIN oscillation

OCO oscillation or stop

φ=f(XIN)/4

CM7=1

CM6=0

CM5=0

CM4=1

CM3=0 CM8=*

XIN oscillation

XCIN oscillation

OCO stop

φ =f(XCIN)/2

CM7=0 (invalid)

CM6=0 (invalid)

CM5=0

CM4=1

CM3=1 CM8=1

XIN oscillation

XCIN oscillation

OCO stop

φ =f(XCIN)/2

CM7=1 (invalid)

CM6=0 (invalid)

CM5=0

CM4=1

CM3=1 CM8=1

CM6

XIN oscillation (frequency/2)

XCIN stop

OCO oscillation or stop

φ=f(XIN)/2

CM7=0

CM6=0

CM5=0

CM4=0

CM3=0 CM8=*

XIN oscillation (frequency/4)

XCIN stop

OCO oscillation or stop

φ=f(XIN)/4

CM7=1

CM6=0

CM5=0

CM4=0

CM3=0 CM8=*

* : The OCO oscillating at “0”; the OCO stopped at “1”.

CM6

CM7

CM3

CM6

CM7

CM3

CM6

(CM7)

CM6

CM5

(CM7)

CM6

CM5

CM3

Notes 1:Switchthemodebythearrowsshownbetweenthemodeblocks.

Theallmodescanbeswitchedtothestopmodeorthewaitmode.

2: Timer and LCD operate in the wait mode. System is returned to the

source mode when the wait mode is ended.

3: The CM4 value is retained in the stop mode. When the stop mode is

ended, the operation mode varies as follows:

In the QzROM version: Mode set by the OSCSEL pin state

In the flash memory version: On-chip oscillator mode

The input level applied to the OSCSEL pin is determined when executing

the STP instruction.

4: Before executing the STP instruction, set the values to generate the

wait time required for oscillation stabilization to timer 1 and timer 2, and

set to "0" (interrupts disabled) to the interrupt enable bits of timer 1

and timer 2.

5: Execute the transition after the oscillation used in the destination mode

is stabilized.

6: When system goes to on-chip oscillator mode, the oscillation stabilizing

wait time is not needed.

7: The on-chip oscillator can be stopped in all kinds of state of frequency/

2,4 mode.

8:In all X

IN mode, stop of on-chip oscillator is enabled.

9: The example assumes that 8 MHz is being applied to the XIN pin and 32

kHz to the XCIN pin. f(OCO) indicates the oscillation frequency of on-

chip oscillator.

10: When selecting the on-chip oscillator for the WDT clock, the on-chip

oscillator does not stop.

Also, in low-speed mode, the on-chip oscillator stops in the QzROM

version regardless of the on-chip oscillator stop bit value. The on-chip

oscillator does not stop in the flash memory version, so set this bit to

"1" to stop the oscillation.

In on-chip oscillator mode, even if this bit is set to "1", the on-chip

oscillator oscillation does not stop in the flash memory version, but

stops in the QzROM version.

11: In low-speed mode, the XCIN-XCOUT oscillation stops if the port XC

switch bit is set to "0".

12:In X

IN mode, the XIN-XOUT oscillation does not stop even if the XIN-

XOUT oscillation stop bit is set to "1".

13: 12.5 MHz <f(XIN)≤16 MHz is not available in the frequency/2 mode.

14: In the flash memory version, set the on-chip oscillator stop bit to "1"

(oscillation stops) because OCO is in the state set by the setting value

of the on-chip oscillator stop bit.

On-chip oscillator stop bit

0:Oscillating

1 : Stopped

Not used (do not write “1”)

Not used

(returns “0” when read)

Not used (do not write “1”)

Processor mode bits

b1 b0

0 0 : Single-chip mode

01:

10:

11:

Stack page selection bit

0:0page

1:1page

Internal system clock selection bit

0 : Main clock selected

(includes OCO, XIN)

1:X

CIN–XCOUT selected

Port Xc switch bit

0 : I/O port function (Oscillation stop)

1:X

CIN–XCOUT oscillating function

XIN–XOUT oscillation stop bit

0 : Oscillating

1 : Stopped

Main clock division ratio selection bit

(Valid only when CM3=0)

b7 b8

00:f(XIN)/2 (frequency/2 mode)

01:f(X

IN)/8 (frequency/8 mode)

10:f(X

IN)/4 (frequency/4 mode)

1 1 : On-chip oscillator

b7 b0

CPU mode register 2

CPUM2

(address 001116, QzROM version, OSCSEL=L, initial value: 0016)

( QzROM version, OSCSEL=H, initial value: 0116)

( Flash memory version, initial value: 0016)

CM8

b7 b0

CPU mode register

CPUM

(address 003B16, QzROM version, OSCSEL=L, initial value: E016)

( QzROM version, OSCSEL=H, initial value: 4016)

( Flash memory version, initial value: E016)

CM0CM1

CM2CM3CM4

CM5

CM6CM7

Not available

(13)

• QzROM version

• Flash memory version

OSCSEL=L

• QzROM version

OSCSEL=H

(14)

(12)

(11)

Rev.3.02 Apr 10, 2008 Page 64 of 131

REJ03B0177-0302

38D2 Group

• Oscillation External Output Function

The 38D2 group has the oscillation external output function to

output the rectangular waveform of the clock obtained by the

oscillation circuits from P41 and P40.

In order to validate the oscillation external output function, set

P40 or P41, or both to the output mode (set the corresponding

direction register to “1”).

The level of the XCOUT external output signal becomes “H” by

the P40/P41 oscillation output control bits (bits 0 and 1) of the

oscillation output control register (address 001016) in the

following states;

• the function to output the signal from the XCOUT pin externally

is selected

• the sub clock (XCIN−XCOUT) is in the stop oscillating or stop

mode.

Likewise, the level of the XOUT external output signal becomes

“H” by the P40/P41 oscillation output control bits (bits 0 and 1)

of the oscillation output control register (address 001016) in the

following states;

• the function to output the signal from the XOUT pin externally

is selected

• the main clock (XIN−XOUT) is in the stop oscillating or stop

mode.

<Note>

When the signal from the XOUT pin or XCOUT pin of the

oscillation circuit is input directly to the circuit except this MCU

and used, the system operation may be unstabilized.

In order to share the oscillation circuit safely, use the clock

output from P40 and P41 by this function for the circuits except

this MCU.

Fig. 63 Structure of oscillation output control register

Fig. 64 Block diagram of oscillation external output function

Oscillation output control register

(OSCOUT : address 001016)

P40/P41 oscillation output control bits

b1 b0

0 0 : P41, P40 = Normal port

0 1 : P41 = Normal port, P40 = XOUT

1 0 : P41 = Normal port, P40 = XCOUT

1 1 : P41 = XCOUT , P40 = XOUT

Not used (Do not write to “1”.)

STP instruction

XIN XOUT

Interrupt request

Interrupt disable flag I

Reset

XIN-XOUT oscillation stop bit

(CPUM Bit 5)

P61/XCIN P62/XCOUT

Port XC switch bit

(CPUM Bit 4)

P41/OOUT1

P40/OOUT0

P41 direction register

P40 direction register

OSCOUT control

P41 output latch

P40 output latch

Oscillation

output

selection

circuit

Rev.3.02 Apr 10, 2008 Page 65 of 131

REJ03B0177-0302

38D2 Group

QzROM WRITING MODE

In the QzROM writing mode, the user ROM area can be

rewritten while the microcomputer is mounted on-board by using

a serial programmer which is applicable for this microcomputer.

Table 14 lists the pin description (QzROM writing mode) and

Figure 65 shows the pin connection.

Refer to Figure 66 to Figure 69 for examples of a connection

with a serial programmer.

Contact the manufacturer of your serial programmer for serial

programmer. Refer to the user’s manual of your serial

programmer for details on how to use it.

Table 14 Pin description (QzROM writing mode)

Pin Name I/O Function

VCC, VSS Power source Input • Apply 2.7 to 5.5 V to VCC, and 0 V to VSS.

RESET Reset input Input • Reset input pin for active “L”. Reset occurs when RESET pin is

held at an “L” level for 16 cycles or more of XIN.

XIN Clock input Input • Set the same termination as the single-chip mode.

XOUT Clock output Output

VREF Analog reference

voltage

Input • Input the reference voltage of A/D converter to VREF.

AVSS Analog power source Input • Connect AVss to Vss.

P00−P07

P10−P17

P20−P27

P33−P37

P40−P47

P50−P57

P60−P62

I/O port I/O • Input “H” or “L” level signal or leave the pin open.

OSCSEL VPP input Input • QzROM programmable power source pin.

P32ESDA input/output I/O • Serial data I/O pin.

P31ESCLK input Input • Serial clock input pin.

P30ESPGMB input Input • Read/program pulse input pin.

Rev.3.02 Apr 10, 2008 Page 66 of 131

REJ03B0177-0302

38D2 Group

Fig. 65 Pin connection diagram

Package type : PLQP0064GA-A(64P6U-A)/PLQP0064KB-A(64P6Q-A)

P06/SEG6

P07/SEG7

P10/SEG8

P11/SEG9

P12/SEG10

P13/SEG11

P14/SEG12

P15/SEG13

P16/SEG14

P17/SEG15

6 7 8 9 10 11 12 13 14 15 16

45 44 43 42 41 40 39 38 37 36 35 34 33

P24/SEG20

P25/SEG21

COM2

COM1

COM0

P27/SEG23/VL2

P26/SEG22/VL1

COM3

P03/SEG3/(KW7)

/SEG

P05/SEG5

P51/INT1

P56/SCLK1/(KW2)

P55/TXD1/(KW1)

P54/RXD1/(KW0)

P53/T4OUT/PWM1

P20/SEG16

P21/SEG17

P22/SEG18

P23/SEG19

48 47 46

12345

M38D2XGXFP/HP

P36/T2OUT/CKOUT/(LED6)

P52/T3OUT/PWM0

VREF

VL3

P47/RTP1/AN7

P46/RTP0/AN6

P32/TXD2/(LED2)

P31/SCLK2/(LED1)

P33/RXD2/(LED3)

P50/INT0

AVSS

P02/SEG2/(KW6)

P01/SEG1/(KW5)

P00/SEG0/(KW4)

P57/SRDY1/(KW3)

P35/TXOUT1/(LED5)

P34/INT2/(LED4)

P30/SRDY2/(LED0)

P60/CNTR1

P37/CNTR0/TXOUT2/(LED7)

XOUT

P43/AN3

P42/ADKEY/AN2

P44/AN4

P45/AN5

VSS

P41/OOUT1/AN1

P40/OOUT0/AN0

OSCSEL

P62/XCOUT

P61/XCIN

VCC

XIN

RESET

GND

VPP

RESET

Vcc

ESPGMB

ESCLK

ESDA

* : Connect to oscillation circuit.

: QzROM pin

Rev.3.02 Apr 10, 2008 Page 67 of 131

REJ03B0177-0302

38D2 Group

Fig. 66 When using E8 programmer, connection example (1) (OSCSEL = “L”)

38D2 Group

RESET

circuit

Set the same termination as the

single-chip mode.

Vcc

P32 (ESDA)

P31 (ESCLK)

P30 (ESPGMB)

RESET

Vss

AVss

XIN XOUT

*1 : Open-collector buffer

Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.

Vcc

OSCSEL

4.7 kΩ

QzROM version

Rev.3.02 Apr 10, 2008 Page 68 of 131

REJ03B0177-0302

38D2 Group

Fig. 67 When using E8 programmer, connection example (2) (OSCSEL = “H”)

38D2 Group

RESET

circuit

Set the same termination as the

single-chip mode.

VCC

OSCSEL

P32 (ESDA)

P31 (ESCLK)

P30 (ESPGMB)

RESET

Vss

AVss

XIN XOUT

Jumper

switch

4.7 kΩ

*1: Open-collector buffer

*2: When programming 38D2 Group is performed, disconnect Vcc from OSCSEL by a jumper switch.

Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.

Vcc

4.7 kΩ

QzROM version

Rev.3.02 Apr 10, 2008 Page 69 of 131

REJ03B0177-0302

38D2 Group

Fig. 68 When using programmer of Suisei Electronics System Co., LTD, connection example (1) (OSCSEL = “L”)

38D2 Group

T_VDD

T_VPP

T_RXD

T_SCLK

T_PGM/OE/MD

T_RESET

GND

RESET circuit

Set the same termination as the

single-chip mode.

Vcc

OSCSEL

P32 (ESDA)

P31 (ESCLK)

P30 (ESPGMB)

RESET

Vss

AVss

XIN XOUT

4.7kΩ

Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.

T_BUSY

T_TXD

N.C.

4.7kΩ

QzROM version

Rev.3.02 Apr 10, 2008 Page 70 of 131

REJ03B0177-0302

38D2 Group

Fig. 69 When using programmer of Suisei Electronics System Co., LTD, connection example (2) (OSCSEL = “H”)

38D2 Group

T_VDD

T_VPP

T_RXD

T_SCLK

T_PGM/OE/MD

T_RESET

GND

RESET circuit

Set the same termination as the

single-chip mode.

Vcc

OSCSEL

P32 (ESDA)

P31 (ESCLK)

P30 (ESPGMB)

RESET

Vss

AVss XIN XOUT

Jumper

switch

4.7kΩ

*1 : When programming QzROM is performed, disconnect Vcc from OSCSEL by a jumper switch.

Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.

T_TXD

T_BUSY N.C.

4.7kΩ

QzROM version

Rev.3.02 Apr 10, 2008 Page 71 of 131

REJ03B0177-0302

38D2 Group

FLASH MEMORY MODE

The 38D2 Group flash memory version has the flash memory

that can be rewritten with a single power source.

For this flash memory, three flash memory modes are available

in which to read, program, and erase: the parallel I/O and

standard serial I/O modes in which the flash memory can be

manipulated using a programmer and the CPU rewrite mode in

which the flash memory can be manipulated by the Central

Processing Unit (CPU). For details of each mode, refer to the

next and after pages. Contact the manufacturer of your

programmer for the programmer. Refer to the user's manual of

your programmer for details on how to use it.

This flash memory version has some blocks on the flash memory

as shown in Figure 70 and each block can be erased.

In addition to the ordinary User ROM area to store the MCU

operation control program, the flash memory has a Boot ROM

area that is used to store a program to control rewriting in CPU

rewrite and standard serial I/O modes. This Boot ROM area has

had a standard serial I/O mode control program stored in it when

shipped from the factory. However, the user can write a rewrite

control program in this area that suits the user’s application

system. This Boot ROM area can be rewritten in only parallel I/O

mode.

Performance overview

Table 15 lists the performance overview of the 38D2 Group flash

memory version.

NOTE:

1. The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory.

This Boot ROM area can be erased and written in only parallel I/O mode.

Table 15 Performance overview of 38D2 Group flash memory version

Parameter Function

Power source voltage (Vcc) VCC = 2.7 to 5.5 V

Program/Erase VPP voltage (VPP)VCC = 2.7 to 5.5 V

Flash memory mode 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU

rewrite mode

Erase block division User ROM area/Data ROM area Refer to Figure 70.

Boot ROM area (1) Not divided (4K bytes)

Program method In units of bytes

Erase method Block erase

Program/Erase control method Program/Erase control by software command

Number of commands 5 commands

Number of program/Erase times 100

ROM code protection Available in parallel I/O mode and standard serial I/O mode

Rev.3.02 Apr 10, 2008 Page 72 of 131

REJ03B0177-0302

38D2 Group

Boot Mode

The control program for CPU rewrite mode must be written into

the User ROM or Boot ROM area in parallel I/O mode

beforehand. (If the control program is written into the Boot ROM

area, the standard serial I/O mode becomes unusable.)

See Figure 70 for details about the Boot ROM area.

Normal microcomputer mode is entered when the

microcomputer is reset with pulling CNVSS pin low. In this case,

the CPU starts operating using the control program in the User

ROM area.

When the microcomputer is reset and the CNVSS pin high after

pulling the P32/TxD2 pin and CNVSS pin high, the CPU starts

operating (start address of program is stored into addresses

FFFC16 and FFFD16) using the control program in the Boot

ROM area. This mode is called the “Boot mode”. Also, User

ROM area can be rewritten using the control program in the Boot

ROM area.

Block Address

Block addresses refer to the maximum address of each block.

These addresses are used in the block erase command.

CPU Rewrite Mode

In CPU rewrite mode, the internal flash memory can be operated

on (read, program, or erase) under control of the Central

Processing Unit (CPU).

In CPU rewrite mode, only the User ROM area shown in Figure

70 can be rewritten; the Boot ROM area cannot be rewritten.

Make sure the program and block erase commands are issued for

only the User ROM area and each block area.

The control program for CPU rewrite mode can be stored in

either User ROM or Boot ROM area. In the CPU rewrite mode,

because the flash memory cannot be read from the CPU, the

rewrite control program must be transferred to internal RAM

area before it can be executed.

Fig 70. Block diagram of built-in flash memory

Data block A:

1K bytes

Block 1: 26K bytes

Block 0: 32 K bytes

FFFF16

800016

180016

140016

100016

User ROM area

Data block B:

1K bytes

SFR area

Internal RAM area

(2K bytes)

FFFF16

100016

0FFF16

0FE016

083F16

004016

000016

FFFF16

F00016

Boot ROM area

4K bytes

SFR area

Internal flash memory area

(60K bytes)

RAM

Notes1: The boot ROM area can be rewritten

in a parallel I/O mode. (Access to

except boot ROM area is disabled.)

2: To specify a block, use the maximum

address in the block.

3: The QzROM version has the reserved

ROM area. Note the difference of the

area.

Rev.3.02 Apr 10, 2008 Page 73 of 131

REJ03B0177-0302

38D2 Group

Outline Performance

CPU rewrite mode is usable in the single-chip or Boot mode. The

only User ROM area can be rewritten.

In CPU rewrite mode, the CPU erases, programs and reads the

internal flash memory as instructed by software commands. This

rewrite control program must be transferred to internal RAM

area before it can be executed.

The MCU enters CPU rewrite mode by setting “1” to the CPU

rewrite mode select bit (bit 1 of address 0FE016). Then, software

commands can be accepted.

Use software commands to control program and erase

operations. Whether a program or erase operation has terminated

normally or in error can be verified by reading the status register.

Figure 71 shows the flash memory control register 0.

Bit 0 of the flash memory control register 0 is the RY/BY status

flag used exclusively to read the operating status of the flash

memory. During programming and erase operations, it is “0”

(busy). Otherwise, it is “1” (ready).

Bit 1 of the flash memory control register 0 is the CPU rewrite

mode select bit. When this bit is set to “1”, the MCU enters CPU

rewrite mode. And then, software commands can be accepted. In

CPU rewrite mode, the CPU becomes unable to access the

internal flash memory directly. Therefore, use the control

program in the internal RAM for write to bit 1. To set this bit 1 to

“1”, it is necessary to write “0” and then write “1” in succession

to bit 1. The bit can be set to “0” by only writing “0”.

Bit 2 of the flash memory control register 0 is the user block 1

E/W enable bit. By setting combination of bit 4 (user block 0

E/W enable bit) of the flash memory control register 2 (address

0FE216) and this bit as shown in Table 16, E/W is disabled to

user block in the CPU rewriting mode.

Bit 3 of the flash memory control register 0 is the flash memory

reset bit used to reset the control circuit of internal flash memory.

This bit is used when flash memory access has failed. When the

CPU rewrite mode select bit is “1”, setting “1” for this bit resets

the control circuit. To release the reset, it is necessary to set this

bit to “0”.

Bit 5 of the flash memory control register 0 is the User ROM

area select bit and is valid only in the boot mode. Setting this bit

to “1” in the boot mode switches an accessible area from the boot

ROM area to the user ROM area. To use the CPU rewrite mode

in the boot mode, set this bit to “1”. To rewrite bit 5, execute the

user original reprogramming control software transferred to the

internal RAM in advance.

Bit 6 of the flash memory control register 0 is the program status

flag. This bit is set to “1” when writing to flash memory is failed.

When program error occurs, the block cannot be used.

Bit 7 of the flash memory control register 0 is the erase status

flag.

This bit is set to “1” when erasing flash memory is failed. When

erase error occurs, the block cannot be used.

Figure 72 shows the flash memory control register 1.

Bit 0 of the flash memory control register 1 is the Erase suspend

enable bit. By setting this bit to “1”, the erase suspend mode to

suspend erase processing temporary when block erase command

is executed can be used. In order to set this bit 0 to “1”, writing

“0” and “1” in succession to bit 0. In order to set this bit to “0”,

write “0” only to bit 0.

Bit 1 of the flash memory control register 1 is the erase suspend

request bit. By setting this bit to “1” when erase suspend enable

bit is “1”, the erase processing is suspended.

Bit 6 of the flash memory control register 1 is the erase suspend

flag. This bit is cleared to “0” at the flash erasing.

Fig 71. Structure of flash memory control register 0

Fig 72. Structure of flash memory control register 1

Flash memory control register 0

(FMCR0: address : 0FE016, initial value: 0116)

RY/BY status flag

0 : Busy (being written or erased)

1 : Ready

CPU rewrite mode select bit(1)

0 : CPU rewrite mode invalid

1 : CPU rewrite mode valid

User block 1 E/W enable bit(1, 2)

0 : E/W disabled (180016-7FFF16)

1 : E/W enabled (180016-7FFF16)

Flash memory reset bit(3, 4)

0 : Normal operation

1 : reset

Not used (do not write “1” to this bit.)

User ROM area select bit(5)

0 : Boot ROM area is accessed

1 : User ROM area is accessed

Program status flag

0: Pass

1: Error

Erase status flag

0: Pass

1: Error

b7 b0

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and

then a “1” to it in succession. For this bit to be set to “0”, write

“0” only to this bit.

2: This bit can be written only when CPU rewrite mode select bit is

“1”.

3: Effective only when the CPU rewrite mode select bit = “1”. Fix

this bit to “0” when the CPU rewrite mode select bit is “0”.

4: When setting this bit to “1” (when the control circuit of flash

memory is reset), the flash memory cannot be accessed for 10 μs.

5: Write to this bit in program on RAM

Flash memory control register 1

(FMCR1: address: 0FE116, initial value: 4016)

Erase Suspend enable bit(1)

0 : Suspend invalid

1 : Suspend valid

Erase Suspend request bit(2)

0 : Erase restart

1 : Suspend request

Not used (do not write “1” to this bit.)

Erase Suspend flag

0 : Erase active

1 : Erase inactive (Erase Suspend mode)

Not used (do not write “1” to this bit.)

b7 b0

Notes 1: For this bit to be set to “1”, the user needs to write a “0”

and then a “1” to it in succession. For this bit to be set to

“0”, write “0” only to this bit.

2: Effective only when the suspend enable bit = “1”.

Rev.3.02 Apr 10, 2008 Page 74 of 131

REJ03B0177-0302

38D2 Group

Fig 73. Structure of flash memory control register 2

Figure 74 shows a flowchart for setting/releasing CPU rewrite mode.

Fig 74. CPU rewrite mode set/release flowchart be sure to execute

Flash memory control register 2

(FMCR2: address : 0FE216, initial value: 4516)

Not used (return “1” when read)

Not used (do not write “1” to this bit.)

Not used (return “1” when read)

Not used (return “0” when read)

User block 0 E/W enable bit (1, 2)

0 : E/W disabled (800016-FFFF16)

1 : E/W enabled (800016-FFFF16)

Not used (return “0” when read)

Not used (return “1” when read)

Not used (return “0” when read)

b7 b0

Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a

“1” to it in succession. For this bit to be set to “0”, write “0” only to this

bit.

2: Effective only when the CPU rewrite mode select bit = “1”.

Table 16 State of E/W inhibition function

User block 0

E/W enable bit

User block 1

E/W enable bit

User block 0

Addresses 800016 to FFFF16

User block 1

Addresses 180016 to 7FFF16

Data block

Addresses 100016 to 17FF16

0 0 E/W disabled E/W disabled E/W enabled

0 1 E/W disabled E/W enabled E/W enabled

1 0 E/W enabled E/W disabled E/W enabled

1 1 E/W enabled E/W enabled E/W enabled

Start

Single-chip mode or Boot mode

Set CPU mode register(1)

Jump to control program transferred to internal RAM

(Subsequent operations are executed by control program in

this RAM)

Transfer CPU rewrite mode control program to internal RAM

Set CPU rewrite mode select bit to “1” (by writing “0” and

then “1” in succession)

Using software command executes erase, program, or other

operation

End

Write “0” to CPU rewrite mode select bit

Set user block 0 E/W enable bit to “1” (by writing “0” and

then “1” in succession)

Set user block 1 E/W enable bit (At E/W disabled; writing

“0” , at E/W enabled;

writing “0” and then “1” in succession

Execute read array command(2)

Set user block 0 E/W enable bit to “0”

Set user block 1 E/W enable bit to “0”

Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16).

2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command.

Rev.3.02 Apr 10, 2008 Page 75 of 131

REJ03B0177-0302

38D2 Group

Take the notes described below when rewriting the flash memory

in CPU rewrite mode.

(1) Operation speed

During CPU rewrite mode, set the system clock φ to 4.0 MHz or

less using the main clock division ratio selection bits (bits 6 and

7 of address 003B16).

(2) Instructions inhibited against use

The instructions which refer to the internal data of the flash

memory cannot be used during CPU rewrite mode.

(3) Interrupts

The interrupts cannot be used during CPU rewrite mode because

they refer to the internal data of the flash memory.

(4) Watchdog timer

If the watchdog timer has been already activated, internal reset

due to an underflow will not occur because the watchdog timer is

surely cleared during program or erase.

(5) Reset

Reset is always valid. The MCU is activated using the boot mode

at release of reset in the condition of CNVSS = “H”, so that the

program will begin at the address which is stored in addresses

FFFC16 and FFFD16 of the boot ROM area.

Rev.3.02 Apr 10, 2008 Page 76 of 131

REJ03B0177-0302

38D2 Group

Software Commands

Table 17 lists the software commands.

After setting the CPU rewrite mode select bit to “1”, execute a

software command to specify an erase or program operation.

Each software command is explained below.

• Read Array Command (FF16)

The read array mode is entered by writing the command code

“FF16” in the first bus cycle. When an address to be read is input

in one of the bus cycles that follow, the contents of the specified

address are read out at the data bus (D0 to D7).

The read array mode is retained until another command is

written.

• Read Status Register Command (7016)

When the command code “7016” is written in the first bus cycle,

the contents of the status register are read out at the data bus (D0

to D7) by a read in the second bus cycle.

The status register is explained in the next section.

• Clear Status Register Command (5016)

This command is used to clear the bits SR4 and SR5 of the status

operation has ended in an error. To use this command, write the

command code “5016” in the first bus cycle.

• Program Command (4016)

Program operation starts when the command code “4016” is

written in the first bus cycle. Then, if the address and data to

program are written in the 2nd bus cycle, program operation

(data programming and verification) will start.

Whether the write operation is completed can be confirmed by

read status register or the RY/BY status flag. To read the status

status register bit 7 (SR7) is set to “0” at the same time the

program starts and returned to “1” upon completion of the

program. The read status mode remains active until the read

array command (“FF16”) is written.

The RY/BY status flag is set to “0” during program operation

and “1” when the program operation is completed as is the status

At program end, program results can be checked by reading the

status register.

Fig 75. Program flowchart

NOTES:

1. SRD = Status Register Data

2. WA = Write Address, WD = Write Data

3. BA = Block Address to be erased (Input the maximum address of each block.)

4. X denotes a given address in the User ROM area.

Start

Write “4016”

SR7 = “1”?

RY/BY = “1”?

Read status register

Program completed

YES

Write Write address

Write data

SR4 = “0”? Program error

YES

Table 17 List of software commands (CPU rewrite mode)

Command cycle

number

First bus cycle Second bus cycle

Mode Address Data

(D0 to D7)Mode Address Data

(D0 to D7)

Read array 1 Write X(4) FF16

Read status register 2 Write X 7016 Read X SRD(1)

Clear status register 1 Write X 5016

Program 2 Write X 4016 Write WA(2) WD(2)

Block erase 2 Write X 2016 Write BA(3) D016

Rev.3.02 Apr 10, 2008 Page 77 of 131

REJ03B0177-0302

38D2 Group

• Block Erase Command (2016/D016)

By writing the command code “2016” in the first bus cycle and

the confirmation command code “D016” and the block address in

the second bus cycle that follows, the block erase (erase and

erase verify) operation starts for the block address of the flash

memory to be specified.

Whether the block erase operation is completed can be confirmed

by read status register or the RY/BY status flag of flash memory

control register. To read the status register, write the status

“0” at the same time the block erase operation starts and returned

to “1” upon completion of the block erase operation. The read

status mode at this time remains active until the read array

command (“FF16”) is written.

The RY/BY status flag register is set to “0” during block erase

operation and “1” when the block erase operation is completed as

is the status register bit 7 (SR7).

After the block erase ends, erase results can be checked by

reading the status register. For details, refer to the section where

the status register is detailed.

Fig 76. Erase flowchart

Write “2016”

Write “D016”

Block address

Read status register

SR7 = “1”?

RY/BY = “1”?

Erase completed

(write read command “FF16”)

YES

Start

SR5 = “0”? Erase error

YES

Rev.3.02 Apr 10, 2008 Page 78 of 131

REJ03B0177-0302

38D2 Group

• Status Register

The status register shows the operating status of the flash

memory and whether erase operations and programs ended

successfully or in error. It can be read in the following ways:

(1) By reading an arbitrary address from the User ROM area

after writing the read status register command (7016)

(2) By reading an arbitrary address from the User ROM area in

the period from when the program starts or erase operation

starts to when the read array command (FF16) is input.

Also, the status register can be cleared by writing the clear status

After reset, the status register is set to “8016”.

Table 18 shows the status register. Each bit in this register is

explained below.

• Sequencer status (SR7)

The sequencer status indicates the operating status of the flash

memory. This bit is set to “0” (busy) during write or erase

operation and is set to “1” when these operations ends.

After power-on, the sequencer status is set to “1” (ready).

• Erase status (SR5)

The erase status indicates the operating status of erase operation.

If an erase error occurs, it is set to “1”. When the erase status is

cleared, it is reset to “0”.

• Program status (SR4)

The program status indicates the operating status of write

operation.

When a write error occurs, it is set to “1”.

The program status is reset to “0” when it is cleared.

If “1” is written for any of the SR5 and SR4 bits, the read array,

program, and block erase commands are not accepted. Before

executing these commands, execute the clear status register

command (5016) and clear the status register.

Also, if any commands are not correct, both SR5 and SR4 are set

to “1”.

Table 18 Definition of each bit in status register

Each bit of

SRD bits Status name Definition

“1” “0”

SR7 (bit7) Sequencer status Ready Busy

SR6 (bit6) Reserved −−

SR5 (bit5) Erase status Terminated in error Terminated normally

SR4 (bit4) Program status Terminated in error Terminated normally

SR3 (bit3) Reserved −−

SR2 (bit2) Reserved −−

SR1 (bit1) Reserved −−

SR0 (bit0) Reserved −−

Rev.3.02 Apr 10, 2008 Page 79 of 131

REJ03B0177-0302

38D2 Group

Full Status Check

By performing full status check, it is possible to know the

execution results of erase and program operations. Figure 77

shows a full status check flowchart and the action to be taken

when each error occurs.

Fig 77. Full status check flowchart and remedial procedure for errors

Read status register

SR4 = “1”

and

SR5 = “1”?

Command

sequence error

YES Execute the clear status register command (5016)to

clear the status register. Try performing the

operation one more time after confirming that the

command is entered correctly.

SR5 = “0”?

YES

Block erase error

NO Should an erase error occur, the block in error

cannot be used.

SR4 = “0”?

YES

Program error

End (block erase, program)

Note: When one of SR5 and SR4 is set to “1”, none of the read array, program,

and block erase commands is accepted. Execute the clear status register

command (5016) before executing these commands.

Should a program error occur, the block in error

cannot be used.

Rev.3.02 Apr 10, 2008 Page 80 of 131

REJ03B0177-0302

38D2 Group

Functions To Inhibit Rewriting Flash Memory Version

To prevent the contents of internal flash memory from being read

out or rewritten easily, this MCU incorporates a ROM code

protect function for use in parallel I/O mode and an ID code

check function for use in standard serial I/O mode.

• ROM Code Protect Function

The ROM code protect function is the function to inhibit reading

out or modifying the contents of internal flash memory by using

the ROM code protect control address (address FFDB16) in

parallel I/O mode. Figure 78 shows the ROM code protect

control address (address FFDB16). (This address exists in the

User ROM area.)

If one or both of the pair of ROM code protect bits is set to “0”,

the ROM code protect is turned on, so that the contents of

internal flash memory are protected against readout and

modification. The ROM code protect is implemented in two

levels. If level 2 is selected, the flash memory is protected even

against readout by a shipment inspection LSI tester, etc. When an

attempt is made to select both level 1 and level 2, level 2 is

selected by default.

If both of the two ROM code protect reset bits are set to “00”, the

ROM code protect is turned off, so that the contents of internal

flash memory can be readout or modified. Once the ROM code

protect is turned on, the contents of the ROM code protect reset

bits cannot be modified in parallel I/O mode. Use standard serial

I/O mode or other modes to rewrite the contents of the ROM

code protect disable bits.

Rewriting of only the ROM code protect control address (address

FFDB16) cannot be performed. When rewriting the ROM code

protect reset bit, rewrite the whole user ROM area (block 0)

containing the ROM code protect control address.

Fig 78. Structure of ROM code protect control address

ROM code protect control address (address FFDB16)

ROMCP (FF16 when shipped)

Reserved bits (“1” at read/write)

ROM code protect level 2 set bits (ROMCP2)(1, 2)

b3b2

0 0: Protect enabled

0 1: Protect enabled

1 0: Protect enabled

1 1: Protect disabled

ROM code protect reset bits (ROMCR)(3)

b5b4

0 0: Protect removed

0 1: Protect set bits effective

1 0: Protect set bits effective

1 1: Protect set bits effective

ROM code protect level 1 set bits (ROMCP1)(1)

b7b6

0 0: Protect enabled

0 1: Protect enabled

1 0: Protect enabled

1 1: Protect disabled

1 1

Notes 1: When ROM code protect is turned on, the internal flash memory is protected

against readout or modification in parallel I/O mode.

2: When ROM code protect level 2 is turned on, ROM code readout by a shipment

inspection LSI tester, etc. also is inhibited.

3: The ROM code protect reset bits can be used to turn off ROM code protect level

1 and ROM code protect level 2.

However, no change can be made in parallel I/O mode. Use serial I/O mode or

other modes to change settings.

Rev.3.02 Apr 10, 2008 Page 81 of 131

REJ03B0177-0302

38D2 Group

• ID Code Check Function

Use this function in standard serial I/O mode. When the contents

of the flash memory are not blank, the ID code sent from the

programmer is compared with the ID code written in the flash

memory to see if they match. If the ID codes do not match, the

commands sent from the programmer are not accepted. The ID

code consists of 8-bit data, and its areas are FFD416 to FFDA16.

Write a program which has had the ID code preset at these

addresses to the flash memory.

Fig 79. ID code store addresses

ID7

ID6

ID5

ID4

ID3

ID2

ID1

Address

ROM code protect control

Interrupt vector area

FFD516

FFD416

FFD616

FFD716

FFD816

FFD916

FFDA16

FFDB16

Rev.3.02 Apr 10, 2008 Page 82 of 131

REJ03B0177-0302

38D2 Group

Parallel I/O Mode

The parallel I/O mode is used to input/output software

commands, address and data in parallel for operation (read,

program and erase) to internal flash memory.

• User ROM and Boot ROM Areas

In parallel I/O mode, the User ROM and Boot ROM areas shown

in Figure 70 can be rewritten. Both areas of flash memory can be

operated on in the same way.

The Boot ROM area is 4 Kbytes in size and located at addresses

F00016 through FFFF16. Make sure program and block erase

operations are always performed within this address range.

(Access to any location outside this address range is prohibited.)

In the Boot ROM area, an erase block operation is applied to

only one 4 K byte block. The boot ROM area has had a standard

serial I/O mode control program stored in it when shipped from

the factory. Therefore, using the MCU in standard serial I/O

mode, do not rewrite to the Boot ROM area.

Rev.3.02 Apr 10, 2008 Page 83 of 131

REJ03B0177-0302

38D2 Group

Standard serial I/O Mode

The standard serial I/O mode inputs and outputs the software

commands, addresses and data needed to operate (read, program,

erase, etc.) the internal flash memory. This I/O is clock

synchronized serial. This mode requires a purpose-specific

peripheral unit.

The standard serial I/O mode is different from the parallel I/O

mode in that the CPU controls flash memory rewrite (uses the

CPU rewrite mode), rewrite data input and so forth. The standard

serial I/O mode is started by connecting “H” to the CNVSS pin

and “H” to the P32 (BOOTENT) pin, and releasing the reset

operation. (In the ordinary microcomputer mode, set CNVSS pin

to “L” level.) This control program is written in the Boot ROM

area when the product is shipped from Renesas. Accordingly,

make note of the fact that the standard serial I/O mode cannot be

used if the Boot ROM area is rewritten in parallel I/O mode. The

standard serial I/ O mode has standard serial I/O mode 1 of the

clock synchronous serial and standard serial I/O mode 2 of the

clock asynchronous serial. Tables 19 and 20 show description of

pin function (standard serial I/O mode). Figure 80 to 82 show the

pin connections for the standard serial I/O mode.

In standard serial I/O mode, only the User ROM area shown in

Figure 70 can be rewritten. The Boot ROM area cannot be

written.

In standard serial I/O mode, a 7-byte ID code is used. When there

is data in the flash memory, this function determines whether the

ID code sent from the peripheral unit (programmer) and those

written in the flash memory match. The commands sent from the

peripheral unit (programmer) are not accepted unless the ID code

matches.

Rev.3.02 Apr 10, 2008 Page 84 of 131

REJ03B0177-0302

38D2 Group

Table 19 Description of pin function (Flash Memory Standard Serial I/O Mode 1)

Pin name Signal name I/O Function

VCC,VSS Power supply I Apply 2.7 to 5.5 V to the VCC pin and 0 V to the Vss pin.

CNVSS CNVSS I After input of port is set, input “H” level.

RESET Reset input I Reset input pin. To reset the microcomputer, RESET pin should be

held at an “L” level for 16 cycles or more of XIN.

XIN Clock input I Connect an oscillation circuit between the XIN and XOUT pins.

As for the connection method, refer to the “clock generating circuit”.

XOUT Clock output O

AVSS Analog power supply input Connect AVss to VSS.

VREF Reference voltage input I Apply reference voltage of A/D convertor to this pin.

P00−P07, P10−P17,

P20−P27, P34−P37,

P40−P47, P50−P57,

P60−P62

I/O port I/O Input “L” or “H” level, or keep open.

P33RxD input I Serial data input pin.

P32TxD output O Serial data output pin.

P31SCLK input I Serial clock input pin.

P30BUSY output O BUSY signal output pin.

Table 20 Description of pin function (Flash Memory Standard Serial I/O Mode 2)

Pin name Signal name I/O Function

VCC,VSS Power supply I Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the VSS pin.

CNVSS CNVSS I After input of port is set, input “H” level.

RESET Reset input I Reset input pin. To reset the microcomputer, RESET pin should be

held at an “L” level for 16 cycles or more of XIN.

XIN Clock input I Connect an oscillation circuit between the XIN and XOUT pins.

As for the connection method, refer to the “clock generating circuit”.

XOUT Clock output O

AVSS Analog power supply input Connect AVss to VSS.

VREF Reference voltage input I Apply reference voltage of A/D convertor to this pin.

P00−P07, P10−P17,

P20−P27, P34−P37,

P40−P47, P50−P57,

P60−P62

I/O port I/O Input “L” or “H” level, or keep open.

P33RxD input I Serial data input pin.

P32TxD output O Serial data output pin.

P31SCLK input I Input “L” level.

P30BUSY output O BUSY signal output pin.

Rev.3.02 Apr 10, 2008 Page 85 of 131

REJ03B0177-0302

38D2 Group

Fig 80. Connection for standard serial I/O mode 1

Package type: PLQP0064GA-A (64P6U-A)/PLQP0064KB-A (64P6Q-A)

P06/SEG6

P07/SEG7

P10/SEG8

P11/SEG9

P12/SEG10

P13/SEG11

P14/SEG12

P15/SEG13

P16/SEG14

P17/SEG15

6 7 8 9 10111213141516

45 44 43 42 41 40 39 38 37 36 35 34 33

P24/SEG20

P25/SEG21

COM2

COM1

COM0

P27/SEG23/VL2

P26/SEG22/VL1

COM3

P03/SEG3/(KW7)

/SEG

P05/SEG5

P51/INT1

P56/SCLK1/(KW2)

P55/TXD1/(KW1)

P54/RXD1/(KW0)

P53/T4OUT/PWM1

P20/SEG16

P21/SEG17

P22/SEG18

P23/SEG19

48 47 46

12345

M38D29FFFP/HP

P36/T2OUT/CKOUT/(LED6)

P52/T3OUT/PWM0

VREF

VL3

P47/RTP1/AN7

P46/RTP0/AN6

P32/TXD2/(LED2)

P31/SCLK2/(LED1)

P33/RXD2/(LED3)

P50/INT0

AVSS

P02/SEG2/(KW6)

P01/SEG1/(KW5)

P00/SEG0/(KW4)

P57/SRDY1/(KW3)

P35/TXOUT1/(LED5)

P34/INT2/(LED4)

P30/SRDY2/(LED0)

P60/CNTR1

P37/CNTR0/TXOUT2/(LED7)

XOUT

P43/AN3

P42/AN2/ADKEY

P44/AN4

P45/AN5

VSS

P41/OOUT1/AN1

P40/OOUT0/AN0

P62/XCOUT

P61/XCIN

VCC

XIN

RESET

GND

VPP

RESET

Vcc

CNVSS

*Connect oscillation circuit.

indicates flash memory pin.

SCLK

BUSY

TxD

RxD

Rev.3.02 Apr 10, 2008 Page 86 of 131

REJ03B0177-0302

38D2 Group

Fig 81. When using programmer (in standard serial I/O mode 1) of Suisei Electronics System Co., LTD, connection

example

38D2 Group

Set the same termination as

the single-chip mode.

Vcc

P31(SCLK)

P30(BUSY)

RESET

Vss

AVss

XIN XOUT

Note 1: For the programmer circuit, the wiring capacity of each signal pin must not exceed 47pF.

CNVSS

T_VDD

T_VPP

T_SCLK

T_BUSY

RESET circuit

T_RESET

GND

4.7 kΩ

T_PGM/OE/MD

P33(RxD)

T_TXD

4.7 kΩ

T_RXD P32(TxD)

Flash memory version

N.C.

Rev.3.02 Apr 10, 2008 Page 87 of 131

REJ03B0177-0302

38D2 Group

Fig 82. When using E8 programmer (in standard serial I/O mode 1) connection example

38D2 Group

RESET

circuit

Vcc

P32(TxD)

P31(SCLK)

P30(BUSY)

RESET

Vss

AVss

XIN XOUT

4.7 kΩ

*1: Open-collector buffer

Note 1: For the programmer circuit, the wiring capacity of each signal pin must not exceed 47pF.

Vcc

CNVSS

4.7 kΩ

P33(RxD)

Set the same termination as

the single-chip mode.

4.7 kΩ

Flash memory version

Rev.3.02 Apr 10, 2008 Page 88 of 131

REJ03B0177-0302

38D2 Group

Fig 83. Operating waveform for standard serial I/O mode 1

Fig 84. Operating waveform for standard serial I/O mode 2

Power source

RESET

CNVSS

P32(TXD)

P31(SCLK)

P30(BUSY)

P33(RXD)

td(CNVSS-RESET)

td(P32-RESET)

Notes: In the standard serial I/O mode 1, input “H” to the P31 pin.

Be sure to set the CNVss pin to “H” before rising RESET.

Be sure to set the P32 pin to “H” before rising RESET.

td(CNVSS-RESET)

td(P32-RESET)

Symbol Min. Max.Typ. Unit

Limits

Flash memory version

Power source

RESET

CNVSS

P32(TXD)

P30(BUSY)

P33(RXD)

P31(SCLK)

td(CNVSS-RESET)

td(P32-RESET)

td(CNVSS-RESET)

td(P32-RESET)

Symbol Min. Max.Typ. Unit

Limits Notes: In the standard serial I/O mode 2, input “H” to the P31 pin.

Be sure to set the CNVss pin to “H” before rising RESET.

Be sure to set the P32 pin to “H” before rising RESET.

Flash memory version

Rev.3.02 Apr 10, 2008 Page 89 of 131

REJ03B0177-0302

38D2 Group

NOTES ON USE

Processor Status Register

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”.

After a reset, initialize flags which affect program execution.

In particular, it is essential to initialize the index X mode (T) and

the decimal mode (D) flags because of their effect on

calculations. Initialize these flags at biginning of the program.

Interrupt

The contents of the interrupt request bits do not change

immediately after they have been written. After writing to an

interrupt request register, execute at least one instruction before

performing a BBC or BBS instruction.

Decimal Calculations

• To calculate in decimal notation, set the decimal mode flag (D)

to “1”, then execute an ADC or SBC instruction. After

executing an ADC or SBC instruction, execute at least one

instruction before executing a SEC, CLC, or CLD instruction.

• In decimal mode, the values of the negative (N), overflow (V),

and zero (Z) flags are invalid.

Timers

The division ratio is 1/(n+1) when the value n (0 to 255) is

written to the timer latch.

Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Direction Registers

The values of the port direction registers cannot be read. This

means, it is impossible to use the LDA instruction, memory

operation instruction when the T flag is “1”, addressing mode

using direction register values as qualifiers, and bit test

instructions such as BBC and BBS. It is also impossible to use bit

operation instructions such as CLB and SEB, and read-modify-

write instructions to direction registers, including calculations

such as ROR. To set the direction registers, use instructions such

as LDM or STA.

Serial Interface

In clock synchronous serial I/O, if the receive side is using an

external clock and it is to output the SRDY signal, set the transmit

enable bit, the receive enable bit, and the SRDY output enable bit

to “1”.

Serial I/O continues to output the final bit from the TXD pin after

transmission is completed.

A/D Converter

The comparator is constructed linked to a capacitor. The

conversion accuracy may be low because the charge is lost if the

conversion speed is not enough. Accordingly, set f(XIN) to at

least 500kHz during A/D conversion in the XIN mode.

Also, do not execute the STP or WIT instruction during an A/D

conversion.

In the low-speed mode, since the A/D conversion is executed by

the on-chip oscillator, the minimum value of f(XIN) frequency is

not limited.

LCD Drive Control Circuit

Execution of the STP instruction sets the LCD enable bit (bit 3 of

the LCD mode register) and bits 0 to 5 and bit 7 of the LCD

power control register to “0” and the LCD panel turns off. To

make the LCD panel turn on after returning from the stop mode,

set these bits to “1”.

Instruction Execution Time

The instruction execution time is obtained by multiplying the

frequency of the internal clock φ by the number of cycles needed

to execute an instruction.

Power Source Voltage

When the power source voltage value of a microcomputer is less

than the value which is indicated as the recommended operating

conditions, the microcomputer does not operate normally and

may perform unstable operation.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power supply is turned off,

reset a microcomputer when the power source voltage is less

than the recommended operating conditions and design a system

not to cause errors to the system by this unstable operation.

Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor

suitable for high frequencies as bypass capacitor between power

source pin (VCC pin) and GND pin (Vss pin), and between power

source pin (VCC pin) and analog power source pin (AVCC).

Besides, connect the capacitor to as close as possible. For bypass

capacitor which should not be located too far from the pins to be

connected, a ceramic capacitor of 0.1 μF is recommended.

LCD drive power supply

Power supply capacitor may be insufficient with the division

resistance for LCD power supply, and the characteristic of the

LCD panel. In this case, there is the method of connecting the

bypass capacitor about 0.1−0.33μF to VL1 −VL3 pins. The

example of a strengthening measure of the LCD drive power

supply is shown below.

Fig. 85 Strengthening measure example of LCD drive

power supply

• Connect by the shortest

possible wiring.

• Connect the bypass capacitor

to the VL1 −VL3 pins as short

as possible.

(Referential value:0.1−0.33 μF)

VL3

VL2

VL1

Rev.3.02 Apr 10, 2008 Page 90 of 131

REJ03B0177-0302

38D2 Group

NOTES ON QzROM VERSION

Wiring to OSCSEL pin

1. OSCSEL = L

Connect the OSCSEL pin the shortest possible to the GND

pattern which is supplied to the VSS pin of the microcomputer.

In addition connecting an approximately 5 kΩ resistor in series

to the GND could improve noise immunity. In this case as well

as the above mention, connect the pin the shortest possible to

the GND pattern which is supplied to the VSS pin of the

microcomputer.

2. OSCSEL = H

Connect the OSCSEL pin the shortest possible to the VCC

pattern which is supplied to the VCC pin of the microcomputer.

In addition connecting an approximately 5 kΩ resistor in series

to the VCC could improve noise immunity. In this case as well

as the above mention, connect the pin the shortest possible to

the VCC pattern which is supplied to the VCC pin of the

microcomputer.

•Reason

The OSCSEL pin is the power source input pin for the built-in

QzROM.

When programming in the QzROM, the impedance of the

OSCSEL pin is low to allow the electric current for writing to

flow into the built-in QzROM. Because of this, noise can enter

easily. If noise enters the OSCSEL pin, abnormal instruction

codes or data are read from the QzROM, which may cause a

program runaway.

Fig. 86 Wiring for the OSCSEL pin

Precautions Regarding Overvoltage in QzROM Version

Make sure that voltage exceeding the VCC pin voltage is not

applied to other pins. In particular, ensure that the state indicated

by bold lines in figure below does not occur for OSCSEL pin

(VPP power source pin for QzROM) during power-on or power-

off. Otherwise the contents of QzROM could be rewritten.

Fig. 87 Example of Overvoltage

Product shipped in blank

As for the product shipped in blank, Renesas does not perform

the writing test to user ROM area after the assembly process

though the QzROM writing test is performed enough before the

assembly process. Therefore, a writing error of approximate

0.1% may occur.

Moreover, please note the contact of cables and foreign bodies on

a socket, etc. because a writing environment may cause some

writing errors.

Notes On QzROM Writing Orders

When ordering the QzROM product shipped after writing,

submit the mask file (extension: .msk) which is made by the

mask file converter MM.

• Be sure to set the ROM option data* setup when making the

mask file by using the mask file converter MM.. The ROM

code protect is specified according to the ROM option data* in

the mask file which is submitted at ordering. Note that the

mask file which has nothing at the ROM option data* or has

the data other than “0016”, “FE16” and “FF16” can not be

accepted.

•Set “FF16” to the ROM code protect address in ROM data

regardless of the presence or absence of a protect. When data

other than “FF16” is set, we may ask that the ROM data be

submitted again.

* ROM option data: mask option noted in MM

Data Required For QzROM Writing Orders

The following are necessary when ordering a QzROM product

shipped after writing:

1. QzROM Writing Confirmation Form*

2. Mark Specification Form*

3. ROM data...........Mask file

* For the QzROM writing confirmation form and the mark

specification form, refer to the “Renesas Technology Corp.”

Homepage (http://www.renesas.com/homepage.jsp).

Note that we cannot deal with special font marking (customer's

trademark etc.) in QzROM microcomputer.

QzROM Receive Flow

When writing to QzROM is performed by user side, the

receiving inspection by the following flow is necessary.

Fig. 88 QzROM receive flow

OSCSEL

VSS

The shortest

about 5 kΩ

Termination of OSCSEL pin

OSCSEL

VCC

The shortest

about 5 kΩ

(1) OSCSEL = L (2) OSCSEL = H

(1)

Note 1: It shows the microcomputer’s pin

VCC pin voltage

OSCSEL pin voltage

“H” input

OSCSEL pin voltage

“L” input

1.8V 1.8V

(1) Input voltage to other MCU pins rises before VCC pin voltage.

(2) Input voltage to other MCU pins falls after VCC pin voltage.

Note: The internal circuitry is unstable when VCC is below the minimum voltage

specification of 1.8 V (shaded portion), so particular care should be

exercised regarding overvoltage.

(1) (2)

∼

∼∼

∼

QzROM product shipped in blank

Programming

Verify test

Receiving inspection of

unprotected area (Verify test)

Programming to unprotected area

Verify test for unprotected area

Shipping

User

QzROM product shipped after writing

“protect disabled”

“protect enabled to the protect area 1”

Renesas

Receiving inspection

(Blank check)

Programming

Verify test for all area

Shipping

User

Renesas

Rev.3.02 Apr 10, 2008 Page 91 of 131

REJ03B0177-0302

38D2 Group

NOTES ON FLASH MEMORY VERSION

CPU Rewrite Mode

(1) Operation speed

During CPU rewrite mode, set the system clock

4.0 MHz or

less using the main clock division ratio selection bits (bits 6 and

7 of address 003B16).

(2) Instructions inhibited against use

The instructions which refer to the internal data of the flash

memory cannot be used during the CPU rewrite mode.

(3) Interrupts inhibited against use

The interrupts cannot be used during the CPU rewrite mode

because they refer to the internal data of the flash memory.

(4) Watchdog timer

In case of the watchdog timer has been running already, the

internal reset generated by watchdog timer underflow does not

happen, because of watchdog timer is always clearing during

program or erase operation.

(5) Reset

Reset is always valid. In case of CNVSS = “H” when reset is

released, boot mode is active. So the program starts from the

address contained in address FFFC16 and FFFD16 in boot ROM

area.

CNVSS Pin

The CNVSS pin determines the flash memory mode.

Connect the CNVSS/VPP pin the shortest possible to the GND

pattern which is supplied to the VSS pin of the microcomputer.

In addition connecting an approximately 5 kΩ. resistor in series

to the GND could improve noise immunity. In this case as well as

the above mention, connect the pin the shortest possible to the

GND pattern which is supplied to the VSS pin of the

microcomputer.

Note. When the boot mode or the standard serial I/O mode is used, a

switch of the input level to the CNVSS pin is required.

Fig 89. Wiring for the CNVSS

NOTES ON DIFFERENCES BETWEEN QzROM

VERSION AND FLASH MEMORY VERSION

The QzROM version and flash memory versions differ in their

manufacturing processes, built-in ROM, and layout patterns.

Because of these differences, characteristic values, operation

margins, noise immunity, and noise radiation and oscillation

circuit constants may vary within the specified range of electrical

characteristics.

When switching to the QzROM version, implement system

evaluations equivalent to those performed in the flash memory

version.

Confirm page 11 about the differences of functions.

The shortest

CNVSS

VSS

Approx. 5kΩ

The shortest

(1)

Note 1: It shows the microcomputer’s pin.

Rev.3.02 Apr 10, 2008 Page 92 of 131

REJ03B0177-0302

38D2 Group

Countermeasures against noise

(1) Shortest wiring length

1. Wiring for RESET pin

Make the length of wiring which is connected to the RESET

pin as short as possible. Especially, connect a capacitor across

the RESET pin and the VSS pin with the shortest possible

wiring (within 20 mm).

•Reason

The width of a pulse input into the RESET pin is determined by

the timing necessary conditions. If noise having a shorter pulse

width than the standard is input to the RESET pin, the reset is

released before the internal state of the microcomputer is

completely initialized. This may cause a program runaway.

Fig. 90 Wiring for the RESET pin

2. Wiring for clock input/output pins

• Make the length of wiring which is connected to clock I/O

pins as short as possible.

• Make the length of wiring (within 20 mm) across the

grounding lead of a capacitor which is connected to an

oscillator and the VSS pin of a microcomputer as short as

possible.

• Separate the VSS pattern only for oscillation from other VSS

patterns.

•Reason

If noise enters clock I/O pins, clock waveforms may be

deformed.

This may cause a program failure or program runaway. Also, if a

potential difference is caused by the noise between the VSS level

of a microcomputer and the VSS level of an oscillator, the correct

clock will not be input in the microcomputer.

Fig. 91 Wiring for clock I/O pins

(2) Connection of bypass capacitor across VSS line and VCC

line

In order to stabilize the system operation and avoid the latch-up,

connect an approximately 0.1 μF bypass capacitor across the VSS

line and the VCC line as follows:

• Connect a bypass capacitor across the VSS pin and the VCC pin

at equal length.

• Connect a bypass capacitor across the VSS pin and the VCC pin

with the shortest possible wiring.

• Use lines with a larger diameter than other signal lines for VSS

line and VCC line.

• Connect the power source wiring via a bypass capacitor to the

VSS pin and the VCC pin.

Fig. 92 Bypass capacitor across the VSS line and the VCC

line

RESET

Reset

circuit

Noise

VSS

N.G.

Reset

circuit

VSS

RESET

VSS

O.K.

Noise

XIN

XOUT

VSS

N.G.

XIN

XOUT

VSS

O.K.

VSS

VCC

VSS

VCC

N.G. O.K.

Rev.3.02 Apr 10, 2008 Page 93 of 131

REJ03B0177-0302

38D2 Group

(3) Oscillator concerns

In order to obtain the stabilized operation clock on the user

system and its condition, contact the oscillator manufacturer and

select the oscillator and oscillation circuit constants. Be careful

especially when range of voltage and temperature is wide.

Also, take care to prevent an oscillator that generates clocks for a

microcomputer operation from being affected by other signals.

1. Keeping oscillator away from large current signal lines

Install a microcomputer (and especially an oscillator) as far as

possible from signal lines where a current larger than the

tolerance of current value flows.

•Reason

In the system using a microcomputer, there are signal lines for

controlling motors, LEDs, and thermal heads or others. When a

large current flows through those signal lines, strong noise

occurs because of mutual inductance.

2. Installing oscillator away from signal lines where potential

levels change frequently

Install an oscillator and a connecting pattern of an oscillator

away from signal lines where potential levels change

frequently. Also, do not cross such signal lines over the clock

lines or the signal lines which are sensitive to noise.

•Reason

Signal lines where potential levels change frequently (such as the

CNTR pin signal line) may affect other lines at signal rising edge

or falling edge. If such lines cross over a clock line, clock

waveforms may be deformed, which causes a microcomputer

failure or a program runaway.

Fig. 93 Wiring for a large current signal line/Wiring of

signal lines where potential levels change

frequently

(4) Analog input

The analog input pin is connected to the capacitor of a voltage

comparator. Accordingly, sufficient accuracy may not be

obtained by the charge/discharge current at the time of A/D

conversion when the analog signal source of high-impedance is

connected to an analog input pin. In order to obtain the A/D

conversion result stabilized more, please lower the impedance of

an analog signal source, or add the smoothing capacitor to an

analog input pin.

(5) Difference of memory size

When memory size differ in one group, actual values such as an

electrical characteristics, A/D conversion accuracy, and the

amount of proof of noise incorrect operation may differ from the

ideal values.

When these products are used switching, perform system

evaluation for each product of every after confirming product

specification.

XIN

XOUT

VSS

Microcomputer

Mutual inductance

Large

current

GND

XIN

XOUT

VSS

CNTRDo not cross.

N.G.

1. Keeping oscillator away from large current signal lines

2. Installing oscillator away from signal lines where potential

levels change frequently

Rev.3.02 Apr 10, 2008 Page 94 of 131

REJ03B0177-0302

38D2 Group

QzROM VERSION ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Table 21 Absolute maximum ratings

Symbol Parameter Conditions Ratings Unit

VCC Power source voltage

All voltages are based

on VSS.

When an input voltage

is measured, output

transistors are cut off.

−

0.3 to 6.5 V

VIInput voltage

P00

P07, P10

P17, P20

P27, P30

P37, P40

P47, P50

P57, P60

P62

−

0.3 to VCC+0.3 V

VIInput voltage VL1

−

0.3 to VL2 V

VIInput voltage VL2 VL1 to VL3 V

VIInput voltage VL3 VL2 to 6.5 V

VIInput voltage RESET, XIN, OSCSEL

−

0.3 to VCC+0.3 V

VOOutput voltage

−

, P1

−

, P2

−

at output port

−

0.3 to VCC+0.3 V

at segment port

−

0.3 to VL3+0.3 V

VOOutput voltage COM0-COM3

−

0.3 to VL3+0.3 V

VOOutput voltage

−

, P5

−

, P6

−

0.3 to VCC+0.3 V

VOOutput voltage XOUT

−

0.3 to VCC+0.3 V

PdPower dissipation Ta = 25°C300mW

Topr Operating temperature −

−

20 to 85 °C

Tstg Storage temperature −

−

40 to 125 °C

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 95 of 131

REJ03B0177-0302

38D2 Group

Recommended Operating Conditions

NOTES:

1. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.

2. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

3. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and

operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency

oscillator.

f: Oscillation frequency (1 MHz ≤ f(XIN) ≤ 8 MHz) of oscillator. When the 8 MHz oscillation is used, assign “8” to “f”.

Table 22 Recommended operating conditions (1)

(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ. Max.

VCC Power source voltage (1) Frequency/2

mode (2)

f(XIN) ≤ 12.5MHz 4.5 5.5 V

f(XIN) ≤ 8.0MHz 4.0 5.5 V

f(XIN) ≤ 4.0MHz 2.0 5.5 V

f(XIN) ≤ 2.0MHz 1.8 5.5 V

Frequency/4

mode

f(XIN) ≤ 16MHz 4.5 5.5 V

f(XIN) ≤ 8.0MHz 2.0 5.5 V

f(XIN) ≤ 4.0MHz 1.8 5.5 V

Frequency/8

mode

f(XIN) ≤ 16MHz 4.5 5.5 V

f(XIN) ≤ 8.0MHz 2.0 5.5 V

f(XIN) ≤ 4.0MHz 1.8 5.5 V

Low-speed mode 1.8 5.5 V

On-chip oscillator mode 1.8 5.5 V

When start oscillating (3) 0.05 × f + 1.9 V

VSS Power source voltage 0V

VL3 LCD power source voltage 2.5 5.5 V

VREF A/D converter reference voltage 2.0 VCC V

AVSS Analog power source voltage 0 V

VIA Analog input voltage AN0−AN7AVSS VCC V

VIH “H” input voltage

P04−P07, P10−P17, P20−P27, P30, P32, P35, P36, P40−P47,

P52, P53, P62

0.7VCC VCC V

VIH “H” input voltage

P00−P03, P31, P33, , P34, P37, P50, 51, P54−P57, P60, P61

0.8VCC VCC V

VIH “H” input voltage RESET 2.2V < VCC ≤ 5.5V 0.8VCC VCC V

VCC ≤ 2.2V 65 × VCC−99

VCC − 100

VCC V

VIH “H” input voltage XIN 0.8VCC VCC V

VIL “L” input voltage

P04−P07, P10−P17, P20−P27, P30, P32, P35, P36, P40−P47,

P52, P53, P62

00.3VCC V

VIL “L” input voltage

P00−P03, P31, P33, P34, P37, P50, P51, P54−P57, P60, P61,

OSCSEL

00.2V

CC V

VIL “L” input voltage RESET 2.2V < VCC ≤ 5.5V 0 0.2VCC V

VCC ≤ 2.2V 0 65 × VCC −99

100

VIL “L” input voltage XIN 00.2VCC V

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 96 of 131
REJ03B0177-0302
38D2 Group
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
value measured over 100 ms. The total peak current is the peak value of all the currents. 
2. The peak output current is the peak current flowing in each port.
3. The average output current is average value measured over 100 ms.
Table 23  Recommended operating conditions (3)
(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
ΣIOH(peak) “H” total peak output current (1)
P00−P07, P10−P17, P20−P27, P30−P37
−40 mA
ΣIOH(peak) “H” total peak output current (1)
P40−47, P50−P57, P60−P62
−40 mA
ΣIOL(peak) “L” total peak output current (1)
P00−P07, P10−P17, P20−P27
40 mA
ΣIOL(peak) “L” total peak output current (1)
P40−P47, P50, P51, P54−P57, P60−P62
40 mA
ΣIOL(peak) “L” total peak output current (1)
P30−P37, P52, P53
110 mA
ΣIOH(avg) “H” total average output current (1)
P00−P07, P10−P17, P20−P27, P30−P37
−20 mA
ΣIOH(avg) “H” total average output current (1)
P40−P47, P50−P57, P60−P62
−20 mA
ΣIOL(avg) “L” total average output current (1)
P00−P07, P10−P17, P20−P27
20 mA
ΣIOL(avg) “L” total average output current (1)
P40−P47, P50, P51, P54−P57, P60−P62
20 mA
ΣIOL(avg) “L” total average output current (1)
P30−P37, P52, P53
90 mA
IOH(peak) “H” peak output current (2)
P00−P07, P10−P17, P20−P27
−2.0 mA
IOH(peak) “H” peak output current (2)
P30−P37, P40−P47, P50−P57, P60−P62
−5.0 mA
IOL(peak) “L” peak output current (2)
P00−P07, P10−P17, P20−P27
5.0 mA
IOL(peak) “L” peak output current (2)
P40−P47, P50, P51, P54−P57, P60−P62
10 mA
IOL(peak) “L” peak output current (2)
P30−P37, P52, P53
30 mA
IOH(avg) “H” average output current (3)
P00−P07, P10−P17, P20−P27
−1.0 mA
IOH(avg) “H” average output current (3)
P30−P37, P40−P47, P50−P57, P60−P62
−2.5 mA
IOL(avg) “L” average output current (3)
P00−P07, P10−P17, P20−P27
2.5 mA
IOL(avg) “L” average output current (3)
P40−P47, P50, P51, P54−P57, P60−P62
5.0 mA
IOL(avg) “L” average output current (3)
P30−P37, P52, P53
15 mA
QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 97 of 131

REJ03B0177-0302

38D2 Group

NOTES:

1. Relationship between system clock φ frequency and power source voltage is shown in the graph below.

2. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.

3. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

4. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and

operation temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency

oscillator.

5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.

Table 24 Recommended operating conditions (4)

(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Conditions Limits Unit

Min. Typ. Max.

f(CNTR0)

f(CNTR1)

Timer X and Timer Y

Input frequency (duty cycle 50%)

4.5 ≤ VCC ≤ 5.5V 6.25 MHz

4.0 ≤ VCC < 4.5V 2 × Vcc −4MHz

2.0 ≤ VCC < 4.0V Vcc MHz

VCC < 2.0V 5 × Vcc −8MHz

f(Tclk) Timer X, Timer Y,

Timer 1, Timer 2,

Timer 3, Timer 4 clock input frequency

(Count source frequency of each timer)

4.5 ≤ VCC ≤ 5.5V 16 MHz

4.0 ≤ VCC < 4.5V 4 × Vcc −8MHz

2.0 ≤ VCC < 4.0V 2 × Vcc MHz

VCC < 2.0V 10 × Vcc −16 MHz

f(φ)System clock φ frequency (1) 4.5 ≤ VCC ≤ 5.5V 6.25 MHz

4.0 ≤ VCC < 4.5V 4 MHz

2.0 ≤ VCC < 4.0V Vcc MHz

VCC < 2.0V 5 × Vcc −8MHz

f(XIN) Main clock input frequency

(duty cycle 50%) (2)(3)

4.5 ≤ VCC ≤ 5.5V 1.0 16 MHz

2.0 ≤ VCC < 4.5V 1.0 8.0 MHz

VCC < 2.0V 1.0 20 × Vcc −32 MHz

f(XCIN) Sub-clock oscillation frequency

(duty cycle 50%)(4)(5) 32.768 80 kHz

System clock φ frequency

[MHz]

6.25

4.0

2.0

1.0

01.8 2.0 4.0 4.5 5.5 [V]

Power source voltage

Main clock XIN frequency

[MHz]

8.0

4.0

1.0

01.8 2.0 4.5 5.5 [V]

Power source voltage

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 98 of 131

REJ03B0177-0302

38D2 Group

Electrical Characteristics

NOTE:

1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is “1”, the drivability of P62 is different from the above.

Table 25 Electrical characteristics (1)

(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

VOH “H” output voltage

P00−P07, P10−P17, P20−P27

IOH= −2.5mA VCC−2.0 V

IOH= −0.6mA

VCC=2.5V

VCC−1.0

VOH “H” output voltage

P30−P37, P40−P47, P50−P57,

P60−P62 (1)

IOH= −5mA VCC−2.0 V

IOH= −1.25mA VCC−0.5

IOH= −1.25mA

VCC=2.5V

VCC−1.0

VOL “L” output voltage

P00−P07, P10−P17, P20−P27

IOL=5mA 2.0 V

IOL=1.25mA 0.5

IOL=1.25mA

VCC=2.5V

1.0

VOL “L” output voltage

P40−P47, P50, P51, P54−P57,

P60−P61 (1)

IOL=10mA 2.0 V

IOL=2.5mA 0.5

IOL=2.5mA

VCC=2.5V

1.0

VOL “L” output voltage

P30−P37, P52, P53

IOL=15mA 2.0 V

IOL=3.0mA

VCC=2.5V

0.8

VT+ − VT−Hysteresis

CNTR0, CNTR1, INT0−INT2,

KW0−KW7

0.5 V

VT+ − VT−Hysteresis

RXD1, RXD2, SCLK1, SCLK2

0.5 V

VT+ − VT−Hysteresis

RESET

VCC = 2.0 V to 5.5 V on RESET 0.5 V

IIH “H” input current

P00−P07, P10−P17, P20−P27

VI=VCC 5.0 μA

IIH “H” input current

P30−P37, P40−P47, P50−P57,

P60−P62

VI=VCC 5.0 μA

IIH “H” input current

RESET

, OSCSEL

VI=VCC 5.0 μA

IIH “H” input current

XIN

VI=VCC 4.0 μA

IIL “L” input current

P00−P07, P10−P17, P20−P27

VI=VSS Pull-up “OFF” −5.0 μA

VCC=5.0V, VI=VSS Pull-up “ON” −60 −120 −240 μA

VCC=3.0V, VI=VSS Pull-up “ON” −25 −50 −100 μA

IIL “L” input current

P30−P37, P40−P47, P50−P57, P60−

P62

VI=VSS Pull-up “OFF” −5.0 μA

VCC=5.0V, VI=VSS Pull-up “ON” −30 −70 −140 μA

VCC=3.0V, VI=VSS Pull-up “ON” −6.5 −25 −45 μA

IIL “L” input current

RESET

, OSCSEL

VI=VSS −5.0 μA

IIL “L” input current

XIN

VI=VSS −4.0 μA

f(OCO) On-chip oscillator frequency VCC=5.0V, Ta =25°C 2500 5000 7500 kHz

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 99 of 131

REJ03B0177-0302

38D2 Group

A/D Converter Characteristics

NOTE:

1. Confirm the recommended operating condition for main clock input frequency.

Table 26 Electrical characteristics (2)

(Vcc = 1.8 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, A/D

converter stopped, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

VRAM RAM hold voltage When clock is stopped 1.8 5.5 V

ICC Power source current Frequency/2 mode VCC=5.0V f(XIN)=12.5MHz 6.4 13 mA

f(XIN)=12.5MHz (in WIT state) 1.5 3.0 mA

f(XIN)=4MHz 2.2 3.0 mA

VCC=2.5V f(XIN)=4MHz 0.6 1.2 mA

f(XIN)=4MHz (in WIT state) 0.3 0.6 mA

f(XIN)=2MHz 0.4 0.8 mA

Frequency/4 mode VCC=5.0V f(XIN)=12.5MHz 3.5 10 mA

f(XIN)=12.5MHz (in WIT state) 1.5 3.0 mA

f(XIN)=4MHz 1.5 2.5 mA

VCC=2.5V f(XIN)=8MHz 0.8 2.5 mA

f(XIN)=8MHz (in WIT state) 0.3 0.6 mA

f(XIN)=4MHz 0.5 1.0 mA

Frequency/8 mode VCC=5.0V f(XIN)=12.5MHz 2.5 5.0 mA

f(XIN)=12.5MHz (in WIT state) 1.5 3.0 mA

f(XIN)=4MHz 1.2 1.6 mA

VCC=2.5V f(XIN)=8MHz 0.5 1.0 mA

f(XIN)=8MHz (in WIT state) 0.3 0.6 mA

f(XIN)=4MHz 0.3 0.6 mA

Low-speed mode VCC=5.0V f(XIN)=stop 17 26 μA

in WIT state 5.5 11 μA

VCC=2.5V f(XIN)=stop 7.0 14 μA

in WIT state 3.5 7.0 μA

On-chip oscillator mode

f(XIN), f(XCIN) = stop

VCC=5.0V 270 540 μA

VCC=2.5V 35 90 μA

VCC=2.5V (in WIT state) 25 75 μA

All oscillations stopped

(in STP state)

Ta = 2 5 °C0.1 1.0 μA

Ta = 8 5 °C10 μA

Current increased

at A/D converter operating

f(XIN)=12.5 MHz, VCC=5 V

in frequency/2, 4 or 8 mode 0.5 mA

f(XIN)= stop, VCC = 5 V

in on-chip oscillator operating 0.5 mA

f(XIN) = stop, VCC = 5 V

in low-speed mode 0.4 mA

Table 27 A/D converter recommended operating condition

(Vcc = 2.0 to 5.5 V, VSS = 0V, Ta = −20 to 85°C, output transistors in cut-off state, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

VCC Power source voltage 2.0 5.0 5.5 V

VIH “H” input voltage ADKEY 0.9VCC VCC V

VIL “L” input voltage ADKEY 00.7

× VCC−0.5 V

f(φAD)AD converter clock frequency (1)

(Low-speed • on-chip oscillator mode excluded)

4.5V < VCC ≤ 5.5V 6.25 MHz

4.0V < VCC ≤ 4.5V 4.0 MHz

2.0V < VCC ≤ 4.0V VCC MHz

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 100 of 131

REJ03B0177-0302

38D2 Group

NOTES:

1. tc(φAD): one cycle of AD conversion clock. AD conversion clock can be selected from φSOURCE/2 or φSOURCE/8. φSOURCE

represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or

the low-speed mode.

When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) ≥ 500 kHz.

Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy.

Table 28 A/D converter characteristics

(Vcc = 2.0 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, low-speed • on-chip oscillator mode

included, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

−Resolution 10 Bits

ABS Absolute accuracy

(quantification error

excluded)

10bitAD

mode

4.5V < VCC ≤ 5.5V,

AD conversion clock

f(X

)/2, f(X

)/8

≤

6.25MHz

4LSB

4.0V < VCC ≤ 4.5V,

AD conversion clock

f(XIN)/2, f(XIN)/8 ≤ 4MHz

2.2V ≤ VCC ≤ 4.0V,

AD conversion clock

=f(X

)/2, f(X

)/8

≤

VccMHz

2.0V ≤ VCC ≤ 5.5V,

AD conversion clock

f(OCO)/8, f(OCO)/32

8bitAD

mode

4.5V < VCC ≤ 5.5V,

AD conversion clock

f(X

)/2, f(X

)/8

≤

6.25MHz

4.0V < VCC ≤ 4.5V,

AD conversion clock

f(XIN)/2, f(XIN)/8 ≤ 4MHz

2.2V < VCC ≤ 4.0V,

AD conversion clock

=f(X

)/2, f(X

)/8

≤

VccMHz

2.0V ≤ VCC ≤ 2.2V,

AD conversion clock

f(X

)/2, f(X

)/8

≤

(6Vcc

−

11)MHz

2.0V ≤ VCC ≤ 2.2V,

AD conversion clock

f(XIN)/8 ≤ VccMHz

2.0V ≤ VCC ≤ 5.5V,

AD conversion clock

f(OCO)/8, f(OCO)/32

tCONV Conversion time(1) 10bitAD mode tc(φAD)×61 tc(φAD)×62 μs

8bitAD mode tc(φAD)×49 tc(φAD)×50

RLADDER Ladder resistor 12 35 100 kΩ

IVREF Reference input

current

VREF=5.0V 50 150 200 μA

IIA Analog input current 5.0 μA

AD conversion clock frequency

[MHz]

6.25

4.0

2.2

2.0

1.0

01.8 2.0 2.2 4.0 4.5 5.5 [V]

Power source voltage VCC

Note: f(XIN) ≥ 500kHz

f(XIN)/2 or f(XIN)/8

8bitAD=2LSB

f(XIN)/8

8bitAD=2LSB

f(XIN)/2 or f(XIN)/8

10bitAD=4LSB

8bitAD=2LSB

AD conversion clock

•frequency/2 mode,

frequency/4 and

frequency/8 mode:

f(XIN)/2 or

f(XIN)/8

10bitAD=4LSB

8bitAD=2LSB

AD conversion clock

•Low-speed mode and

on-chip oscillator mode:

f(OCO)/8 or

f(OCO)/32

(Note)

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 101 of 131

REJ03B0177-0302

38D2 Group

LCD power supply characteristics

NOTE:

1. The value is the average of each one division resistor.

Table 29 LCD power supply characteristics (when connecting division resistors for LCD power supply)

(VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

RLCD Division resister for

LCD power supply (1)

RSEL=”10” 200 kΩ

RSEL=”11” 5

LCD drive

timing A

LCD circuit division ratio =

divided by 1

RSEL=”01” 120

RSEL=”00” 90

LCD circuit division ratio =

divided by 2

RSEL=”01” 150

RSEL=”00” 120

LCD circuit division ratio =

divided by 4

RSEL=”01” 170

RSEL=”00” 150

LCD circuit division ratio =

divided by 8

RSEL=”01” 190

RSEL=”00” 170

LCD drive

timing B

LCD circuit division ratio =

divided by 1

RSEL=”01” 150

RSEL=”00” 120

LCD circuit division ratio =

divided by 2

RSEL=”01” 170

RSEL=”00” 150

LCD circuit division ratio =

divided by 4

RSEL=”01” 190

RSEL=”00” 170

LCD circuit division ratio =

divided by 8

RSEL=”01” 190

RSEL=”00” 190

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 102 of 131
REJ03B0177-0302
38D2 Group
Timing Requirements and Switching Characteristics
NOTES:
1. 80 ns in the frequency/2 mode.
2. 32 ns in the frequency/2 mode.
3. When bit 6 of address 001A16, 001F16 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16, 001F16 are “0” (UART).
NOTE:
1. When bit 6 of address 001A16, 001F16 are “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16, 001F are “0” (UART).
Table 30 Timing requirements (1) 
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
tW(RESET) Reset input “L” pulse width 2 μs
tC(XIN) Main clock input
cycle time
4.5V ≤ VCC ≤ 5.5V (1) 62.5 ns
4.0V ≤ VCC < 4.5V 125 ns
tWH(XIN) Main clock input
“H” pulse width
4.5V ≤ VCC ≤ 5.5V (2) 25 ns
4.0V ≤ VCC < 4.5V 50 ns
tWL(XIN) Main clock input
“L” pulse width
4.5V ≤ VCC ≤ 5.5V (2) 25 ns
4.0V ≤ VCC < 4.5V 50 ns
tC(CNTR) CNTR0, CNTR1 input cycle time 250 ns
tWH(CNTR) CNTR0, CNTR1 input 
“H”
 pulse width 105 ns
tWL(CNTR) CNTR0, CNTR1 input 
“L”
 pulse width 105 ns
tWH(INT) INT0−INT2 input 
“H”
 pulse width 80 ns
tWL(INT) INT0−INT2 input 
“L”
 pulse width 80 ns
tC(SCLK)Serial I/O1, 2 clock input cycle time (3) 800 ns
tWH(SCLK)Serial I/O1, 2 clock input “H” pulse width (3) 370 ns
tWL(SCLK)Serial I/O1, 2 clock input 
“L”
 pulse width (3) 370 ns
tsu(RXD-SCLK) Serial I/O1, 2 input setup time 220 ns
th(SCLK-RXD) Serial I/O1, 2 input hold time 100 ns
Table 31 Timing requirements (2)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
tW(RESET) Reset input “L” pulse width 2 μs
tC(XIN) Main clock input cycle time 
(XIN input)
2.0V ≤ VCC ≤ 4.0V 125 ns
VCC < 2.0V 166 ns
tWH(XIN) Main clock input “H” pulse width 2.0V ≤ VCC ≤ 4.0V 50 ns
VCC < 2.0V 70 ns
tWL(XIN) Main clock input “L” pulse width 2.0V ≤ VCC ≤ 4.0V 50 ns
VCC < 2.0V 70 ns
tC(CNTR) CNTR0, CNTR1 input cycle time 2.0V ≤ VCC ≤ 4.0V 1000/VCC ns
VCC < 2.0V 1000/(5 × VCC-8) ns
tWH(CNTR) CNTR0, CNTR1 input “H” pulse width tc(CNTR)/2-20 ns
tWL(CNTR) CNTR0, CNTR1 input “L” pulse width tc(CNTR)/2-20 ns
tWH(INT) INT0−INT2 input “H” pulse width 230 ns
tWL(INT) INT0−INT2  input “L” pulse width 230 ns
tC(SCLK)Serial I/O1, 2 clock input cycle time (1) 2000 ns
tWH(SCLK)Serial I/O1, 2 clock input “H” pulse width (1) 950 ns
tWL(SCLK)Serial I/O1, 2 clock input “L” pulse width (1) 950 ns
tsu(RXD-SCLK) Serial I/O1, 2 input setup time 400 ns
th(SCLK-RXD)Serial I/O1, 2 input hold time 200 ns
QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 103 of 131

REJ03B0177-0302

38D2 Group

NOTE:

1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [001F16]) of UART control register is “0”.

NOTE:

1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [001F16]) of UART control register is “0”.

Fig 94. Circuit for measuring output switching characteristics

Table 32 Switching characteristics (1)

(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ Max.

tWH(SCLK) Serial I/O1, 2 clock output “H” pulse width tc(SCLK)/2-30 ns

tWL(SCLK) Serial I/O1, 2 clock output “L” pulse width tc(SCLK)/2-30 ns

td(SCLK-TxD) Serial I/O1, 2 output delay time (1) 140 ns

tv(SCLK-TxD) Serial I/O1, 2 output valid time (1) −30 ns

tr(SCLK) Serial I/O1, 2 clock output rising time 30 ns

tf(SCLK) Serial I/O1, 2 clock output falling time 30 ns

Table 33 Switching characteristics (2)

(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ Max.

tWH(SCLK) Serial I/O1, 2 clock output “H” pulse width tc(SCLK)/2-80 ns

tWL(SCLK) Serial I/O1, 2 clock output “L” pulse width tc(SCLK)/2-80 ns

td(SCLK-TxD) Serial I/O1, 2 output delay time (1) 350 ns

tv(SCLK-TxD) Serial I/O1, 2 output valid time (1) -30 ns

tr(SCLK) Serial I/O1, 2 clock output rising time 80 ns

tf(SCLK) Serial I/O1, 2 clock output falling time 80 ns

Measurement output pin

100pF

CMOS output

Measurement output pin

100pF

N-channel open-drain output (Note)

Note: When bit 4 of the UART control register

(address 001B16 [address 0FF116]) is “1.”

(N-channel open-drain output mode)

1kΩ

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 104 of 131

REJ03B0177-0302

38D2 Group

Fig 95. Timing diagram

tC(CNTR)

tWL(CNTR)

tWH(CNTR)

0.8VCC 0.2VCC

CNTR0, CNTR1

INT0−INT2

RESET

tWL(INT)tWH(INT)

0.8VCC 0.2VCC

0.8VCC

0.2VCC

tW(RESET)

tC(SCLK)

tWL(SCLK)

0.8VCC

0.2VCC

tWH(SCLK)

tftr

tsu(RXD-SCLK)th(SCLK-RXD)

td(SCLK-TXD) tV(SCLK-TXD)

0.2VCC

0.8VCC

SCLK1

SCLK2

RXD1

RXD2

TXD1

TXD2

XIN

tC(XIN)

tWL(XIN)

tWH(XIN)

0.8VCC 0.2VCC

QzROM VERSION

Rev.3.02 Apr 10, 2008 Page 105 of 131

REJ03B0177-0302

38D2 Group

FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Table 34 Absolute maximum ratings

Symbol Parameter Conditions Ratings Unit

VCC Power source voltage

All voltages are based on

VSS.

When an input voltage is

measured, output

transistors are cut off.

−0.3 to 6.5 V

VIInput voltage

P00−P07, P10−P17, P20−P27, P30−P37, P40−P47,

P50−P57, P60−P62

−0.3 to VCC+0.3 V

VIInput voltage VL1 −0.3 to VL2 V

VIInput voltage VL2 VL1 to VL3 V

VIInput voltage VL3 VL2 to 6.5 V

VIInput voltage RESET, XIN, CNVSS −0.3 to VCC+0.3 V

VOOutput voltage

P00−P07, P10−P17, P20−P27

At output port −0.3 to VCC+0.3 V

At segment output −0.3 to VL3+0.3 V

VOOutput voltage COM0−COM3−0.3 to VL3+0.3 V

VOOutput voltage

−

, P4

−

, P5

−

, P6

−

−0.3 to VCC+0.3 V

VOOutput voltage XOUT −0.3 to VCC+0.3 V

Pd Power dissipation Ta=25°C 300 mW

Topr Operating temperature −−20 to 85 °C

Tstg Storage temperature - −40 to 125 °C

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 106 of 131

REJ03B0177-0302

38D2 Group

Recommended Operating Conditions

NOTES:

1. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.

2. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

Table 35 Recommended operating conditions (1)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ. Max.

VCC Power source

voltage(1)

Frequency/2 mode (2) f(XIN) ≤ 12.5MHz 4.5 5.5 V

f(XIN) ≤ 8MHz 4.0 5.5 V

f(XIN) ≤ 4MHz 2.7 5.5 V

Frequency/4 mode f(XIN) ≤ 16MHz 4.5 5.5 V

f(XIN) ≤ 8MHz 2.7 5.5 V

Frequency/8 mode f(XIN) ≤ 16MHz 4.5 5.5 V

f(XIN) ≤ 8MHz 2.7 5.5 V

Low-speed mode 2.7 5.5 V

On-chip oscillator mode 2.7 5.5 V

VSS Power source voltage 0V

VL3 LCD power source voltage 2.5 5.5 V

VREF A/D converter reference voltage 2.7 VCC V

AVSS Analog power source voltage 0 V

VIA Analog input voltage AN0−AN7AVSS VCC V

VIH “H” input voltage P04−P07, P10−P17, P20−P27, P30, P32, P35,

P36, P40−P47, P52, P53, P62

0.7VCC VCC V

VIH “H” input voltage P00−P03, P31, P33, P34, P37, P50, P51, P54−

P57, P60, P61

0.8VCC VCC V

VIH “H” input voltage RESET 0.8VCC VCC V

VIH “H” input voltage XIN 0.8VCC VCC V

VIL “L” input voltage P04−P07, P10−P17, P20−P27, P30, P32, P35,

P36, P40−P47, P52, P53, P62

00.3VCC V

VIL “L” input voltage P00−P03, P31, P33, P34, P37, P50, P51, P54−

P57, P60, P61, CNVSS

00.2VCC V

VIL “L” input voltage RESET 00.2VCC V

VIL “L” input voltage XIN 00.2VCC V

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 107 of 131
REJ03B0177-0302
38D2 Group
NOTES:
1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average 
value measured over 100 ms. The total peak current is the peak value of all the currents. 
2. The peak output current is the peak current flowing in each port.
3. The average output current is average value measured over 100 ms.
Table 36 Recommended operating conditions (3)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)
Symbol Parameter Limits Unit
Min. Typ. Max.
ΣIOH(peak) “H” total peak output current (1)
P00−P07, P10−P17, P20−P27, P30−P37
−40 mA
ΣIOH(peak) “H” total peak output current (1)
P40−P47, P50−P57, P60−P62
−40 mA
ΣIOL(peak) “L” total peak output current (1)
P00−P07, P10−P17, P20−P27
40 mA
ΣIOL(peak) “L” total peak output current (1)
P40−P47, P50, P51, P54−P57, P60−P62
40 mA
ΣIOL(peak) “L” total peak output current (1)
P30−P37, P52, P53
110 mA
ΣIOH(avg) “H” total average output current (1)
P00−P07, P10−P17, P20−P27, P30−P37
−20 mA
ΣIOH(avg) “H” total average output current (1)
P40−P47, P50−P57, P60−P62
−20 mA
ΣIOL(avg) “L” total average output current (1)
P00−P07, P10−P17, P20−P27
20 mA
ΣIOL(avg) “L” total average output current (1)
P40−P47, P50, P51, P54−P57, P60−P61
20 mA
ΣIOL(avg) “L” total average output current (1)
P30−P37, P52, P53
90 mA
IOH(peak) “H” peak output current (2)
P00−P07, P10−P17, P20−P27
−2.0 mA
IOH(peak) “H” peak output current (2)
P30−P37, P40−P47, P50−P57, P62−P62
−5.0 mA
IOL(peak) “L” peak output current (2)
P00−P07, P10−P17, P20−P27
5.0 mA
IOL(peak) “L” peak output current (2)
P40−P47, P50, P51, P54−P57, P60−P62
10 mA
IOL(peak) “L” peak output current (2)
P30−P37, P52, P53
30 mA
IOH(avg) “H” average output current (3)
P00−P07, P10−P17, P20−P27
−1.0 mA
IOH(avg) “H” average output current (3)
P30−P37, P40−P47, P50−P57, P60−P62
−2.5 mA
IOL(avg) “L” average output current (3)
P00−P07, P10−P17, P20−P27
2.5 mA
IOL(avg) “L” average output current (3)
P40−P47, P50, P51, P54−P57, P60−P62
5.0 mA
IOL(avg) “L” average output current (3)
P30−P37, P52, P53
15 mA
FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 108 of 131

REJ03B0177-0302

38D2 Group

NOTES:

1. Relationship between system clock φ frequency and power source voltage is shown in the graph below.

2. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter.

3. 12.5 MHz < f(XIN) ≤ 16 MHz is not available in the frequency/2 mode.

4. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and

operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency

oscillator.

5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.

Table 37 Recommended operating conditions (4)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Conditions Limits Unit

Min. Typ. Max.

f(CNTR0)

f(CNTR1)

Timer X and Timer Y

Input frequency (duty cycle 50%)

4.5V ≤ VCC ≤ 5.5V 6.25 MHz

4.0V ≤ VCC < 4.5V 2×Vcc−4MHz

2.7V ≤ VCC < 4.0V Vcc MHz

f(Tclk) Timer X, Timer Y, Timer 1, Timer 2,

Timer 3, Timer 4 clock input frequency

(Count source frequency of each timer)

4.5V ≤ VCC ≤ 5.5V 16 MHz

4.0V ≤ VCC < 4.5V 4×Vcc−8MHz

2.7V ≤ VCC < 4.0V 2×Vcc MHz

f(φ)System clock φ frequency (1) 4.5V ≤ VCC ≤ 5.5V 6.25 MHz

4.0V ≤ VCC < 4.5V 4 MHz

2.7V ≤ VCC < 4.0V Vcc MHz

f(XIN) Main clock input frequency

(duty cycle 50%) (2)(3)

4.5V ≤ VCC ≤ 5.5V 1.0 16 MHz

2.7V ≤ VCC < 4.5V 1.0 8.0 MHz

f(XCIN)Sub-clock oscillation frequency (duty cycle 50%) (4)(5) 32.768 80 kHz

4.0 4.5 5.5

2.7

4.0

6.25

[MHz]

[V]

System clock φ frequency

Power source voltage

02.7

2.7 4.5 5.5

8.0

[MHz]

[V]

Main clock XIN frequency

Power source voltage

1.0

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 109 of 131

REJ03B0177-0302

38D2 Group

Electrical Characteristics

NOTE:

1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is “1”, the drivability of P62 is different from the above.

Table 38 Electrical characteristics (1)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

VOH “H” output voltage

P00−P07, P10−P17, P20−P27

IOH= −2.5mA VCC−2.0 V

VOH “H” output voltage

P30−P37, P40−P47, P50−P57, P60−

P62(1)

IOH= −5mA VCC−2.0 V

IOH= −1.25mA VCC−0.5 V

VOL “L” output voltage

P00−P07, P10−P17, P20−P27

IOL=5mA 2.0 V

IOL=1.25mA 0.5

VOL “L” output voltage

P40−P47, P50, P51, P54−P57, P60−

P62(1)

IOL=10mA 2.0 V

IOL=2.5mA 0.5

VOL “L” output voltage

P30−P37, P52, P53

IOL=15mA 2.0 V

VT+−VT−Hysteresis

CNTR0, CNTR1, INT0−INT2, KW0−

KW7

0.5 V

VT+−VT−Hysteresis

RxD1, RxD2, SCLK1, SCLK2

0.5 V

VT+−VT−Hysteresis RESET 0.5 V

IIH “H” input current

P00−P07, P10−P17, P20−P27

VI=VCC 5.0 μA

IIH “H” input current

P30−P37, P40−P47, P50−P57, P60−P62

VI=VCC 5.0 μA

IIH “H” input current RESET, CNVSS VI=VCC 5.0 μA

IIH “H” input current XIN VI=VCC 4.0 μA

IIL “L” input current

P00−P07, P10−P17, P20−P27

VI=VSS

Pull-up “OFF” −5.0 μA

VCC=5.0V, VI=VSS

Pull-up “ON” −60 −120 −240 μA

VCC=3.0V, VI=VSS

Pull-up “ON” −25 −50 −100 μA

IIL “L” input current

P30−P37, P40−P47, P50−P57, P60−P67

VI=VSS

Pull-up “OFF” −5.0 μA

VCC=5.0V, VI=VSS

Pull-up “ON” −30 −70 −140 μA

VCC=3.0V, VI=VSS

Pull-up “ON” −6.5 −25 −45 μA

IIL “L” input current RESET, CNVSS VI=VSS −5.0 μA

IIL “L” input current XIN VI=VSS −4.0 μA

f(OCO) On-chip oscillator frequency VCC=5V, Ta=25°C 2500 5000 7500 kHz

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 110 of 131

REJ03B0177-0302

38D2 Group

A/D Converter Characteristics

NOTE:

1. Confirm the recommended operating condition for main clock input frequency.

Table 39 Electrical characteristics (2)

(Vcc = 2.7 to 5.5 V, VSS = 0 V, Ta = −20 to 85°C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state,

A/D converter stopped, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

VRAM RAM hold voltage When clock is stopped 2.2 5.5 V

ICC Power source current Frequency/2 mode Vcc=5.0V f(XIN)=12.5MHz 4.0 7.0 mA

f(XIN)=12.5MHz (in WIT state) 2.0 3.5 mA

f(XIN)=4MHz 2.0 3.5 mA

Vcc=2.7V f(XIN)=4MHz 1.5 3 mA

f(XIN)=4MHz (in WIT state) 1.0 2.5 mA

f(XIN)=2MHz 1.0 2.5 mA

Frequency/4 mode Vcc=5.0V f(XIN)=12.5MHz 3.2 5.6 mA

f(XIN)=12.5MHz (in WIT state) 1.6 3.2 mA

f(XIN)=4MHz 1.6 3.2 mA

Vcc=2.7V f(XIN)=8MHz 1.6 3.2 mA

f(XIN)=8MHz (in WIT state) 1.0 2.5 mA

f(XIN)=4MHz 1.0 2.5 mA

Frequency/8 mode Vcc=5.0V f(XIN)=12.5MHz 2.5 5 mA

f(XIN)=12.5MHz (in WIT state) 1.5 3 mA

f(XIN)=4MHz 1.5 3 mA

Vcc=2.7V f(XIN)=8MHz 1.5 3 mA

f(XIN)=8MHz (in WIT state) 1.0 2.5 mA

f(XIN)=4MHz 1.0 2.5 mA

Low-speed mode Vcc=5.0V f(XIN)=stop 400 800 μA

in WIT state Ta=2 5°C4.0 10 μA

Ta=8 5°C20

Vcc=2.7V f(XIN)=stop 300 600 μA

in WIT state Ta=25°C3.79

μA

Ta=8 5°C18

On-chip oscillator mode

f(XIN), f(XCIN): stop

Vcc=5.0V 600 1200 μA

Vcc=2.7V 500 1000 μA

Vcc=2.7V (in WIT state) 500 1000 μA

All oscillations are stopped

(in STP state)

Ta = 2 5 °C0.63.0μA

Ta = 8 5 °C1.0μA

Current increased at A/D

converter operating

f(XIN)=12.5MHz, VCC=5V

in frequency/2, 4 or 8 mode

1.0 mA

f(XIN)=stop, VCC=5V

in on-chip oscillator operating

1.0 mA

f(XIN)=stop, VCC=5V

in low-speed mode

0.8 mA

Table 40 A/D converter recommended operating condition

(Vcc = 2.7 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

VCC Power source voltage 2.7 5.0 5.5 V

VIH “H” input voltage ADKEY 0.9VCC VCC V

VIL “L” input voltage ADKEY 00.7

× VCC − 0.5 V

f(φAD)AD converter clock frequency (1)

(Low-speed • on-chip oscillator

mode excluded)

4.5V < VCC ≤ 5.5V 6.25 MHz

4.0V < VCC ≤ 4.5V 4.0 MHz

2.7V < VCC ≤ 4.0V VCC MHz

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 111 of 131

REJ03B0177-0302

38D2 Group

NOTES:

1. tc(φAD): one cycle of AD conversion clock. AD conversion clock can be selected from φSOURCE/2 or φSOURCE/8. φSOURCE

represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or

the low-speed mode.

When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) ≥ 500 kHz.

Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy.

Table 41 A/D converter characteristics

(Vcc = 2.7 to 5.5 V, Ta = −20 to 85°C, output transistors in cut-off state, low-speed • on-chip oscillator mode

included, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

−Resolution 10 Bits

ABS Absolute accuracy

(quantification error

excluded)

10bitAD

mode

4.5V < VCC ≤ 5.5V,

AD conversion clock

=f(XIN)/2, f(XIN)/8≤6.25MHz

4LSB

4.0V < VCC ≤ 4.5V,

AD conversion clock

=f(XIN)/2, f(XIN)/8≤4MHz

2.7V ≤ VCC ≤ 4.0V,

AD conversion clock

=f(XIN)/2, f(XIN)/8≤VccMHz

2.7V ≤ VCC ≤ 5.5V,

f(OCO)/8, f(OCO)/32

8bitAD

mode

4.5V < VCC ≤ 5.5V,

AD conversion clock

=f(XIN)/2, f(XIN)/8≤6.25MHz

4.0V < VCC ≤ 4.5V,

AD conversion clock

=f(XIN)/2, f(XIN)/8≤4MHz

2.7V ≤ VCC ≤ 4.0V,

AD conversion clock

=f(XIN)/2, f(XIN)/8≤VccMHz

2.7V ≤ VCC ≤ 5.5V,

f(OCO)/8, f(OCO)/32

tCONV Conversion time(1) 10bitAD mode tc(φAD) × 61 tc(φAD) × 62 μs

8bitAD mode tc(φAD) × 49 tc(φAD) × 50

RLADDER Ladder resistor 12 35 100 kΩ

IVREF Reference input

current

VREF=5V 50 150 200 μA

IIA Analog input

current

5.0 μA

4.0 4.5 5.5

4.0

6.25

[MHz]

[V]

AD conversion clock frequency

Power source voltage VCC

Note: f(XIN) ≥ 500kHz

2.7

10bitAD=4LSB

8bitAD=2LSB

AD conversion clock

• frequency/2 mode,

frequency/4 and

frequency/8 mode:

f(XIN)/2 or

f(XIN)/8

(Note)

AD conversion clock

• Low-speed mode and

on-chip oscillator mode:

f(OCO)/8 or

f(OCO)/32

f(XIN)/2 or f(XIN)/8

10bitAD=4LSB

8bitAD=2LSB

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 112 of 131

REJ03B0177-0302

38D2 Group

LCD power supply characteristics

NOTE:

1. The value is the average of each one division resistor.

Table 42 LCD power supply characteristics (when connecting division resistors for LCD power supply)

(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

RLCD Division resister for

LCD power supply (1)

RSEL=”10” 200 kΩ

RSEL=”11” 5

LCD drive

timing A

LCD circuit division ratio =

divided by 1

RSEL=”01” 120

RSEL=”00” 90

LCD circuit division ratio =

divided by 2

RSEL=”01” 150

RSEL=”00” 120

LCD circuit division ratio =

divided by 4

RSEL=”01” 170

RSEL=”00” 150

LCD circuit division ratio =

divided by 8

RSEL=”01” 190

RSEL=”00” 170

LCD drive

timing B

LCD circuit division ratio =

divided by 1

RSEL=”01” 150

RSEL=”00” 120

LCD circuit division ratio =

divided by 2

RSEL=”01” 170

RSEL=”00” 150

LCD circuit division ratio =

divided by 4

RSEL=”01” 190

RSEL=”00” 170

LCD circuit division ratio =

divided by 8

RSEL=”01” 190

RSEL=”00” 190

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 113 of 131

REJ03B0177-0302

38D2 Group

Timing Requirements And Switching Characteristics

NOTES:

1. 80 ns in the frequency/2 mode.

2. 32 ns in the frequency/2 mode.

3. When bit 6 of address 001A16, 001F16 are “1” (clock synchronous).

Divide this value by four when bit 6 of address 001A16, 001F16 are “0” (UART).

NOTE:

1. When bit 6 of address 001A16, 001F16 are “1” (clock synchronous).

Divide this value by four when bit 6 of address 001A16, 001F16 are “0” (UART).

Table 43 Power supply circuit characteristics

(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Test conditions Limits Unit

Min. Typ. Max.

td(P-R) Internal power source voltage

stabilizes time at power-on

2.7 ≤ VCC ≤ 5.5V 2 ms

Table 44 Timing requirements (1)

(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ. Max.

tW(RESET) Reset input “L” pulse width 2 μs

tC(XIN) Main clock input cycle time 4.5V ≤ VCC ≤ 5.5V (1) 62.5 ns

4.0V ≤ VCC < 4.5V 125 ns

tWH(XIN) Main clock input “H” pulse width 4.5V ≤ VCC ≤ 5.5V (2) 25 ns

4.0V ≤ VCC < 4.5V 50 ns

tWL(XIN) Main clock input “L” pulse width 4.5V ≤ VCC ≤ 5.5V (2) 25 ns

4.0V ≤ VCC < 4.5V 50 ns

tC(CNTR) CNTR0, CNTR1 input cycle time 250 ns

tWH(CNTR) CNTR0, CNTR1 input

“H”

pulse width 105 ns

tWL(CNTR) CNTR0, CNTR1 input

“L”

pulse width 105 ns

tWH(INT) INT0−INT2 input

“H”

pulse width 80 ns

tWL(INT) INT0−INT2 input

“L”

pulse width 80 ns

tC(SCLK)Serial I/O1, 2 clock input cycle time (3) 800 ns

tWH(SCLK)Serial I/O1, 2 clock input “H” pulse width (3) 370 ns

tWL(SCLK)Serial I/O1, 2 clock input

“L”

pulse width (3) 370 ns

tsu(RxD-SCLK) Serial I/O1, 2 input setup time 220 ns

th(SCLK-RxD) Serial I/O1, 2 input hold time 100 ns

Table 45 Timing requirements (2)

(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ. Max.

tW(RESET) Reset input “L” pulse width 2 μs

tC(XIN) Main clock input cycle time (XIN input) 125 ns

tWH(XIN) Main clock input “H” pulse width 50 ns

tWL(XIN) Main clock input “L” pulse width 50 ns

tC(CNTR) CNTR0, CNTR1 input cycle time 1000/VCC ns

tWH(CNTR) CNTR0, CNTR1 input “H” pulse width tc(CNTR)/2−20 ns

tWL(CNTR) CNTR0, CNTR1 input “L” pulse width tc(CNTR)/2−20 ns

tWH(INT) INT0−INT2 input “H” pulse width 230 ns

tWL(INT) INT0−INT2 input “L” pulse width 230 ns

tC(SCLK) Serial I/O1, 2 clock input cycle time 2000 ns

tWH(SCLK) Serial I/O1, 2 clock input “H” pulse width 950 ns

tWL(SCLK) Serial I/O1, 2 clock input “L” pulse width 950 ns

tsu(RXD-SCLK) Serial I/O1, 2 input setup time 400 ns

th(SCLK-RXD) Serial I/O1, 2 input hold time 200 ns

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 114 of 131

REJ03B0177-0302

38D2 Group

NOTE:

1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [0FF116]) of UART control register is “0”.

NOTE:

1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [0FF116]) of UART control register is “0”.

Fig 96. Circuit for measuring output switching characteristics

Table 46 Switching characteristics (1)

(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ Max.

tWH (SCLK) Serial I/O1, 2 clock output “H” pulse width tC(SCLK)/2−30 ns

tWL (SCLK) Serial I/O1, 2 clock output “L” pulse width tC(SCLK)/2−30 ns

td (SCLK-TXD) Serial I/O1, 2 output delay time (1) 140 ns

tV (SCLK-TXD) Serial I/O1, 2 output valid time (1) −30 ns

tr (SCLK) Serial I/O1, 2 clock output rising time 30 ns

tf (SCLK) Serial I/O1, 2 clock output falling time 30 ns

Table 47 Switching characteristics (2)

(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = −20 to 85°C, unless otherwise noted)

Symbol Parameter Limits Unit

Min. Typ Max.

tWH (SCLK) Serial I/O1, 2 clock output “H” pulse width tC(SCLK)/2−80 ns

tWL (SCLK) Serial I/O1, 2 clock output “L” pulse width tC(SCLK)/2−80 ns

td (SCLK-TXD) Serial I/O1, 2 output delay time (1) 350 ns

tV (SCLK-TXD) Serial I/O1, 2 output valid time (1) −30 ns

tr (SCLK) Serial I/O1, 2 clock output rising time 80 ns

tf (SCLK) Serial I/O1, 2 clock output falling time 80 ns

Measurement output pin

100pF

CMOS output

Measurement output pin

100pF

N-channel open-drain output (Note)

1kΩ

Note: When bit 4 of the UART control register

(address 001B16 [address 0FF116]) is “1.”

(N-channel open-drain output mode)

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 115 of 131

REJ03B0177-0302

38D2 Group

Fig 97. Timing diagram (in single-chip mode)

INT0−INT2

CNTR0, CNTR1

0.2VCC

tWL(INT)

0.8VCC

tWH(INT)

0.2VCC

0.8VCC

0.2VCC

tWL(XIN)

0.8VCC

tWH(XIN)

tc(XIN)

XIN

0.2VCC 0.8VCC

tw(RESET)

tftr

0.2VCC

tWL(CNTR)

0.8VCC

tWH(CNTR)

tc(CNTR)

td(SCLK-TXD)

tV(SCLK-TXD)

tC(SCLK)

tWL(SCLK)tWH(SCLK)

th(SCLK-RXD)

tsu(RXD-SCLK)

TXD1

TXD2

RXD1

RXD2

SCLK1

SCLK2

RESET

FLASH MEMORY VERSION

Rev.3.02 Apr 10, 2008 Page 116 of 131

REJ03B0177-0302

38D2 Group

PACKAGE OUTLINE

Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas

Technology website.

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

116

Index mark

Detail F

Previous CodeJEITA Package Code RENESAS Code

PLQP0064GA-A 64P6U-A

MASS[Typ.]

0.7gP-LQFP64-14x14-0.80

1.0

0.125

0.35

1.0

0.20

0.145

0.09

0.420.370.32

MaxNomMin

Dimension in Millimeters

Symbol

Reference

14.114.013.9

1.4

16.216.015.8

1.7

0.20.1

0.70.50.3

8°0°

0.8

0.10

Rev.3.02 Apr 10, 2008 Page 117 of 131

REJ03B0177-0302

38D2 Group

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

116

3348

Detail F

P-LQFP64-10x10-0.50 0.3g

MASS[Typ.]

64P6Q-A / FP-64K / FP-64KVPLQP0064KB-A

RENESAS CodeJEITA Package Code Previous Code

1.0

0.125

0.18

1.25

0.08

0.20

0.145

0.09

0.250.200.15

MaxNomMin

Dimension in Millimeters

Symbol

Reference

10.110.0

9.9

10.110.0

9.9

1.4

12.212.011.8

1.7

0.15

0.1

0.05

0.65

0.5

0.35

8°0°

0.5

0.08

Rev.3.02 Apr 10, 2008 Page 118 of 131

REJ03B0177-0302

38D2 Group

APPENDIX

Note on Programming

1. Processor Status Register

(1) Initialization of the processor status register

It is required to initialize the processor status register (PS) flags

which affect program execution. It is particularly essential to

initialize the T and D flags because of their effect on

calculations. Initialize these flags at the beginning of the

program.

At a reset, the contents of the processor status register (PS) are

undefined except for the I flag which is “1”.

Fig. 98 Initialization of processor status register flags

(2) How to refer the processor status register

To refer the contents of the processor status register (PS), execute

the PHP instruction once and then read the contents of (S+1). If

necessary, execute the PLP instruction to return the stored PS to

its original status.

Fig. 99 Stack memory contents after PHP instruction

execution

2. Decimal Calculations

(1) Instructions for decimal calculations

To perform decimal calculations, set the decimal mode (D) flag

to “1” with the SED instruction and execute the ADC or SBC

instruction. In that case, after the ADC or SBC instruction,

execute another instruction before the SEC, CLC, or CLD

instruction.

Fig. 100 Instructions for decimal calculations

(2) Status flag at decimal calculations

When the ADC or SBC instruction is executed in decimal mode

(D flag = “1”), three of the status flags (N, V, and Z) are disabled.

The carry (C) flag is set to “1” if a carry is generated and is

cleared to “0” if a borrow is generated as a result of a calculation,

so it can be used to determine whether the calculation has

generated a carry or borrow.

Initialize the C flag before each calculation.

Reset

Initialize the flags

Main program

Stored PS

(S)

(S) + 1

Set the decimal mode (D) flag to “1”

Execute the ADC or SBC instruction

NOP

Execute the SEC, CLC, or CLD instruction

Rev.3.02 Apr 10, 2008 Page 119 of 131

REJ03B0177-0302

38D2 Group

3. JMP Instruction

When using the JMP instruction (indirect addressing mode), do

not specify the address where “FF16” is allocated to the low-

order 8 bits as the operand.

4. Multiplication and Division Instructions

(1) The MUL and DIV instructions are not affected by the T and

D flags.

(2) Executing these instructions does not change the contents of

the processor status register.

5. Read-Modify-Write Instruction

Do not execute any read-modify-write instruction to the read

invalid (address) SFR.

The read-modify-write instruction reads 1-byte of data from

memory, modifies the data, and writes 1-byte the data to the

original memory.

In the 740 Family, the read-modify-write instructions are the

following:

(1) Bit handling instructions:

CLB, SEB

(2) Shift and rotate instructions:

ASL, LSR, ROL, ROR, RRF

(3) Add and subtract instructions:

DEC, INC

(4) Logical operation instructions (1’s complement):

COM

Although not the read-modify-write instructions, add and

subtract/logical operation instructions (ADC, SBC, AND, EOR,

and ORA) when T flag = “1” operate in the way as the read-

modify-write instruction. Do not execute them to the read invalid

SFR.

When the read-modify-write instruction is executed to the read

invalid SFR, the following may result:

As reading is invalid, the read value is undefined. The instruction

modifies this undefined value and writes it back, so the written

value will be indeterminate.

Notes on Peripheral Functions

Notes on I/O Ports

1. Use in Stand-By State

When using the MCU in stand-by state*1 for low-power

consumption, do not leave the input level of an I/O port

undefined. Be especially careful to the I/O ports for the N-

channel open-drain.

In this case, pull-up (connect to Vcc) or pull-down (connect to

Vss) these ports through a resistor.

When determining a resistance value, note the following:

• External circuit

• Variation in the output level during ordinary operation

When using a built-in pull-up resistor, note variations in current

values:

• When setting as an input port: Fix the input level

• When setting as an output port: Prevent current from

flowing out externally.

Even if a port is set to output by the direction register, when the

content of the port latch is “1”, the transistor becomes the OFF

state, which allows the port to be in the high-impedance state.

This may cause the level to be undefined depending on external

circuits.

As described above, if the input level of an I/O port is left

undefined, the power source current may flow because the

potential applied to the input buffer in the MCU will be unstable.

*1 Stand-by state: Stop mode by executing the STP instruction

Wait mode by executing the WIT instruction

2. Modifying Output Data with Bit Handling Instruction

When the port latch of an I/O port is modified with the bit

handling instruction*1, the value of an unspecified bit may

change.

I/O ports can be set to input mode or output mode in byte units.

When the port register is read or written, the following will be

operated:

• Port as input mode

Read: Read the pin level

Write: Write to the port latch

• Port as output mode

Read: Read the port latch or peripheral function output

(specifications vary depending on the port)

Write: Write to the port latch (output the content of the port

latch from the pin)

Meanwhile, the bit handling instructions are the read-modify-

write instructions*2. Executing the bit handling instruction to the

port register allows reading and writing a bit unspecified with the

instruction at the same time.

If an unspecified bit is set to input mode, the pin level is read and

the value is written to the port latch. At this time, if the original

content of the port latch and the pin level do not match, the

content of the port latch changes.

If an unspecified bit is set to output mode, the port latch is

normally read, but the peripheral function output is read in some

ports and the value is written to the port latch. At this time, if the

original content of the port latch and the peripheral function

output do not match, the content of the port latch changes.

*1 Bit handling instructions: CLB, SEB

*2 Read-modify-write instruction: Reads 1-byte of data from

memory, modifies the data, and writes 1-byte of the data to

the original memory.

Rev.3.02 Apr 10, 2008 Page 120 of 131

REJ03B0177-0302

38D2 Group

3. Direction Registers

The values of the port direction registers cannot be read. This

means, it is impossible to use the LDA instruction, memory

operation instruction when the T flag is “1”, addressing mode

using direction register values as qualifiers, and bit test

instructions such as BBC and BBS. It is also impossible to use bit

operation instructions such as CLB and SEB, and read-modify-

write instructions to direction registers, including calculations

such as ROR. To set the direction registers, use instructions such

as LDM or STA.

4. Pull-Up Control

Only for the pin set to input mode, pull-up is controlled by the

PULL register and the segment output disable register.

Notes on Termination of Unused Pins

1. Termination of Unused Pins

Perform the following at the shortest possible distance (20 mm or

less) from the MCU pins.

(1) I/O ports

Set the ports to input mode and connect each pin to VCC or VSS

through a resistor of 1 k to 10 kΩ. An internal pull-up resistor can

also be used for the port where the internal pull-up resister is

selectable.

To set the ports to output mode, leave open at “L” or “H” output.

• When setting the ports to output mode and leave open,

input mode in the initial state remains until the mode of the

ports are switched to output mode by a program after a

reset. This may cause the voltage level of the pins to be

undefined and the power source current to increase while

the ports remains in input mode. For any effects on the

system, careful system evaluations should be implemented

on the user side.

• The direction registers may be changed due to a program

runaway or noise, so reset the registers periodically by a

program to increase the program reliability.

2. Termination Concerns

(1) When setting I/O ports to input mode

[1] Do not leave open

• The power source current may increase depending on the

first-stage circuit.

• The ports are more likely affected by noise when compared

with the termination shown on the above “1. (1) I/O ports”

[2] Do not connect to VCC or VSS directly

If the direction registers are changed to output mode due to a

program runaway or noise, a short circuit may occur.

[3] Do not connect multiple ports in a lump to VCC or VSS

through a resistor.

If the direction registers are changed to output mode due to a

program runaway or noise, a short circuit may occur between the

ports.

Rev.3.02 Apr 10, 2008 Page 121 of 131

REJ03B0177-0302

38D2 Group

Notes on Interrupts

1. Changing Related Register Settings

If the interrupt occurrence synchronized with the following

settings is not required, take the sequence shown below.

• When selecting the external interrupt active edge

• When selecting the interrupt source of the interrupt vector

address where two or more interrupt sources are allocated

Fig. 101 Sequence for setting related register

In the following cases, the interrupt request bit of the

corresponding interrupt may be set to “1”.

•INT

0 interrupt edge selection bit

(bit 0 of interrupt edge selection register (address 003A16))

•INT

1 interrupt edge selection bit

(bit 1 of interrupt edge selection register)

•INT2 interrupt edge selection bit

(bit 2 of interrupt edge selection register)

•CNTR

0 active edge switch bits

(bits 6 and 7 of timer X control register 1 (address 002E16))

•CNTR

1 active edge switch bit

(bits 6 of timer Y mode register (address 003816))

<When switching the interrupt source of the interrupt vector

address where two or more interrupt sources are allocated>

• INT2/Key input interrupt switch bit

(bit 3 of interrupt edge selection register)

• Timer Y/CNTR1 interrupt switch bit

(bit 4 of interrupt edge selection register)

2. Checking Interrupt Request Bit

To check the interrupt request bit with the BBC or BBS

instruction immediately after this bit is set to “0”, take the

following sequence.

If the BBC or BBS instruction is executed immediately after the

interrupt request bit is set to “0”, the bit value before being set to

“0” is read.

Fig. 102 Sequence for setting interrupt request bit

3. Setting Unused Interrupts

Set the interrupt enable bit of the unused interrupt to “0”

(disabled).

Set the interrupt edge selection bit (active edge

switch bit) or interrupt (source) selection bit.

NOP (one or more instructions)

Set the corresponding interrupt enable bit to

“0” (disabled).

Set the corresponding interrupt request bit to “0”

(no interrupt request).

Set the corresponding interrupt enable bit to “1”

(enabled).

NOP (one or more instructions)

Set the interrupt request bit to “0” (no interrupt)

Execute the BBC or BBS instruction

Rev.3.02 Apr 10, 2008 Page 122 of 131

REJ03B0177-0302

38D2 Group

Notes on Timers

1. Frequency Divider

All timers shares one circuit for the frequency divider to generate

the count source.

Thus the frequency divider is not initialized when each

individual timer is activated. When the frequency divider is

selected as the count source, a one-cycle delay of the maximum

count source will result between when the timer is activated and

when it starts counting or outputs the waveform.

The count source cannot be observed externally.

2. Division Ratio for Timer 1 to 4

The division ratio is 1/(n+1) when the value n (0 to 255) is

written to the timer latch.

3. Switching Frequency and Count Source for Timer 1

to 4, X, and Y

Switch the frequency division or count source* while the timer

count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

4. Setting Timer 1 and 2 When STP Instruction

Executed

Before executing the STP instruction, first set the wait time at

return.

5. Setting Order to Timer 1 to 4

When switching the count source of timer 1 to timer 4, a narrow

pulse may be generated at the count input, which causes the timer

count value to be undefined. Also, if the timers are used in

cascade connection, a narrow pulse may be generated at the

output when writing to the pervious timer, which causes the next

timer count value to be undefined.

Thus set the value from timer 1 in order after setting the count

source of timer 1 to timer 4.

6. Write to Timer 2, 3, and 4

When writing to the latch only, if the write timing to the reload

latch and the underflow timing are almost the same, the value is

set into the timer and the timer latch at the same time. At this

time, count is stopped during write operation to the reload latch.

7. Timer 3 PWM0 Mode, Timer 4 PWM1 Mode

(1) When PWM output is suspended once it starts, the time to

resume outputting may be delayed one section (256 × ts) of

the short interval depending on the level of the output pulse

at that time:

Stop at “H”: No output delay

Stop at “L”: Output is delayed time of 256 × ts

(2) When PWM mode is used, the interrupt requests and values

of timer 3 and timer 4 are updated every cycle of the long

interval (4 × 256 × ts).

8. Write Order to Timer X

(1) When timer mode, pulse output mode, event counter mode,

or pulse width measurement mode is set, write to the

following registers in the order below:

The timer X register (extension)

The timer X register (low-order)

The timer X register (high-order)

Writing to only one of these registers cannot be performed.

When either of the above modes is set and timer X operates

as a 16-bit counter, if the timer X register (extension) is never

set after a reset release, setting the timer X register

(extension) is not required. In that case, write the timer X

next. However, once the timer X register (extension) is

written, note that the value is retained in the reload latch.

(2) Write to the timer X register by the 16-bit unit. Do not read

the timer X register while write operation is performed. If the

write operation is not completed, normal operation will not

be performed.

(3) When IGBT output mode or PWM mode is set, do not write

“1” to the timer X register (extension). If “1” has been

already written to the timer X register, be sure to write “0” to

the register before use.

Write to the following registers in the order below:

The compare registers 1, 2, 3 (high- and low-order)

The timer X register (extension)

The timer X register (low-order)

The timer X register (high-order)

The compare registers (high- and low-order) can be written

in either order. However, be sure to write both the compare

registers 1, 2, 3 and the timer X register at the same time.

9. Read Order to Timer X

(1) In all modes, read the following registers in the order below:

The timer X register (extension)

The timer X register (high-order)

The timer X register (low-order)

When reading the timer X register (extension) is not

required, read the timer X register (high-order) first and the

timer X register (low-order) next.

The read order to the compare registers 1, 2, 3 is not

specified.

(2) Read the timer X register in 16-bit units. Do not write to it

during read operation. If read operation is terminated in

progress, normal operation will not be performed.

Rev.3.02 Apr 10, 2008 Page 123 of 131

REJ03B0177-0302

38D2 Group

10. Write to Timer X

(1) Timer X can select either writing data to both the latch and

the timer at the same time or writing data only by the timer

X write control bit (b3) in the timer X mode register

(address 002D16). When writing to the latch only, if a value

is written to the timer X address, the value is set into the

reload latch and the timer is updated at the next underflow.

After a reset release, if a value is written to the timer X

address, the value is set into the timer and the timer latch at

the same time, because they are written simultaneously.

When writing to the latch only, if the write timing to the

high-order reload latch and the underflow timing are almost

the same, the value is set into the timer and the timer latch at

the same time. At this time, count is stopped during write

operation to the high-order reload latch.

(2) Switch the frequency division or count source* while the

timer count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

11. Setting Timer X Mode Register

When PWM mode or IGBT output mode is set, be sure to set the

write control bit in the timer X mode register to “1” (writing to

latch only). After writing to the timer X register (high-order), the

contents of both registers are simultaneously reflected in the

output waveform at the next underflow.

12. Timer X Output Control Functions

To use the output control functions (INT1 and INT2), set the

levels of INT1 and INT2 to “H” for the falling edge active or to

“L” for the rising edge active before switching to IGBT output

mode.

13. CNTR0 Active Edge Selection

(1) Setting the CNTR0 active edge switch bits also affects the

interrupt active edge at the same time.

(2) When the pulse width is measured, set bit 7 of the CNTR0

active edge switch bits to “0”.

14. When Timer X Pulse Width Measurement Mode

Used

When timer X pulse mode measurement mode is used, enable the

event counter wind control data (bit 5 of timer X mode register

(address 002D16)) by setting to “0”.

If the event counter window control data (bit 5 of timer X mode

enable/disable the CNTR0 input, the input is not accepted after

the timer 1 underflow.

15. CNTR1 Active Edge Selection

Setting the CNTR1 active edge switch bits also affects the

interrupt active edge at the same time.

However, in pulse width HL continuous HL measurement mode,

the CNTR1 interrupt request is generated at both rising and

falling edges of the pin regardless of the settings of the CNTR1

active edge switch bits.

16. Read from/Write to Timer Y

(1) When reading from/writing to timer Y, read from/write to

both the high-order and low-order bytes of timer Y. To read

the value, read the high-order bytes first and the low-order

bytes next. To write the value, write the low-order bytes first

and the high-order bytes next.

Writing/reading should be preformed in 16-bit units. If

write/read operation is changed in progress, normal

operation will not be performed.

(2) Timer Y can select either writing data to both the latch and

the timer at the same time or writing data only by the timer

Y write control bit (b0) in the timer Y control register

(address 003916). When writing to the latch only, if a value

is written to the timer Y address, the value is set into the

reload latch and the timer is updated at the next underflow.

After a reset release, if a value is written to the timer Y

address, the value is set into the timer and the timer latch at

the same time, because they are written simultaneously.

When writing to the latch only, if the write timing to the

high-order reload latch and the underflow timing are almost

the same, the value is set into the timer and the timer latch at

the same time. At this time, count is stopped during write

operation to the high-order reload latch.

(3) Switch the frequency division or count source* while the

timer count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

17. Real time port control

When switching the setting of the real time port control bits

between valid and invalid, write to the timer Y mode register in

byte units with the LDM or STA instruction so that both bits are

switched at the same time. Also, before using this function, set

the P46 and P47 port direction registers to output.

Rev.3.02 Apr 10, 2008 Page 124 of 131

REJ03B0177-0302

38D2 Group

Notes on Serial I/O1

Becaouse the operation of the serial I/O2 is as same as serial

I/O1, the following notes are written about the serial I/O1.

1. Write to Baud Rate Generator

Write to the baud rate generator while transmission/reception is

stopped.

2. Setting Sequence When Serial I/O1 Transmit

Interrupt Used

To use the serial I/O1 transmit interrupt, if the interrupt

occurrence synchronized with settings is not required, take the

following sequence:

(1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of

interrupt control register 2 (address 003F16)) to “0”

(disabled).

(2) Set the transmit enable bit to “1”.

(3) After one or more instructions have been executed, set the

serial I/O1 transmit interrupt request bit (bit 2 of interrupt

request register 2 (address 003D16)) to “0” (no interrupt).

(4) Set the serial I/O1 transmit interrupt enable bit to “1”

(enabled).

When the transmit enable bit is set to “1”, the transmit buffer

empty flag (bit 0 of serial I/O1 status register) and the transmit

shift completion flag are set to “1”.

This allows an interrupt request to be generated regardless of

which interrupt occurrence source has been selected by the

transmit interrupt source selection bit (bit 3 of serial I/O1 control

“1”.

3. Data Transmission Control Using Transmit Shift

Completion Flag

After transmit data is written to the transmit buffer register, the

transmit shift completion flag (bit 2 of serial I/O1 status register

(address 001916)) changes from “1” to “0” after a delay of 0.5 to

1.5 cycles of the system clock. Thus, after transmit data is written

to the transmit buffer register, note this delay when controlling

data transmission by referencing the transmit shift completion

flag.

4. Setting Serial I/O1 Control Register

Before setting the serial I/O1 control register again, first set both

the transmit enable bit and the receive enable bit to “0” and

initialize the transmission and reception circuits.

Fig. 103 Sequence of setting serial I/O1 control register

5. Pin Status After Transmission Completed

After transmission is completed, the TxD pin retains the level

when transmission is completed.

When the internal clock is selected in clock synchronous serial

I/O mode, the SCLK1 pin is set to “H”.

6. Serial I/O1 Enable Bit during Transmit Operation

During transmission, if the serial I/O1 enable bit (bit 7 of serial

I/O1 control register (address 001A16)) is set to “0”, the pin

function is set to an I/O port and the internal transmit operation

continues even though transmit data is not output externally.

Also, if the transmit buffer register is written in this state,

transmit operation starts internally. If the serial I/O1 enable bit is

set to “1” at this time, transmit data is output to the TxD pin from

that point.

7. Transmission Control When External Clock

Selected

During data transmission, if the external clock is selected as the

synchronous clock, set the transmit enable bit to “1” while SCLK1

is set to “H”. Also, write to the transmit buffer register while

SCLK1 is set to “H”.

8. Receive Operation in Clock Synchronous Serial I/O

Mode

During reception in clock synchronous serial I/O mode, set both

the transmit enable bit and the receive enable bit to “1”. Then

write dummy data to the transmit buffer register. When the

internal clock is selected as the synchronous clock, the

synchronous clock is output at this point and receive operation

starts. When the external clock is selected, reception is enabled at

this point and inputting the external clock starts transmit

operation.

The P55/TXD1 [P32/TxD2] pin outputs dummy data written in the

transmit buffer register.

9. Transmit/Receive Operation in Clock Synchronous

Serial I/O Mode

In clock synchronous serial I/O mode, set the transmit enable bit

and the receive enable bit to “0” simultaneously to stop

transmit/receive operations. If only one of the operations is

stopped, transmission and reception cannot be synchronized,

which will cause a bit error.

Set bits 0 to 3, and 6 of the serial I/O1 control

Set both the transmit enable bit (TE) and the

receive enable bit (RE) to “0”

Set both the transmit enable bit (TE) and the receive

enable bit (RE), or one of them to “1”.

Settings can be made with

the LDM instruction at the

same time

Rev.3.02 Apr 10, 2008 Page 125 of 131

REJ03B0177-0302

38D2 Group

Notes on A/D Conversion

1. Analog Input Pin

Set the signal source impedance for analog input low, or equip an

analog input pin with an external capacitor of 0.01 μF to 1 μF.

In addition, operations of application products should be verified

thoroughly on the user side.

An analog input pin has a built-in capacitor for analog voltage

comparison. Thus if a signal from the high impedance signal

source is input to the analog input pin, charge and discharge

noise will be generated. This may cause the A/D

conversion/comparison accuracy to drop.

2. Clock Frequency during A/D Conversion

The comparator input consists of a capacity coupling. If the

conversion rate is too low, the A/D conversion accuracy may

deteriorate due to a charge lost, so set f(XIN) 500 kHz or more for

A/D conversion in XIN mode. Also, do not execute the STP or

WIT instruction during A/D conversion.

In low-speed mode (when on-chip oscillator is selected), as A/D

conversion is performed using the internal on-chip oscillator,

there is no limit on the minimum frequency for f(XIN).

3. ADKEY Function

When the ADKEY enable bit is set to “1”, the analog input pin

selection bits are disabled. Do not execute the A/D conversion by

a program while ADKEY is enabled. Enabling ADKEY does not

change bits 0 to 2 of ADCON.

4. A/D Conversion Immediately After ADKEY Function

Started

In the ADKEY function, A/D conversion is not performed to the

analog input voltage immediately after starting the function. This

causes the A/D conversion result immediately after starting the

function to be undefined. If the A/D conversion result of the

analog input voltage applied to the ADKEY pin is required,

select the analog input pin corresponding to ADKEY before

performing A/D conversion.

5. Input Voltage Applied to ADKEY Pin

Set the input to the ADKEY pin into a steep falling waveform

and stabilize the input voltage within eight cycles (1 μs when

f(XIN) = 8 MHz) from the moment the input voltage reaches VIL

or lower.

The actual threshold voltage for the ADKEY pin is between VIH

and VIL.

To prevent unnecessary ADKEY operation due to noise or other

factors, set the ADKEY pin voltage to VIH (0.9 VCC) or more

while the input is waited.

6. Register Operation during A/D Conversion

The A/D conversion operation is not guaranteed if the following

are preformed:

• The CPU mode register is operated during A/D conversion

operation

• The AD control register is operated during A/D conversion

operation

• The STP or WIT instruction is executed during A/D

conversion operation

7. A/D Converter Power Source Pin

Connect to the A/D converter power source pin to AVSS or VSS

whether the A/D conversion function is used or not.

If the AVSS pin is left open, the MCU may operate incorrectly

because the pin will be affected by noise or other factors.

Rev.3.02 Apr 10, 2008 Page 126 of 131

REJ03B0177-0302

38D2 Group

Notes on LCD Drive Control Circuit

1. Setting Data to LCD Display RAM

To write data to the LCD display RAM when the LCD enable bit

is set to “1” and while LCD is turned on, set fixed data.

Rewriting with temporary data may cause LCD to flicker. The

following shows a processing example to write data to the LCD

display RAM while LCD is turned on.

Fig. 104 Processing example when writing data to LCD display RAM While LCD Turned On

(1) Ccorrect processing

LCD

on or

off

*Content at address 004016: “FF16”

Off

Set LCD display RAM data

LRAM0 (address 004016) ← “FF16”

LCD on or off?

Set LCD display RAM data

LRAM0 (address 004016) ←“0016”・Set fixed data to LCD display RAM

(2) Incorrect processing

LCD

on or

off

*Content at address 004016: “FF16”

Off

Set LCD display RAM data

LRAM0 (address 004016) ← “FF16”

LCD on or off?

Set LCD display RAM data

LRAM0 (address 004016) ←“0016”・Set off data to LCD display RAM

LCD

off

・Set fixed data to LCD display RAM

Rev.3.02 Apr 10, 2008 Page 127 of 131

REJ03B0177-0302

38D2 Group

2. Executing STP Instruction

Execution of the STP instruction sets the LCD enable bit (bit 3 of

the LCD mode register) and bits 0 to 5 and bit 7 of the LCD

power control register to “0” and the LCD panel turns off. To

make the LCD panel turn on after returning from the stop mode,

set these bits to “1”.

3. VL3 Pin

To use the LCD drive control circuit while VL3 is set to the

voltage equal to VCC, apply the VCC voltage to the VL3 pin and

write “1” to the VL3 connection bit of LCD power control

4. LCD Drive Power Supply

Power supply capacitor may be insufficient with the division

resistance for LCD power supply, and the characteristic of the

LCD panel. In this case, there is the method of connecting the

bypass capacitor about 0.1−0.33μF to VL1−VL3 pins. The

example of a strengthening measure of the LCD drive power

supply is shown below.

Fig. 105 Strengthening measure example of LCD drive

power supply

Notes on ROM Correction Function

1. Returning to Main Program

To return to the main program from the correction program, use

the JMP instruction (3-byte instruction).

2. Using ROM Correction Function

If the ROM correction function is used, be sure to enable the

ROM correction enable bit after setting the ROM correction

3. Address

Do not set addresses other than the ROM area in the ROM

correction address registers. Also, do not set the same address in

the ROM correction address 1 register and the ROM correction

address 2 register.

4. ROM Correction Process

Include the ROM correction process in the program beforehand.

5. Using No ROM Correction Function

If the ROM correction function is not used, the ROM correction

vector can be used as normal RAM/ROM. When using as normal

RAM/ROM, be sure to set bits 1 and 0 of the ROM correction

enable register to “0” (disabled).

Notes on Clock Generating Circuit

1. Oscillation Circuit Constants

The oscillation circuit constants vary depending on the resonator.

Use values recommended by the oscillator manufacturer.

A feed-back resistor is implemented between the XIN and XOUT

pins (an external feed-back resistor may be required depending

on conditions). As no feed-back resistor is implemented between

XCIN and XCOUT, add a feedback resistor of about 10 MΩ.

2. Transition between Modes

When the MCU transits between on-chip oscillator mode, XIN

mode, or low-speed mode, both the XIN and XCIN oscillations

must be stabilized. Be especially careful when turning the power

on and returning from stop mode. Refer to the clock state

transition diagram for a transition between each mode. Also, set

the frequency in the condition that f(XIN) ≥ 3 × (XCIN).

When XIN mode is not used (the XIN-XOUT oscillation or

external clock input to XIN is not performed), connect XIN to

VCC through a resistor.

3. Oscillation Stabilization

Before executing the STP instruction, set the values * to generate

the wait time required for oscillation stabilization to timer 1 latch

and timer 2 latch (low-order 8 bits of timer 1 and high-order 8

bits of timer 2).

*Referential values

(Set values according to your oscillator and system)

• OSCSEL = “L” in the flash memory and QzROM versions:

..................................................................... 000516 or more

•OSCSEL = “H” in the QzROM version:

.....................................................................01FF16 or more

4. Low-Speed Mode, XIN Mode

To use low-speed mode or XIN mode, wait until oscillation

stabilizes after enabling the XIN-XOUT and XCIN-XCOUT

oscillation, then switch to the mode.

• Connect by the shortest

possible wiring.

• Connect the bypass capacitor

to the VL1 −VL3 pins as short

as possible.

(Referential value:0.1−0.33 μF)

VL3

VL2

VL1

Rev.3.02 Apr 10, 2008 Page 128 of 131

REJ03B0177-0302

38D2 Group

Notes on Flash Memory Mode

• CPU Rewrite Mode

(1) Operating Speed

During CPU rewrite mode, set the system clock φ to 4.0 MHz or

less using the main clock division ratio selection bits (bits 6 and

7 of address 003B16).

(2) Prohibited Instructions

During CPU rewrite mode, the instructions which reference data

in the flash memory cannot be used.

(3) Interrupts

During CPU rewrite mode, interrupts cannot be used because

they reference data in the flash memory.

(4) Watchdog Timer

If the watchdog timer has been running already, the internal reset

by underflow will not occur because the watchdog timer is

continuously cleared during program or erase operation.

(5) Reset

Reset is always valid. If CNVSS = “H” when a reset is released,

boot mode is active. The program starts from the address stored

in addresses FFFC16 and FFFD16 in boot ROM area.

Notes on Watchdog Timer

1. Watchdog Timer Underflow

The watchdog timer does not operate in stop mode, but it

continues counting during the wait time to release the stop state

and in wait mode. Write to the watchdog timer control register so

that the watchdog timer will not underflow during these periods.

2. Stopping On-Chip Oscillator Oscillation

When the on-chip oscillator is selected by the watchdog timer

count source selection bit 2, the on-chip oscillator forcibly

oscillates and it cannot be stopped. Also, in this time, set the STP

instruction function selection bit to “1” at this time.

Select “0” (φSOURCE) for the watchdog timer count source

selection bit 2 at the system which on-chip oscillator is stopped.

3. Watchdog Timer Control Register

Bits 7 to 5 can be rewritten only once after a reset. After writing,

rewriting is disabled because they are locked. These bits are set

to “0” after a reset.

Notes on Differences between QzROM Version and

Flash Memory Version

The flash memory and QzROM versions differ in their

manufacturing processes, built-in ROM, memory size, and

layout patterns. Because of these differences, characteristic

values, operation margins, noise immunity, and noise radiation

and oscillation circuit constants may vary within the specified

range of electrical characteristics.

When switching to the QzROM version, implement system

evaluations equivalent to those performed in the flash memory

version.

Confirm page 11 about the differences of functions.

Notes on Power Source Voltage

When the power supply voltage value of the MCU is less than

the value indicated in the recommended operating conditions, the

MCU may not operate normally and perform unstable operation.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power is turned off, reset

the MCU when the power source voltage is less than the

recommended operating conditions, and design the system so

that this unstable operation does not cause errors to it.

Notes on Handling Power Source Pins

Before using the MCU, connect a capacitor suitable for high

frequencies as a bypass capacitor between the following:

The power source pin (VCC pin) and the GND pin (VSS pin)

The power source pin (VCC pin) and the analog power source

input pin (AVSS pin). As a bypass capacitor, a ceramic capacitor

of 0.01 μF to 0.1 μF is recommended.

Also, use the shortest possible wiring to connect a bypass

capacitor between the power source pin and the GND pin and

between the power source pin and the analog power source pin.

Notes on Memory

1. RAM

The RAM content is undefined at a reset. Be sure to set the initial

value before use.

Rev.3.02 Apr 10, 2008 Page 129 of 131

REJ03B0177-0302

38D2 Group

Notes on QzROM Version

Wiring to OSCSEL pin

(1) OSCSEL = L

Connect the OSCSEL pin the shortest possible to the GND

pattern which is supplied to the VSS pin of the microcomputer. In

addition connecting an approximately 5 kΩ resistor in series to

the GND could improve noise immunity. In this case as well as

the above mention, connect the pin the shortest possible to the

GND pattern which is supplied to the VSS pin of the

microcomputer.

(2) OSCSEL = H

Connect the OSCSEL pin the shortest possible to the VCC pattern

which is supplied to the VCC pin of the microcomputer. In

addition connecting an approximately 5 kΩ resistor in series to

the VCC could improve noise immunity. In this case as well as

the above mention, connect the pin the shortest possible to the

VCC pattern which is supplied to the VCC pin of the

microcomputer.

The OSCSEL pin is the power source input pin for the built-in

QzROM.

When programming in the QzROM, the impedance of the

OSCSEL pin is low to allow the electric current for writing to

flow into the built-in QzROM. Because of this, noise can enter

easily. If noise enters the OSCSEL pin, abnormal instruction

codes or data are read from the QzROM, which may cause a

program runaway.

Fig. 106 Wiring for OSCSEL pin

Overvoltage in QzROM Version

Make sure that voltage exceeding the VCC pin voltage is not

applied to other pins. In particular, ensure that the state indicated

by bold lines in figure below does not occur for pin OSCSEL pin

(VPP power source pin for QzROM) during power-on or power-

off. Otherwise the contents of QzROM could be rewritten.

Fig. 107 Timing Diagram (Bold-lined periods are applicable)

QzROM Version Product Shipped in Blank

As for the product shipped in blank, Renesas does not perform

the writing test to user ROM area after the assembly process

though the QzROM writing test is performed enough before the

assembly process. Therefore, a writing error of approximate

0.1% may occur.

Moreover, please note the contact of cables and foreign bodies on

a socket, etc. because a writing environment may cause some

writing errors.

Ordering QzROM Writing

1. Notes On QzROM Writing Orders

When ordering the QzROM product shipped after writing,

submit the mask file (extension: .msk) which is made by the

mask file converter MM.

• Be sure to set the ROM option data* setup when making the

mask file by using the mask file converter MM.. The ROM

code protect is specified according to the ROM option data* in

the mask file which is submitted at ordering. Note that the

mask file which has nothing at the ROM option data* or has

the data other than “0016”, “FE16” and “FF16” can not be

accepted.

•Set “FF16” to the ROM code protect address in ROM data

regardless of the presence or absence of a protect. When data

other than “FF16” is set, we may ask that the ROM data be

submitted again.

* ROM option data: mask option noted in MM

2. Data Required for QzROM Ordering

The following are necessary when ordering a QzROM product

shipped after writing:

• QzROM Writing Confirmation Form*

• Mark Specification Form*

• ROM data: Mask file

* For the QzROM writing confirmation form and the mark

specification form, refer to the “Renesas Technology Corp.”

Homepage (http://www.renesas.com/homepage.jsp).

Note that we cannot deal with special font marking (customer's

trademark etc.) in QzROM microcomputer.

3. QzROM Product Receiving Procedure

When writing to QzROM is performed by user side, the

receiving inspection by the following flow is necessary.

OSCSEL

VSS

The shortest

about 5 kΩ

Termination of OSCSEL pin

OSCSEL

VCC

The shortest

about 5 kΩ

(1) OSCSEL = L (2) OSCSEL = H

(1)

Note 1: It shows the microcomputer’s pin

VCC pin voltage

OSCSEL pin voltage

“H” input

OSCSEL pin voltage

“L” input

1.8V 1.8V

(1) Input voltage to other MCU pins rises before VCC pin voltage.

(2) Input voltage to other MCU pins falls after VCC pin voltage.

Note: The internal circuitry is unstable when VCC is below the minimum voltage

specification of 1.8 V (shaded portion), so particular care should be

exercised regarding overvoltage.

(1) (2)

∼

∼∼

∼

Rev.3.02 Apr 10, 2008 Page 130 of 131

REJ03B0177-0302

38D2 Group

Fig. 108 QzROM receiving procedure

Notes on Flash Memory Version

CPU Rewrite Mode

1. Operating Speed

QzROM product shipped in blank

Programming

Verify test

Receiving inspection of

unprotected area (Verify test)

Programming to unprotected area

Verify test for unprotected area

Shipping

User

QzROM product shipped after writing

“protect disabled”

“protect enabled to the protect area 1”

Renesas

Receiving inspection

(Blank check)

Programming

Verify test for all area

Shipping

User

Renesas

Rev.3.02 Apr 10, 2008 Page 131 of 131

REJ03B0177-0302

38D2 Group

During CPU rewrite mode, set the system clock

4.0 MHz or

less using the main clock division ratio selection bits (bits 6 and

7 of address 003B16).

2. Prohibited Instructions

The instructions which refer to the internal data of the flash

memory cannot be used during the CPU rewrite mode.

3. Interrupts

The interrupts cannot be used during the CPU rewrite mode

because they refer to the internal data of the flash memory.

4. Watchdog Timer

In case of the watchdog timer has been running already, the

internal reset generated by watchdog timer underflow does not

happen, because of watchdog timer is always clearing during

program or erase operation.

5. Reset

Reset is always valid. In case of CNVSS = “H” when reset is

released, boot mode is active. So the program starts from the

address contained in address FFFC16 and FFFD16 in boot ROM

area.

CNVSS Pin

The CNVSS pin determines the flash memory mode.

Connect the CNVSS pin the shortest possible to the GND pattern

which is supplied to the VSS pin of the microcomputer.

In addition connecting an approximately 5 kΩ. resistor in series

to the GND could improve noise immunity. In this case as well as

the above mention, connect the pin the shortest possible to the

GND pattern which is supplied to the VSS pin of the

microcomputer.

Note. When the boot mode or the standard serial I/O mode is used, a

switch of the input level to the CNVSS pin is required.

Fig. 109 Wiring for CNVSS pin

The shortest

CNVSS

VSS

Approx. 5kΩ

The shortest

(1)

Note 1: It shows the microcomputer’s pin.

(1/4)

REVISION HISTORY 38D2 Group Datasheet

Rev. Date Description

Page Summary

1.00 Jan. 23, 2006 −First edition issued

2.00 Mar. 24, 2006 1 FEATURES : Description of reset circuit eliminated and Power source voltage

revised.

3 Performance overview: Oscillation frequency and Power source voltage revised.

4 FUNCTIONAL BLOCK DIAGRAM : Description of reset circuit eliminated.

7 Fig. 4 and Table 3 38D29GC, 38D29G8 added.

12 Fig. 9 Memory map diagram revised.

15 Table 7 Non-port function of port P54−P57 revised.

Related SFRs of port P40 and P41 revised.

18 Fig. 15 (18) Port P61 revised.

26 Fig. 22 Timer 12 mode register revised.

29 Notes on Timer X: (1), (2) revised.

32 • Real Time Port Control revised.

36 Fig. 32 UART control register revised.

38 Fig. 34 Note 1 revised.

42 Fig. 38 Note 2 revised.

48 Fig. 46 Memory map revised.

49 Note 1 revised.

50 Clock output function revised.

51 Reset circuit revised.

53 (1)Stop mode: Description revised.

54 Fig. 58 φSOURCE added.

55 Fig. 60 State transitions of system clock: Note 3 revised.

56 Address of oscillation ouput control register revised.

60 Fig. 64 Connection of XIN and XOUT revised.

65-75 Electrical characteristics added.

2.01 Nov. 15, 2006 1 DESCRIOTION revised

Power dissipation described.

3 Main clock / Sub-clock generating circuits: Built-in feed back resistor → Built-in

Power dissipation described.

5AV

SS: GND input pin → Analog power source input pin

12 ROM and ROM Code Protect Address : Description revised.

Fig. 9 is revised.

15 Table 7 : As for CKOUT, non-port function and related SFRs are added.

19 Termination of unused pins : As for I/O ports, description added.

VL3 : Terminations 1 and 2 revised.

25 Timer 1, Timer 2 : Description revised.

28 Timer X : Description revised.

29 Fig. 24 : TXCON1 bit 5 = 1 → TXCON1 bit 5 = 0

31 Timer Y : Description revised.

Fig. 26 : Note added.

37 Fig. 33 : Note and φ source added.

REVISION HISTORY

(2/4)

REVISION HISTORY 38D2 Group Datasheet

2.01 Nov. 15, 2006 42 LCD Power Circuit

• Description added

• Fig. 38 : Note 3 eliminated

• Fig. 39 : Bit name described

48 Fig. 46 : Reserved ROM area address revised.

ROM CORRECTION FUNCTION : Description added.

49 Fig. 48 : On-chip oscillator → On-chip oscillator/4

Note added.

Fig. 49 : On-chip oscillator → On-chip oscillator/4

φ source/1024 → Count sorce/1024

φ source/4 → Count sorce/4

53 (5) Low-speed Mode : Description added

54 Fig. 58 : Note added and circuit expression is revised.

56 Fig. 61 : Circuit expression is revised.

57 Table 12: As for VREF and AVSS, function revised.

59 to 62 Fig. 63 to Fig. 66 added and revised.

71 Table 17

IIH and IIL : OSCSEL added.

75 Table 23: Note revised.

3.01 Sep.18, 2007 −Flash memory version function: added

1 DESCRIPTION: flash memory version contents added

FEATURES: flash memory version contents added

Power source voltages: flash memory version contents added

Power dissipation: flash memory version contents added

Flash memory mode: added

2 Fig. 1: Note is added

3 Table 1: Power source voltage: revised and flash memory version contents added

Power dissipation: flash memory version contents added

5 Table 2: LED0 to 7 and KW0 to 3 are added to pin name

6 Pin discription table is divided (to Table 2 and Table 3)

Table 3: CNVSS pin is added

7 Fig. 3: F (Flash memory) is added to memory type

8 Flash memory size is added

Fig. 4: Some “Under developing” are erased

9 Table 3: Flash memory version products are added

10 Table 5 “Differences between QzROM and flash memory versions” and “Notes on

Differences between QzROM and Flash Memory Versions” are added

12 Fig. 6: “Push contents of processor status register on stack” position is moved

14 CPU mode register explanation is revised

Fig. 7: Some notes are added

15 Fig. 8: Flash memory version flow is added

16 Fig. 9: Flash memory version SRF is added

17 Fig. 10: Flash memory version SRF and notes are added

19 Table 2: LED0 to 7 and KW0 to 3 are added to pin name

24-28 “Interrupt” is wholly revised

32 “Frequency Divider for Timer” is revised

35 “Frequency Divider for Timer” is revised

Rev. Date Description

Page Summary

(3/4)

REVISION HISTORY 38D2 Group Datasheet

3.01 Sep.18, 2007 35 “(6) Pulse Width Measurement Mode” is revised

36 “(3) Write To Timer X” is revised

37 “(7) When Timer X Pulse Width Measurement Mode Used”

38 “(5) Real Time Port Control” is added

39 “Notes on Timer Y” is revised

44 “Conparator and Control Circuit” is revised

45 Fig. 37: Revised

“ADKEY Control Circuit” is revised

56 “Initial value of watchdog timer” is revised

“Bit 6 of Watchdog Timer Control Register” and “<Notes>” are revised

Fig. 51: Revised

Fig. 52: Revised

57 Fig. 54: Revised

“[RRF register (RRFR)]” is added

58 Explaination is revised

Fig. 56: revised

Fig. 57: Notes are added

59 Fig. 58: Revised

60 Explanation is revised

62 Fig. 61: Revised

63 Fig. 62: Revised

65 Table 14: Revised

71-88 “Flash Memory Mode” is added

89 Revised to “Notes on Use” from “Notes on Programming” contents

90 Added “NOTES on QzROM VERSION”

91 Added “NOTES on FLASH MEMORY VERSION” and “NOTES ON DIFFERENCES

BETWEEN QzROM VERSION AND FLASH MEMORY VERSION”

94 Table 21: Revised

95-101 Table 22 to 29: “VSS=0V” are added to condition

95 Table 22: VIL of XCIN is deleted

98 Table 25: “VCC = 4.0 t

o 5.0 V” → “VCC = 1.8 to 5.5 V”

100 Table 28:

• ABS of 10bitAD mode

“2.2V < VCC ≤ 4.0V” → “2.2V ≤ VCC ≤ 4.0V”

“1.8V ≤ VCC ≤ 5.5V” → “2.0V ≤ VCC ≤ 5.5V”

• ABS of 8bitAD mode

“2.2V < VCC ≤ 4.0V” → “2.2V ≤ VCC ≤ 4.0V”

“1.8V ≤ VCC ≤ 5.5V” → “2.0V ≤ VCC ≤ 5.5V”

•tCONV is separated to 10bitAD mode and 8bitADmode, and note is added

102 Table 30: TC, TwH, and TwL of XIN

“4.5 V to 5.5 V” → “4.5V ≤ VCC ≤ 5.5V”

“4.0 V to 5.5 V” → “4.0V ≤ VCC ≤ 5.5V”

Table 31: TC of XIN and CNTR, and TwH and TwL of XIN

“2.0V < VCC ≤ 4.0V” → “2.0V ≤ VCC ≤ 4.0V”

“VCC ≤ 2.0V” → “VCC < 2.0V”

104 Fig. 95: XCIN timing is deleted

105-115 Flash memory version electrical characteristics is added

Rev. Date Description

Page Summary

(4/4)

REVISION HISTORY 38D2 Group Datasheet

3.01 Sep.18, 2007 118-131 Appendix is added

3.02 Apr. 09, 2008 2 Fig. 1: Revised

3 Table 1: Revised

5 Table 2: Revised

18 “Direction Registers”: Peripheral output name is added and deleted

21 Fig. 14: Revised

23 Table 9: Revised

25 “External Interrupt Pin Selection” is deleted

26 Fig. 17:Revised

29 Port name is revised

34 Fig. 26: Revised

38 “Timer Y” is revised

44 Fig. 36: Revised

49 Fig. 41: Revised

57 Fig. 53 and 54 are revised

58 Fig. 56: Revised

63 Fig. 63: Revised

64 Fig. 63: Revised

65 Table 14: Revised

66 Fig. 65: Revised

74 Fig. 73: Revised

85 Fig. 80: Revised

86 Fig. 81: Revised

90 Notes On ROM Code Protect is revised

95 Table 22: Revised

99 Table 27: Revised

102 Table 30: Revised

109 NOTE of Table 38: Revised

110 Table 40: Revised

129 Notes On ROM Code Protect is revised

Rev. Date Description

Page Summary

Notes:

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes

warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property

rights or any other rights of Renesas or any third party with respect to the information in this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,

but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass

destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws

and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this

document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,

please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be

disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a

result of errors or omissions in the information included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability

of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular

application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications

or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality

and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or

undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall

have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing

applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,

movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages

arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain

rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage

caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software

alone is very difficult, please evaluate the safety of the final products or system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as

swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.

Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have

any other inquiries.

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.

Renesas Technology America, Inc.

450 Holger Way, San Jose, CA 95134-1368, U.S.A

Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501

Renesas Technology Europe Limited

Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.

Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900

Renesas Technology (Shanghai) Co., Ltd.

Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120

Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898

Renesas Technology Hong Kong Ltd.

7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong

Tel: <852> 2265-6688, Fax: <852> 2377-3473

Renesas Technology Taiwan Co., Ltd.

10th Floor, No.99, Fushing North Road, Taipei, Taiwan

Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399

Renesas Technology Singapore Pte. Ltd.

1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632

Tel: <65> 6213-0200, Fax: <65> 6278-8001

Renesas Technology Korea Co., Ltd.

Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea

Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145

Renesas Technology Malaysia Sdn. Bhd

Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia

Tel: <603> 7955-9390, Fax: <603> 7955-9510

RENESAS SALES OFFICES

Colophon .7.2