SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DWide Operating Voltage Range of 2 V to 6 V
DHigh-Current Inverting Outputs Drive Up To
10 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 14 ns
D±4-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
D8-Bit Parallel-Out Storage Register
Performs Serial-to-Parallel Conversion With
Storage
DAsynchronous Parallel Clear
DActive-High Decoder
DEnable Input Simplifies Expansion
DExpandable for n-Bit Applications
DFour Distinct Functional Modes
description/ordering information
These 8-bit addressable latches are designed for
general-purpose storage applications in digital
systems. Specific uses include working registers,
serial-holding registers, and active-high decoders
or demultiplexers. They are multifunctional
devices capable of storing single-line data in eight
addressable latches and being a 1-of-8 decoder
or demultiplexer with active-high outputs.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 25 SN74HC259N SN74HC259N
Tube of 40 SN74HC259D
SOIC − D Reel of 2500 SN74HC259DR HC259
−40°C to 85°C
SOIC − D
Reel of 250 SN74HC259DT
HC259
−40 C to 85 C
SOP − NS Reel of 2000 SN74HC259NSR HC259
TSSOP − PW
Reel of 2000 SN74HC259PWR
HC259
TSSOP − PW Reel of 250 SN74HC259PWT HC259
CDIP − J Tube of 25 SNJ54HC259J SNJ54HC259J
−55°C to 125°CCFP − W Tube of 150 SNJ54HC259W SNJ54HC259W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HC259FK SNJ54HC259FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54HC259 ...J OR W PACKAGE
SN74HC259 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
G
D
NC
Q7
Q6
S2
Q0
NC
Q1
Q2
SN54HC259 . . . FK PACKAGE
(TOP VIEW)
S1
S0
NC
Q4
Q5 CLR
Q3
GND
NC VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S0
S1
S2
Q0
Q1
Q2
Q3
GND
VCC
CLR
G
D
Q7
Q6
Q5
Q4
NC − No internal connection
Copyright 2003, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
%(#"! "%' /011 '' %$$! $ $!$(
#'$!! *$,!$ $() '' *$ %(#"! %(#"
%"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs. In the
addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch
follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all
latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latches, G should be held high (inactive) while the address lines
are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the
D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data
inputs.
Function Tables
FUNCTION
INPUTS OUTPUT OF
ADDRESSED
EACH
OTHER
FUNCTION
CLR G
ADDRESSED
LATCH
OTHER
OUTPUT
FUNCTION
H L D QiO Addressable latch
HHQ
iO QiO Memory
LLD L8-line demultiplexer
L H L L Clear
LATCH SELECTION
SELECT INPUTS
LATCH
S2 S1 S0
LATCH
ADDRESSED
L L L 0
LLH 1
LHL 2
LHH 3
HLL 4
HLH 5
HHL 6
H H H 7
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram
D
C
R
4
1Q0
S0
D
C
R
5Q1
D
C
R
6
2Q2
S1
D
C
R
7Q3
D
C
R
10
3
Q5
S2 D
C
R
9Q4
D
C
R
11 Q6
14
G
D
C
R
12 Q7
13
D
15
CLR
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
Q
Q
Q
Q
Q
Q
Q
Q
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram, each internal latch (positive logic)
C
R
TG
C
C
C
C
TG
C
C
DQ
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC259 SN74HC259
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage VCC = 4.5 V 3.15 3.15 V
VIH
High-level input voltage
VCC = 6 V 4.2 4.2
V
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VIL
Low-level input voltage
VCC = 6 V 1.8 1.8
V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆vInput transition rise/fall time VCC = 4.5 V 500 500 ns
∆t/∆v
Input transition rise/fall time
VCC = 6 V 400 400
ns
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC259 SN74HC259
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
I
OH
= −20 µA4.5 V 4.4 4.499 4.4 4.4
V
OH
V
I
= V
IH
or V
IL
IOH = −20 µA
6 V 5.9 5.999 5.9 5.9 V
VOH
VI = VIH or VIL
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
V
IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
I
OL
= 20 µA4.5 V 0.001 0.1 0.1 0.1
V
OL
V
I
= V
IH
or V
IL
IOL = 20 µA
6 V 0.001 0.1 0.1 0.1 V
VOL
VI = VIH or VIL
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
V
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V to 6 V 3 10 10 10 pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC259 SN74HC259
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 80 120 100
CLR low 4.5 V 16 24 20
tw
Pulse duration
CLR low
6 V 14 20 17
ns
twPulse duration 2 V 80 120 100 ns
G low 4.5 V 16 24 20
G low
6 V 14 20 17
2 V 75 115 95
t
su
Setup time, data or address before G↑4.5 V 15 23 19 ns
tsu
Setup time, data or address before G↑
6 V 13 20 16
ns
2 V 555
t
h
Hold time, data or address after G↑4.5 V 555ns
th
Hold time, data or address after G
6 V 555
ns
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HC259 SN74HC259
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 60 150 225 190
t
PHL
CLR Any Q 4.5 V 18 30 45 38 ns
tPHL
CLR
Any Q
6 V 14 26 38 32
ns
2 V 56 130 195 165
Data Any Q 4.5 V 17 26 39 33
Data
Any Q
6 V 13 22 33 28
2 V 74 200 300 250
t
pd
Address Any Q 4.5 V 21 40 60 50 ns
tpd
Address
Any Q
6 V 17 34 51 43
ns
2 V 66 170 255 215
GAny Q 4.5 V 20 34 51 43
G
Any Q
6 V 16 29 43 37
2 V 28 75 110 95
t
t
Any 4.5 V 8 15 22 19 ns
tt
Any
6 V 6 13 19 16
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per latch No load 33 pF
SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50%
V
CC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VC
C
VO
H
VO
L
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VO
H
VO
L
tr
tf
tPHL tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
85519012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85519012A
SNJ54HC
259FK
8551901EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8551901EA
SNJ54HC259J
8551901FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 8551901FA
SNJ54HC259W
JM38510/65402BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65402BEA
M38510/65402BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65402BEA
SN54HC259J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC259J
SN74HC259D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259DTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC259N
SN74HC259NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC259N
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74HC259NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWLE OBSOLETE TSSOP PW 16 TBD Call TI Call TI -40 to 85
SN74HC259PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWT ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SN74HC259PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC259
SNJ54HC259FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 85519012A
SNJ54HC
259FK
SNJ54HC259J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8551901EA
SNJ54HC259J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC259, SN74HC259 :
•Catalog: SN74HC259
•Military: SN54HC259
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC259DR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC259NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC259PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC259PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Oct-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC259DR SOIC D 16 2500 364.0 364.0 27.0
SN74HC259DRG4 SOIC D 16 2500 333.2 345.9 28.6
SN74HC259NSR SO NS 16 2000 367.0 367.0 38.0
SN74HC259PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74HC259PWT TSSOP PW 16 250 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Oct-2013
Pack Materials-Page 2
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