ANALOG DEVICES Octal Sample-and-Hold with Multiplexed Input SMP-18 FEATURES High Speed Version of SMP-08 Internal Hold Capacitors Low Droop Rate TTL/CMOS Compatible Logic Inputs Single or Dual Supply Operation Break-Before-Make Channel Addressing Compatible With CD4051 Pinout Low Cost APPLICATIONS Multiple Path Timing Deskew for A.T.E. Memory Programmers Mass Flow/Process Control Systems Multichannel! Data Acquisition Systems Robotics and Control Systems Medical and Analytical Instrumentation Event Analysis Stage Lighting Control GENERAL DESCRIPTION The SMP-18 is a monolithic octal sample-and-hold; it has eight internal buffer amplifiers, input multiplexer, and internal hold capacitors. It is manufactured in an advanced oxide isolated CMOS technology to obtain high accuracy, low droop rate, and fast acquisition time. The SMP-18 has a typical linearity error of only 0.01% and can accurately acquire a 10-bit input signal to +1/2 LSB in less than 2.5 microseconds. The SMP-18s output swing includes the negative supply in both single and dual sup- ply operation. The SMP-18 was specifically designed for systems that use a calibration cycle to adjust a multiple of system parameters. The low cost and high level of integration make the SMP-18 ideal for calibration requirements that have previously required an ASIC, or high cost multiple D/A converters. The SMP-18 is also ideally suited for a wide variety of sample- and-hold applications including amplifier offset or VCA gain adjustments. One or more SMP-18s can be used with single or multiple DACs to provide multiple set points within a system. REV.A FUNCTIONAL BLOCK DIAGRAM (LSB) (MSB) A B c INPUT INH 3 (11) (40 3 $ 8) DGND 1 OF 8 DECODER dG 16)Vop {sw}e 13) CH y OUT {31 wh 14) CH,OUT few} 15) CH 20UT {sw} 12)CH, OUT {sw} 1)CH, OUT lawl {sw} 5) CH, OUT {sw} 2) CH OUT {sw} 4) CH, OUT Hococars L111 tit tL (INTERNAL) 7) ss SMP-18 The SMP-18 offers significant cost and size reduction over dis- crete designs. It is available in a 16-pin hermetic or plastic DIP or surface mount SOIC package. The SMP-18 is a higher speed direct replacement for the SMP-08. SAMPLE/TRACK-HOLD AMPLIFIERS 4-119SMP-18 SPECIFICATIONS (@ Voy = +5 V, Vog = 5 V, DGND = 0 V, R, = No Load, T, = 40C to +85C for ELECTRICAL CHARACTERIST. Ics SMP-18F, unless otherwise noted) Parameter Symbol Conditions Min | Typ Max Units Linearity Error -3VeEVy =73V 0.01 % Buffer Offset Voltage Vos Ta = +25C, Vin = OV 2.5 10 mV -40C = Ty = +85C, Vin = 0V 3.5 20 mV Hold Step Vus Vin =0V 4 6 mV Droop Rate AVen/At Ta = +25C, Vin = OV 2 40 mV/s Output Source Current Isource Vin = OV! 1.2 mA Output Sink Current Isink Vin = 0V! 0.5 mA Output Voltage Range R, = 20k 3.0 +3.0 Vv LOGIC CHARACTERISTICS Logic Input High Voltage | Vinu 2.4 v Logic Input Low Voltage Vint 0.8 v Logic Input Current Iw Vin =24V 05 9 1 pA DYNAMIC PERFORMANCE Acquisition Time Tag Ta = +25C, -3 V to +3 V to 0.1% 350 | pS Hold Mode Settling Time ty To +1 mV of Final Value 1 pS Channel Select Time tor 90 ns Channel Deselect Time tocs 45 ns Inhibit Recovery Time tr 90 ns Slew Rate SR 6 Vins Capacitive Load Stability | <30% Overshoot 500 pF Analog Crosstalk | | 3 Vito +3 V Step -72 [_ dB SUPPLY CHARACTERISTICS i Power Supply Rejection Ratio PSRR | Ves = +5 Vito +6V 60 75 dB Supply Current Ipp Ta = +25C 5.5 7.5 mA -40C = T, = +85C 75 | 95 mA NOTES Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels. ?All input control signals are specified with t, = t, = 5 ns 110% to 90% of +5 Vand timed from a voltage level of 1.6 V. Specifications subject to change without nouce. (@ Von = +12 V, Vos = OV, DGND = OV, R, = No Load, T, = ~40C to +85C for ELECTRICAL CHARACTERISTICS SMP-18F, unless otherwise noted) Parameter Symbol | Conditions Min Typ Max | Units Linearity Error 60 mV < Vix < 10V 0.01 % Buffer Offset Voltage Vos Ty = +28C, Vin = 6V 2.5 10 mV ; ~40C < Ty = +85C, Vy = 6V 3.5 . 20 mV Hold Step Vis Vin = 6V 4 | 6 mV Droop Rate bo AVE y/At Ty = +25C, Vin = 6V 2 | 40 mV/s Output Source Current i loource Vin = 6V! 1.2 mA Output Sink Current | Law Vin = 6V! 0.5 | mA Output Voltage Range R, = 20k 0.06 | 10.0 Vv i R, = 10k 0.06 9.5 LOGIC CHARACTERISTICS | Logic Input High Voltage Vinn | 24 v Logic Input Low Voltage Vin. 0.8 v Logic Input Current Iw Via = 24V 05 | 1 pA DYNAMIC PERFORMANCE? ; Acquisition Time | tag T, = +25C, 0 to 10 V to 0.1% 2.5 ps Hold Mode Settling Time | tay To +1 mV of Final Value 1 BS Channel Select Time tou | 90 ns Channel Deselect Time toes 45 ns Inhibit Recovery Time ur 90 ns Slew Rate* SR 7 Vins Capacitive Load Stability <30% Overshoot 500 pF Analog Crosstalk L 0 to 10 V Step -72 dB 4-120 SAMPLE/TRACK-HOLD AMPLIFIERS REV.ASMP-18 Parameter Symbol Conditions Min Typ Max Units SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8 V = Vpp = 13.2 V 60 75 dB Supply Current Ipp Ty, = +25C 6.0 8.0 mA -40C = T, = +85C 8.0 10.0 mA NOTES Outputs are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load levels. ?All input control signals are specified with t, = t; = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. ?Slew rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 2 : VoptoDGND ..... 0.0.0 e cece cece ees -o3v,17v__ Package Type 8a Src Units Vpp tO Vsg wt eee -0.3.V,17V 16-Pin Hermetic DIP (Q) 94 12 CW Viocic 10 DGND 10... eee -0.3 V, Vpp 16-Pin Plastic DIP (P) 76 33 CiWw Vin tODGND 0200.00 c ccc ccs Ves: Vpp _ 1 6-Pin_ SOIC (S) 92 27 CN Vout to DGND .. 00... ee eee Vss> Vpp NOTES Analog Output Current... 2.0... 0. ee ~=20 mA 1. Absolute maximum ratings apply to both DICE and packaged parts, un- (Not short-circuit protected) Operating Temperature Range FQ, FP, FS 2.0... 2... eee eee 40C to +85C Junction Temperature... 0.0.00... 0200s +150C Storage Temperature ................ -65C to +150C Lead Temperature (Soldering, 60 sec) ........... + 300C CAUTION less otherwise noted. 2. 8,4 is specified for worst case mounting conditions, i.e., 6; is specified for device in socket for cerdip and plastic DIP packages; 8), is specified for device soldered to printed circuit board for SOIC package. 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. Digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam or packaging at all times until ready to use. Use proper antistatic handling procedures. WARNING! ee ESO SENSITIVE DEVICE 3. Remove power before inserting or removing units from their sockets. PIN CONNECTIONS cH,out [7] 2 7 116] Voo cH,out [2 15] CH2OUT INPUT [a] [14] CH, OUT CH; OUT 3 SMP-18 [13] cHoouT CH, OUT TOP VIEW 12] CH, OUT 5 5 (Not to Scale) 12] 30U INH [47] A CONTROL Vsg [7 [10] B CONTROL penp [a] 9 | C CONTROL REV.A ORDERING GUIDE* Package: 16-Pin DIP/SOIC Operating Cerdip Plastic Temperature 16-Pin 16-Pin | Range TBAt MIL SMP-18FQ | SMP-18FP | XIND SMP-18FS XIND NOTES *Burn-in is available on industrial temperature range parts in cerdip and plastic DIP packages. tConsult factory for 883 data sheet. SAMPLE/TRACK-HOLD AMPLIFIERS 4-121SMP-18 DIE SIZE 0.080 x 0.120 INCH, 9,600 $q. mils (2.032 x 3.048 mm, 6.193 sq. mm) DICE CHARACTERISTICS 1. CH, OUT . CHg OUT , INPUT . CH7 OUT . CH, OUT (NH Vs DGND 7 NO mM & wow HN 14, 15. 16. . CONTROL . B CONTROL . ACONTROL . CH OUT . CHy OUT CH, OUT CH, OUT Yoo (@ Voy = +12 V, Veg = DEND = OV, R, = No Load, T, = +25C for SMP-18GBC, unless otherwise WAFER TEST LIMITS specified) Parameter Symbol Conditions Limits Units Buffer Offset Voltage Vos Vin = +6V 20 mV max Droop Rate AVeq/At Vin = +6V 40 mV/s max Output Source Current TsourcE Vin = +6V 1.2 mA min Output Sink Current Ign Vin = +6V 0.5 mA min Output Voltage Range R, = 20k 0.06/10.0 V max/min R, = 10k 0.06/9.5 V max/min LOGIC CHARACTERISTICS Logic Input High Voltage Vinu 2.4 V min Logic Input Low Voltage Vint 0.8 V max Logic Input Current lin Vin = 2.4V 1 A max SUPPLY CHARACTERISTICS Power Supply Rejection Ratio PSRR 10.8 V = Von = 13.2 60 dB min Supply Current Ipp 8.0 mA max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield Joss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 4-122 SAMPLE/TRACK-HOLD AMPLIFIERS REV. ATypical Performance Characteristics SMP-18 100 5 Vop = +12V / Ty = +88C Vgg = 0V / : Vop= +12V 2 Vin = +6V 2 2 Vgs = OV = 10 IN $ 2 = = > NO E Ryi=10kQ V E a t 14 i E w & 1 E Ty, = +25C < a a 4 Vop= +12V | a 8 8 Vsg = 0V 8 NO LOAD Bos 5 Le & 3 0.01 6 40-200 420 40 4660 8 (100 o 123 45 6 7 8 9 0123 45 6 6 8 9 10 TEMPERATURE - C INPUT VOLTAGE - Voits INPUT VOLTAGE - Volts Droop Rate vs. Temperature Droop Rate vs. Input Voltage Droop Rate vs. input Voltage Tp = +25C Vpp= +12V Vpp= +12V 18 Ty=+25C Vgs = 0V 1 Vsgg = 0V 2 NO LOAD z & | NOLOAD 1 dos > a Ww yw E -2 & 0 a o a 9 05 = 6-3 2 a = 4 a ~4 15 Ss +2 01 23 4 5 67 8 9 55-35 15 5 25 45 65 85 105 125 10 1 1201314415 16 1718 INPUT VOLTAGE - Volts TEMPERATURE - C Vpp Volts Hold Step vs. input Voltage Hold Step vs. Temperature Slew Rate vs. Voo 4 Ty= +25C Vop = +12V 2 > op > E Vss = 0V E z uw t 10 Gg 3 uw < z x a a a 3 > $ g 4 ti Gi rs Ry = 20k2 o +6 o . w Ris Ry = 10kQ So , -10 012 3 45 67 86 9 0123 45 6728989 0 0123 45 67 8 9 0 INPUT VOLTAGE - Volts INPUT VOLTAGE - Volts INPUT VOLTAGE - Voits Offset Voltage vs. Input Voltage Offset Voltage vs. input Voltage Offset Voltage vs. Input Voltage REV.A SAMPLE/TRACK-HOLD AMPLIFIERS 4-123SMP-18Typical Performance Characteristics 0 14 Vpp = +12 Vpp = +12V a Vgg = OV Veg = OV SS Vgg = OV NO LOAD - wn Vin = +5V RL= 10k2 = oS OFFSET VOLTAGE - mV SUPPLY CURRENT - mA a 7 -8 -55 -35-15 5 25 45 65 85 105 125 4 6 TEMPERATURE -C Offset Voltage vs. Temperature 90 Tp = +25C Vop= +6V J 4s Vg = -6V . 0 NOLOAD Jo z o. Will 3 . PHASE b Zz <q-2 - 2 a <q 3 -135 5 a 4 -180 +5 -225 100 1k 10k 100k 1M 10M FREQUENCY - Hz Gain, Phase Shift vs. Frequency 15 Ta = +25C & 2 Vpp = +6V ( Ves = ~-6V 5 NO LOAD - 5 9 36 z wi 6 a 6 F 5 3 a FREQUENCY - Hz Maximum Output Voltage vs. Frequency 4-124 SAMPLE/TRACK-HOLD AMPLIFIERS Vy = +6 Tq = 425C NO LOAD REJECTION RATIO - dB G 100 1k 10k 100k 1M FREQUENCY - Hz Supply Current vs. Vop Sample Made Power Supply Rejection 35 Ty = +25C a 30 Vpp = +12V t Vgg = OV 3 25 T NO LOAD w 20 ty a 215 KE 2 & 10 3 5 0 10 100s tk 10k = 100k = 1M FREQUENCY - Hz Output Impedance vs. Frequency 60 80 a oa i 2 Ta = 425C <9 Vpp= +12V z Vss = OV Q NO LOAD - Oo 10 w HOLD CAPS REFERENCED TO Veg -PSRR 10 100 tk 10k 100k 1M FREQUENCY - Hz Hold Mode Power Supply Rejection REV.ASMP-18 R3 R2 +15V Burn-in Circuit APPLICATIONS INFORMATION The SMP-18, a multiplexed octal S/H, minimizes board space in systems requiring cycled calibration or an array of control volt- ages. When used in conjunction with a low cost 10-bit D/A, the SMP-18 can easily be integrated into microprocessor based sys- tems. Since the SMP-18 features break-before-make switching and an internal decoder, no external logic is required. The SMP-18 has an internally regulated TTL supply so that TTL/ CMOS compatibility is maintained over the full supply range. See Figure 1 for channel decode address information. POWER SUPPLIES The SMP-18 is capable of operating with either single or dual supplies, over a voltage range of 7 to 15 volts. Based on the sup- ply voltages chosen, Vpp and Vgg establish the output voltage range, which is: (Ves + 0.06 V) < Vour = Vpp - 2V) Note that several specifications, including acquisition time, off- set and output voltage, compliance will degrade for supply volt- ages of less than 7 V. If split supplies are used, the negative supply should be by- passed with a 0.1] F capacitor in parallel with a 10 uF to ground. The internal hold capacitors are connected to this sup- ply pin and any noise will appear at the outputs. In single supply applications, it is extremely important that the Vss (negative supply) pin is connected to a clean ground. The hold capacitors are internally tied to the Vgg (negative) rail. Any ground noise or disturbance will directly couple to the output of the sample-and-hold, degrading the signal-to-noise perfor- mance. The analog and digital ground traces on the circuit board should be physically separated to reduce digital switching noise from entering the analog circuitry. REV.A POWER SUPPLY SEQUENCING Vpp Should be applied to the SMP-18 before the logic input signals. The SMP-18 has been designed to be immune to latch- up, but standard precautions should still be taken. OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15) The buffer offset specification is 10 mV; this is less than 1/2 LSB of an 8-bit DAC with 10 V full scale. The hold step (mag- nitude of step caused in the output voltage when switching from sample-to-hold mode, also referred to as the pedestal error or sample-to-hold offset) is about 4 mV with little variation over the full output voltage range. The droop rate of a held channel is 2 mV/s typical and 40 mV/s maximum. The buffers are designed to drive loads connected to ground. The outputs can source more than 20 mA, over the full voltage range, but have limited current sinking capability near Vsg. In split supply operation, symmetrical output swings can be ob- tained by restricting the output range to 2 V from either supply. On-chip SMP-18 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capaci- tive loads up to 500 pF. However, since the SMP-18s buffer outputs are not short circuit protected, care should be taken to avoid shorting any output to the supplies or ground. SIGNAL INPUT (Pin 3) The signal input should be driven from a low impedance voltage source such as the output of an op amp. The op amp should have a high slew rate and fast settling time if the SMP-18's ac- quisition time characteristics are to be maintained. As with all CMOS devices, all input voltages should be kept within range of the supply rails (Vss = Vin, = Vpp) to avoid the possibility of latch-up. If single supply operation is desired, op amps such as the OP-21, OP-80, or OP-90 that have input and output voltage compliances including ground, can be used to drive the inputs. Split supplies, such as +7.5 V, can be used with the SMP-18. APPLICATION TIPS All unused digital inputs should be connected to logic LOW. For analog inputs that may become temporarily disconnected, a resistor to Vyp, Vss or analog ground should be used with a value ranging from 200 kO to 1 MQ. Do not apply signals to the SMP-18 with power off unless the input current is limited to less than 10 mA. SAMPLE/TRACK-HOLD AMPLIFIERS 4-125SMP-18 TYPICAL APPLICATIONS An 8-Channel Multiplexed D/A Converter Figure | illustrates a typical multiplexing function of the SMP- 18. It is used to sample-and-hold eight different output voltages corresponding to eight different digital codes from a D/A con- verter. The SMP-18s droop rate of 40 mV/s requires a refresh OIGITAL INPUTS wr ADDRESS AODRESS DECODE once every 250 ms before the voltage drifts beyond 1/2 LSB ac- SMP-18 oC 13) CHy 4) CH, 2) cH, CHANNEL DECODING - PINS PIN1O PIN11 PING c B A INH CHOPIN 2) CH 0 0 0 o 613 0 0 1 0 1 14 0 1 0 o 2 15 0 1 1 0 3 (12 1 0 0 0 4 1 1 0 1 0 5 5 1 1 o 0 6 2 1 1 1 Qo 7 4 x x x 1 NONE - Figure 1. 8-Channel Multiplexed D/A Converter 4-126 SAMPLE/TRACK-HOLD AMPLIFIERS curacy (1 LSB of an 8-bit DAC is equivalent to 19.5 mV, out of a full-scale voltage of 5 V). For a 10-bit DAC, the refresh rate must be less than 60 ms, and for a 12-bit system, 15 ms. This implementation is very cost effective compared to using multiple DACs as the number of output channels increases. REV. A