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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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tm
74VHC161 4-Bit Binary Counter with Asynchronous Clear
May 2007
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4
74VHC161
4-Bit Binary Counter with Asynchronous Clear
Features
■
High Speed: f
MAX
=
185MHz (Typ.) at T
A
=
25°C
■
Synchronous counting and loading
■
High-speed synchronous expansion
■
Low power dissipation: I
CC
=
4µA (Max.) at T
A
=
25°C
■
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
■
Power down protection provided on all inputs
■
Low noise: V
OLP
=
0.8V (Max.)
■
Pin and function compatible with 74HC161
General Description
The VHC161 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHC161 is a high-speed
synchronous modulo-16 binary counter. This device is
synchronously presettable for application in program-
mable dividers and have two types of Count Enable
inputs plus a Terminal Count output for versatility in
forming synchronous multistage counters. The VHC161
has an asynchronous Master Reset input that overrides
all other inputs and forces the outputs LOW. An input
protection circuit insures that 0V to 7V can be applied to
the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and
two supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
Connection Diagram Pin Description
Order Number
Package
Number Package Description
74VHC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names Description
CEP Count Enable Parallel Input
CET Count Enable Trickle Input
CP Clock Pulse Input
MR Asynchronous Master Reset Input
P
0
–P
3
Parallel Data Inputs
PE Parallel Enable Inputs
Q
0
–Q
3
Flip-Flop Outputs
TC Terminal Count Output
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 2
Logic Symbols
IEEE/IEC
Functional Description
The VHC161 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL).
The clock inputs of all flip-flops are driven in parallel
through a clock buffer. Thus all changes of the Q outputs
(except due to Master Reset of the VHC161) occur as a
result of, and synchronous with, the LOW-to-HIGH tran-
sition of the CP input signal. The circuits have four fun-
damental modes of operation, in order of precedence:
asynchronous reset, parallel load, count-up and hold.
Five control inputs—Master Reset, Parallel Enable (PE),
Count Enable Parallel (CEP) and Count Enable Trickle
(CET)—determine the mode of operation, as shown in
the Mode Select Table. A LOW signal on MR overrides
all other inputs and asynchronously forces all outputs
LOW. A LOW signal on PE overrides counting and
allows information on the Parallel Data (P
n
) inputs to be
loaded into the flip-flops on the next rising edge of CP.
With PE and MR HIGH, CEP and CET permit counting
when both are HIGH. Conversely, a LOW signal on
either CEP or CET inhibits counting.
The VHC161 uses D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the ris-
ing edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used
with the CEP and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup
time sets the upper limit on clock frequency. For faster
clock rates, the carry lookahead connections shown in
Figure 2 are recommended. In this scheme the ripple
delay through the intermediate stages commences with
the same clock that causes the first stage to tick over
from max to min to start its final cycle. Since this final
cycle requires 16 clocks to complete, there is plenty of
time for the ripple to progress through the intermediate
stages. The critical timing that limits the clock period is
the CP to TC delay of the first stage plus the CEP to CP
setup time of the last stage. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asyn-
chronous reset for flip-flops, registers or counters.
Logic Equations:
Count Enable
=
CEP • CET • PE
TC
=
Q
0
• Q
1
• Q
2
• Q
3
• CET
Figure 1. Multistage Counter with Ripple Carry
Figure 2. Multistage Counter with Lookahead Carry
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 3
Mode Select Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
State Diagram
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
MR PE CET CEP
Action on the Rising
Clock Edge ( )
LXXXReset (Clear)
HLXXLoad (P
n
→
Q
n
)
HHHHCount (Increment)
HHLXNo Change (Hold)
HHXLNo Change (Hold)
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5V to +7.0V
V
IN
DC Input Voltage –0.5V to +7.0V
V
OUT
DC Output Voltage –0.5V to V
CC
+ 0.5V
I
IK
Input Diode Current –20mA
I
OK
Output Diode Current ±20mA
I
OUT
DC Output Current ±25mA
I
CC
DC V
CC
/ GND Current ±50mA
T
STG
Storage Temperature –65°C to +150°C
T
L
Lead Temperature (Soldering, 10 seconds) 260°C
Symbol Parameter Rating
V
CC
Supply Voltage 2.0V to +5.5V
V
IN
Input Voltage 0V to +5.5V
V
OUT
Output Voltage 0V to V
CC
T
OPR
Operating Temperature –40°C to +85°C
t
r
, t
f
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 5
DC Electrical Characteristics
Noise Characteristics
Note:
2. Parameter guaranteed by design.
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
T
A
=
–40°C to
+85°C
UnitsMin. Typ. Max. Min. Max.
V
IH
HIGH Level Input
Voltage
2.0 1.50 1.50 V
3.0–5.5 0.7 x V
CC
0.7 x V
CC
V
IL
LOW Level Input
Voltage
2.0 0.50 0.50 V
3.0–5.5 0.3 x V
CC
0.3 x V
CC
V
OH
HIGH Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OH
=
–50µA 1.9 2.0 1.9 V
3.0 2.9 3.0 2.9
4.5 4.4 4.5 4.4
3.0 I
OH
=
–4mA 2.58 2.48
4.5 I
OH
=
–8mA 3.94 3.80
V
OL
LOW Level
Output Voltage
2.0 V
IN
=
V
IH
or V
IL
I
OL
=
50µA 0.0 0.1 0.1 V
3.0 0.0 0.1 0.1
4.5 0.0 0.1 0.1
3.0 I
OL
=
4mA 0.36 0.44
4.5 I
OL
=
8mA 0.36 0.44
I
IN
Input Leakage
Current
0–5.5 V
IN
=
5.5V or GND ±0.1 ±1.0 µA
I
CC
Quiescent
Supply Current
5.5 V
IN
=
V
CC
or GND 4.0 40.0 µA
Symbol Parameter V
CC
(V) Conditions
T
A
=
25°C
UnitsTyp. Limits
VOLP(2) Quiet Output Maximum
Dynamic VOL
5.0 CL = 50pF 0.4 0.8 V
VOLV(2) Quiet Output Minimum
Dynamic VOL
5.0 CL = 50pF –0.4 –0.8 V
VIHD(2) Minimum HIGH Level
Dynamic Input Voltage
5.0 CL = 50pF 3.5 V
VILD(2) Maximum LOW Level
Dynamic Input Voltage
5.0 CL = 50pF 1.5 V
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 6
AC Electrical Characteristics
Note:
3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
ICC (opr) = CPD • VCC • fIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ∆ICC which is obtained
from the following formula:
CQ0–CQ3 and CTC are the capacitances at Q0–Q3 and TC, respectively. FCP is the input frequency of the CP.
Symbol Parameter VCC (V) Conditions
TA = 25°C
TA = –40° to
+85°C
UnitsMin. Typ. Max. Min. Max.
tPLH, tPHL Propagation Delay
Time (CP–Qn)
3.3 ± 0.3 CL = 15pF 8.3 12.8 1.0 15.0 ns
CL = 50pF 10.8 16.3 1.0 18.5
5.0 ± 0.5 CL = 15pF 4.9 8.1 1.0 9.5 ns
CL = 50pF 6.4 10.1 1.0 11.5
tPLH, tPHL Propagation Delay
Time (CP–TC, Count)
3.3 ± 0.3 CL = 15pF 8.7 13.6 1.0 16.0 ns
CL = 50pF 11.2 17.1 1.0 19.5
5.0 ± 0.5 CL = 15pF 4.9 8.1 1.0 9.5 ns
CL = 50pF 6.4 10.1 1.0 11.5
tPLH, tPHL Propagation Delay
Time (CP–TC, Load)
3.3 ± 0.3 CL = 15pF 11.0 17.2 1.0 20.0 ns
CL = 50pF 13.5 20.7 1.0 23.5
5.0 ± 0.5 CL = 15pF 6.2 10.3 1.0 12.0 ns
CL = 50pF 7.7 12.3 1.0 14.0
tPLH, tPHL Propagation Delay
Time (CET–TC)
3.3 ± 0.3 CL = 15pF 7.5 12.3 1.0 14.5 ns
CL = 50pF 10.5 15.8 1.0 18.0
5.0 ± 0.5 CL = 15pF 4.9 8.1 1.0 9.5 ns
CL = 50pF 6.4 10.1 1.0 11.5
tPHL Propagation Delay
Time (MR –Qn)
3.3 ± 0.3 CL = 15pF 8.9 13.6 1.0 16.0 ns
CL = 50pF 11.2 17.1 1.0 19.5
5.0 ± 0.5 CL = 15pF 5.5 9.0 1.0 10.5 ns
CL = 50pF 7.0 11.0 1.0 12.5
tPHL Propagation Delay
Time (MR –TC)
3.3 ± 0.3 CL = 15pF 8.4 13.2 1.0 15.5 ns
CL = 50pF 10.9 16.7 1.0 19.0
5.0 ± 0.5 CL = 15pF 5.0 8.6 1.0 10.0 ns
CL = 50pF 6.5 10.6 1.0 12.0
fMAX Maximum Clock
Frequency
3.3 ± 0.3 CL = 15pF 80 130 70 MHz
CL = 50pF 55 85 50
5.0 ± 0.5 CL = 15pF 135 185 115 MHz
CL = 50pF 95 125 85
CIN Input Capacitance VCC = Open 4 10 10 pF
CPD Power Dissipation
Capacitance
(3) 23 pF
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 7
AC Operating Requirements
Note:
4. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V.
Symbol Parameter VCC (V)(4)
TA = 25°C
TA = –40°C to
+85°C
UnitsTyp. Guaranteed Minimum
tSMinimum Setup Time (Pn–CP) 3.3 5.5 6.5 ns
5.0 4.5 4.5
tSMinimum Setup Time (PE –CP) 3.3 8.0 9.5 ns
5.0 5.0 6.0
tSMinimum Setup Time (CEP or CET–CP) 3.3 7.5 9.0 ns
5.0 5.0 6.0
tHMinimum Hold Time (Pn–CP) 3.3 1.0 1.0 ns
5.0 1.0 1.0
tHMinimum Hold Time (PE –CP) 3.3 1.0 1.0 ns
5.0 1.0 1.0
tHMinimum Hold Time (CEP or CET–CP) 3.3 1.0 1.0 ns
5.0 1.0 1.0
tW(L), tW(H) Minimum Pulse Width CP (Count) 3.3 5.0 5.0 ns
5.0 5.0 5.0
tW(L) Minimum Pulse Width (MR) 3.3 5.0 5.0 ns
5.0 5.0 5.0
tREC Minimum Removal Time 3.3 2.5 2.5 ns
5.0 1.5 1.5
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 8
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 3. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 9
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 4. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 10
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 5. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
0.65
4.4±0.1
MTC16rev4
0.11
4.55
5.00
5.00±0.10
12°
7.354.45
1.45
5.90
74VHC161 4-Bit Binary Counter with Asynchronous Clear
©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VHC161 Rev. 1.4 11
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production
First Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I26
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designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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