74LCX374MTCX - National Semiconductor

TL/F/11996

74LCX374 Low-Voltage Octal D Flip-Flop with 5V Tolerant Inputs and Outputs

November 1996

74LCX374

Low-Voltage Octal D Flip-Flop

with 5V Tolerant Inputs and Outputs

General Description

The LCX374 consists of eight D-type flip-flops featuring sep-

arate D-type inputs for each flip-flop and TRI-STATEÉout-

puts for bus-oriented applications. A buffered clock (CP)

and Output Enable (OE) are common to all flip-flops. The

LCX374 is designed for low-voltage (3.3V) VCC applications

with capability of interfacing to a 5V signal environment.

The LCX374 is fabricated with an advanced CMOS technol-

ogy to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

Y5V tolerant inputs and outputs

Y8.5 ns tPD max, 10 mAI

CCQ max

YPower-down high impedance inputs and outputs

YSupports live insertion/withdrawal

Y2.0V–3.6V VCC supply operation

Yg24 mA output drive

YImplements patented Quiet SeriesTM noise/EMI

reduction circuitry

YFunctionally compatible with the 74 series 374

YLatch-up performance exceeds 500 mA

YESD performance:

Human Body Model l2000V

Machine Model l200V

Logic Symbols

TL/F/11996–1

IEEE/IEC

TL/F/11996– 2

Connection Diagram

Pin Assignment for

SOIC, SSOP and TSSOP

TL/F/11996– 3

Pin Names Description

D0–D7Data Inputs

CP Clock Pulse Input

OE Output Enable Input

O0–O7TRI-STATE Outputs

SOIC JEDEC SOIC EIAJ SSOP Type II TSSOP JEDEC

Order Number 74LCX374WM 74LCX374SJ 74LCX374MSA 74LCX374MTC

74LCX374WMX 74LCX374SJX 74LCX374MSAX 74LCX374MTCX

See NS Package Number M20B M20D MSA20 MTC20

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

Quiet SeriesTM is a trademark of National Semiconductor Corporation.

C1996 National Semiconductor Corporation RRD-B30M17/Printed in U. S. A. http://www.national.com

Functional Description

The LCX374 consists of eight edge-triggered flip-flops with

individual D-type inputs and TRI-STATE true outputs. The

buffered clock and buffered Output Enable are common to

all flip-flops. The eight flip-flops will store the state of their

individual D inputs that meet the setup and hold time re-

quirements on the LOW-to-HIGH Clock (CP) transition. With

the Output Enable (OE) LOW, the contents of the eight flip-

flops are available at the outputs. When the OE is HIGH, the

outputs go to the high impedance state. Operation of the

OE input does not affect the state of the flip-flops.

Truth Table

Inputs Outputs

DnCP OE On

HLLH

LLLL

XL L O

XXH Z

HIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

ZeHigh Impedance

LeLOW-to-HIGH Transition

O0ePrevious O0before HIGH to LOW of CP

Logic Diagram

TL/F/11996– 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Symbol Parameter Value Conditions Units

VCC Supply Voltage b0.5 to a7.0 V

VIDC Input Voltage b0.5 to a7.0 V

VODC Output Voltage b0.5 to a7.0 Output in TRI-STATE V

b0.5 to VCC a0.5 Output in High or Low State (Note 2) V

IIK DC Input Diode Current b50 VIkGND mA

IOK DC Output Diode Current b50 VOkGND mA

a50 VOlVCC

IODC Output Source/Sink Current g50 mA

ICC DC Supply Current per Supply Pin g100 mA

IGND DC Ground Current per Ground Pin g100 mA

TSTG Storage Temperature b65 to a150 §C

Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these

limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the Absolute Maximum Ratings. The ‘‘Recommended Operating

Conditions’’ table will define the conditions for actual device operation.

Note 2: IOAbsolute Maximum Rating must be observed.

Recommended Operating Conditions

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VIInput Voltage 0 5.5 V

VOOutput Voltage HIGH or LOW State 0 VCC V

TRI-STATE 0 5.5

IOH/IOL Output Current VCC e3.0V– 3.6V g24 mA

VCC e2.7V g12

TAFree-Air Operating Temperature b40 85 §C

Dt/DV Input Edge Rate, VIN e0.8V– 2.0V, VCC e3.0V 0 10 ns/V

DC Electrical Characteristics

Symbol Parameter Conditions VCC TAeb

40§Ctoa

85§CUnits

(V) Min Max

VIH HIGH Level Input Voltage 2.7–3.6 2.0 V

VIL LOW Level Input Voltage 2.7–3.6 0.8 V

VOH HIGH Level Output Voltage IOH eb

100 mA 2.7–3.6 VCC b0.2 V

IOH eb

12 mA 2.7 2.2 V

IOH eb

18 mA 3.0 2.4 V

IOH eb

24 mA 3.0 2.2 V

VOL LOW Level Output Voltage IOL e100 mA 2.7–3.6 0.2 V

IOL e12 mA 2.7 0.4 V

IOL e16 mA 3.0 0.4 V

IOL e24 mA 3.0 0.55 V

IIInput Leakage Current 0 sVIs5.5V 2.7–3.6 g5.0 mA

IOZ TRI-STATE Output Leakage 0 sVOs5.5V 2.7 – 3.6 g5.0 mA

VIeVIH or VIL

IOFF Power-Off Leakage Current VIor VOe5.5V 0 10 mA

ICC Quiescent Supply Current VIeVCC or GND 2.7–3.6 10 mA

3.6V sVI,V

Os5.5V 2.7–3.6 g10 mA

DICC Increase in ICC per Input VIH eVCC b0.6V 2.7–3.6 500 mA

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AC Electrical Characteristics

Symbol Parameter

TAeb

40§Ctoa

85§C

Units

VCC e3.3V g0.3V VCC e2.7V

Min Max Min Max

fMAX Maximum Clock Frequency 150 MHz

tPHL Propagation Delay 1.5 8.5 1.5 9.5 ns

tPLH CP to On1.5 8.5 1.5 9.5

tPZL Output Enable Time 1.5 8.5 1.5 9.5 ns

tPZH 1.5 8.5 1.5 9.5

tPLZ Output Disable Time 1.5 7.5 1.5 8.5 ns

tPHZ 1.5 7.5 1.5 8.5

tsSetup Time 2.5 2.5 ns

tHHold Time 1.5 1.5 ns

tWPulse Width 3.3 3.3 ns

tOSHL Output to Output Skew (Note 1) 1.0 ns

tOSLH 1.0

Note 1: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).

Dynamic Switching Characteristics

Symbol Parameter Conditions VCC

(V)

TAe25§CUnits

Typical

VOLP Quiet Output Dynamic Peak VOL CLe50 pF, VIH e3.3V, VIL e0V 3.3 0.8 V

VOLV Quiet Output Dynamic Valley VOL CLe50 pF, VIH e3.3V, VIL e0V 3.3 b0.8 V

Capacitance

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC eOpen, VIe0V or VCC 7pF

OUT Output Capacitance VCC e3.3V, VIe0V or VCC 8pF

PD Power Dissipation Capacitance VCC e3.3V, VIe0V or VCC,Fe10 MHz 25 pF

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74LCX374 Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

TL/F/11996– 5

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead (0.300×Wide) Molded Small Outline Package, JEDEC

Order Number 74LCX374WM or 74LCX374WMX

NS Package Number M20B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead (0.300×Wide) Molded Small Outline Package, EIAJ

Order Number 74LCX374SJ or 74LCX374SJX

NS Package Number M20D

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Physical Dimensions All dimensions are in millimeters (Continued)

20-Lead Molded Shrink Small Outline Package, EIAJ, Type II

Order Number 74LCX374MSA or 74LCX374MSAX

NS Package Number MSA20

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74LCX374 Low-Voltage Octal D Flip-Flop with 5V Tolerant Inputs and Outputs

Physical Dimensions All dimensions are in millimeters (Continued)

20-Lead Thin Shrink Small Outline Package, JEDEC

Order Number 74LCX374MTC or 74LCX374MTCX

NS Package Number MTC20

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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