TC514CPJ - TelCom Semiconductor

3-19

TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS

FEATURES

■Precision (up to 17 Bits) A/D Converter "Front End"

■3-Pin Control Interface to Microprocessor

■Flexible: User Can Trade-Off Conversion Speed

for Resolution

■Single Supply Operation (TC510/514)

■4 Input, Differential Analog MUX (TC514)

■Automatic Input Voltage Polarity Detection

■Low Power Dissipation ...........TC500/500A: 10mW

TC510/514: 18mW

■Wide Analog Input Range .......±4.2V (TC500A/510)

■Directly Accepts Bipolar and Differential Input

Signals

GENERAL DESCRIPTION

The TC500/500A/510/514 family are precision analog

front ends that implement dual slope A/D converters having

a maximum resolution of 17 bits plus sign. As a minimum,

each device contains the integrator, zero crossing compara-

tor and processor interface logic. The TC500 is the base

(16 bit max) device and requires both positive and negative

power supplies. The TC500A is identical to the TC500,

except it has improved linearity allowing it to operate to a

maximum resolution of 17 bits. The TC510 adds an on-

board negative power supply converter for single supply

operation. The TC514 adds both a negative power supply

converter and a 4 input differential analog multiplexer.

Each device has the same processor control interface

consisting of 3 wires: control inputs A and B and zero-

crossing comparator output (CMPTR). The processor ma-

nipulates A, B to sequence the TC5xx through four phases

of conversion: Auto Zero, Integrate, Deintegrate and Inte-

grator Zero. During the Auto Zero phase, offset voltages in

the TC5xx are corrected by a closed-loop feedback mecha-

nism. The input voltage is applied to the integrator during the

Integrate phase. This causes an integrator output dv/dt

directly proportional to the magnitude of the input voltage.

The higher the input voltage, the greater the magnitude of

the voltage stored on the integrator during this phase. At the

start of the Deintegrate phase, an external voltage reference

is applied to the integrator, and at the same time, the external

host processor starts its on-board timer.

The processor main-

FUNCTIONAL BLOCK DIAGRAM

LEVEL

SHIFT

CONTROL LOGIC

ANALOG

SWITCH

CONTROL

SIGNALS

ACOM

+VREF

+–BUF

CAZ

BUFFER

INTEGRATOR

SWR

–

SWIZ

CMPTR 1 CMPTR 2

CMPTR

OUTPUT

DGND

CONTROL LOGIC

SW1

TC500

TC500A

TC510

TC514

CREF

SWR

CREF

CAZ

RINT

CINT

SWRI +

SWRI

SWRI –

SWRI

SWZ

SWI

SWZ

OSC

–

PHASE

DECODING

LOGIC

POLARITY

DETECTION

DC-TO-DC

CONVERTER

(TC510 & TC514)

–

A B

0 0 ZERO INTEGRATOR OUTPUT

0 1 AUTO-ZERO

1 0 SIGNAL INTEGRATE

1 1 DEINTEGRATE

VREF

VOUT

COUT

1.0µF1.0µF

VSS

–

SWI

A0 A1

DIF.

MUX

(TC514)

CH1 +

CH2 +

CH3 +

CH4 +

CH1 –

CH2 –

CH3 –

CH4 –

CAP–CAP+

(TC500

TC500A)

CONVERTER STATE

TC500

TC500A

TC510

TC514

TC500/A/510/514-3 10/3/96

ORDERING INFORMATION

Part No. Package Temp. Range

TC500ACOE 16-Pin SOIC 0°C to +70°C

C500ACPE 16-Pin Plastic DIP (Narrow) 0°C to +70°C

TC500COE 16-Pin SOIC 0°C to +70°C

TC500CPE 16-Pin Plastic DIP (Narrow) 0°C to +70°C

TC510COG 24-Pin SOIC 0°C to +70°C

TC510CPF 24-Pin Plastic DIP (300 Mil.) 0°C to +70°C

TC514COI 28-Pin SOIC 0°C to +70°C

TC514CPJ 28-Pin Plastic DIP (300 Mil.) 0°C to +70°C

TC500EV Evaluation Kit for TC500/500A/510/514

EVALUATION

KIT

AVAILABLE

3-20 TELCOM SEMICONDUCTOR, INC.

* Static-sensitive device. Unused devices must be stored in conductive

material. Protect devices from static discharge and static fields. Stresses

above those listed under "Absolute Maximum Ratings" may cause perma-

nent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those

indicated in the operation sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

GENERAL DESCRIPTION (Cont.)

tains this state until a transition occurs on the CMPTR output,

at which time the processor halts its timer. The resulting

timer count is the converted analog data. Integrator Zero

(the final phase of conversion) removes any residue remain-

ing in the integrator in preparation for the next

conversion.

The TC500/500A/510/514 offer high resolution (up to 17

bits) superior 50Hz/60Hz noise rejection, low power opera-

tion, minimum I/O connections, low input bias currents and

lower cost compared to other converter technologies having

similar conversion speeds.

ABSOLUTE MAXIMUM RATINGS*

TC510/514 Positive Supply Voltage

(VDD to GND) .................................................. +10.5V

TC500/500A Supply Voltage

(VDD to VSS) ....................................................... +18V

TC500/500A Positive Supply Voltage

(VDD to GND) ..................................................... +12V

TC500/500A Negative Supply Voltage

(VSS to GND) ...................................................... – 8V

Analog Input Voltage (V+

IN or V_

IN) ....................VDD to VSS

Logic Input Voltage ..................VDD +0.3V to GND – 0.3V

Voltage on OSC ..... – 0.3V to (VDD +0.3V) for VDD < 5.5V

Ambient Operating Temperature Range ......0°C to +70°C

Storage Temperature Range ................– 65°C to +150°C

Lead Temperature (Soldering, 10 sec) .................+300°C

ELECTRICAL CHARACTERISTICS: TC510/514: VDD = +5V, TC500/500A: VS = ±5V unless otherwise

specified. CAZ = CREF = 0.47 µF

TA = +25°C TA = 0°C to +70°C

Symbol Parameter Test Conditions Min Typ Max Min Typ Max Unit

Analog

Resolution Note 1 60 — — — — — µV

ZSE Zero-Scale Error TC500/510/514 — — 0.005 — 0.005 0.012 % F.S.

with Auto Zero Phase TC500A — — 0.003 — 0.003 0.009

ENL End Point Linearity

TC500/510/514, Notes 1, 2,

— 0.005 0.015 — 0.015 0.060

% F.S.

TC500A

— — 0.010 — 0.010 0.045

% F.S.

NL Best Case Straight

TC500/510/514, Notes 1, 2,

— 0.003 0.008 — — —

% F.S.

Line Linearity

TC500A

— — 0.005 — — —

% F.S.

ZSTC Zero-Scale Over Operating — — — 1 2 µV/°C

Temperature Temperature Range

Coefficient

SYE Full-Scale Symmetry Note 3 — 0.01 — — 0.03 — % F.S.

Error (Roll-Over Error)

FSTC Full-Scale Temperature Over Operating — — — — 10 —

ppm/°C

Coefficient Temperature Range

External Reference

TC = 0ppm/°C

IIN Input Current VIN = 0V — 6 — — — — pA

VCMR Common-Mode VSS +1.5 — VDD – 1.5 VSS +1.5 — VDD – 1.5 V

Voltage Range

Integrator Output Swing VSS +0.9 — VDD – 0.9 VSS +0.9 — VSS +0.9 V

Analog Input Signal RangeACOM = GND = 0V VSS +1.5 — VDD – 1.5 VSS +1.5 — VSS +1.5 V

VREF Voltage Reference Range V_

REF V+

REF VSS +1 — VDD – 1 VSS +1 — VDD – 1 V

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

3-21

TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

ELECTRICAL CHARACTERISTICS: (Cont.)

TA = +25°C TA = 0°C to +70°C

Symbol Parameter Test Conditions Min Typ Max Min Typ Max Unit

Digital

VOH Comparator Logic 1, ISOURCE = 400µA4——4——V

Output High

VOL Comparator Logic 0, ISINK = 2.1mA — — 0.4 — — 0.4 V

Output Low

VIH Logic 1, Input High Voltage 3.5 — — 3.5 — — V

VIL Logic 0, Input Low Voltage — — 1 — — 1 V

ILLogic Input Current Logic 1 or 0 — — — — 0.3 — µA

tDComparator Delay — 2 — — 3 — µsec

Multiplexer (TC514 Only)

Maximum Input Voltage VDD = 5V – 2.5 — 2.5 – 2.5 — 2.5 V

RDSON Drain/Source ON Resistance VDD = 5V — 6 10 — — — kΩ

Power (TC510/514 Only)

ISSupply Current VDD = 5V, A = 1, B = 1 — 1.8 2.4 — — 3.5 mA

PDPower Dissipation VDD = 5V — 18 — — — — mW

VDD Positive Supply 4.5 — 5.5 4.5 — 5.5 V

Operating Voltage Range

ROUT Operating Source Resistance IOUT = 10mA — 60 85 — — 100 Ω

Oscillator Frequency (Note 3) — 100 — — — — kHz

IOUT Maximum Current Out VDD = 5V — — – 10 — — – 10 mA

Power (TC500/500A Only)

ISSupply Current VS = ±5V, A = B = 1 — 1 1.5 — — 2.5 mA

PDPower Dissipation VDD = 5V, VSS = – 5V — 10 — — — — mW

VDD Positive Supply 4.5 — 7.5 4.5 — 7.5 V

Operating Voltage Range

VSS Negative Supply – 4.5 — – 7.5 – 4.5 — – 7.5 V

Operating Voltage Range

NOTES: 1. Integrate time ≥ 66msec, auto-zero time ≥ 66msec, VINT (peak) ≈ 4V.

2. End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.

3. Roll-over error is related to CINT, CREF, CAZ characteristics.

3-22 TELCOM SEMICONDUCTOR, INC.

CAP

DGND

V A

CREF

CINT

CAZ

BUF

ACOM

N/C

TC510CPF

CREF

REF

VREF

–

VOUT

–VOUT

–

VOUT

–

CREF

CINT

CAZ

BUF

ACOM

N/C

CREF

REF

VREF

–

VDD

OSC

CMPTR OUT

VIN

–

VIN

N/C

CAP+

CAP

DGND

–

VDD

OSC

CMPTR OUT

VIN

–

VIN

N/C

CAP+

TC510COG

CAP

DGND

V A

CREF

CINT

CAZ

BUF

ACOM

CH4–

CH3–

CH2–

TC514CPJ

CREF

REF

VREF

–

VDD

OSC

CMPTR OUT

CAP+

CH1–

N/C

CH1+

CH2+

CH3+

CH4+

VOUT

CREF

CINT

CAZ

BUF

ACOM

CREF

REF

VREF

–

CAP

DGND

–

VDD

OSC

CMPTR OUT

CAP+

TC514COI

N/C

CH4–

CH3–

CH2–

CH1–

CH1+

CH2+

CH3+

CH4+

13BUF

CMPTR OUT

–

VSS

CINT

DIGITAL GND

–

VDD

ACOM ACOM

TC500/

TC500A

CPE

VIN

VREF

–

VREF

CREF

CAZ

TC500/

TC500A

COE

BUF

–

VSS

CINT

–

VREF

CREF

CAZ CMPTR OUT

DIGITAL GND

VDD

VIN

VREF

–

PIN CONFIGURATIONS

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

3-23

TELCOM SEMICONDUCTOR, INC.

PIN DESCRIPTION

Pin No Pin No Pin No

(TC500, 500A) (TC510) (TC514) Symbol Description

122C

INT Integrator output. Integrator capacitor connection.

2 Not Used Not Used VSS Negative power supply input (TC500/500A only).

333C

AZ Auto-zero input. The Auto-zero capacitor connection.

4 4 4 BUF Buffer output. The Integrator capacitor connection.

5 5 5 ACOM This pin is grounded in most applications. It is recommended that

ACOM and the input common pin (V–

IN or C–

HN ) be within the

analog common mode range (CMR).

666C

–

REF Input. Negative reference capacitor connection.

777C

REF Input. Positive reference capacitor connection.

888V

–

REF Input. External voltage reference (–) connection.

999V

REF Input. External voltage reference (+) connection.

10 15 Not Used V–

IN Negative analog input.

11 16 Not Used V+

IN Positive analog input.

12 18 22 A Input. Converter phase control MSB. (See input B.)

13 17 21 B Input. Converter phase control LSB. The states of A, B place the

TC5xx in one of four required phases. A conversion is complete

when all four phases have been executed:

00: Integrator Zero

Phase control input pins: AB = 01: Auto Zero

10: Integrate

11: Deintegrate

14 19 23 CMPTR OUT Zero crossing comparator output. CMPTR is HIGH during the

Integration phase when a positive input voltage is being integrated

and is LOW when a negative input voltage is being integrated. A

HIGH-to-LOW transition on CMPTR signals the processor that the

Deintegrate phase is completed. CMPTR is undefined during the

Auto-Zero phase. It should be monitored to time the Integrator Zero

phase (see text).

15 23 27 DGND Input. Digital ground.

16 21 25 VDD Input. Power supply positive connection.

22 26 CAP+Input. Negative power supply converter capacitor (+) connection.

24 28 CAP–Input. Negative power supply converter capacitor (–) connection.

11V

–

OUT Output. Negative power supply converter output and reservoir

capacitor connection. This output can be used to power other

devices in the circuit requiring a negative bias voltage.

20 24 OSC Oscillator control input. The negative power supply converter normally

runs at a frequency of 100kHz. The converter oscillator frequency can

be slowed down (to reduce quiescent current) by connecting an

external capacitor between this pin and VDD. (See Typical Character-

istics Curves).

18 CH1+Positive analog input pin. MUX channel 1.

13 CH1–Negative analog input pin. MUX channel 1.

17 CH2+Positive analog input pin. MUX channel 2.

12 CH2–Negative analog input pin. MUX channel 2.

16 CH3+Positive analog input pin. MUX channel 3.

11 CH3–Negative analog input pin. MUX channel 3.

15 CH4+Positive analog input pin. MUX channel 4.

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

3-24 TELCOM SEMICONDUCTOR, INC.

Figure 2. Basic Dual-Slope Converter

PHASE

CONTROL

COMPARATOR

INTEGRATOR

OUTPUT

INTEGRATOR

CINT

ANALOG

INPUT

(VIN)

SWITCH DRIVER

REF

VOLTAGE CONTROL

LOGIC

POLARITY

CONTROL

I/O

TIMER

COUNTER

ROM

RAM

MICROCOMPUTER

CMPTR OUT

VSUPPLY

TINT

TC510

VINT

VIN ' VFULL SCALE

VIN ' 1/2 VFULL SCALE

TDEINT

–

RINT VINT

–

PIN DESCRIPTION (Cont.)

Pin No Pin No Pin No

(TC500/A) (TC510) (TC514) Symbol Description

10 CH4–Negative analog input pin. MUX channel 4

20 A0 Multiplexer input channel select input LSB. (See A1).

19 A1 Multiplexer input channel select input MSB.

00 = Channel 1

Phase control input pins: A1, A0 = 01 = Channel 2

10 = Channel 3

11 = Channel 4

GENERAL THEORY OF OPERATION

Dual-Slope Conversion Principles (Figure 2)

Actual data conversion is accomplished in two phases:

input signal Integration and reference voltage Deintegration.

The integrator output is initialized to 0V prior to the start

of Integration. During Integration, analog switch S1 con-

nects VIN to the integrator input where it is maintained for a

fixed time period (tINT). The application of VIN causes the

integrator output to depart 0V at a rate determined by the

magnitude

VIN, and a direction determined by the

polarity

of VIN. The Deintegration phase is initiated immediately at

the expiration of tINT.

During Deintegration, S1 connects a reference voltage

(having a polarity opposite that of VIN) to the integrator input.

At the same time, an external precision timer is started. The

Deintegration phase is maintained until the comparator

output changes state, indicating the integrator has returned

to its starting point of 0V. When this occurs, the precision

timer is stopped. The Deintegration time period (tDEINT), as

measured by the precision timer, is directly proportional to

the magnitude of the applied input voltage.

A simple mathematical equation relates the Input

Signal, Reference Voltage and Integration time:

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

3-25

TELCOM SEMICONDUCTOR, INC.

∫

0.01 0.1 1.0

NORMAL MODE REJECTION (dB)

t = 0.1 sec

LINE FREQUENCY DEVIATION FROM 60 Hz (%)

NORMAL

MODE

REJECTION = 20 LOG

DEV = DEVIATION FROM 60 Hz

t = INTEGRATION PERIOD

SIN 60 t (1 ± )

DEV

100

DEV

100

60 t (1 ± )

Figure 3. Line Frequency Deviation

Figure 4.. Integrating Converter Normal Mode Rejection

0.1/T 1/T 10/T

INPUT FREQUENCY

NORMAL MODE REJECTION (dB)

T = MEASUREMENT

PERIOD

1 tINT VIN (t) dt = VREF tDEINT

RINT CINT 0 RINT CINT

where:

VREF = Reference Voltage

tINT = Signal Integration time (fixed)

tDEINT = Reference Voltage Integration time (variable)

For a constant VIN:

VIN = VREF tDEINT

tINT

The dual-slope converter accuracy is unrelated to the

integrating resistor and capacitor values as long as they are

stable during a measurement cycle.

An inherent benefit is noise immunity. Input noise spikes

are integrated (averaged to zero) during the integration

periods. Integrating ADCs are immune to the large conver-

sion errors that plague successive approximation convert-

ers in high-noise environments.

Integrating converters provide inherent noise rejection

with at least a 20dB/decade attenuation rate. Interference

signals with frequencies at integral multiples of the integra-

tion period are, theoretically, completely removed since the

average value of a sine wave of frequency (1/t) averaged

over a period (t) is zero.

Integrating converters often establish the integration

period to reject 50/60Hz line frequency interference signals.

The ability to reject such signals is shown by a normal mode

rejection plot (Figure 4). Normal mode rejection is limited in

practice to 50 to 65dB, since the line frequency can deviate

by a few tenths of a percent (Figure 3).

TC500/500A/510/514 CONVERTER OPERATION

The TC500/500A/510/514 incorporates an Auto zero

and Integrator phase in addition to the input signal Integrate

and reference Deintegrate phases. The addition of these

phases reduce system errors and calibration steps, and

shorten overrange recovery time. A typical measurement

cycle uses all four phases in the following order:

(1) Auto zero

(2) Input signal integration

(3) Reference deintegration

(4) Integrator output zero

The internal analog switch status for each of these

phases is summarized in Table 1. This table is referenced

to the

Functional Block Diagram

on the first page of this data

sheet.

Auto-Zero Phase (AZ)

During this phase, errors due to buffer, integrator and

comparator offset voltages are nulled out by charging CAZ

(auto-zero capacitor) with a compensating error voltage.

The external input signal is disconnected from the

internal circuitry by opening the two SWI switches. The

internal input points connect to analog common. The refer-

ence capacitor is charged to the reference voltage potential

through SWR. A feedback loop, closed around the integrator

and comparator, charges the CAZ capacitor with a voltage to

compensate for buffer amplifier, integrator and comparator

offset voltages.

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

3-26 TELCOM SEMICONDUCTOR, INC.

Analog Input Signal Integration Phase (INT)

The TC5xx integrates the differential voltage between

the (V+

IN) and (V–

IN) inputs. The differential voltage must be

within the device's common-mode range VCMR.

The input signal polarity is normally checked via soft-

ware at the end of this phase: CMPTR = 1 for positive

polarity; CMPTR = 0 for negative polarity.

Reference Voltage Deintegration Phase (DINT)

The previously charged reference capacitor is con-

nected with the proper polarity to ramp the integrator output

back to zero. An externally-provided, precision timer is used

to measure the duration of this phase. The resulting time

measurement is proportional to the magnitude of the applied

input voltage.

Integrator Output Zero Phase (IZ)

This phase guarantees the integrator output is at 0V

when the Auto Zero phase is entered and that only system

offset voltages are compensated. This phase is used at the

end of the reference voltage deintegration phase and MUST

be used for ALL TC5xx applications having resolutions of 12

bits or more. If this phase is not used, the value of the Auto-

Zero capacitor (CAZ) must be about 2 to 3 times the value of

the integration capacitor (CINT) to reduce the effects of

charge-sharing. The Integrator Output Zero phase should

be programmed to operate until the Output of the Compara-

tor returns "HIGH". The overall Timing System is shown in

Figure 8.

ANALOG SECTION

Differential Inputs (V+

IN, V–

IN)

The TC5xx operates with differential voltages within the

input amplifier common-mode range. The amplifier com-

mon-mode range extends from 1.5V below positive supply

to 1.5V above negative supply. Within this common-mode

voltage range, common-mode rejection is typically 80dB.

Full accuracy is maintained, however, when the inputs are

no less than 1.5V from either supply.

The integrator output also follows the common-mode

voltage. The integrator output must not be allowed to satu-

rate. A worst-case condition exists, for example, when a

large, positive common-mode voltage with a near full-scale

negative differential input voltage is applied. The negative

input signal drives the integrator positive when most of its

swing has been used up by the positive common-mode

voltage. For these critical applications, the integrator swing

can be reduced. The integrator output can swing within 0.9V

of either supply without loss of linearity.

Analog Common

Analog common is used as VIN return during system-

zero and reference deintegrate. If V–

IN is different from analog

common, a common-mode voltage exists in the system.

This signal is rejected by the excellent CMR of the converter.

In most applications, V–

IN will be set at a fixed known voltage

(i.e., power supply common). A common-mode voltage will

exist when V–

IN is not connected to analog common.

Differential Reference

(V+

REF, V–

REF)

The reference voltage can be anywhere within 1V of the

power supply voltage of the converter. Roll-over error is

caused by the reference capacitor losing or gaining charge

due to stray capacitance on its nodes. The difference in

reference for (+) or (–) input voltages will cause a roll-over

error. This error can be minimized by using a large reference

capacitor in comparison to the stray capacitance.

Phase Control Inputs (A, B)

The A, B unlatched logic inputs select the TC5xx oper-

ating phase. The A, B inputs are normally driven by a

microprocessor I/O port or external logic.

Table 1. Internal Analog Gate Status

Internal Analog Gate Status

Conversion Phase SWISW+

RI SW–

RI SWZSWRSW1SWIZ

Auto-Zero (A = 0, B = 1) Closed Closed Closed

Input Signal Integration Closed

(A = 1, B = 0)

Reference Voltage Closed* Closed

Deintegration (A =1, B= 1)

Integrator Output Zero Closed Closed Closed

(A = 0, B = 0)

*Assumes a positive polarity input signal. SW–

RI would be closed for a negative input signal.

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

3-27

TELCOM SEMICONDUCTOR, INC.

Figure 5. Comparator Output

INTEGRATOR

OUTPUT ZERO

CROSSING

COMPARATOR

OUTPUT

REFERENCE

DEINTEGRATE

SIGNAL

INTEGRATE

INTEGRATOR

OUTPUT ZERO

CROSSING

COMPARATOR

OUTPUT

REFERENCE

DEINTEGRATE

SIGNAL

INTEGRATE

B. Negative Input SignalA. Positive Input Signal

Comparator Output

By monitoring the comparator output during the fixed

signal integrate time, the input signal polarity can be deter-

mined by the microprocessor controlling the conversion.

The comparator output is HIGH for positive signals and LOW

for negative signals during the signal-integrate phase (see

timing diagram).

During the reference deintegrate phase, the comparator

output will make a HIGH-to-LOW transition as the integrator

output ramp crosses zero. The transition is used to signal the

processor that the conversion is complete.

The internal comparator delay is 2µsec, typically. Figure

5 shows the comparator output for large positive and nega-

tive signal inputs. For signal inputs at or near zero volts,

however, the integrator swing is very small. If common-

mode noise is present, the comparator can switch several

times during the beginning of the signal-integrate period. To

ensure that the polarity reading is correct, the comparator

output should be read and stored at the end of the signal

integrate phase.

The comparator output is undefined during the Auto-

Zero Phase and is used to time the Integrator Output Zero

phase. (See

Integrator Output Zero Phase of System Timing

section).

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

3-28 TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

APPLICATIONS

Component Value Selection

The procedure outlined below allows the user to arrive

at values for the following TC5xx design variables:

(1) Integration Phase Timing

(2) Integrator Timing Components (RINT, CINT)

(3) Auto Zero and Reference Capacitors

(4) Voltage Reference

Select Integration Time

Integration time must be picked as a multiple of the

period of the line frequency. For example, tINT times of

33msec, 66msec and 132msec maximize 60Hz line rejec-

tion.

DINT and IZ Phase Timing

The duration of the DINT phase is a function of the

amount of voltage stored on the integrator during TINT, and

the value of VREF. The DINT phase must be initiated imme-

diately following INT and terminated when an integrator

output zero-crossing is detected. In general, the maximum

number of counts chosen for DINT is twice that of INT (with

VREF chosen at VIN (max)/2).

Calculate Integrating Resistor (RINT)

The desired full-scale input voltage and amplifier output

current capability determine the value of RINT. The buffer

and integrator amplifiers each have a full-scale current of

20µA.

The value of RINT is therefore directly calculated as

follows: RINT(in MΩ) = VIN MAX

where: VIN MAX = Maximum input voltage (full count voltage)

RINT =Integrating Resistor (in MΩ)

For loop stability, RINT should be ≥ 50kΩ.

Select Reference (CREF) and Auto Zero (CAZ) Capacitors

CREF and CAZ must be low leakage capacitors (such as

polypropylene). The slower the conversion rate, the larger

the value CREF must be. Recommended capacitors for CREF

and CAZ are shown in Table 1. Larger values for CAZ and

CREF may also be used to limit roll-over errors.

Table 1. CREF and CAZ Selection

Conversions Typical Value of Suggested *

Per Second CREF, CAZ (µF) Part Number

>7 0.1 WIMA MK12 .1/63/20

2 to 7 0.22 WIMA MK12 .22/63/20

2 or less 0.47 WIMA MK12 .47/63/20

*WIMA Corp. listing on the last page of this data sheet.

Calculate Integrating Capacitor (CINT)

The integrating capacitor must be selected to maximize

integrator output voltage swing. The integrator output volt-

age swing is defined as the absolute value of VDD (or VSS)

less 0.9V (i.e., VDD – 0.9V or VSS +0.9V ). Using the 20µA

buffer maximum output current, the value of the integrating

capacitor is calculated using the following equation.

CINT = (in µF) =

where: tINT = Integration Period

VS = Applied Supply Voltage

It is critical that the integrating capacitor has a very low

dielectric absorption. Polypropylene capacitors are an ex-

ample of one such chemistry. Polyester and Polybicarbonate

capacitors may also be used in less critical applications.

Table 2 summarizes recommended capacitors for CINT.

Table 2. Recommend Capacitor for CINT

Value Suggested Part Number*

0.1 WIMA MK12 .1/63/20

0.22 WIMA MK12 .22/63/20

0.33 WIMA MK12 .33/63/20

0.47 WIMA MK12 .47/63/20

*WIMA Corp. listing on the last page of this data sheet.

Calculate VREF

The reference deintegration voltage is calculated

using:

VREF

(in Volts) = (VS – 0.9) (CINT) (RINT)

2(tINT)

(tINT) (20 x 10 –6)

(VS – 0.9)

3-29

TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

Figure 6. Noise

NTH

LowREF

NTH

Normal

VREF

NTH

High

30 µV

VREF

SLOPE (S) = NTH = Noise Threshold

VREF

INT

Figure 7. Overshoot

INTEGRATOR

OUTPUT

COMPARATOR

OUTPUT COMP

INTEGRATE

PHASE

DEINTEGRATE PHASE

INTEGRATOR

ZERO PHASE

ZERO

CROSSING

OVERSHOOT



Figure 8 shows the overall timing for a typical system in

which a TC5xx is interfaced to a microcontroller. The

microcontroller drives the A, B inputs with I/O lines and

monitors the comparator output, CMPTR, using an I/O line

or dedicated timer-capture control pin. It may be necessary

to monitor the state of the CMPTR output in addition to

having it control a timer directly for the Reference Deintegra-

tion phase. (This is further explained below.)

The timing diagram in Figure 8 is not to scale as the

timing in a real system depends on many system parameters

and component value selections. There are four critical

timing events (as shown in Figure 8): sampling the input

polarity; capturing the deintegration time; minimizing over-

shoot and properly executing the Integrator Output Zero

phase.

Auto-Zero Phase

The length of this phase is usually set to be equal to the

Input Signal Integration time. This decision is virtually arbi-

trary since the magnitudes of the various system errors are

not known. Setting the Auto-Zero time equal to the Input

Integrate time should be more than adequate to null out

system errors. The system may remain in this phase indefi-

nitely, i.e., Auto-Zero is the appropriate idle state for a TC5xx

device.

Input Signal Integrate Phase

The length of this phase is constant from one conversion

to the next and depends on system parameters and compo-

nent value selections. The calculation of tINT is shown

elsewhere in this data sheet. At some point near the end of

this phase, the microcontroller should sample CMPTR to

determine the input signal polarity. This value is, in effect,

the Sign Bit for the overall conversion result. Optimally,

CMPTR should be sampled just before this phase is termi-

nated by changing AB from 10 to 11. The consideration here

)

DESIGN CONSIDERATIONS

Noise

The threshold noise (NTH) is the algebraic sum of the

integrator noise and the comparator noise. This value is

typically 30µV. Figure 6 shows how the value of the refer-

ence voltage can affect the final count. Such errors can be

reduced by increased integration times, in the same way

that 50/60Hz noise is rejected. The signal-to-noise ratio is

related to the integration time (tINT) and the integration time

constant (RINT) (CINT) as follows:

S/N (dB) = 20 Log VIN •tINT

30 x 10–6 (RINT) • (CINT)

System Timing

To obtain maximum performance from the TC5xx, the

overshoot at the end of the Deintegration phase must be

minimized. Also, the Auto Zero phase must be terminated as

soon as the comparator output returns high. (See timing

diagram, Figure 8).

(

3-30 TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

Figure 8. Typical Dual Slope A/D Converter System Timing

,,

,,

AUTO -ZERO INTEGRATE

FULL SCALE INPUT

REFERENCE

DEINTEGRATE OVERSHOOT INTEGRATOR

OUTPUT

ZERO

CONVERTER

STATUS

TIME

INTEGRATOR

VOLTAGE

COMPARATOR

OUTPUT

AB INPUTS

CONTROLLER

OPERATION

NOTES

COMPARATOR DELAY

BEGIN CONVERSION

WITH AUTO-ZERO PHASE

(POSITIVE INPUT SHOWN)

SAMPLE INPUT POLARITY

The length of this phase

is chosen almost arbitrarily

but needs to be long enough

to null out worst case errors

(see text)

MINIMIZING OVERSHOOT

WILL MINIMIZE I.O.Z. TIME

READY FOR NEXT

CONVERSION

(AUTO-ZERO IS IDLE

STATE)

TIME INPUT

INTEGRATION

PHASE

CAPTURE

DEINTEGRATION

TIME

NTEGRATOR

OUTPUT

ZERO PHASE

COMPLETE

UNDEFINED

A = 0

B = 1

A = 1

0 FOR NEGATIVE INPUT

1 FOR POSITIVE INPUT

B = 0 B = 1 B = 0

A = 1 A = 0

VINT

TYPICALLY = tINT tINT

COMPARATOR DELAY +

PROCESSOR LATENCY

is that, during the initial stage of input integration when the

integrator voltage is low, the comparator may be affected by

noise and its output unreliable. Once integration is well

underway, the comparator will be in a defined state.

Reference Deintegration

The length of this phase must be precisely measured

from the transition of AB from 10 to 11 to the falling edge of

CMPTR. The comparator delay contributes some error in

timing this phase. The typical delay is specified to be 2µsec.

This should be considered in the context of the length of a

single count when determining overall system performance

and possible single-count errors. Additionally, Overshoot

will result in charge accumulating on the integrator after its

output crosses zero. This charge must be nulled during the

Integrator Output Zero phase.

Integrator Output Zero phase

The comparator delay and the controller's response

latency may result in Overshoot causing charge buildup on

the integrator at the end of a conversion. This charge must

be removed or performance will degrade. The Integrator

Output Zero phase should be activated (AB = 00) until

CMPTR goes high. It is absolutely critical that this phase be

terminated immediately so that Overshoot is not allowed to

occur in the opposite direction. At this point, it can be

assured that the integrator is near zero. Auto Zero should be

entered (AB = 01) and the TC5xx held in this state until the

next cycle is begun.

3-31

TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

USING THE TC510/514

Negative Supply Voltage Converter (TC510, TC514)

A capacitive charge pump is employed to invert the

voltage on VDD for negative bias within the TC510/514. This

voltage is also available on the V–

OUT pin to provide negative

bias elsewhere in the system. Two external capacitors are

required to perform the conversion.

Timing is generated by an internal state machine driven

from an on-board oscillator. During the first phase, capacitor

CF is switched across the power supply and charged to V+

This charge is transferred to capacitor C–

OUT during the

second phase. The oscillator normally runs at 100kHz to

ensure minimum output ripple. This frequency can be re-

duced by placing a capacitor from OSC to VDD. The relation-

ship between the capacitor value is shown in the typical

characteristics curves at the end of this data sheet.

Analog Input Multiplexer (TC514)

The TC514 is equipped with a four input differential

analog multiplexer. Input channels are selected using select

inputs (A1, A0). These are high-true control signals

(i.e., channel 0 is selected when (A1, A0 = 00).

EVALUATION KIT (TC500EV)

The TC500EV consists of a pre-assembled, 4 inch by 6

inch printed circuit board that connects to the serial port of

any PC or dumb terminal. Design software is also included.

TC500EV helps reduce design time and optimize converter

performance. Please contact your local TelCom representa-

tive for more information.

Design Example

Given: Required Resolution: 16 Bits (65,536 counts).

Maximum VIN:±2V

Power Supply Voltage: +5V

60Hz System

Step 1: Pick integration time (tINT) as a multiple of the

line frequency:

1/60Hz = 16.6msec. Use 4x line frequency = 66msec

Step 2: Calculate RINT

RINT (in MΩ) = VINMAX/20 = 2/20 = 100kΩ

Step 3: Calculate CINT for maximum (4V) integrator

output swing:

CINT (in µF) = (tINT) (20 x 10 –6) / (VS – 0.9)

= (.066) (20 x 10 –6) / (4.1)

= .32µF (use closest value: 0.33µF)

NOTE: TelCom recommended capacitor:

WIMA p/n: MK12 .33/63/10

Step 4: Choose CREF and CAZ based on conversion rate

Conversions/sec

= 1/(tAZ + tINT + 2 tINT + 2msec)

= 1

/(66msec + 66msec +132msec+2msec)

= 3.7 conversions/sec

From which CAZ = CREF = 0.22µF (see Table 1)

NOTE: TelCom recommended capacitor:

WIMA p/n: MK12 .22/63/10

Step 5: Calculate VREF

VREF (in Volts) = (VS – 0.9) (CINT) (RINT)

2(tINT)

= (4.1) (0.33 x 10 –6) (105) / 2(.066)

= 1.025V

3-32 TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

Figure 8. TC510 Design Example (See "Design Example")

Figure 9. TC510 to IBM Compatible Printer Port

MICRO

CONTROLLER

INPUT+

INPUT –

+5V

PIN 2

PIN 19

PIN 2

PIN 19

CINT

0.33µF

VIN

TYPICAL WAVEFORMS

1µF

CAZ

0.22µF

CREF

VIN

RINT

100k

CAP

DGND

OUT

REF

INT

BUF

ACOM

TC510

REF

–

CAP

CMPTR

0.22µF

0.01µF

10k

+5V

TC05

–

R3, 10k

PRINTER

PORT

0378

HEX

INPUT

–

+5V

10kΩ

10k

100kΩ

1µF

121

CAP

DGND

OUT

REF

INT

BUF

ACOM

TC510

TC04

REF

–

CAP

CMPTR

0.22µF

0.01µF

0.33µF

3-33

TELCOM SEMICONDUCTOR, INC.

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514

MICRO

CONTROLLER

+5V

PIN 2

PIN 23

PIN 2

PIN 23

CINT

0.33µF

VIN

TYPICAL WAVEFORMS

1µF1µF

CAZ

0.22µF

CREF

0.22µF

VIN

RINT

100k

CAP

DGND

VOUT

CREF

CINT

CAZ

BUF

ACOM

TC514

CREF

REF

VREF

–

CAP+

VDD

CMPTR

ANALOG

MUX LOGIC

INPUT 1+

INPUT 1–

INPUT 2+

INPUT 2–

INPUT 3+

INPUT 3–

INPUT4+

INPUT4–

CH1+

CH2+

CH2–

CH3+

CH3–

CH4+

CH4–

CH1–

C1, .01µF

10k

+5V

TC05

–

Figure 11. TC514 to IBM Compatible Printer Port

Figure 10. TC514 Design Example (See "Design Example")

IBM

PRINTER PORT

PORT

0378

HEX

+5V

10kΩ

100kΩ

1µF

CAP –

DGND

OUT

REF

TC514 TC04

–

BUF

0.22µF

10k

0.22µF

0.01µF

0.33µF

CH1+

INPUT 1

+18

–13

INPUT 2

+17

–12

INPUT 3

+16

–11

INPUT 4

+15

–10

CAP+

REF

–

REF

–

REF

INT

ACOM

CH1–

CH2+

CH2–

CH3+

CH3–

CH4+

CH4–

CMPTR

ANALOG MUX

CONTROL LOGIC

3-34 TELCOM SEMICONDUCTOR, INC.

TYPICAL PERFORMANCE CHARACTERISTICS OF INTERNAL DC-TO-DC CONVERTER

LOAD CURRENT (mA) OUTPUT CURRENT (mA)

–5

–4

–3

–2

–1

01020304050 60 70 0 6 8 104214161812 2080

OUTPUT VOLTAGE (V)

Output Voltage vs Load Current

–0

–1

–3

–2

–4

–5

–7

–6

–8

OUTPUT VOLTAGE (V)

Output Voltage vs. Output Current

OSCILLATOR CAPACITANCE (pF)

100

1110 100 1000

OSCILLATOR FREQUENCY (kHz)

Oscillator Frequency vs. Capacitance

LOAD CURRENT (mA)

0 345612 78910

100

125

150

175

200

OUTPUT RIPPLE (mV PK-PK)

Output Ripple vs. Load Current

TEMPERATURE (°C)

100

40–50 025

–25 50 75 100

OUTPUT SOURCE RESISTANCE (Ω)

Output Source Resistance vs. Temperature

= 25°C

V+ = 5V

= +25°C

V+ = 5V

= 25°C

Slope 60Ω

V+ = 5V, TA = 25°C

Osc. Freq. = 100kHz

CAP = 1µF

CAP = 10µF

V+ = 5V

IOUT = 10mA

TEMPERATURE (°C)

125

150

100

–50 025–25 50 75 125100

OSCILLATOR FREQUENCY (kHz)

Oscillator Frequency vs. Temperature

V+ = 5V

PRECISION ANALOG FRONT ENDS

TC500

TC500A

TC510

TC514

3-35

TELCOM SEMICONDUCTOR, INC.

Australia:

ADILAM ELECTRONICS (PTY.) LTD.

P.O. Box 664

3 Nicole Close

Bayswater 3153

Tel.: 3-761-4466

Fax: 3-761-4161

Canada:

R-THETA INC.

130 Matheson Blvd. East, Unit 2

Mississauga, Ont. L4Z1Y6

Tel.: 905-890-0221

Fax: 905-890-1628

Hong Kong:

REALTRONICS CO. LTD.

E-3, Hung-On Building

2, King's Road

Tel.: 25-70-1151

Fax: 28-06-8474

India:

SUSAN AGENCIES

P.O. Box 2138

Srirampuram P.O.

Bangalore-560 021

Tel.: 080-332-0662

Fax: 080-332-4338

Israel:

M.G.R. TECHNOLOGY

P.O. Box 2229

Rehavot 76121

Tel.: 972-841-1719

Fax: 972-841-4178

Japan:

UNIDUX INC.

5-1-21, Kyonan-Cho

Musashino-Shi

Tokyo 180

Tel.: 04-2232-4111

Fax: 04-2232-0331

Malaysia:

MA ELECTRONICS (M) SDN BHD

346-B Jalan Jelutong

11600 Penang

Tel.: 604-281-4518

Fax: 604-281-4515

Singapore:

MICROTRONICS ASSOC. (PTE.) LTD.

8, Lorong Bakar Batu

03-01, Kolam Ayer Ind. Park

Singapore 1334

Tel.: 65-748-1835

Tlx: 34 929

Fax: 65-743-3065

South Africa:

KOPP ELECTRONICS LIMITED

P.O. Box 3853

2128 Rivonia

Tel.: 011-444-2333

Fax: 011-444-1706

South Korea:

YONG JUN ELECTRONIC CO.

#201, Sungwook Bldg.

1460-16, Seocho-Dong

Seocho-Ku

Seoul, Korea

Tel.: 25-231-8002

Fax: 25-231-803

Taiwan, R.O.C.:

SOLOMON TECHNOLOGY CORP.

7th Floor No. 2

Lane 47, Sec. 3

Nan Kang Road

Taipei

Tel.: 886-2788-8989

Fax: 886-288-8275

Thailand:

MICROTRONICS THAI LTD.

50/68 T.T. Court

Cheng Wattana Road

Amphur Pak-Kreed

Nonthaburi 11120

Tel.: 66-2584-5807, Ext. 102

Fax: 66-2583-3775

USA:

THE INTER-TECHNICAL GROUP, INC.

WIMA DIVISION

175 Clearbrook Road

P.O. Box 535

Elmsford, NY 10523-0535

Tel.: 914-347-2474

Fax: 914-347-7230

TAW ELECTRONICS, INC.

4215, W. Burbank, Blvd.

Burbank, CA, 91505

Tel.: 818-846-3911

Fax: 818-846-1194

Venezuela:

MAGNETICA, S.A.

Apartado 78117

Caracas 1074 A

Tel.: 58-2241-7509

Fax: 58-2241-5542

WIMA Corporation Capacitor Representatives (Tables 1 and 2 in Applications Section)

PRECISION ANALOG FRONT ENDS TC500

TC500A

TC510

TC514