20 Am29SL800C
PRELIMINARY
RY/BY#: Read y/Bu sy#
The RY/BY # is a dedica ted , op en-drai n o utp ut p i n tha t
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the de vice is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Tabl e 6 shows the outpu ts for RY/ BY#. F igures 14, 17
and 18 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Togg le Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mod e. To gg le B it I m ay be read at any add re ss , an d is
valid aft er the ri sing edg e of the fin al W E# pu l se in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
Du r ing an E m bed de d Pro gram or E ra se a l go r ithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The syste m may u se either OE# or CE#
to control the read cycles). When the operation is co m-
plete, DQ6 stops toggling.
Af t er an e ra s e comm an d s e qu en ce i s wri t ten , i f al l se c-
tors selected f or erasing are protected, DQ6 toggles f or
approximately 100 µs, then returns to reading array
data . If not al l s el ec ted se cto rs ar e pro te cted , the E m -
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
prot ected.
The system can use DQ6 and DQ2 together to deter-
mine whether a s ector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see t he subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approxim ately 1 µs afte r the program
command sequence is written, then returns to reading
array da ta.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Tab le 6 sho ws the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 20 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 21 shows the differences between
DQ 2 an d D Q 6 in gra phi c al for m. Se e als o the sub sec -
tion on DQ2: Toggle Bit II.
DQ2: Togg le Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sect or is erase- suspended. Toggle Bit
II is v alid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE # or CE # read cycle.
DQ2 toggles when the system reads at addresses
with in those sect ors that have been selected for era s-
ure. B ut DQ 2 ca nnot dist ingui sh w hethe r the sect or is
actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish
whi ch sectors are selected for e rasure. Thus, bo th sta-
tus bits are required for sector and mode information.
Ref er to Tabl e 6 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. Se e also the DQ6: Toggle Bit I sub section.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical f orm.
Reading Toggle Bits DQ6/DQ2
Ref er to Figure 6 for the fol lowing discussion. Whenev er
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twi ce i n a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the s econd read, the system w ould com-
pare the new value of the toggl e bit w ith the first. If the
toggle bit is not toggling, the dev ice has completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
However, if after the initial two re ad cycles, the syste m
deter mines t hat the to ggle bit is s till toggling, t he sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
the n det ermin e again w hethe r the t ogg le bit is togg lin g,
sin ce the to ggle bit may have stop ped tog gling j ust as
DQ5 went high. I f the toggle bit is no longer toggling,
the device has succes sfully completed the program or
erase operation. If it is still toggling, th e device did not
completed the operatio n successfully, and the system
must write the reset command to return to reading
array da ta.