Am29SL800CT100EIB - Advanced Micro Devices

PRELIMINARY

This doc um ent contains inform ation on a produc t under developmen t at Advanc ed Mi c r o Devices. Th e information

is intended to help you ev aluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 22230 Rev: AAmendment/0

Issue Date: August 1998

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29SL800C

8 Megabi t (1 M x 8- Bit/51 2 K x 16-Bi t)

CMOS 1.8 Volt-on l y Super Low Vol ta ge Flash Memory

DISTINCTIVE CHARACTERISTICS

■Si ngle power supply op eration

— 1.8 to 2.2 V for read, program, and erase

operations

— Ideal for battery-powered applications

■Manufactured on 0.32 µm pro cess te chnology

— Compatible with 0.35 µm Am29SL800B device

■High perfo rmance

— Access times as fast as 100 ns

■Ultra low power consumption (typical val ues at

5 MHz)

— 65 nA Automatic Sleep Mode current

— 65 nA standby mode current

— 5 mA read current

— 10 mA program/erase current

■Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

fifteen 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

fifteen 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

A ha rdwar e method of lo ckin g a secto r to

pr event an y program or erase oper ations within

that sector

Se ctors can be lo cke d in-s ystem or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■Unlock Bypass Program Command

— Reduces overall programming time when

iss uing multiple program command s equences

■Top or bottom boot block configurations

available

■Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designat ed sector s

— Embed ded Pr ogram algorithm automatically

writes and verifies data at specified addresses

■Minimum 1,000,000 write cycle guarantee per

sector

■Package option

— 48-pin TSOP

— 48-ball FBGA

■Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write prot ecti on

■Dat a# Polling and toggle bits

— Provides a software method of detecting

pr ogram or erase operat ion co mpletion

■Re ady /B u sy # pin (RY /B Y#)

— Provides a hardware method of detecting

program or erase cycle comp letion

■Er as e Sus pe nd /E r as e Res um e

— Suspends an erase operation to read data from,

or pr ogram data to, a sector that is not bei ng

erased, then resumes the erase operation

■Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

2 Am29SL800C

PRELIMINARY

GENERAL DESCRIPTION

The Am29SL800C is an 8 Mbit, 1.8 V volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The device is offered in 48-pin TSOP and 48-

ball FBGA packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data

appe ars on DQ7–DQ0. This device is d esigned to be

programmed and erased in-system with a single 1.8

volt VCC supply. No VPP is for write or erase operations.

The device can also be programmed in standard

EPROM programmers.

The standard device offers access times of 100, 120,

and 150 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The devic e re q uir es on ly a single 1.8 v olt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely comma nd set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of th e device is similar to reading from other

Fl ash or EPRO M devices .

Devic e p ro gram m ing occ u rs by executin g th e program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Dev ice eras ure oc curs b y ex ecut ing the erase command

sequence. This initiates the Embedded Erase algo-

rithm—an internal algorithm that automatically prepro-

gr ams the array (if it is not already programmed) before

executing the erase operation. During erase, the device

automatically times the erase pulse widths and verifies

proper cell margin.

The host system can detect whether a program or

eras e op eration is co mpl ete by ob ser vin g the RY/B Y#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(tog gle ) stat us bits . After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

er ased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits wr ite opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

opera tions in any combination of the sect ors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The Erase Suspend feature enables the user to put

erase on hol d for any pe r iod of ti m e to rea d da ta fr om ,

or program data to, any secto r that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading arra y data. The RESET# p in may be tied to the

system reset circ uitr y. A sys tem re set would thu s also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device off ers tw o power-saving features. When ad-

dresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the de vice into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within

a sector simultaneously via Fowler-Nordheim tun-

neling. The data is programmed using hot electron

injection.

Am29SL800C 3

PRELIMINARY

PR ODUCT SELECTOR GUIDE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29SL800C

Speed Options 100 120 150

Max access time, ns (tACC)100 120 150

Max CE# access time, ns (tCE)100 120 150

Max OE# access time, ns (tOE)35 50 65

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

BYTE#

CE#

OE#

STB

DQ0

–

DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A18

22230A-1

4 Am29SL800C

PRELIMINARY

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A18

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

22230A-2

Reverse TSOP

Standard TSOP

Am29SL800C 5

PRELIMINARY

CONNECTION DIAGRAMS

Special Handling Instructions for FBGA

Packages

Special handling is required f or Flash Memory products

in FBGA packages.

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data i ntegrity may be compromi sed

if the package body is exposed to temperatures above

150°C for prolonged periods of time.

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSS

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5NCNCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18NCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSS

CE#A0A1A2A4A3

22230A-3

48-Ball FBGA (Bottom View)

6 Am29SL800C

PRELIMINARY

PIN CONFIGURATION

A0– A 18 = 19 addr es se s

DQ 0– DQ 1 4 = 15 data in pu ts/ outputs

DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (L SB ad dre s s inpu t, byt e mo de)

BYT E# = Selects 8- bit or 16-bit mode

CE# = Chip enable

OE# = Output enable

WE# = Wr ite en abl e

RESET# = Hardware res et pin, acti v e low

RY/BY# = Ready/Busy# output

VCC = 1.8–2.2 V single power supply

VSS = Device ground

NC = Pin not conn ected internally

LOGIC SYMBOL

22230A-4

19 16 or 8

DQ0–DQ15

(A-1)

A0–A18

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

Am29SL800C 7

PRELIMINARY

ORDERING INFORMATION

Standard Products

AM D stan dard p roduc ts ar e avai lable in several p ackag es and op erati ng rang es. The or der num ber (Valid Co mbi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this de vice. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBE R/DE SCRIP TION

Am29SL800C

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

CE100Am29SL800C T

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

WB = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

Valid Combinations

Am29SL800CT100,

Am29SL800CB100

EC, EI, FC, FI, WBC, WBI

Am29SL800CT120,

Am29SL800CB120

Am29SL800CT150,

Am29SL800CB150

8 Am29SL800C
PRELIMINARY
DEVI CE BUS OPERATIONS
This section describes the requirements and use of the
device bus  operations, which are initiated through the
internal command register. The command register it-
self  does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address an d data infor ma-
tion needed to e xec ute the command . The contents of
the register serve as inputs to the inter nal state ma-
chine. The state machine outputs dictate the function of
the d evice. Ta ble 1 li s ts th e d evice bus o perati o ns, th e
inputs and control le v els they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29SL800C Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
 = 10 
± 
1.0 V, X = Don’t Care, A
IN
 = Address In, D
IN
 = Data In, D
OUT
 = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V
IH
), A18:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector 
Protection/Unprotection” section.
Wor d/Byte Configuration
The BY TE# p in  contr ols  whethe r the  device d ata I/O  pi ns
DQ15–DQ0 operate in the byte or word configuration. If the
BYTE# pin is set at logi c ‘1’, the device is in word configu-
rat io n, DQ 15–DQ0  are ac tive and con trolle d by C E# and
OE#.
If the BYTE# pin  is set at l ogic  ‘0’, the de vice is in  byte  con-
figuration,  and only data I/O pins DQ0–DQ7  are active  and
controlled by CE# and OE#. The data  I/O pins DQ8–DQ14
are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function. 
Requirements for Reading Arra y Data
To read arra y d ata from  the  outputs, the system must driv e
the CE# and OE# pins to VIL.  CE# is the power control  and
selects the device. OE #  is the output control and gates
array data to  the outpu t pins. W E# shoul d remai n at VIH.
The BYTE# pin determines whether the devic e outputs
arra y data in words or b ytes.
The internal state machine is set  for reading array  data
upon device power-up, or after a hardware reset. This en-
sures that no spurious alteration of the memory content oc-
curs during the power transition. No command is
necessary in this mode to obtain array data. Standard mi-
cro proce ssor  r ead cy cles th at asse r t valid ad dresse s on
the device address inputs produce v alid data on the de vice
data outputs. The de vice remains enabled f or read access
until the command register c ontents are al tered.
See “Reading Array Data” for more information. Refer to
the AC Read Operations table for timing specifications  and
to Figure 13 for the  timing diagram. ICC1 in the DC Charac-
teristics  table represents  the active current  specification for
reading array data.
Writing C om mands/Command Se que nces
To w rite a comm and or c ommand seque nce (which i n-
cludes programming data to the device and erasing sectors
of memory), the system mu st drive WE# an d CE#  to VIL,
and OE# to VIH.
Operation CE# OE# WE# RESET# Addresses
(Note 1) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H AIN DOUT DOUT DQ8–DQ14 = High-Z, 
DQ15 = A-1
Write L H L H AIN DIN DIN
Standby VCC ± 
0.3 V XXV
CC ± 
0.3 V X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L VID
Sector Address, 
A6 = L, A1 = H, 
A0 = L DIN XX
Sector Unprotect (Note 2) L H L VID
Sector Address, 
A6 = H, A1 = H, 
A0 = L DIN XX
Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z

Am29SL800C 9
PRELIMINARY
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more infor-
matio n. 
The device features an Unlock Bypass mo de to facilitate
faster programming.  Once the device enters the Unlock
Bypass mode, only two write cycles are required to pro-
gram a word or byte, instead of four. The “Word/Byte Pro-
gram Command Sequence” section has details on
program ming  d ata to the device usi ng both stand ard and
Unlock Bypass command sequences.
An erase  operation can erase one sector, multiple sectors ,
or th e enti re device. Tables  2  and 3 i ndica te the  add ress
space  tha t eac h  sector  oc cup ies. A “ s ector  addr ess ” co n-
sists of the address bits required to uniquely select a sector.
The “Command Definitions” section has details on erasing
a sector or the entire chip, or  suspending/res uming the
erase operation.
After the system writes the autoselect command se-
quence, the device  enters  the  a utoselect mode. The sys-
tem can then read autoselect codes from the internal
register (which is separate from the memor y a rray) on
DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to the Autoselect Mode and Autoselect Command
Sequence sections for more information.
ICC2 in the D C C haracter isti cs table repres ents the active
curr ent  speci fic ation fo r the  w rite  mode . T he “ AC Ch arac-
teristics” section contains timing specification tables and
timing diagrams for write operations.
Program and Erase Operation St atus
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on DQ7–DQ0. Standa rd re ad cycle  timings  a nd ICC read
sp ecificat ions ap ply. Refer to “ Write  Opera tion Sta tus” for
more inf ormation, and to “A C Characteristics” for timi ng di-
agrams.
Standby Mode
When the system is not reading or writing to the device, it
ca n plac e the  dev ice i n the s tand by  mode.  In th is mo de,
current consumption is greatly reduced, and the outputs
are placed in the high i mpedance state, i ndependent of the
OE# input. 
The device enters the CMOS standby mode when the CE#
and RESET # pins are  both held at VCC ± 0.3 V. (Note that
this is a more restricted voltage range than VIH.) If  CE#  and
RESET# are held at VIH, b ut  not within VCC  ± 0.3  V,  the  de-
vice will be in the standby mode, but the standby current will
be greater . The de vi ce requires standard access time (tCE)
for r ead access when the device is i n either of these
standb y modes, before it is ready to read data.
The device also enters the standby mode when the RE-
SET# pin  is driven low. Refer to the  next  section,  RESET#:
Hardw are Reset  Pin.
If the device is deselected during erasure or programming,
th e de v i c e dr a ws  act i ve cur r e nt  unt il the o p er a t io n  i s  com-
pleted.
ICC3 in the DC Characteristics table represents the standby
current specificati on. 
A u toma ti c S lee p Mo de
The automatic sleep mode minimi zes Flash de vice energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 50 ns. The
automatic  sleep mode is independent of the CE#, WE#,
and OE# control signals.  Standard address access ti mings
provide new data wh en addresses are c hanged. Whi le  in
sleep mode, output data is latched and alwa ys av ailable to
the system. ICC4 in the DC Characteristics table represents
the automatic sleep mode current specification.
RE SET #: H ar d wa re  Rese t P in
The RESET# pin provi des a hardware method of resetting
the device to reading arra y data. When the RESET# pin is
dri ven low  fo r a t  least  a perio d o f tRP, the device immed i-
ately terminates any operation in progress, tristates all
output pins, and ignores all read/w rite commands for the
duration of the RESET# pulse. The device a l so r esets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure
data integrity.
Current  is reduced for  the duration of the RESET#  pulse.
When  RESET# is hel d at V SS±0 .3  V, the device  draws
CMOS  standb y current (ICC4). If RE SET# is held at VIL but
not wi thin VSS±0.3 V, the standby current will be greater.
The R ESET# pin may be tied  to the  system reset circuitry.
A syst em res et would thus a lso reset the  F lash mem or y,
enabling the system to read the boot-up firmware from the
Fl as h m e mo ry.
If RESET#  is asserted during a program or  e rase opera-
tion, the RY/B Y# pin remains a “0” (b usy) until the internal
reset operation is complete, which requires a time of
tREADY (during Embedded Algorithms). The system can
thus  monitor RY/BY# to determine whether the reset oper-
ation is complete. If RESET# is asserted when a program
or erase operation i s not e x ecuting (RY/BY# pin i s “1”), the
reset operation is completed within a time of tREADY (not
during Embedded Algorithms). The system can read data
tRH after the RESE T# pin returns to VIH.
Refer to the AC Characteristics tabl es f or RESET# param-
eters and to Figure 14 f or the timing diagram.
Output Disab le Mode
When  the OE# input is at VIH, output from the device is dis-
abled . The out put pi ns are plac ed in the  high im pedan ce
state.

10 Am29SL800C

PRELIMINARY

Table 2. Am29SL800CT Top Boot Block Sector Address Table

Sector A18 A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range (x16)

Address Range

SA00000XXX 64/32 00000h–0FFFFh 00000h–07FFFh

SA10001XXX 64/32 10000h–1FFFFh 08000h–0FFFFh

SA20010XXX 64/32 20000h–2FFFFh 10000h–17FFFh

SA30011XXX 64/32 30000h–3FFFFh 18000h–1FFFFh

SA40100XXX 64/32 40000h–4FFFFh 20000h–27FFFh

SA50101XXX 64/32 50000h–5FFFFh 28000h–2FFFFh

SA60110XXX 64/32 60000h–6FFFFh 30000h–37FFFh

SA70111XXX 64/32 70000h–7FFFFh 38000h–3FFFFh

SA81000XXX 64/32 80000h–8FFFFh 40000h–47FFFh

SA91001XXX 64/32 90000h–9FFFFh 48000h–4FFFFh

SA10 1010XXX 64/32 A0000h–AFFFFh 50000h–57FFFh

SA11 1011XXX 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA12 1100XXX 64/32C0000h–CFFFFh 60000h–67FFFh

SA13 1101XXX 64/32D0000h–DFFFFh 68000h–6FFFFh

SA14 1110XXX 64/32 E0000h–EFFFFh 70000h–77FFFh

SA15 11110XX 32/16 F0000h–F7FFFh 78000h–7BFFFh

SA16 1111100 8/4 F8000h–F9FFFh 7C000h–7CFFFh

SA17 1111101 8/4 FA000h–FBFFFh 7D000h–7DFFFh

SA18 111111X 16/8 FC000h–FFFFFh 7E000h–7FFFFh

Am29SL800C 11

PRELIMINARY

Table 3. Am29SL800CB Bottom Boot Block Sector Address Table

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration”

section for more information.

Sector A18 A17 A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

(x8)

Address Range (x16)

Address Range

SA0000000X 16/8 00000h–03FFFh 00000h–01FFFh

SA10000010 8/4 04000h–05FFFh 02000h–02FFFh

SA20000011 8/4 06000h–07FFFh 03000h–03FFFh

SA300001XX 32/16 08000h–0FFFFh 04000h–07FFFh

SA40001XXX 64/32 10000h–1FFFFh 08000h–0FFFFh

SA50010XXX 64/32 20000h–2FFFFh 10000h–17FFFh

SA60011XXX 64/32 30000h–3FFFFh 18000h–1FFFFh

SA70100XXX 64/32 40000h–4FFFFh 20000h–27FFFh

SA80101XXX 64/32 50000h–5FFFFh 28000h–2FFFFh

SA90110XXX 64/32 60000h–6FFFFh 30000h–37FFFh

SA10 0111XXX 64/32 70000h–7FFFFh 38000h–3FFFFh

SA11 1000XXX 64/32 80000h–8FFFFh 40000h–47FFFh

SA12 1001XXX 64/32 90000h–9FFFFh 48000h–4FFFFh

SA13 1010XXX 64/32 A0000h–AFFFFh 50000h–57FFFh

SA14 1011XXX 64/32 B0000h–BFFFFh 58000h–5FFFFh

SA15 1100XXX 64/32C0000h–CFFFFh 60000h–67FFFh

SA16 1101XXX 64/32D0000h–DFFFFh 68000h–6FFFFh

SA17 1110XXX 64/32 E0000h–EFFFFh 70000h–77FFFh

SA18 1111XXX 64/32 F0000h–FFFFFh 78000h–7FFFFh

12 Am29SL800C
PRELIMINARY
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a de vice to be programmed with
its co rresponding programming  algorithm. Howeve r,
the  aut oselec t co des c an  also  be a cces sed in -sy stem
through the command register .
When using programming equipment, the autoselect
mode requires VID on address pin A9.  Addres s pins A6,
A1, and A0 must be as sh own in Table 4. In addition,
when verifying sector protection, the sector address
must  appear on  the app ropriate h ighest or der address
bits (see Tables 2 and 3 ). Table  4 shows the remaining
address bits that are don’t care. When all  necessary  bits
have been set as  required, the programming equipment
may then read the corresponding identifier code on
DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command reg ister, as s hown in Table 5. This method
does not require VID. See “Command Definitions” for
details on using the  autoselect mode.
Table 4. Am29SL800C Autoselect Codes (High Voltage Method)
L = Logic Low = V
IL
, H = Logic High = V
IH
,  SA = Sector Address, X = Don’t care.
Sector Protection/Unpr otection
The hardware sector protection feature disables both
program and erase operations in any sector . The hard-
ware secto r unp rotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two method s. 
The primary  method  requires V ID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 23 show s the timi ng diagram. This
method uses standard microprocessor bus cycle tim-
ing. For s ector unprotect, all unprotected sec tors must
first be protected prior to the first sector unprotect write
cycle. 
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
wri t te n  f or  ea rl ier  3 . 0 volt- o nl y  AMD   fla s h d evi c e s.  P ub-
lication number 21622 contains  further details. Contact
an AMD represe ntative to request the document con-
taining further details.
The device is shipped with all sectors unprotected.
AMD offe rs the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or  unprotected. See “Autoselec t Mode” for details.
Temporary Sector Unpro tect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sec tor  U n pr ot ect  m ode  i s  activated  by s etting  th e  RE -
SET # pi n to VID. D ur ing th is mo de, fo rm er ly prote cted
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the  RE-
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
Description Mode CE# OE# WE#
A18
to 
A12
A11
to
A10 A9
A8
to
A7 A6
A5
to
A2 A1 A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD L L H X X VID XLXLL X 01h
Device ID: 
Am29SL800C
(Top Boot Block)
Word L L H XXV
ID XLXLH22h EAh
Byte L L H X EAh
Device ID: 
Am29SL800C
(Bottom Boot  Bloc k)
Word L L H XXV
ID XLXLH22h 6Bh
Byte L L H X 6Bh
Sector Protection Verification L L H SA X VID XLXHL X01h 
(protected)
X00h 
(unprotected)

Am29SL800C 13

PRELIMINARY

Figure 1. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

22230A-5

14 Am29SL800C
PRELIMINARY
Figure 2. Temporary Sector Unprotect Operation
Hardware Data P ro tection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system le vel signals during VCC pow er-up and
power-down tran sitions, or from system noise.
Low VCC Write Inhibit
When V CC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
al l int ernal  p rogr am/er ase  circ uit s are di sa ble d, an d the
de v i ce r es e t s.  Sub s eq ue nt  wri t es ar e i g n or ed un ti l  VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writ es whe n VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#  or
WE# do not  initiate a write cycle.
Logical Inhibit
Write c ycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or W E# = V IH. To  initi a te  a  wri te  c y -
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power
up, the  device d oes no t  accept  comman ds  on th e
ri sing edge of W E#. The  int er nal state ma chine  is
automatically reset to reading array data on
power-up.
COMMAND DEFINITI ONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing  them in t he improper sequence resets
the device to readin g array data. 
All addresses are latched on  the falling edge of WE#  or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characterist ics” sect ion .
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again  read array data with the  same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mo de.
The  system 
must
 issue the reset command to  re-ena-
ble the  devic e for rea din g ar ray da ta if D Q5  goe s hi gh ,
or while in  the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Arra y Data” in the
“Device Bus Op erations” sectio n for  more information .
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice  to re ading  ar ray da ta . A d dr ess bi ts  are  don’ t  car e
for this comman d. 
START
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = VID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
22230A-6

Am29SL800C 15
PRELIMINARY
The reset command may be written between the se-
quence  cyc les i n a n era se comman d s e qu enc e before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset  commands until the o peration is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device  i g no re s   res et  commands  u ntil   th e
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once  in the autoselect mode, the reset command 
must
be wr itten to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 g oes high during a program or erase operation,
wr itin g the re set com mand  returns  the d evi ce to re ad-
ing array data (al so applies during Erase Suspend).
Autoselect Comman d Sequence
The  autoselect command sequence allows the host
system to access the manufacture r and de vices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM program mers  and requi res V ID
on address bit A9.
The autosel ect comm and sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect c om-
mand. The device then enters the autoselect mode,
and  the  system  may r ead a t any ad dress  any  numbe r
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
ture r cod e. A r ead  cycle  at  addr ess  01h  in  word m od e
(or 02 h in byte  m od e) ret ur ns the devi ce code. A  r ead
cycle containing a sector address  (SA) and the address
02h in word mode (or 04h in byte mode) returns 01h if
that sector is protected,  or 00h if it is unprotected. Ref er
to Tables 2 an d 3 for valid sector addres ses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/ Byte Program Comman d Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
mi ng  is a   four- bus-c y cle operatio n.  T h e  pr ogra m  com -
mand sequence  is  in itiated by writing two unlock  wr ite
cyc l es, followed  by th e pr ogra m se t- up c o mm a nd . Th e
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is 
not
 required to provide further controls or tim-
ing s.  The  device a utoma tica lly ge nerat es t he pro gram
pul se s  and  verifies th e pr ogra m me d c e ll m ar gin . Table
5 shows the address and data requirements for the
byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
min e t he st atus  of  the  prog ra m ope rat io n by  us ing D Q7,
DQ6, or RY/BY#. Se e “Write Operation Status” for in-
formation on these status bits. 
Any  commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to  a “1”. Attempting to do so ma y halt
the o peration and set DQ5 to “1”, or cause t he Data#
Polling algorithm to indicate the operation was suc-
cessful. Ho wever, a succeeding read will show that the
dat a i s s till  “0 ”. On l y  er ase  op er a t ion s  ca n co n vert a “ 0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gr am  b y te s  or  wor ds  t o t he  device  fast er  th an  us in g t he
standard program command  sequence. The unlock b y-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
co ntaini ng th e unlo ck bypass c omm and , 20h. T he de -
vice t he n  enter s t he u nlo ck bypass m o de. A  two-cy cle
unl ock by p ass  program  c o mm an d  sequenc e  is all  tha t
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resultin g in faster to tal program-
ming time. Table 5 shows the requirements f or  the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are  valid. To exit t he un lock bypa ss mod e,  th e syste m
must issue the two-cycle unlock bypass reset com-
man d se quen ce. The fi rst cy cle mu st co ntain  the  data
90h; the second cycle the data 00h. Addresses are
don’t cares. The device then returns to reading array
data.
Figure  3 illustrates the algorithm  for the program oper-
at ion. Se e the Eras e/Pro gram Op erat ions tabl e in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.

16 Am29SL800C
PRELIMINARY
Note: See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Comm and Seq uence
Chip erase is a  six bus cycle op erat ion. The chip erase
command sequence is initiated by writing two unlock
cyc les, followed  by a set- up com mand . Two a ddi tional
unlock write cycles are then followed b y the chip erase
co mm an d,  w hich  i n t urn invokes t he  E mb ed ded  E ras e
algorithm. The device does 
not
 require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
eras e. Th e system  is n ot re qui red to  provi de any  con-
trols or timings during these operations. Table 5 shows
the ad dress and data requiremen ts for the chip  erase
comm and seque nce.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset dur ing  the  c h ip e rase operation  im media tely   ter -
minates the operation. The Chip  Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integri ty.
The system can determine the st atus of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus  bits.  W h en th e E m be dd ed Era s e alg or ithm is  com -
plete, the device returns to reading array data and
addresses are no longer latched. 
Figure 4 illustrates the algorithm for the erase opera-
tio n. See th e Era se/Pr ogram O perat ions tabl es in “ AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed  by a set -up comman d. Two add i-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
eras e com mand . Table 5 s hows th e addr ess  a nd dat a
requirements f or the sector erase command sequence.
The device does 
not
 require the syst em to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all  zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors ma y  be from  one sector  to all sectors. The time be-
tween these additional cycles must be  less than 50  µs,
otherwise the last address and command might not be
accepted, and erasure may beg in. It is recommended
that processor interrupts be disabled during this time to
ensur e all com mands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The  sy st em  c an mo ni t or D Q 3  to  det e rmin e i f  the  s ect or
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of  the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Er as e S us pen d c o mma nd  is  vali d . Al l  ot he r co mma n ds
are ignored. Note that a hardware reset during the
se cto r era s e o pe ratio n i m me dia t ely  t ermin ate s th e op-
erati o n. T he  S ec tor  E rase  com m and se qu en ce s h ou ld
be r einit iated o nce th e device ha s retur ned to r eading
array data, to ensure data integrity.
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded
Program
algorithm
 in progress
22230A-7

Am29SL800C 17
PRELIMINARY
When the Embedded Erase algorithm is complete, the
device  returns to reading  array data and addresses are
no l onge r latc hed.  The sy stem  can d eter mi ne the  sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
R Y/ BY#.  (Ref er  to “W rite O per atio n St atus” f or  inf orma-
tion on these status bits.)
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Char acteristics” section fo r parameters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Era se Suspend  command allows the system to in-
terrupt  a sector erase  operation and then read data
from, or program data to, any sector not selected for
erasure. This c ommand is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
ti me -o ut pe ri od  an d su sp e nd s th e er a s e o pe r ati o n.  Ad-
dresses  are  “d on’t-c ar es ”  whe n w riting the E ras e S us -
pend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-o ut, the device immedia tely ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system  can read array data from or program data to
any sector not selected for erasure . (The de vice “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See  “Wr ite  Ope ration  Stat us”  fo r i nfo rm ation  on t hes e
status bits.
After an  erase-suspended program operation is com-
plete, the system can once again  read arra y data within
non-suspended sectors. The system can determine
the status of the program operat ion usin g the DQ7 or
DQ 6 s tatu s  b its, j u st a s i n  th e s tandard  pr ogram op er -
ation. See “Write Operation Status” for more informa-
tion.
The system may also write the autoselect command
sequence when the  device is in the  Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. Se e “Autoselect Comma nd Sequen ce”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to e xit the erase suspend
mode  an d c o nti n ue t he  s ect or  er as e o pe r ati on . Fu rt h er
writes o f the Resume com mand  are ignored. Anot her
Era se Sus pend co mma nd  ca n be w ritt en afte r th e de-
vice has resumed erasing.
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
START
Write Erase 
Command Sequence
Data Poll 
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded 
Erase
algorithm
in progress
22230A-8

18 Am29SL800C
PRELIMINARY
Table 5 . Am29SL800C Command Definitions
Legend:
X = Don’t care
RA = Address of the memor y loca tion to be read. 
RD = Data read from location RA during read operation.
PA = Address of the m emory location to be programmed. 
Addresses latch on t he falling edge of the WE# or CE# pulse,  
whichever happens l ater.
PD = Data to be programmed  at location PA. Data latches on the 
rising edge of WE# or CE# pulse, whichever  happens fi rst.
SA = Address of the sector to be v erified (in autoselect mode) or 
erased. Addr ess bits A18–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operat ions.
2. All values are  in hexadecimal.
3. Except  w hen reading array or aut osel ect data, all bus cycl es 
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for  unlock and 
comm and cycl es.
5. Address bi ts A18–A11 are don’t cares for unlock and 
comm and cycl es, unless SA or PA required.
6. No unlock or command cycle s required when reading array 
data, unless SA or PA required.
7. The Reset command is required to return to readin g array 
data when device is in the autosel ect  mode, or if  DQ5 goes 
high (while the dev ice is providing status data).
8. The fourth cycl e of the autoselect  command sequence i s a 
read cycle.
9. The data is 00h for an unprotected sector and 01h for  a 
prote cted sector. See “Aut oselect Command S equenc e” for 
more information.
10. The Unl ock Bypass command is required prior to the U nlock 
Bypass Program command.
11. The Unlock Bypass Reset command is required to retur n to  
reading array data w hen th e device is in the unlock bypass 
mode.
12. The system may read and program in non-erasing sectors, or 
enter  the autose lect mode, when in the Erase Suspend 
mode. The Erase S uspend command is valid only  during a 
sector erase operation.
13. The Erase Resume command is v ali d only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-5)
First Second Third  Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 R A RD
Reset (Note 7) 1 X XX F0
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID, 
Top Boot Block  Word 4555 AA 2AA 55 555 90 X01 22EA
Byte AAA 555 AAA X02 EA
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 226B
Byte AAA 555 AAA X02 6B
Sector Protect  Veri f y 
(Note 9)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 XXX 90 XX X 00
Chip Er a se Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
Cycles
Autoselect (Note 8)

Am29SL800C 19

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,

and RY/BY#. Tab le 6 and the f ollowing subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# P olling

The Data# P olli ng bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 stat us al so applies to pro-

gramming during Erase Suspend. When the

Em bedde d Pr ogram a lgor ithm i s comp lete, t he devic e

outputs the datum programmed to DQ7. The system

mus t p rovi d e th e p ro gram ad dr es s to r ea d val id statu s

information on DQ7. If a program address falls within a

protecte d sector , Data# P olling on DQ7 is active f or ap-

proximately 1 µs, then the device returns to reading

array da ta.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, o r if the device enters the Erase

Suspend mode, Data# Pollin g produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must pr ovide an address within any of

the sectors selected for erasure to read valid status in-

form ati o n on DQ7 .

Af t er an e ra s e comm an d s e qu en ce i s wri t ten , i f al l se c-

tors selected for erasing are protected, Data# Polling

on D Q 7 is ac ti ve f o r ap pr oxi m at e ly 10 0 µs , th en t he de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the sys tem detects DQ7 has changed fro m the

compleme nt to true dat a, it can read valid data at DQ7–

DQ0 on the

following

read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, Data#

Polling Timings (Durin g Emb edded Algorithms), in the

“AC Characterist ics” sect ion illustrates this.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Dat a# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

22230A-9

Figure 5. Data# Polling Algorithm

20 Am29SL800C
PRELIMINARY
RY/BY#: Read y/Bu sy#
The  RY/BY # is a dedica ted , op en-drai n o utp ut p i n tha t
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device  is actively  erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the de vice is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Tabl e 6 shows the  outpu ts for RY/ BY#. F igures  14,  17
and 18 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Togg le Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mod e.  To gg le B it I m ay be read at any  add re ss , an d is
valid aft er the ri sing  edg e of the fin al W E# pu l se in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
Du r ing  an E m bed de d Pro gram   or  E ra se  a l go r ithm  op-
eration, successive read cycles to any address  cause
DQ6 to toggle  (The syste m may u se either  OE#  or CE#
to control the read cycles). When  the operation is co m-
plete, DQ6 stops toggling.
Af t er an  e ra s e  comm an d s e qu en ce i s  wri t ten ,  i f al l  se c-
tors selected f or erasing are protected, DQ6  toggles f or
approximately 100 µs, then returns to reading array
data . If not  al l s el ec ted  se cto rs  ar e  pro te cted , the E m -
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
prot ected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a s ector is actively erasing or  is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see t he subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approxim ately 1 µs afte r the program
command sequence is written, then returns to reading
array da ta.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Tab le 6 sho ws the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 20 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 21 shows the differences between
DQ 2 an d D Q 6 in gra phi c al  for m.  Se e als o the sub sec -
tion on DQ2: Toggle Bit II.
DQ2: Togg le Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that  is, the Embedded Erase algorithm  is in progress),
or whether that sect or is erase- suspended. Toggle  Bit
II is v alid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE # or CE # read  cycle. 
DQ2 toggles when the system reads at addresses
with in those sect ors that have been selected for era s-
ure. B ut DQ 2 ca nnot  dist ingui sh w hethe r the  sect or is
actively erasing or is erase-suspended. DQ6, by com-
parison,  indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish
whi ch sectors are selected for e rasure.  Thus, bo th sta-
tus bits are required for sector and mode information.
Ref er to Tabl e 6 to compare outputs for DQ2  and  DQ6. 
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. Se e also the DQ6: Toggle Bit I sub section.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical f orm. 
Reading Toggle Bits DQ6/DQ2
Ref er to Figure 6 for the fol lowing discussion. Whenev er
the system initially begins reading toggle bit status, it
must read DQ7–DQ0 at least twi ce i n a row to determine
whether a toggle bit is toggling. Typically, the system
would note and store the value of the toggle bit after the
first read. After the s econd read, the system w ould com-
pare the new value of the toggl e bit w ith  the first. If the
toggle bit is not toggling, the dev ice has  completed the
program or erase operation. The system can read array
data on DQ7–DQ0 on the following read cycle.
However, if after  the initial two re ad cycles, the syste m
deter mines t hat the to ggle bit is s till toggling, t he sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
the n det ermin e again  w hethe r the  t ogg le bit  is  togg lin g,
sin ce the to ggle  bit may have  stop ped tog gling j ust as
DQ5 went high. I f the toggle bit is no longer toggling,
the  device has succes sfully  completed  the program or
erase operation. If it is  still toggling,  th e device did not
completed the operatio n successfully, and the system
must write the reset command to return to reading
array da ta.  

Am29SL800C 21

PRELIMINARY

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle b it and DQ5 throu gh successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

syste m tasks. In this case, the system must start at the

beg i nn ing of t h e a lgo ri thm w h en it re t urns to de te rmi ne

the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ 5 in dic ate s wh ether the pr ogra m or e rase time ha s

ex ceeded a spe cified inter nal pulse count lim it. Under

thes e co ndi tions D Q5 produ ces a “1 .” Th is is a failur e

condition that indicates the prog ram or era se cycle w as

not successfully completed.

The DQ5 failure condition may appear if the system

tries to pr ogram a “1” to a location that is pre viously pro-

gr am med to “ 0.” Onl y an eras e op erati on c an c hange

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “1.”

Und er both th ese c ond itio ns , th e sy stem mu st issu e t he

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chi p erase command.) If additi onal

sectors are selected f or erasure, the entire time-out also

applies after each additional sector erase command.

When the time-out is complete, DQ3 switches from “0” to

“1.” If the time between additional sector erase com-

mands from the system c an be assumed to be less than

50 µs, the system need n ot monitor DQ3. See also the

“Sector Erase Command Sequence” section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing ) o r DQ6 (Toggle Bit I) to en s ur e th e device has ac -

cepted the command sequence, and then read DQ3. If

DQ3 is “1 ”, t he i nt e rnall y c o nt r oll e d er a se cy cl e ha s b e-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

acc e pt ed, t he sys t em so ft w ar e shou l d check the st a tus

of DQ3 prio r to and following each subsequent se ctor

eras e command. If DQ3 is high on the second statu s

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

22230A-10

Figure 6. Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

22 Am29SL800C

PRELIMINARY

Table 6. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a v alid address when reading status inf ormation. Ref er to the appropriate subsection for further details.

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Eras e

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Am29SL800C 23

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Res pect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#,

and RESET# (Note 2) . . . . . . . .–0.5 V to +11.0 V

All other pins (Note 1) . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V

–2.0 V f or periods of up to 20 ns . See Figure 7. Maximum

DC voltage on input or I/O pins is V

+0.5 V. During

voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 8.

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V

to –2.0 V f or periods of up to

20 ns. See Figure 7. Maximum DC input voltage on pin A9

is +11.0 V which may overshoot to 12.5 V for periods up

to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 7. Maximum Negative Overshoo t

Waveform

Figure 8. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industr ial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

VCC Supply Voltages

VCC, all speed options . . . . . . . . . . . .+ 1.8 V to +2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

0.0 V

–0.5 V

20 ns

–2.0 V

22230A-11

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

22230A-12

24 Am29SL800C
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The I
CC
 current listed is typically less than 1 mA/MHz, with OE# at V
IL
. Typical V
CC
 is 2.0 V.
2. The maximum I
CC
 specifications are tested with V
CC 
= V
CC
max.
3. I
CC
 active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
 + 50 ns.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 11.0 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode 5 MHz 5 10
mA
1 MHz 1 3
CE# = VIL, OE# = VIH,
Word Mode 5 MHz 5 10
1 MHz 1 3
ICC2 VCC Active Write Current 
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 25 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 1 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 1 5 µA
ICC5 Automatic Sleep Mode 
(Notes 2, 3) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 15µA
V
IL Input Low Voltage –0.5 0.2 x VCC V
VIH Input High Voltage 0.8 x VCC VCC + 0.3 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V
VOL1 Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.25 V
VOL2 IOL = 100 µA, VCC = VCC min 0.1
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min  0.7 x VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.1
VLKO L ow VCC Lock-Out Voltage 
(Note 4) 1.2 1.5 V

Am29SL800C 25

PRELIMINARY

DC CHARACTERISTICS (Conti nued)

Zero Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Supp ly Current in mA

Time in ns

Note: Addresses are switching at 1 MHz

22230A-13

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

1 2345

F reque ncy in MHz

Sup ply Current in mA

Note: T = 25

22230A-14

Figure 10. Typical ICC1 vs. Frequency

1.8 V

2.2 V

26 Am29SL800C

PRELIMINARY

TEST CONDITIONS Table 7. Test Speci fications

KEY TO SWITCHIN G WAVE FORMS

Device

Under

Test

22230A-15

Fig ur e 11 . Test Se tup

Test Condition 100 120, 150 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–2.0 V

Input timing measurement

reference levels 1.0 V

Output timing measurement

reference levels 1.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

2.0 V

0.0 V 1.0 V 1.0 V OutputMeasurement LevelInput

22230A-16

Figure 12. Input Waveforms and Measureme n t Levels

Am29SL800C 27

PRELIMINARY

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup 100 120 150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 100 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 100 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 100 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 35 50 65 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 50 60 60 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 50 60 60 ns

tOEH Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 30 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

22230A-17

Figure 13. Read O perations Timings

28 Am29SL800C

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (see Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (see Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (see Note) Min 200 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

22230A-18

Figure 14. RESET# Timings

Am29SL800C 29

PRELIMINARY

AC CHARACTERISTICS

Word/ Byte Config uratio n (BYTE#)

Parameter

Description 100 120 150JEDEC Std Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 10 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 50 60 60 ns

tFHQV BYTE# Switching High to Output Active Min 100 120 150 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

22230A-19

Figure 15. BY TE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for t

and t

specifications.

22230A-20

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

30 Am29SL800C

PRELIMINARY

AC CHARACTERISTICS

Erase/Pr ogram Operati on s

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

100 120 150JEDEC Std Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 100 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 50 60 70 ns

tDVWH tDS Data Setup Time Min 50 60 70 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 50 60 70 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 µs

Word Typ 12

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

tVCS VCC Setup Time Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 200 ns

Am29SL800C 31

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

Data

Addresses

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

GHWL

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

BUSY

Notes:

1. PA = program address, PD = program data, D

OUT

is the true data at the program address.

2. Illustration shows device in word mode.

22230A-21

Figure 17. Program Operation Timings

32 Am29SL800C

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

22230A-22

Figure 18. Chip/Sector Erase Operati on Timings

Am29SL800C 33

PRELIMINARY

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

22230A-23

Figure 19. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: V A = Valid address; not required f or DQ6. Illustr ation shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

22230A-24

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

34 Am29SL800C

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unpro tect

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

22230A-25

Figure 21. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

10 V

0 or 1.8 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 1.8 V

22230A-26

Figure 22. Tempo rary Sector Unprotect Timing Diagram

Am29SL800C 35

PRELIMINARY

AC CHARACTERISTICS

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

22230A-27

Figure 23. Sector Protect/Unprotect Timing Diagram

36 Am29SL800C

PRELIMINARY

AC CHARACTERISTICS

Alter nate CE# Controlled Erase/P rogram Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

100 120 150JEDEC Std Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 100 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 50 60 70 ns

tDVEH tDS Data Setup Time Min 50 60 70 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 50 60 70 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation

(Notes 1, 2) Byte Typ 10 µs

Word Typ 12

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

Am29SL800C 37

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, D

OUT

= data written

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

22230A-28

Figure 24. Altern ate CE# Controlled Write Operation Timi ngs

38 Am29SL800C

PRELIMINARY

ERASE AND PROGRAMMING P E RFORM ANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 2.0 V V

, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V

= 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTE RISTICS

Includes all pins except V

. Test conditions: V

= 1.8 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 2 15 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 38 s

Byte Programming Time 10 300 µs

Excludes system level

overhead (Note 5)

Word Programming Time 12 360 µs

Chip Programming Time

(Note 3)

Byte Mode 10 80 s

Word Mode 7 60 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 11.0 V

Input voltage with respect to VSS on all I/O pins –0.5 V VCC + 0.5 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

Am29SL800C 39

PRELIMINARY

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP (measured in mill imeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering

TSR048—48-Pin Re verse TSOP (meas ured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DA101

8-8-94 ae

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48

TSR048

DA104

8-8-94 ae

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

40 Am29SL800C

PRELIMINARY

PHY SICAL DIMENSIONS

FGB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm (measured in millimeters)

5.80

6.20

8.80

9.20

DATUM B

DATUM A

INDEX

0.025

CHAMFER

0.15 MZBM

5.60

BSC

0.40

4.00

BSC

0.08 MZAB

0.10 Z

0.25

0.45

0.80

DETAIL A

0.20 Z

DETAIL A

1.20 MAX

0.40 ± 0.08 (48x) 0.40

16-038-FGB-2

EG137

12-2-97 lv

Am29SL800C 41

PRELIMINARY

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.