Datasheet Please read the Important Notice and Warnings at the end of this document V 2.1
www.infineon.com/gdLowSide 1 of 20 2019-06-13
1ED44176N01F
Single-channel low-side gate driver IC with over-current protection
Features
Over-current detection with positive voltage input
0.5 V over-current threshold with accurate ±5%
tolerance
Single pin for fault output and enable
Programmable fault clear time
Under voltage lockout
CMOS Schmitt-triggered inputs
3.3 V, 5 V and 15 V input logic compatible
Output in phase with input
Separate logic and power ground
2 kV ESD HBM
RoHS compliant
Evaluation board available: EVAL-1ED44176N01F
Potential applications
Digitally controlled PFC
Air conditioner
Home appliances
Industrial applications
General purpose low-side gate driver for single-ended
topologies
Description
The 1ED44176N01F is a low-voltage, power MOSFET and IGBT non-inverting gate driver. Proprietary latch immune CMOS
technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL
output. The output driver features a current buffer stage. The 1ED44176N01F has OCP pin for over current protection
sense and a FAULT status output (Once it is active, EN/FLT pin is internally pulled down.). There is a dedicated pin (FLTC)
to program fault clear time. The EN/FLT needs to be outside pulled up to provide normal operation, pulling EN/FLT low
disable the driver. Internal circuitry on VCC pin provides an under voltage lockout protection that holds output low until
Vcc supply voltage is within operating range.
Vin
Vout
Gnd
Vdd
I/O1
VCC
µC
I/O2 VSS
OUT
OCP
FLTC
COM
VCC
IN
1ED44176N01F
EN/FLT
Figure 1 Typical application
Ordering information
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC JESD47/22 and J-STD-020.
Product type
Package
Standard pack
Orderable part number
Form
Quantity
1ED44176N01F
PG-DSO-8
Tape and Reel
2500
1ED44176N01FXUMA1
(Refer to lead assignments for correct
pin configuration). This diagram show
electrical connections only. Please refer
to our application notes and design tips
for proper circuit board layout.
Datasheet 2 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
Table of contents
Features ........................................................................................................................................ 1
Table of contents ............................................................................................................................ 2
1 Block diagram ........................................................................................................................ 3
2 Pin configuration and functionality .......................................................................................... 4
2.1 Pin configuration ..................................................................................................................................... 4
2.2 Input/output logic truth table ................................................................................................................ 5
3 Qualification information ........................................................................................................ 6
4 Electrical parameters ............................................................................................................. 7
4.1 Absolute maximum ratings ..................................................................................................................... 7
4.2 Recommended operating conditions..................................................................................................... 7
4.3 Static electrical characteristics .............................................................................................................. 8
4.4 Dynamic electrical characteristics.......................................................................................................... 8
5 Application information and additional details .......................................................................... 9
5.1 IGBT/MOSFET gate driver........................................................................................................................ 9
5.2 Switching and timing relationships ........................................................................................................ 9
5.3 Input logic compatibility ....................................................................................................................... 10
5.4 Undervoltage lockout (Vcc) .................................................................................................................. 10
5.5 Over current protection (OCP) .............................................................................................................. 11
5.6 Fault reporting and programmable fault clear timer .......................................................................... 13
5.7 Enable input .......................................................................................................................................... 14
6 Package outline .................................................................................................................... 15
7 Tape and reel details: PG-DSO8 ............................................................................................... 16
8 Part marking information ...................................................................................................... 17
9 Similar products ................................................................................................................... 18
10 Related documents ............................................................................................................... 18
Revision history............................................................................................................................. 19
Datasheet 3 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
1 Block diagram
15
7
1
8
4
COM
VCC
IN
FLTC
OUT
OCP BLK
OCP
VSS/COM
level shift
VOCT H
2
VFLTCTH
UVLO
EN/FLT
3
6
VSS
IFLTC
QFLT
Q
S
R
UVLO &
Filter
PWM
disable
logic
Figure 2 Block diagram
Datasheet 4 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
2 Pin configuration and functionality
2.1 Pin configuration
Table 1 Pin configuration
1
3 6
OUT
IN
VSS
2
8
7
COM
4 5
VCC
OCP
FLTC
EN/FLT
Figure 3 PG-DSO-8-70 (top view)
Pin no.
Name
Function
1
OCP
Current sense input
2
FLTC Fault clear time program input
3 EN/FLT
Enable and fault reporting pin, two functions:
1. Logic input to enable I/O functionality. I/O logic functions when ENABLE is high and
enable function is not latched.
2. Fault reporting function like over-current or undervoltage lockout, this pin has
negative logic and an open-drain output.
4
IN
Logic input for gate driver output (OUT), in phase
5
VCC
Supply voltage
6
VSS Logic ground
7
OUT Gate drive output
8
COM Gate drive return
Datasheet 5 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
2.2 Input/output logic truth table
Table 2 Input/output logic truth table
1) UVLO “L” state is under-voltage protection.
2) OCP “H” state is over-current protection.
3) EN/FLT “H” state is EN/FLT pin externally pulling up and internally pull down MOSFET (QFLT) is off.
(See block diagram.)
IN
UVLO
1)
OCP
2)
/
3)
OUT
Note
L
H
L
H
L
OUT = L
H
H
L
H
H
OUT = H
X L X L L
OUT = L,
EN/FLT =
L, (UVLO protection will disable I/O
logic until EN/FLT returns to high level.)
X H H L L
OUT = L,
EN/FLT
= L, (Over current protection will
disable I/O logic until EN/FLT returns to high level.)
X H X L L
OUT = L (Externally pull down
EN/FLT
pin will disable
I/O logic until EN/FLT returns to high level.)
Datasheet 6 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
3 Qualification information
Qualification level
Industrial
1)
Comments: This family of ICs has passed JEDEC’s Industrial
qualification.
Consumer qualification level is granted by
extension of the higher Industrial level.
Moisture sensitivity level
MSL3 2) 260°C
(per JEDEC standard J-STD-020)
ESD
Charged device model
1000 V (Class C3)
(per ANSI/ESDA/JEDEC standard JS-002)
Human body model
Class 2
(per ANSI/ESDA/JEDEC standard JS-001)
IC latch-up test
Class II, Level A
(per JESD78)
RoHS compliant
Yes
1)
Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon
sales representative for further information.
2)
Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales
representative for further information.
Datasheet 7 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
4 Electrical parameters
4.1 Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. The device may not
function or not be operable above the recommended operating conditions and stressing the parts to these levels is not
recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect
device reliability. All voltage parameters are absolute voltages referenced to VSS. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Table 3 Absolute maximum ratings
4.2 Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to VSS unless otherwise stated in the table.
Table 4 Recommended operating conditions
Symbol
Definition
Min
Max
Units
VCC
Fixed supply voltage
0.5
25
V
VO
Output voltage (OUT)
COM - 0.5
VCC + 0.5
VOCP
Voltage at current sense pin (OCP)
0.5
VCC +0.5
V
EN/FLT
Voltage at enable and fault reporting pin (EN/FLT)
0.5
VCC + 0.5
VFLTC
Voltage at fault clear time program pin ( FLTC)
0.5
VCC + 0.5
VIN
Logic input voltage ( IN )
0.5
VCC + 0.5
COM
Driver return voltage
– 5
VCC + 0.5
PD
Package power dissipation @ TA ≤ 25°C
PG-DSO-8
0.625
W
RthJA
Thermal resistance, junction to ambient
200
°C/W
TJ
Junction temperature
40
150
°C
TS
Storage temperature
55
150
TL
Lead temperature (soldering, 10 seconds)
300
Symbol
Definition Min Max Units
VCC
Fixed supply voltage
12.7
20
V
VO
Output voltage
COM
VCC
VOCP
Voltage at current sense pin (OCP)
0
VCC
V
EN/FLT
Voltage at enable and fault reporting pin (EN/FLT)
0
VCC
VFLTC
Voltage at fault clear time program pin ( FLTC)
0
VCC
VIN
Logic input voltage ( IN )
0
VCC
COM
Logic ground with respect to VSS
– 5
+5
TA
Ambient temperature
40
125
°C
Datasheet 8 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
4.3 Static electrical characteristics
VCC = 15 V, VSS=COM, TA = 25°C unless otherwise specified. The VIN, VEN, VFLTCTH, VOCTH, IIN, I FLT , and IFLTC parameters are
referenced to VSS and are applicable to input leads: IN,EN/FLT, FLTC and OCP. The VO and IO parameters are referenced to
COM and are applicable to the output lead: OUT.
Table 5 Static electrical characteristics
4.4 Dynamic electrical characteristics
VCC = 15 V, TA = 25°C, and CL = 1000 pF unless otherwise specified.
Table 6 Dynamic electrical characteristics
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
VCCUV+
Vcc supply undervoltage positive going threshold
11.2
11.9
12.7
V
VCCUV-
Vcc supply undervoltage negative going threshold
10.7
11.4
12.2
VCCUVH
Vcc supply undervoltage lockout hysteresis
0.5
VINL
Logic “0” input voltage (OUT = LO)
0.8
1
1.2
VINH
Logic “1” input voltage (OUT = HI)
1.7
2.1
2.5
VENL
Logic “0” disable voltage
0.8
1
1.2
VENH
Logic “1” enable voltage
1.7
2.1
2.5
VFLTCTH
Fault clear threshold Voltage
2.4
2.7
3
VOH
High level output voltage, VCC -VOUT
0.05
0.2
IO = 2 mA
VOL
Low level output voltage, VOUT
0.02
0.1
IO = 2 mA
VOCTH
Current limit threshold voltage
475
500
525
mV
IIN+
Logic “1” input bias current IN pin
35
50
70
µA
VIN = 5 V
IIN-
Logic “0” input bias current IN pin
-5
VIN = 0 V
IQCC
Quiescent VCC supply current
750
VIN = 0 V or 5 V
IO+ Output sourcing short circuit pulsed current 0.56 0.8
A
V
O
= 0 V
PW ≤ 10 µs
IO- Output sinking short circuit pulsed current 1.23 1.75
V
O
= 15 V
PW ≤ 10 µs
I
FLT
EN/FLT pull down sinking current
20
mA
V
EN/FLT
= 0.4 V
IFLTC
Fault clear sourcing current
-40
-25
-15
µA
VFLTC = 0 V
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
ton
Turn-on propagation delay
50
95
ns
Figure 6
VIN pulse = 5 V
toff
Turn-off propagation delay
50
95
tr
Turn-on rise time
50
80
tf
Turn-off fall time
25
35
tEN
Enable propagation delay
50
95
Figure 14
V
EN
pulse = 5 V
tDISA
Disable propagation delay
50
95
tOCPDEL
Over current protection propagation delay
380
470
Figure 10 Figure 11
REN =10kΩ t o Vcc
VOCP pulse = 1 V
tOCPFLT OCP to low level EN/FLT signal delay 350 440
tFLTC FAULT clear time 75 110 180 µs Figure 10 Figure 11
CFLTC =1nF to VSS
tBLK Over current protection blanking time 100 180 250 ns
Figure 11
RFLT =0Ω, C
FLT = NC
VOCP pulse = 1V
tvCCUV
VCC supply UVLO filter time
2
µs
Figure 8
Datasheet 9 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
5 Application information and additional details
Information regarding the following topics is included as subsections within this section of the datasheet.
IGBT/MOSFET gate driver
Switching and timing relationships
Input logic compatibility
Undervoltage lockout protection
Over current protection (OCP)
Fault reporting and programmable fault clear timer
Enable input
See the 1ED44176N01F application note AN2018-03 Low - Side Driver with Over Current Protection and Fault/Enable for
interface circuit examples and recommended layout guidelines.
5.1 IGBT/MOSFET gate driver
The 1ED44176N01F is designed to drive MOSFET or IGBT power devices. Figure 4 and Figure 5 illustrate several parameters
associated with the gate driver functionality of the driver. The output current of the driver, used to drive the gate of the
power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VOUT.
Figure 4
Gate output sourcing current
Figure 5
Gate output sinking current
5.2 Switching and timing relationships
The relationships between the input and output signals of the 1ED44176N01F are illustrated below in Figure 6. From the
figure, we can see the definitions of several timing parameters (i.e. ton, toff, tr, and tf) associated with this device.
50% 50%
10%
90%
10%
90%
ton trtoff tf
OUT
IN
Figure 6 Switching time waveforms
Datasheet 10 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
5.3 Input logic compatibility
The input of this IC is compatible with standard CMOS and TTL outputs. The 1ED44176N01F has been designed to be
compatible with 3.3 V, 5 V and 15 V logic-level signals. The input high threshold (VINH) is typ. 2.1 V and low threshold (VINL) is
typ. 1 V. Input hysteresis offers enhanced noise immunity. The 1ED44176N01F includes an important feature: wherein,
whenever the input pin is in a floating condition, the output is held in the low state. This is achieved using GND pull-down
resistors on the input pin. Figure 7 illustrates an input signal to the 1ED44176N01F, its input threshold values, and the logic
state of the IC as a result of the input signal.
Figure 7 IN input thresholds
5.4 Undervoltage lockout (Vcc)
The 1ED44176N01F has an internal UVLO protection feature on the VCC pin supply circuit blocks.Upon power-up, if the
VCC voltage fails to reach the VCCUV+ threshold, the driver cannot turn on. Additionally, if the VCC voltage decreases below
the VCCUV- threshold and the VCC bias voltage remains lower than the VCCUV- threshold exceeding UVLO filter time (tVCCUV)
during operation, the undervoltage lockout circuitry will recognize a fault condition and shut-down the drive output. The
EN/FLT will then transit to the low state to inform the controller of the fault condition, regardless of the status of the IN
input pin. The tVCCUV about 2μs helps t o suppress noise from the UVLO circuit, so that negative-going voltage spikes at the
supply pin will avoid parasitic UVLO events.
When VCC is higher than VCCUV+ and longer than tFLTC, EN/FLT becomes high and the OUT will follow the input signal IN.
(Figure 8 shows the UVLO time is shorter than tFLTC.)
IN
OUT
VCC
FLTC
EN/FLT
VCCUV+
VCCUV-
tVCCUV
VFLTCTH
tFLTC
Figure 8 Vcc under voltage protection waveform definitions one
Datasheet 11 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
Once EN/FLT enters UVLO mode, EN/FLT keeps low until tFLTC is over and VCC supply voltage higher than VCCUV+. (Figure 9
shows the UVLO time is longer than tFLTC.)
IN
OUT
VCC
FLTC
EN/FLT
V
CCUV+
V
CCUV-
tV
CCUV
V
FLTCTH
t
FLTC
Figure 9 Vcc under voltage protection waveform definitions two
5.5 Over current protection (OCP)
The 1ED44176N01F has a function of over current protection with a threshold VOCTH at the OCP pin. The voltage at this pin is
the voltage across the current sense resistor. To avoid false tripping due to the fast high current switch on transient that
occurs at the switch on of MOSFET or IGBT resulting from the circuit parasitic capacitors, there is blanking interval which
disables over current detection for the period of tBLK. (An additional RC filter is recommended, if the internal tBLK is not
sufficient to suppress the noise.) After tBLK and the voltage of OCP pin is over VOCTH, the 1ED44176N01F causes fault logic to
initiate a fault shutdown sequence. This sequence starts with the generation of a fault signal. The internal MOSFET QFLT is
turned on and EN/FLT pin is pulled down.
At the same time the 1ED44176N01F terminates the present cycle, and the gate output is immediately pulled down with
internal propagation delay (tOCPDEL), see the Figure 10 and Figure 11.
Figure 10 is the diagram of 1ED44176N01F in Boost application. And Figure 11 is the typical waveforms of the application.
If EN/FLT pin enters over current protection mode, EN/FLT pin keeps low until fault clear time is over and OCP terminal
voltage lower than over current threshold voltage.
Figure 11 shows the OCP time is shorter than tFLTC. Figure 12 shows the OCP time is longer than tFLTC.
Datasheet 12 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
Note: If OCP fault condition is removed and the time is longer than fault clear time (tFLTC), the internal pull down MOSFET
QFLT of EN/FLT is released and EN/FLT will be pull up again with Vdd, then the OUT will follow the input signal IN.
R
FLT
C
FLT
C
FLTC
Vin
Gnd
Vdd
I/O1
VCC
µC
I/O2
VSS
OUT
OCP
FLTC
COM
VCC
IN
1ED44176N01F
EN/FLT
Vout
Figure 10 1ED44176N01F in Boost application
IN
OCP
50%
t
OCPDEL
Q
FLT
off
Q
FLT
on
50%
OUT
t
OCPFLT
EN/FLT
FLTC
V
OCTH
V
FLT CTH
t
FLTC
Pulse < t
BLK
Figure 11 OCP fault detection and fault clear waveforms one
Datasheet 13 of 20 V 2.1
www.infineon.com/gdLowSide 2019-06-13
1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
IN
OCP
50%
tOCPDEL
Q
FLT
off
Q
FLT
on
50%
OUT
tOCPFLT
EN/FLT
FLTC
VOCTH
VFLTC TH
tFLTC
Pulse < tBLK
Figure 12 OCP fault detection and fault clear waveforms two
5.6 Fault reporting and programmable fault clear timer
The 1ED44176N01F provides a dedicated fault reporting output pin (EN/FLT ) and a programmable fault clear time pin
(FLTC). There are two situations which would cause the driver to report a fault via the EN/FLT pin. The first is an under
voltage condition of VCC and the second is if the OCP pin recognizes a fault. Once the fault condition occurs, the EN/FLT
pin is internally pulled down to VSS. The EN/FLT output stays in the low state until the fault condition has been removed
and the fault clear timer expires; once the fault clear timer expires, the voltage on the EN/FLT pin will return to its external
pull-up voltage.
The length of the fault clear time period (tFLTC) is programmed by external capacitor which connected between FLTC and
VSS (CFLTC). See Figure 10.
The length of the fault clear time period can be determined by using the equation below.
tFLTC= CFLTC*VFLTCTH/ IFLTC
Note: If the OCP last time is longer than tFLTC, the EN/FLT output keeps low until the OCP input voltage lower than OCP
threshold voltage. See Figure 12.
Datasheet 14 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
5.7 Enable input
1ED44176N01F provides an enable functionality that allows to shutdown or to enable the output. When EN/FLT is pulled
up (the enable voltage is higher than VENH) the output is able to operate normally, pulling EN/FLT low (the enable voltage is
lower than VENL) the output is disable. The enable function is not latched. The relationships between the input, output and
enable signals of the 1ED44176N01F are illustrated below in Figure 13 - Figure 15. From these figures, we can see the
definitions of several timing parameters and threshold voltages (i.e. tDISA, tEN, VENH and VENL) associated with this device.
IN
EN/FLT
OUT
OUT
50%
50%
t
EN
t
DISA
VEN
90%
10%
IN
High
Figure 13
Input/output/enable pins timing diagram
Figure 14
EN pin switching time waveform
Figure 15 EN input thresholds
Datasheet 15 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
6 Package outline
Figure 16 Package outline
Datasheet 16 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
7 Tape and reel details: PG-DSO8
Figure 17 Tape and reel details
CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C11.70 12.30 0.46 0.484
D5.45 5.55 0.214 0.218
E6.30 6.50 0.248 0.255
F5.10 5.30 0.200 0.208
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E98.00 102.00 3.858 4.015
Fn/a 18.40 n/a 0.724
G14.50 17.10 0.570 0.673
H12.40 14.40 0.488 0.566
Metric
Imperial
Metric
Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
Datasheet 17 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
8 Part marking information
1D44176
Part number
Infineon logo
Pin 1
identifier
Date code
H YYWW
(may vary)
Front Side
Back Side
Assembly
site code
X
XXXX
XXXX
XXX
Lot code
Figure 18 Part marking information
Datasheet 18 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
9 Similar products
Channels
Typ.
gate
drive
(Io+/Io-)
Part
number
Max
supply
voltage
UVLO
(on/off)
Typ.
prop.
delay
(on/off)
Logic Package
options
A
V
V
ns
1
0.3 / 0.5 IR44252L 20 5 / 4.15 50 / 50 Single non-inverting channel
Dual OUT pins
SOT23-5L
1.5 / 1.5
IRS44273L 25 10.2 / 9.2 50 / 50 Single non-inverting channel
Dual OUT pins
SOT23-5L
IR44273L 20 5 / 4.15 50 / 50 Single non-inverting channel
Dual OUT pins
SOT23-5L
IR44272L 20 5 / 4.15 50 / 50 Single non-inverting channel
ENABLE
SOT23-5L
2
2.3 / 3.3
IRS4426S 25 50 / 50 Dual inverting channels SOIC-8L
IRS44262S 20 10.2 / 9.2 50 / 50 Dual inverting channels SOIC-8L
IRS4427S 25 50 / 50 Dual non-inverting channels SOIC-8L
IRS4428S 25 50 / 50 Single inverting channel
Single non-inverting channel
SOIC-8L
10 Related documents
1. AN2018-03 Low - Side Driver with Over Current Protection and Fault/Enable
2. AN2018-11 1ED44176N01F evaluation board
Datasheet 19 of 20 V 2.1
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1ED44176N01F
Single
-channel low-side gate driver IC with over-current protection and fault/enable
Revision history
Document
version
Date of release Description of changes
2.0 2018-06-27 Create the document V 2.0
2.1
2019-06-13
Optimize parameter in table 6
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
Document reference
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized representatives of Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
Edition 2019-06-13
Z8F62869814
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