Document No. 70-0246-03 │www.psemi.com
Page 1 of 9
©2008 Peregrine Semiconductor Corp. All rights reserved.
RF1 RF2
CTRLLS
RFC
50Ω50ΩCMOS
Control
Driver
ESD ESD
16-lead 3x3 mm QFN
Figure 2. Package Type
The PE42552 RF Switch is designed for use in Test/ATE,
cellular and other wireless applications. This broadband general
purpose switch maintains excellent RF performance and
linearity from DC through 7500 MHz. The PE42552 integrates
on-board CMOS control logic driven by a single-pin, low voltage
CMOS control input. It also has a logic select pin which enables
changing the logic definition of the control pin. Additional
features include a novel user defined logic table, enabled by the
on-board CMOS circuitry. The PE42552 also exhibits
outstanding isolation of 44 dB at 7500 MHz, fast settling time,
and is offered in a tiny 3x3 mm QFN package.
The PE42552 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance of
GaAs with the economy and integration of conventional CMOS.
Product Specification
SPDT UltraCMOS™ RF Switch
DC - 7500 MHz
Product Description
Figure 1. Functional Diagram
PE42552
Features
• HaRP™-Technology-Enhanced
• Eliminates Gate and Phase Lag
• No insertion loss or phase drift
• Fast settling time
• High linearity: 65 dBm IIP3
• Low insertion loss: 0.65 dB at 3.0 GHz,
0.85 dB at 6.0 GHz, 1.0 at 7.5 GHz
• High isolation of 47 dB at 3.0 GHz,
44 dB at 7.5 GHz
• 1 dB compression point: +34.5 dBm typ.
• Logic Select pin to invert logic control
• High ESD: 1000 V HBM
• Absorptive switch design
• Standard 3x3 mm QFN package
Table 1. Target Electrical Specifications Temp = 25°C, VDD = 3.3V, VSS = 0V / -3.3V
Parameter Conditions Min Typical Max Units
Operation Frequency MHz 9 kHz 7.5 GHz
Insertion Loss
9 KHz
3000 MHz
6000 MHz
7500 MHz
0.6
0.65
0.85
1.0
0.7
0.8
1.0
1.22
dB
dB
dB
dB
Isolation – RF1 to RF2 3000 MHz
6000 MHz
7500 MHz
45
32
25
47
34
28 dB
dB
dB
Isolation – RFC to RFX 3000 MHz
6000 MHz
7500 MHz
44
49
37
47
55
44 dB
dB
dB
Return Loss 3000 MHz
6000 MHz
7500 MHz 20
25
15 dB
dB
dB
Settling Time 50% CTRL to 0.05 dB final value (-40 to +85 °C) Rising Edge
50% CTRL to 0.05 dB final value (-40 to +85 °C) Falling Edge 9
15 11
45
Switching Time 50% CTRL to 90% or 10% of final value (-40 to +85 °C) 5 7 µs
Input 1 dB Compression 800 MHz
7500 MHz 32
34.5
34 dBm
dBm
Input IP3 7500 MHz 65 dBm
Input IP2 7500 MHz 100 dBm
µs
µs
Product Specification
PE42552
Page 2 of 9
©2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
Table 2. Pin Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this de vice contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Figure 3. Pin Configuration (Top View)
Pin No. Pin Name Description
2 RF1 RF Port 1
1, 3, 4, 5, 6,
8, 9, 10, 12 GND Ground
7 RFC RF Common
11 RF2 RF Port 2
13 VSS Negative supply voltage or GND
connection (Note 1)
14 CTRL CMOS level:
15 LS
Logic Select - Used to determine
the definition for the CTRL pin (see
Table 5)
16 VDD Nominal 3.3 V supply connection
Table 5. Control Logic Truth Table
GND
GND
RFC
GND
GND
RF1
GND
GND GND
GND
RF2
GND
Vss
CTRL
LS
Vdd
1
16
15
14
13
12
11
10
9
5
6
7
8
2
3
4
Exceeding absolut e maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input except for
CTRL and LS inputs -0.3 VDD+
0.3 V
VCTRL Voltage on CTRL input 4.0 V
VLS Voltage on LS input 4.0 V
TST Storage temperature range -65 150 °C
PIN Input Power:
9 kHz ≤ 1 MHz
1 MHz ≤ 7.5 GHz
fig. 4,5
30
dBm
dBm
VESD ESD voltage (HBM)1
ESD voltage (Machine Model) 1000
100 V
V
Table 3. Operating Ranges
Parameter Min Typ Max Units
VDD Positive Power Supply Voltage 3.0 3.3 3.6 V
VSS Negative Power Supply Voltage
(external power supply used) -3.6 -3.3 -3.0 V
IDD Power Supply Current
(VSS = 0V, Temp = +85 °C) 15 120 µA
Control Voltage High 0.7xVDD V
Control Voltage Low 0.3xVDD V
RF Power In1(PIN): 9 kHz ≤ 1 MHz
1 MHz ≤ 7.5 GHz
fig. 4,5
30
dBm
dBm
VSS Negative Power Supply Voltage
(internal power supply used) -0.1 0.0 0.0 V
ISS Negative Supply
(VSS = -VDD, Temp = 25 °C) -10 -40 µA
TOP Operating temperature range -40 25 85 °C
Note: 1. Please consult low frequency graphs on page 3 for
recommended operating power level.
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE42552 in
the 16-lead 3x3mm QFN packag e is MSL1.
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
Note: 1. Use VSS (pin 13, VSS = -VDD) to bypass and disable
internal negative voltage generator. Connect VSS (pin 13) to GND
(VSS = 0V) to enable internal negative voltage generator.
Switching Frequency
The PE42552 has a maximum 25 kHz switching rate
when the internal negative voltage gen erator is used
(pin 13=GND). The rate at which the PE4255 2 can be
switched is only limited to the switching time (Table 1) if
an external negative supply is provided at
(pin13=VSS).
LS CTRL RFC-RF1 RFC-RF2
0 0 off on
0 1 on off
1 0 on off
1 1 off on
Spurious Performance
The typical spurious performance of the PE42552 is
-116 dBm when VSS=0V (pin 13 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
Product Specification
PE42552
Page 3 of 9
Document No. 70-0246-03 │www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved.
-12
-10
-8
-6
-4
-2
0
2
4
6
8
2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Vdd (V)
Input Power (dBm)
Upper Power Limit
0
5
10
15
20
25
30
1 10 100 1000
Freq (kHz)
Operating Power Offset (dB)
Figure 5 shows how the power limit in Figure 4 will
increase with frequency. As the frequency increases,
the contours and Maximum Power Limit Curve will
increase with t he increase in power handling shown on
the curve.
Figure 4. Maximum Operating Power Limit
vs. Vdd and Input Power @ 9 KHz Figure 5. Operating Power Offset vs.
Frequency (Normalized to 9kHz)
Figure 4 provides guidelines of how to adjust the Vdd
and input Power to the 42552 device. The upper limit
curve represents the maximum Input Power vs Vdd
recommended for this part.
To allow for sustained operation under any load VSWR condition,
max power should be kept 6dB lower than max power in 50 Ohm.
Power Handling Examples
Example 1: Maximum power handling at 100kHz, Z=50
ohms, VSWR 1:1, and Vdd=3V
• The power handling offset for 100kHz fro m Fig. 5 is
10dB
• The max power handling at Vdd = 3V is 5.5dB from
Fig. 4
• Derate power under mismatch conditions
• Total maximum power handling for this example is
10dB + 5.5dB = 15.5dBm
Low Frequency Power Handling: ZL = 50Ω
Product Specification
PE42552
Page 4 of 9
©2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0123456789
Frequency [GHz]
Insertion Loss [-dB]
3.0 V
3.3 V
3.6 V
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0123456789
Frequency [GHz]
Insertion Loss [-dB]
RF1 Path
RF2 Path
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0123456789
Frequency [GHz]
Isolation [-dB]
+25deg C
+85deg C
-40deg C
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0123456789
Frequency [GHz]
Isolation [-dB]
3.0 V
3.3 V
3.6 V
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0123456789
Frequency [GHz]
Isolation [-dB]
+25deg C
+85deg C
-40deg C
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0123456789
Frequency [GHz]
Insertion Loss [-dB]
+25deg C
+85deg C
-40deg C
Figure 9. Isolation: Active Port to
Isolated Port @ 3.3 V
Figure 8. Insertion Loss: RFX @ 25 °C
Figure 6. Nominal Insertion Loss: RF1, RF2 Figure 7. Insertion Loss: RFX @ 3.3 V
Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated
Figure 10. Isolation: Active Port to
Isolated Port @ 25 °C Figure 11. Isolation: RFC to Isolated Port @ 3.3 V
Product Specification
PE42552
Page 5 of 9
Document No. 70-0246-03 │www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved.
0
10
20
30
40
50
60
70
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
Frequency [Hz]
IIP3 [dBm]
3.0 V
3.3 V
3.6 V
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0123456789
Frequency [GHz]
Isolation [-dB]
3.0 V
3.3 V
3.6 V
-35
-30
-25
-20
-15
-10
-5
0
0123456789
Frequency [GHz]
Return Loss [-dB]
3.0 V
3.3 V
3.6 V
-30
-25
-20
-15
-10
-5
0
0123456789
Frequency [GHz]
Return Loss [-dB]
+25deg C
+85deg C
-40deg C
Figure 14. Return Loss at active port @ 25 °C Figure 15. Return Loss at active port @ 3.3 V
Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated
Figure 12. Isolation: RFC to Isolated Port @ 25 °C Figure 13. IIP3: Third Order Distortion from
10kHz - 7.5GHz
Product Specification
PE42552
Page 6 of 9
©2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
Through Line
L1 WAS INDUCTOR
1
2
J5
142-0761-881/891
1
2
J1
142-0761-881/891
1
2
J3
142-0761-881/891
1
13
35
57
7
22
44
66
88
10 10
12 12
14 14 13
13
9
911
11
J4
HEADER 14
1
2
J2
142-0761-881/891
C1
22pF
R1 DNI
C2
22pF
R2 DNI
C3
22pF
1
2
J6
142-0761-881/891
R3
DNI
C4
68pF
9GND
10 GND
11 RF2
12 GND
13 VSS
14 CTRL
15 LS
16 VDD
1
GND
3
GND
2
RF1
4
GND
5
GND
6
GND
8
GND
7
RFC
U1
QFN50P3X3-16P
R4 0 OHM
L1
0 OHM
LS
RF2
CTRL
VDD
VSS
RF1
RFC
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42552. The
RF common port is connected through a 50 Ω
transmission line via the top SMA connector, J1.
RF1, RF2, RF3 and RF4 are connected through
50 Ω transmission lines via SMA connectors J3,
J5, J2 and J4, respectively. A through 50 Ω
transmission is available via SMA connectors J6
and J7. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The evaluation kit board is constructed of four
metal layers. The dual clad top RF layer is
Rogers RO4003 material with an 8 mil RF core
and er = 3.55. The other two dielectric layers are
FR4 for DC control and overall board strength with
an cumulative board thickness of 60 mils. The RF
transmission lines were designed using a
Grounded co-planar waveguide with a linewidth of
15 mils and gap of 10 mils.
Figure 16. Evaluation Board Layouts
Figure 17. Evaluation Board Schematic
Peregrine Specification 102/0404
Peregrine Specification 101/0334
Product Specification
PE42552
Page 7 of 9
Document No. 70-0246-03 │www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved.
16-lead 3x3 mm QFN
Figure 18. Package Drawing (mm)
QFN 3x3 mm
A MAX 0.800
NOM 0.750
MIN 0.700
Product Specification
PE42552
Page 8 of 9
©2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
16-lead 3x3 mm QFN
Figure 19. Tape and Reel Specifications
Table 6. Ordering Information
Tape Feed Direction
Order Code Part Marking Description Package Shipping Method
PE42552MLIB 42552 PE42552G-16QFN 3x3mm-75A Green 16-lead 3x3mm QFN Bulk or tape cut from reel
PE42552MLIB-Z 42552 PE42552G-16QFN 3x3mm-3000C Green 16-lead 3x3mm QFN 3000 units / T&R
EK42552-02 PE42552-EK PE42552-16QFN 3x3mm-EK Evaluation Kit 1 / Box
Device Orientation in Tape
Top of
Device
Pin 1
Product Specification
PE42552
Page 9 of 9
Document No. 70-0246-03 │www.psemi.com ©2008 Peregrine Semiconductor Corp. All rights reserved.
Sales Offices
The Americas
Peregrine Semiconductor Corporation
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preli m inary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is beli eved to be reliable.
However, Peregrine assumes no li ability for the use of this
information. Use shall be entirely at the user ’s own risk.
No patent rights or licenses to any circuits describe d in this
data sheet are implied or gran ted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to supp ort or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no li ability for damages, including
consequential or incidental da mages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Hi-Rel and Defense Products
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Tel: 858-731-9453
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