0.1 GHz to 20 GHz
GaAs, Nonreflective, SP4T Switch
Data Sheet
HMC641ALP4E
Rev. B Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Broadband frequency range: 0.1 GHz to 20 GHz
Nonreflective 50 Ω design
Low insertion loss: 3.0 dB at 20 GHz
High isolation: 40 dB at 20 GHz
High input linearity at 250 MHz to 20 GHz
P1dB: 24 dBm typical
IP3: 41 dBm typical
High power handling
26.5 dBm through path
23 dBm terminated path
Integrated 2 to 4 line decoder
24-lead, 4 mm × 4 mm LFCSP package
ESD rating: 250 V (Class 1A)
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
NIC
NIC = NOT INT E RNALLY CONNECTED
GND
RFC
GND
NIC
NIC NIC
VSS
CTRLB
CTRLA
GND
NIC
GND
RF4
GND
GND
RF3
GND GND
RF2
GND
GND
RF1
GND
50Ω
50Ω
2:4 DECODER
HMC641ALP4E
PACKAGE
BASE
GND
16094-001
1
2
3
4
5
6
24 23 22 21 20 19
78 9 10 11 12
18
17
16
15
14
13
Figure 1.
GENERAL DESCRIPTION
The HMC641ALP4E is a general-purpose, nonreflective, single-
pole, four-throw (SP4T) switch manufactured using a gallium
arsenide (GaAs) process. This switch offers high isolation, low
insertion loss, and on-chip termination of the isolated ports.
The switch operates with a negative supply voltage range of −5 V to
−3 V and requires two negative logic control voltages.
The HMC641ALP4E includes an on-chip, binary 2 to 4 line
decoder that provides logic control from two logic input lines.
The HMC641ALP4E comes in a 4 mm × 4 mm, 24-lead LFCSP
package and operates from 0.1 GHz to 20 GHz.
HMC641ALP4E Data Sheet
Rev. B | Page 2 of 11
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Power Derating Curves ................................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics .....................................................................5
Typical Performance Charcteristics ................................................6
Insertion Loss, Return Loss, and Isolation ................................6
Input Power Compression and IP3 .............................................7
Theory of Operation .........................................................................8
Application Information ...................................................................9
Evaluation Board ...........................................................................9
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
8/2018—Rev. A to Rev. B
Changes to Insertion Loss, Between RFC and RF1 to RF4 (On)
Parameter, Table 1 ............................................................................. 3
Changed Reflow (MSL1 Rating) to Reflow, Table 2 ..................... 4
Deleted Note 2, Table 2; Renumbered Sequentially ..................... 4
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
7/2017—Rev. 00.1013 to Rev. A
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
Changes to Features Section, Applications Section, General
Description Section, and Figure 1 .................................................. 1
Deleted Truth Table, Bias Voltage and Current Table, and
TTL/CMOS Control Voltages Table .............................................. 3
Changes to Table 1 ............................................................................ 3
Added Power Derating Curves Section and Figure 2;
Renumbered Sequentially ................................................................ 4
Changes to Table 2 ............................................................................. 4
Added Figure 4 ................................................................................... 5
Changes to Figure 3, Table 3, and Figure 5 .................................... 5
Deleted GND Interface Schematic .................................................. 5
Changes to Typical Performance Characteristics Section ........... 6
Added Theory of Operation Section and Table 4; Renumbered
Sequentially ........................................................................................ 8
Added Applications Information Section and Figure 14 ............. 9
Changes to Table 5 ............................................................................. 9
Added Figure 16 ............................................................................. 10
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
Data Sheet HMC641ALP4E
Rev. B | Page 3 of 11
SPECIFICATIONS
VSS = −3 V or −5 V, VCTRL = 0 V or VSS, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 0.1 20 GHz
INSERTION LOSS
Between RFC and RF1 to RF4 (On) 0.1 GHz to 12 GHz 2.0 3.2 dB
12 GHz to 20 GHz 3.0 4.2 dB
ISOLATION
Between RFC and RF1 to RF4 (Off) 0.1 GHz to 12 GHz 30 42 dB
12 GHz to 20 GHz 30 40 dB
RETURN LOSS
RFC and RF1 to RF4 (On) 0.1 GHz to 12 GHz 18 dB
12 GHz to 20 GHz
17
RF1 to RF4 (Off) 0.1 GHz to 20 GHz 13 dB
SWITCHING
Rise and Fall Time
t
RISE
, t
FALL
10% to 90% of radio frequency (RF)
output
30
ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 100 ns
INPUT LINEARITY 1 250 MHz to 20 GHz
1 dB Power Compression P1dB VSS = −5 V 20 24 dBm
VSS = −3 V 22 dBm
Third-Order Intercept IP3 10 dBm per tone, 1 MHz spacing
VSS = −5 V 41 dBm
V
SS
= −3 V
41
dBm
SUPPLY VSS pin
Voltage VSS −5 −3 V
Current
I
SS
1.7
5
mA
DIGITAL CONTROL INPUTS CTRLA and CTRLB pins
Voltage VCTL
Low
V
INL
V
SS
= −5 V
−3
0
V
VSS = −3 V −1 0 V
High VINH VSS = −5 V −5 −4.2 V
VSS = −3 V −3 −2.2 V
Current ICTL
Low IINL 30 µA
High IINH 0.5 µA
1 Input linearity performance degrades at frequencies less than 250 MHz.
HMC641ALP4E Data Sheet
Rev. B | Page 4 of 11
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Negative Supply Voltage (VSS) −7 V
Digital Control Input Voltage VSS − 0.5 V to + 1 V
RF Input Power1
(f = 250 MHz to 20 GHz, TCASE = 85°C)
VSS = −5 V
Through Path 26.5 dBm
Terminated Path
23 dBm
Hot Switching 20 dBm
VSS = −3 V
Through Path 21 dBm
Terminated Path 20 dBm
Hot Switching 17 dBm
Temperature
Junction, TJ 150°C
Storage −65°C to +150°C
Reflow 260°C
Junction to Case Thermal Resistance, θJC
Through Path
201°C/W
Terminated Path 321°C/W
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1 For power derating at frequencies less than 250 MHz, see Figure 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
POWER DERATING CURVES
2
–10 0.10.01 1
POWER DE RATI NG (d B)
FRE Q UE NCY ( GHz)
–8
–6
–4
–2
0
16094-002
Figure 2. Power Derating at Frequencies Less than 250 MHz
ESD CAUTION
Data Sheet HMC641ALP4E
Rev. B | Page 5 of 11
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NIC
GND
RFC
GND
NIC
NIC NIC
V
SS
CTRLB
CTRLA
GND
NIC
GND
RF4
GND
GND
RF3
GND GND
RF2
GND
GND
RF1
GND
HMC641ALP4E
TOP VIEW
(No t t o Scal e)
19
20
21
22
23
24
13
14
15
16
17
18
1
3
4
2
5
6
7
8
9
10
11
12
NOTES
1. NI C = NOT INT E RNALLY CONNECTED. THE P INS ARE
NOT CONNE CTED INTE RNALL Y ; HOW E V E R, ALL DAT A
SHOWN I N THI S DATA SHEE T I S M E AS URE D WI TH
THE SE P INS CONNECTED T O RF /DC G ROUND
EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF /DC G ROUND O F THE P CB.
16094-002
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 5, 6, 13, 18 NIC Not Internally Connected. The pins are not connected internally; however, all data shown in this data sheet
is measured with these pins connected to RF/dc ground externally.
2, 4, 7, 9, 10, 12, 17,
19, 21, 22, 24
GND Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
3 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
8 RF4 RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
11 RF3 RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
14 VSS Negative Supply Voltage Pin.
15 CTRLB Control Input 2 Pin. See Table 4 for the control voltage truth table.
16 CTRLA Control Input 1 Pin. See Table 4 for the control voltage truth table.
20 RF2 RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
23 RF1 RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line
potential is not equal to 0 V dc.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2,
RF3,
RF4
16094-003
Figure 4. RFC to RF4 Interface Schematic
500Ω
CTRLA,
CTRLB
VSS
100kΩ
16094-004
Figure 5. CTRLA and CTRLB Interface Schematic
HMC641ALP4E Data Sheet
Rev. B | Page 6 of 11
TYPICAL PERFORMANCE CHARCTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
0
–5 024
INSERTION LOSS (dB)
FREQUENCY ( GHz)
–4
–3
–2
–1
4812 16 20
+85°C
+25°C
–40°C
16094-005
Figure 6. Insertion Loss Between RFC and RF1 vs. Frequency at Various
Temperatures
0
–35
RET URN LOS S ( dB)
–30
–25
–20
–15
–10
–5
024
FREQUENCY ( GHz)
4 8 12 16 20
RFC
RF1 TO RF4 ON
RF1 TO RF4 OFF
16094-006
Figure 7. Return Loss for RFC, RF1 to RF4 On, and RF1 to RF4 Off vs.
Frequency
0
–5 024
INSERTION LOSS (dB)
FREQUENCY ( GHz)
–4
–3
–2
–1
4812 16 20
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
16094-007
Figure 8. Insertion Loss Between RFC to RFx vs. Frequency
0
–80
ISOLATION (dB)
–70
–60
–50
–40
–30
–20
–10
024
FREQUENCY ( GHz)
4 8 12 16 20
16094-008
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
Figure 9. Isolation Between RFC and RFx vs. Frequency
Data Sheet HMC641ALP4E
Rev. B | Page 7 of 11
INPUT POWER COMPRESSION AND IP3
30
10 0 4 6 10 14 16 18122 8 20 22
INPUT CO M P RE S S IO N ( dBm)
FREQUENCY ( GHz)
15
20
25
16094-009
Figure 10. Input Compression vs. Frequency at Room Temperature,
VSS = −5 V
50
15
INPUT I P 3 ( dBm)
20
25
30
35
40
45
020
FREQUENCY ( GHz)
4 8 12 16
16094-011
Figure 11. Input IP3 vs. Frequency at Room Temperature,
VSS = −5 V
30
10 0 4 6 10 14 16 18122 8 20 22
INPUT CO M P RE S S IO N ( dBm)
FREQUENCY ( GHz)
15
20
25
16094-010
Figure 12. Input Compression vs. Frequency at Room Temperature,
VSS = −3 V
50
15
INPUT I P 3 ( dBm)
20
25
30
35
40
45
020
FREQUENCY ( GHz)
4 8 12 16
16094-012
Figure 13. Input IP3 vs. Frequency at Room Temperature,
VSS = −3 V
HMC641ALP4E Data Sheet
Rev. B | Page 8 of 11
THEORY OF OPERATION
The HMC641ALP4E requires a negative supply voltage at the
VSS pin and two logic control inputs at the CTRLA and CTRLB
pins to control the state of the RF paths.
Depending on the logic level applied to the CTRLA pin and the
CTRLB pin, one RF path is in the insertion loss state while the
other three paths are in an isolation state (see Table 4). The
insertion loss path conducts the RF signal between the RF throw
pin and RF common pin while the isolation paths provide high loss
between RF throw pins terminated to internal 50 Ω resistors and
the insertion loss path.
The ideal power-up sequence is as follows:
1. Ground to the die bottom.
2. Power up VSS.
3. Power up the digital control inputs. The relative order of the
logic control inputs is not important. However, powering the
digital control inputs before the VSS supply can inadvertently
become forward-biased and damage the internal ESD
protection structures.
4. Apply an RF input signal. The design is bidirectional; the RF
input signal can be applied to the RFC pin while the RF throw
pins are the outputs, or the RF input signal can be applied to
the RF throw pins while the RFC pin is the output. All of the
RF pins are dc-coupled to 0 V, and no dc blocking is required
at the RF pins when the RF line potential is equal to 0 V.
The power-down sequence is the reverse of the power-up
sequence.
Table 4. Control Voltage Truth Table
Digital Control Input
RF Paths
CTRLA CTRLB RFC to RF1 RFC to RF2 RFC to RF3 RFC to RF4
High High Insertion loss (on) Isolation (off) Isolation (off) Isolation (off)
Low High Isolation (off) Insertion loss (on) Isolation (off ) Isolation (off)
High
Low
Isolation (off)
Isolation (off)
Insertion loss (on)
Isolation (off)
Low Low Isolation (off) Isolation (off) Isolation (off) Insertion loss (on)
Data Sheet HMC641ALP4E
Rev. B | Page 9 of 11
APPLICATION INFORMATION
EVALUATION BOARD
The EV1HMC641ALP4 is a 4-layer evaluation board. Each
copper layer is 0.5 oz (0.7 mil) and separated by dielectric
materials. Figure 14 shows the stack up for this
evaluation board.
RO4350
0.5oz Cu (0. 7m i l )0.5oz Cu (0. 7m i l )
0.5oz Cu ( 0.7mi l)
TOTAL THICKNESS
~62mil
0.5oz Cu ( 0.7mi l)
0.5oz Cu ( 0.7mi l)
0.5oz Cu (0. 7m i l )
W = 16mil G = 13mil
T = 0.7mi l
H = 10mil
16094-013
FR4-08
RO4350
Figure 14. The EV1HMC641ALP4 Evaluation Board (Cross Sectional View)
All RF and dc traces are routed on the top copper layer whereas
the inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. Top dielectric
material is a 10 mil Rogers RO4350. The middle and bottom
dielectric materials provide mechanical strength. The overall
board thickness is approximately 62 mil, allowing the
subminiature version A (SMA) launchers to be connected at the
board edges.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with trace width of 16 mil and
ground clearance of 13 mil for a characteristic impedance of
50 Ω. For optimal RF and thermal grounding, arrange as many
plated through vias as possible around transmission lines and
under the exposed pad of the package.
Figure 15 shows the layout of the EV1HMC641ALP4 evaluation
board with component placement. Power supply port is connected
to the VSS test point, J8, and control voltages, CTRLA and CTRLB,
are connected to the A and B test points, J6 and J7, and the ground
reference is connected to the GND test point, J9. On the supply
trace, VSS, use a 1000 pF bypass capacitor to filter high
frequency noise.
The RF input and output ports (RFC, RF1, RF2, RF3, and RF4)
are connected through 50 Ω transmission lines to the SMA
launchers, J1 to J5. These SMA launchers are soldered onto the
board. A through calibration line connects the unpopulated J10
and J11 launchers; this transmission line estimates the loss of
the PCB over the environmental conditions being evaluated, as
shown in Figure 16.
Table 5 shows the evaluation board components.
Table 5. Evaluation Board Components
Component Default Value Description
J1 to J5 PCB mount SMA connector
J6 to J9 DC pin
J10, J11 Do not insert PCB mount SMA connector
C1 1000 pF Capacitor, C0402 package
U1 HMC641ALP4E SP4T switch
PCB 600-00782-00-1 Evaluation PCB
HMC641ALP4E Data Sheet
Rev. B | Page 10 of 11
16094-014
Figure 15. The EV1HMC641ALP4 Evaluation Board Component Placement
DNI
J4
J2
J11
J10
J1
J5
J3
HMC641A
NIC
1
GND
2
RFC
3
GND
4
NIC
5
NIC
6
GND
7RF4
8GND
9GND
10 RF3
11 GND
12
NIC 13
VSS
VSS
14
CTRLB 15
CTRLA 16
GND 17
NIC 18
GND 19
GND 21
RF2 20
GND 22
RF1 23
GND 24
EPAD
25
DNI
CTRLB
C1
1000pF
CTRLA
16094-015
Figure 16. The EV1HMC641ALP4 Evaluation Board Schematic
Data Sheet HMC641ALP4E
Rev. B | Page 11 of 11
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
BOTTOM VIEW
TOP VIEW
SIDE VIEW
4.10
4.00 SQ
3.90
0.95
0.85
0.75 0. 05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FO R P ROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
12-08-2017-C
0.30
0.25
0.18
0.20 M I N
2.85
2.70 SQ
2.55
EXPOSED
PAD
PKG-04940
SEATING
PLANE
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 17. 24-Terminal Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.90 mm Package Height
(HCP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
HMC641ALP4E −40°C to +85°C 24-Terminal Lead Frame Chip Scale Package [LFCSP] HCP-24-3
HMC641ALP4ETR −40°C to +85°C 24-Terminal Lead Frame Chip Scale Package [LFCSP] HCP-24-3
EV1HMC641ALP4 Evaluation Board
1 All models are RoHS compliant.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16094-0-8/18(B)
