1
2
3
4
5
6
GND
NR/FB
OUT
GND
IN
EN
1
KTT (DDPAK) PACKAGE
(TOP VIEW)
2
3
4
5
EN
IN
GND
OUT
NR/FB
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (Hz)
100 10k 100k1k
IOUT = 1 mA
TPS79630
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
IOUT = 1.5 A
VIN = 5.5 V
COUT = 2.2 Fm
CNR = 0.1 mF
0
10
20
30
40
50
60
70
80
Frequency (Hz)
1 10k 10M1k
Ripple Rejection dB
IOUT = 1 mA
TPS79630
RIPPLE REJECTION
vs
FREQUENCY
IOUT = 1 A
VIN = 4 V
COUT = 10 Fm
CNR = 0.01 mF
10 100 100k 1M
EN
NC
GND
NR/FB
8
7
6
5
IN
IN
OUT
OUT
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
Output Spectral Noise Density V/- m Hz
Ö
DCQ PACKAGE
SOT223-6
(TOP VIEW)
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
ULTRALOW-NOISE, HIGH PSRR, FAST, RF, 1A
LOW-DROPOUT LINEAR REGULATORS
Check for Samples: TPS796xx
1FEATURES DESCRIPTION
234 1A Low-Dropout Regulator With Enable The TPS796xx family of low-dropout (LDO)
low-power linear voltage regulators features high
Available in Fixed and Adjustable (1.2V to power supply rejection ratio (PSRR), ultralow-noise,
5.5V) Versions fast start-up, and excellent line and load transient
High PSRR (53dB at 10kHz) responses in small outline, 3 × 3 SON, SOT223-6,
Ultralow-Noise (40mVRMS, TPS79630) and DDPAK-5 packages. Each device in the family is
stable with a small 1mF ceramic capacitor on the
Fast Start-Up Time (50ms) output. The family uses an advanced, proprietary
Stable With a 1mF Ceramic Capacitor BiCMOS fabrication process to yield extremely low
Excellent Load/Line Transient Response dropout voltages (for example, 250mV at 1A). Each
device achieves fast start-up times (approximately
Very Low Dropout Voltage (250mV at Full 50ms with a 0.001mF bypass capacitor) while
Load, TPS79630) consuming very low quiescent current (265 mA
3 × 3 SON PowerPAD™, SOT223-6, and typical). Moreover, when the device is placed in
DDPAK-5 Packages standby mode, the supply current is reduced to less
than 1mA. The TPS79630 exhibits approximately
APPLICATIONS 40mVRMS of output voltage noise at 3.0V output, with
RF: VCOs, Receivers, ADCs a 0.1mF bypass capacitor. Applications with analog
components that are noise sensitive, such as portable
Audio RF electronics, benefit from the high PSRR, low
Bluetooth™, Wireless LAN noise features, and the fast response time.
Cellular and Cordless Telephones
Handheld Organizers, PDAs
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments Inc.
3Bluetooth is a trademark of Bluetooth SIG, Inc.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2002–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS796xx
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS796xx yyy zXX is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable).
YYY is package designator.
Zis package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Output voltages from 1.3V to 4.9V in 100mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted). UNIT
VIN range –0.3V to 6V
VEN range –0.3V to VIN + 0.3V
VOUT range 6V
Peak output current Internally limited
ESD rating, HBM 2kV
ESD rating, CDM 500V
Continuous total power dissipation See Thermal Information Table
Junction temperature range, TJ–40°C to +150°C
Storage temperature range, Tstg –65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
THERMAL INFORMATION TPS796xx(3)
THERMAL METRIC(1)(2) DRB DCQ KTT UNITS
8 PINS 6 PINS 5 PINS
qJA Junction-to-ambient thermal resistance(4) 47.8 70.4 25
qJCtop Junction-to-case (top) thermal resistance(5) 83 70 35
qJB Junction-to-board thermal resistance(6) N/A N/A N/A °C/W
yJT Junction-to-top characterization parameter(7) 2.1 6.8 1.5
yJB Junction-to-board characterization parameter(8) 17.8 30.1 8.52
qJCbot Junction-to-case (bottom) thermal resistance(9) 12.1 6.3 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
.ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
.iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
.iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
TPS796xx
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ= –40°C to +125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V(1), IOUT = 1mA,
COUT = 10mF, and CNR = 0.01mF, unless otherwise noted. Typical values are at +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage(1) 2.7 5.5 V
VFB Internal reference (TPS79601) 1.200 1.225 1.250 V
IOUT Continuous output current 0 1 A
Output TPS79601 1.225 5.5 VDD V
voltage range TPS79601(2) 0mAIOUT 1A, VOUT + 1V VIN 5.5V(1) 0.98VOUT VOUT 1.02VOUT V
Output Fixed
voltage 0mAIOUT 1A, VOUT + 1V VIN 5.5V(1) –2.0 +2.0 %
Accuracy VOUT < 5V
Fixed 0mAIOUT 1A, VOUT + 1V VIN 5.5V(1) –3.0 +3.0 %
VOUT = 5V
Output voltage line regulation VOUT + 1V VIN 5.5V 0.05 0.12 %/V
(ΔVOUT%/VIN)(1)
Load regulation (ΔVOUT%/ΔIOUT) 0mAIOUT 1A 5 mV
TPS79628 IOUT = 1A 270 365
TPS79628DRB IOUT = 250mA 52 90
Dropout voltage(3) TPS79630 IOUT = 1A 250 345 mV
(VIN = VOUT (nom) 0.1V) TPS79633 IOUT = 1A 220 325
TPS79650 IOUT = 1A 200 300
Output current limit VOUT = 0V 2.4 4.2 A
Ground pin current 0mAIOUT 1A 265 385 mA
Shutdown current(4) VEN = 0V, 2.7V VIN 5.5V 0.07 1 mA
FB pin current VFB = 1.225V 1 mA
f = 100Hz, IOUT = 10mA 59
f = 100Hz, IOUT = 1A 54
Power-supply ripple TPS79630 dB
rejection f = 10Hz, IOUT = 1A 53
f = 100Hz, IOUT = 1A 42
CNR = 0.001mF 54
CNR = 0.0047mF 46
BW = 100Hz to 100kHz,
Output noise voltage (TPS79630) mVRMS
IOUT = 1A CNR = 0.01mF 41
CNR = 0.1mF 40
CNR = 0.001mF 50
Time, start-up (TPS79630) RL= 3, COUT = 1mF CNR = 0.0047mF 75 ms
CNR = 0.01mF 110
EN pin current VEN = 0V –1 1 mA
UVLO threshold VCC rising 2.25 2.65 V
UVLO hysteresis 100 mV
High-level enable input voltage 2.7V VIN 5.5V 1.7 VIN V
Low-level enable input voltage 2.7V VIN 5.5V 0 0.7 V
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. TPS79650 is tested at VIN = 5.5V.
(2) Tolerance of external resistors not included in this specification.
(3) VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
4Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
_+
Thermal
Shutdown
Bandgap
Reference
1.225 V
VIN
Current
Sense
R2
GND
EN
SHUTDOWN
VREF
UVLO
ILIM
External to
the Device
FB
R1
UVLO
250 k
Quickstart
IN OUT
_+
Thermal
Shutdown
VIN
Current
Sense
R1
R2
GND
EN
SHUTDOWN
VREF
UVLO
ILIM
Bandgap
Reference
1.225 V
UVLO
250 kNR
Quickstart R2 = 40k
IN OUT
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
Table 1. Terminal Functions
TERMINAL
SOT223
(DCQ)
DDPAK SON
NAME (KTT) (DRB) DESCRIPTION
Connecting an external capacitor to this pin bypasses noise generated by the internal
NR 5 5 bandgap. This improves power-supply rejection and reduces output noise.
FB 5 5 This terminal is the feedback input voltage for the adjustable device.
EN 1 8 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator
into shutdown mode. EN can be connected to IN if not used.
GND 3, Tab 6, PowerPAD Regulator ground
IN 2 1, 2 Unregulated input to the device.
OUT 4 3, 4 Output of the regulator.
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
2.95
2.96
2.97
2.98
2.99
3.00
3.01
3.02
3.03
3.04
3.05
0.0 0.2 0.4 0.6 0.8 1.0
VOUT (V)
IOUT (A)
VIN = 4 V
COUT = 10 µF
TJ = 25°C
0
1
2
3
4
−40−25−10 5 20 35 50 65 80 95 110 125
VOUT (V)
TJ (°C)
IOUT = 1 mA
2.795
2.790
2.785
2.780
2.775
IOUT = 1 A
VIN = 3.8 V
COUT = 10 µF
290
300
310
320
330
340
350
−40−25−10 5 20 35 50 65 80 95 110 125
IGND (µA)
TJ (°C)
VIN = 3.8 V
COUT = 10 µF
IOUT = 1 mA
IOUT = 1 A
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (Hz)
100 10k 100k1k
IOUT = 1 mA
IOUT = 1.5 A
VIN = 5.5 V
COUT = 2.2 µF
CNR = 0.1 µF
Output Spectral Noise Density − µV//Hz
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency (Hz)
100 10k 100k1k
Output Spectral Noise Density − µV//Hz
IOUT = 1 mA
IOUT = 1 A
VIN = 5.5 V
COUT = 10 µF
CNR = 0.1 µF
0.0
0.5
1.0
1.5
2.0
2.5
Frequency (Hz)
100 10k 100k1k
VIN = 5.5 V
COUT = 10 µF
IOUT = 1 A
CNR = 0.1 µF
CNR = 0.01 µF
CNR = 0.0047 µF
CNR = 0.001 µF
Output Spectral Noise Density − µV//Hz
TPS796xx
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
TPS79630 TPS79628 TPS79628
OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
vs vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
TPS79630 TPS79630 TPS79630
OUTPUT SPECTRAL NOISE OUTPUT SPECTRAL NOISE OUTPUT SPECTRAL NOISE
DENSITY DENSITY DENSITY
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 4. Figure 5. Figure 6.
6Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
0
50
100
150
200
250
300
350
402510 5 20 35 50 65 80 95 110125
VDO (mV)
TJ(_C)
VIN = 2.7 V
COUT = 10 µF
IOUT = 1 A
IOUT = 250 mA
0
10
20
30
40
50
60
RMS − Root Mean Squared Output Noise − µVRMS
CNR (µF)
IOUT = 250 mA
COUT = 10 µF
0.001 µF0.01 µF0.1 µF0.0047 µF
BW = 100 Hz to 100 kHz
0
0.25
0.50
0.75
1
1.25
1.50
1.75
2
2.25
2.50
2.75
3
0 100 200 300 400 500 600
t (ms)
VIN = 4 V,
COUT = 10 µF,
IOUT = 1.0 A
Enable
CNR =
0.01 µF
CNR =
0.001 µF
CNR =
0.0047 µF
VOUT (V)
0
10
20
30
40
50
60
70
80
Frequency (Hz)
1 10k 10M1k
Ripple Rejection − dB
IOUT = 1 mA
IOUT = 1 A
VIN = 4 V
COUT = 10 µF
CNR = 0.1 µF
10 100 100k 1M
0
20
VIN (V)
t (µs)
5
4
2
−20
−40
3
40
6040200 80 100 120 140 160 180 200
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
dv
dt +1 V
ms
VOUT (mV)
t (µs)
6
5
3
−20
−40
4
0
20
40
6040200 80 100 120 140 160 180 200
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
dv
dt +1 V
ms
VIN (V)VOUT (mV)
t (µs)
2
1
−1
−75
−150
0
0
75
150
3002001000 400 500 600 700 800 900 1000
VIN = 3.8 V
COUT = 10 µF
CNR = 0.01 µF
di
dt +1 A
ms
IOUT (A)VOUT (mV)
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
TYPICAL CHARACTERISTICS (continued)
TPS79630 TPS79628 TPS79630
ROOT MEAN SQUARED OUTPUT
NOISE DROPOUT VOLTAGE RIPPLE REJECTION
vs vs vs
BYPASS CAPACITANCE JUNCTION TEMPERATURE FREQUENCY
Figure 7. Figure 8. Figure 9.
TPS79630 TPS79630
RIPPLE REJECTION RIPPLE REJECTION
vs vs
FREQUENCY FREQUENCY START-UP TIME
Figure 10. Figure 11. Figure 12.
TPS79618 TPS79630 TPS79628
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 13. Figure 14. Figure 15.
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
0
50
100
150
200
250
300
350
0 100 200 300 400 500 600 700 800 9001000
VDO (mV)
IOUT (mA)
TJ = 125°C
TJ = −40°C
TJ = 25°C
0
50
100
150
200
250
300
2.5 3.0 3.5 4.0 4.5 5.0
VDO (mV)
VIN (V)
TJ = 125°C
TJ = −40°C
TJ = 25°C
IOUT = 1 A
COUT = 10 µF
CNR = 0.01 µF
200 µs/Div
4.0
3.5
2.5
0.5
0
3.0
1.0
1.5
2.0
500 mV/Div
3210 4 5 6 7 8 9 10
VOUT = 2.5 V
RL = 10
CNR = 0.01 µF
VIN
VOUT
ESR − Equivalent Series Resistance −
IOUT (mA)
Region of
Instability
100
10
1
0.1
0.01
COUT = 1 µF
Region of Stability
101 500 750 10006030 250125
ESR − Equivalent Series Resistance −
IOUT (mA)
100
10
1
0.1
0.01
COUT = 2.2 µF
Region of Stability
101 500 750 10006030 250125
Region of
Instability
ESR − Equivalent Series Resistance −
IOUT (mA)
100
10
1
0.1
0.01
COUT = 10.0 µF
Region of Stability
101 500 750 10006030 250125
Region of
Instability
TPS796xx
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS79630 TPS79601
TPS79625 DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
POWER UP/POWER DOWN OUTPUT CURRENT INPUT VOLTAGE
Figure 16. Figure 17. Figure 18.
TPS79630 TPS79630 TPS79630
TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE
(ESR) (ESR) (ESR)
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT
Figure 19. Figure 20. Figure 21.
8Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
GNDEN NR
IN OUT
VIN VOUT
0.01µF
TPS796xx
2.2µF1 µF
VOUT +VREF ǒ1)R1
R2Ǔ
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
APPLICATION INFORMATION
The TPS796xx family of low-dropout (LDO) regulators For example, the TPS79630 exhibits 40mVRMS of
has been optimized for use in noise-sensitive output voltage noise using a 0.1mF ceramic bypass
equipment. The device features extremely low capacitor and a 10mF ceramic output capacitor. Note
dropout voltages, high PSRR, ultralow output noise, that the output starts up slower as the bypass
low quiescent current (265mA typically), and enable capacitance increases due to the RC time constant at
input to reduce supply currents to less than 1mA the bypass pin that is created by the internal 250k
when the regulator is turned off. resistor and external capacitor.
A typical application circuit is shown in Figure 22.Board Layout Recommendation to Improve
PSRR and Noise Performance
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
Figure 22. Typical Application Circuit ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
External Capacitor Requirements Regulator Mounting
Although not required, it is good analog design The tab of the SOT223-6 package is electrically
practice to place a 0.1mF to 2.2mF capacitor near the connected to ground. For best thermal performance,
input of the regulator to counteract reactive input the tab of the surface-mount version should be
sources. A 2.2mF or larger ceramic input bypass soldered directly to a circuit-board copper area.
capacitor, connected between IN and GND and Increasing the copper area improves heat dissipation.
located close to the TPS796xx, is required for stability
and improves transient response, noise rejection, and Solder pad footprint recommendations for the devices
ripple rejection. A higher-value input capacitor may be are presented in an application bulletin Solder Pad
necessary if large, fast-rise-time load transients are Recommendations for Surface-Mount Devices,
anticipated and the device is located several inches literature number AB-132, available for download
from the power source. from the TI web site (www.ti.com).
Like most low dropout regulators, the TPS796xx Programming the TPS79601 Adjustable LDO
requires an output capacitor connected between OUT Regulator
and GND to stabilize the internal control loop. The
minimum recommended capacitor is 1mF. Any 1mF or The output voltage of the TPS79601 adjustable
larger ceramic capacitor is suitable. regulator is programmed using an external resistor
divider as shown in . The output voltage is calculated
The internal voltage reference is a key source of using Equation 1:
noise in an LDO regulator. The TPS796xx has an NR
pin which is connected to the voltage reference
through a 250kinternal resistor. The 250kinternal (1)
resistor, in conjunction with an external bypass where:
capacitor connected to the NR pin, creates a VREF = 1.2246V typ (the internal reference
low-pass filter to reduce the voltage reference noise voltage)
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the current Resistors R1 and R2 should be chosen for
flow out of the NR pin must be at a minimum, approximately 40mA divider current. Lower value
because any leakage current creates an IR drop resistors can be used for improved noise
across the internal resistor, thus creating an output performance, but the device wastes more power.
error. Therefore, the bypass capacitor must have Higher values should be avoided, as leakage current
minimal leakage current. The bypass capacitor at FB increases the output voltage error.
should be no more than 0.1mF in order to ensure that
it is fully charged during the quickstart time provided
by the internal switch shown in the functional block
diagram.
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
R1 +ǒVOUT
VREF *1Ǔ R2
C1 +(3 x 10–7) x (R1 )R2)
(R1 x R2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE R1 R2 C1
GND FB
IN OUT
EN
VIN VOUT
R1 C1
R2
TPS79601 1 µF
1.8 V
3.6V
14.0 k
57.9 k
30.1 k
30.1 k
33 pF
15 pF
2.2 µF
TPS796xx
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
www.ti.com
The recommended design procedure is to choose Regulator Protection
R2 = 30.1kto set the divider current at 40mA, C1 = The TPS796xx PMOS-pass transistor has a built-in
15pF for stability, and then calculate R1 using back diode that conducts reverse current when the
Equation 2:input voltage drops below the output voltage (for
example, during power-down). Current is conducted
from the output to the input and is not internally
(2) limited. If extended reverse voltage operation is
anticipated, external limiting might be appropriate.
In order to improve the stability of the adjustable
version, it is suggested that a small compensation The TPS796xx features internal current limiting and
capacitor be placed between OUT and FB. The thermal protection. During normal operation, the
approximate value of this capacitor can be calculated TPS796xx limits output current to approximately 2.8A.
as Equation 3:When current limiting engages, the output voltage
scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
(3) gross device failure, care should be taken not to
The suggested value of this capacitor for several exceed the power dissipation ratings of the package.
resistor ratios is shown in the table below (see If the temperature of the device exceeds
Figure 23). If this capacitor is not used (such as in a approximately +165°C, thermal-protection circuitry
unity-gain configuration) then the minimum shuts it down. Once the device has cooled down to
recommended output capacitor is 2.2mF instead of below approximately +140°C, regulator operation
1mF. resumes.
Figure 23. TPS79601 Adjustable LDO Regulator Programming
10 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
PD+ǒVIN *VOUTǓ IOUT
160
140
120
100
80
60
40
20
0
qJA ( C/W)
°
0 1 2 3 4 5 678 9 10
Board Copper Area ( )in2
DCQ
DRB
KTT
RqJA +()125OC*TA)
PD
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
THERMAL INFORMATION
Knowing the maximum RqJA, the minimum amount of
POWER DISSIPATION PCB copper area needed for appropriate heatsinking
can be estimated using Figure 24.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation.
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
using Equation 4:
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On the SON (DRB) package, the primary conduction
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be Note: qJA value at board size of 9in2(that is, 3in ×
connected to ground or be left floating; however, it 3in) is a JEDEC standard.
should be attached to an appropriate amount of
copper PCB area to ensure the device does not Figure 24. qJA vs Board Size
overheat. On both SOT-223 (DCQ) and DDPAK
(KTT) packages, the primary conduction path for heat Figure 24 shows the variation of qJA as a function of
is through the tab to the PCB. That tab should be ground plane copper area in the board. It is intended
connected to ground. The maximum only as a guideline to demonstrate the effects of heat
junction-to-ambient thermal resistance depends on spreading in the ground plane and should not be
the maximum ambient temperature, maximum device used to estimate actual thermal performance in real
junction temperature, and power dissipation of the application environments.
device and can be calculated using Equation 5:NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
(5) ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Y Y
JT J T JT D
:T =T + P·
Y Y
JB J B JB D
:T =T + P·
35
30
25
20
15
10
5
0
Y Yand ( C/W)
JT JB °
0 2 46 8 10
Board Copper Area (in )
2
51 3 7 9
DCQ YJT
DCQ
DRB
KTT
KTT YJT
DRB YJT
YJB
(a) Example DRB (SON) Package Measurement (b) Example DCQ (SOT-223) Package Measurement
1mm
T on top
of IC
T
T on PCB
surface
B
(c) Example KTT (DDPAK) Package Measurement
1mm X
X
TT
TB
1mm
T on of IC
Ttop (1)
T on PCB
surface
B
(2)
TPS796xx
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
www.ti.com
ESTIMATING JUNCTION TEMPERATURE
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
compatibility, an older qJC,Top parameter is listed as
well.
(6)
Where PDis the power dissipation shown by
Equation 5, TTis the temperature at the center-top of
the IC package, and TBis the PCB temperature
measured 1mm away from the IC package on the
PCB surface (as Figure 26 shows). Figure 25. ΨJT and ΨJB vs Board Size
NOTE: Both TTand TBcan be measured on actual
application boards using a thermo-gun (an infrared For a more detailed discussion of why TI does not
thermometer). recommend using qJC(top) to determine thermal
characteristics, refer to application report SBVA025,
For more information about measuring TTand TB, see Using New Thermal Metrics, available for download
the application note SBVA025,Using New Thermal at www.ti.com. For further information, refer to
Metrics, available for download at www.ti.com.application report SPRA953,IC Package Thermal
By looking at Figure 25, the new thermal metrics (ΨJT Metrics, also available on the TI website.
and ΨJB) have very little dependency on board size.
That is, using ΨJT or ΨJB with Equation 6 is a good
way to estimate TJby simply measuring TTor TB,
regardless of the application board size.
(1) TTis measured at the center of both the X- and Y-dimensional axes.
(2) TBis measured below the package lead on the PCB surface.
Figure 26. Measuring Points for TTand TB
12 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated
TPS796xx
www.ti.com
SLVS351N SEPTEMBER 2002REVISED JANUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (October, 2010) to Revision N Page
Corrected typo in front-page figure ....................................................................................................................................... 1
Changes from Revision L (August, 2010) to Revision M Page
Corrected typo in Figure 26 ................................................................................................................................................ 12
Copyright © 2002–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS79601DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79601KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79601KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79601KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79613DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79613DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79613DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79613DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS79618KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79618KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79618KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79618KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79618KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79625KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79625KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79628DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628DRBR ACTIVE SON DRB 8 TBD Call TI Call TI
TPS79628DRBRG4 ACTIVE SON DRB 8 TBD Call TI Call TI
TPS79628DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS79628DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79628KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79628KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79628KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79630KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79630KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79630KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS79633KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS79633KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79633KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS79650DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS79650DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)