©
1998
DATA SHEET
The mark shows major revised points.
MOS INTEGRATED CIRCUIT
µ
PD70F3003A, 70F3025A, 70F3003A(A)
V853TM
32-BIT SINGLE-CHIP MICROCONTROLLERS
Document No. U13189EJ5V0DS00 (5th edition)
Date Published January 2002 N CP(K)
Printed in Japan
DESCRIPTION
The
µ
PD70F3003A,
µ
PD70F3025A, and
µ
PD70F3003A(A) have a flash memory instead of the internal mask ROM
of the
µ
PD703003A/703004A,
µ
PD703025A, and
µ
PD703003A(A), respectively. This model is useful for small-scale
production of a variety of application sets or early start of production since the program can be written and erased
by the user even with the
µ
PD70F3003 mounted on the board.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V853 Hardware User’s Manual: U10913E
V850 SeriesTM Architecture User’s Manual: U10243E
FEATURES
• Compatible with
µ
PD703003A, 703004A, 703025A, and 703003A(A)
• Can be replaced with mask ROM model for mass production of application set
µ
PD70F3003A →
µ
PD703003A, 703004A
µ
PD70F3025A →
µ
PD703025A
µ
PD70F3003A(A) →
µ
PD703003A(A)
• Internal memory Flash memory: 128KB (
µ
PD70F3003A, 70F3003A(A))
256KB (
µ
PD70F3025A)
Remark For differences among the products, refer to 1. DIFFERENCES BETWEEN PRODUCT.
ORDERING INFORMATION
Part Number Package Quality Grade
µ
PD70F3003AGC-33-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Standard
µ
PD70F3025AGC-33-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Standard
µ
PD70F3003AGC(A)-33-8EU 100-pin plastic LQFP (fine pitch) (14 × 14) Special
The
µ
PD70F3003A and
µ
PD70F3003A(A) differ in the quality grade only.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
2Data Sheet U13189EJ5V0DS
APPLICATIONS
µ
PD70F3003A, 70F3025A: Camcorders, VCRs, PPCs, LBPs, printers, motor controllers, NC machine
tools, mobile telephones, etc.
µ
PD70F3003A(A): Medical equipment, automotive appliances, etc.
PIN CONFIGURATION (Top View)
• 100-Pin Plastic LQFP (fine pitch) (14 × 14)
µ
PD70F3003AGC-33-8EU
µ
PD70F3025AGC-33-8EU
µ
PD70F3003AGC(A)-33-8EU
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P31/TO131
P32/TCLR13
P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
P62/A18
P61/A17
P60/A16
VSS
VDD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
ANO1
AVREF2
AVREF3
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141
P30/TO130
P27/SCK1
P26/RXD1/SI1
P25/TXD1/SO1
P24/SCK0
P23/RXD0/SI0
P22/TXD0/SO0
P21/PWM1
P20/PWM0
NMI
VDD
VSS
P17/INTP123/SCK2
P16/INTP122/SI2
P15/INTP121/SO2
P14/INTP120
P13/TI12
P12/TCLR12
P11/TO121
P10/TO120
AVDD
AVSS
AVREF1
P77/ANI7
P76/ANI6
P43/AD3
P42/AD2
VSS
VDD
P41/AD1
P40/AD0
P90/LBEN
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRO
WAIT
VPP
MODE
RESET
CVDD/CKSEL
X2
X1
CVSS
CLKOUT
VSS
VDD
P110/TO140
Caution Connect VPP pin to VSS pin except the case that
µ
PD70F3003A, 70F3003A(A) or 70F3025A
is used in flash memory programming mode.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
3
Data Sheet U13189EJ5V0DS
P40 to P47: Port 4
P50 to P57: Port 5
P60 to P63: Port 6
P70 to P77: Port 7
P90 to P96: Port 9
P110 to P117: Port 11
PWM0, PWM1: Pulse width modulation
RESET: Reset
R/W: Read/write status
RXD0, PXD1: Receive data
SCK0 to SCK3: Serial clock
SI0 to SI3: Serial input
SO0 to SO3: Serial output
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141: Timer output
TCLR11 to TCLR14: Timer clear
TI11 to TI14: Timer input
TXD0, TXD1: Transmit data
UBEN: Upper byte enable
WAIT: Wait
X1, X2: Crystal
VDD: Power supply
VPP:
Programming power supply
VSS: Ground
PIN NAMES
A16 to A19: Address bus
AD0 to AD15: Address/data bus
ADTRG: A/D Trigger input
ANI0 to ANI7: Analog input
ANO0, ANO1: Analog output
ASTB: Address strobe
AVDD: Analog VDD
AVREF1 to AVREF3: Analog reference voltage
AVSS: Analog VSS
CVDD:
Power supply for clock generator
CVSS: Ground for clock generator
CKSEL: Clock select
CLKOUT : Clock output
DSTB: Data strobe
HLDAK: Hold acknowledge
HLDRQ: Hold request
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143:
Interrupt request from peripherals
LBEN: Lower byte enable
MODE: Mode
NMI:
Non-maskable interrupt request
P00 to P07: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30 to P37: Port 3
µ
PD70F3003A, 70F3025A, 70F3003A(A)
4Data Sheet U13189EJ5V0DS
INTERNAL BLOCK DIAGRAM
INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143
NMI
TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141
TCLR11 to TCLR14
TI11 to TI14
SO0/TXD0
INTC
RPU
CSI2
SIO
BRG2
CSI3
Flash memory
Note 1
RAM
Note 2
CPU
PC
32-bit
barrel shifter
System
register
General-
purpose
register
32 bits × 32
ALU
Multiplier
16 × 16 → 32
Ports
P110 to P117
P90 to P96
P70 to P77
P60 to P63
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P17
P00 to P07
CG
BCU
Instruction
queue
ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A19
AD0 to AD15
HLDRQ
HLDAK
CKSEL
CLKOUT
X1
X2
MODE
RESET
UART0/CSI0
BRG0
UART1/CSI1
BRG1
D/A
converter
A/D
converter
ANI0 to ANI7
AV
REF1
AV
SS
AV
DD
ADTRG
ANO0, ANO1
AV
REF2
, AV
REF3
SI0/RXD0
SCK0
SO1/TXD1
SI1/RXD1
SCK1
SO2
SI2
SCK2
SO3
SI3
SCK3
PWM
PWM0, PWM1
V
DD
V
SS
CV
DD
CV
SS
V
PP
Notes 1.
µ
PD70F3003A, 70F3003A(A): 128 KB
µ
PD70F3025A: 256 KB
2.
µ
PD70F3003A, 70F3003A(A): 4 KB
µ
PD70F3025A: 8 KB
µ
PD70F3003A, 70F3025A, 70F3003A(A)
5
Data Sheet U13189EJ5V0DS
CONTENTS
1. DIFFERENCES BETWEEN PRODUCTS ·························································································· 6
2. PIN FUNCTIONS ································································································································ 7
2.1 Port Pins ····················································································································································· 7
2.2 Non-Port Pins············································································································································· 9
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins························································· 11
3. ELECTRICAL SPECIFICATIONS ······································································································· 14
3.1 Normal Operation Mode ···························································································································· 14
3.2 Flash Memory Programming Mode·········································································································· 37
4. PACKAGE DRAWING ······················································································································· 40
5. RECOMMENDED SOLDERING CONDITIONS ················································································· 41
APPENDIX NOTES ON TARGET SYSTEM DESIGN············································································· 42
µ
PD70F3003A, 70F3025A, 70F3003A(A)
6Data Sheet U13189EJ5V0DS
1. DIFFERENCES BETWEEN PRODUCTS
Item
µ
PD703003A
µ
PD703004A
µ
PD703025A
µ
PD703003A(A)
µ
PD703025A(A)
µ
PD70F3003A
µ
PD70F3025A
µ
PD70F3003A(A)
Internal ROM Mask ROM Flash memory
128 KB 96 KB 256 KB 128 KB 256 KB 128 KB 256 KB 128 KB
Internal RAM 4 KB 8 KB 4 KB 8 KB 4 KB 8 KB 4 KB
Flash memory None Provided
programming mode
VPP pin None Provided
Quality grade Standard Special Standard Special
Electrical specifications
Current consumption, etc. differs. (Refer to each product data sheets).
Others Noise immunity and noise radiation differ because circuit scale and mask layout differ.
Caution There are differences in noise immunity and noise radiation between the flash memory version
and mask ROM version. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation
for commercial samples (not engineering samples) of the mask ROM version.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
7
Data Sheet U13189EJ5V0DS
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name I/O Function Alternate Function
P00 I/O Port 0 TO110
P01 8-bit I/O port. TO111
P02 Input/output can be specified in 1-bit units. TCLR11
P03 TI11
P04 INTP110
P05 INTP111
P06 INTP112
P07
INTP113/ADTRG
P10 I/O Port 1 TO120
P11 8-bit I/O port. TO121
P12 Input/output can be specified in 1-bit units. TCLR12
P13 TI12
P14 INTP120
P15 INTP121/SO2
P16 INTP122/SI2
P17
I
NTP123/SCK2
P20 I/O Port 2 PWM0
P21 8-bit I/O port. PWM1
P22 Input/output can be specified in 1-bit units. TXD0/SO0
P23 RXD0/SI0
P24 SCK0
P25 TXD1/SO1
P26 RXD1/SI1
P27
SCK1
P30 I/O Port 3 TO130
P31 8-bit I/O port. TO131
P32 Input/output can be specified in 1-bit units. TCLR13
P33 TI13
P34 INTP130
P35 INTP131/SO3
P36 INTP132/SI3
P37
I
NTP133/SCK3
P40 to P47 I/O Port 4 AD0 to AD7
8-bit I/O port.
Input/output can be specified in 1-bit units.
P50 to P57 I/O Port 5 AD8 to AD15
8-bit I/O port.
Input/output can be specified in 1-bit units.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
8Data Sheet U13189EJ5V0DS
(2/2)
Pin Name I/O Function Alternate Function
P60 to P63 I/O Port 6 A16 to A19
4-bit I/O port.
Input/output can be specified in 1-bit units.
P70 to P77 Input Port 7 ANI0 to ANI7
8-bit input port.
P90 I/O Port 9 LBEN
P91 7-bit I/O port. UBEN
P92 Input/output can be specified in 1-bit units. R/W
P93 DSTB
P94 ASTB
P95 HLDAK
P96 HLDRQ
P110 I/O Port 11 TO140
P111 8-bit I/O port. TO141
P112 Input/output can be specified in 1-bit units. TCLR14
P113 TI14
P114 INTP140
P115 INTP141
P116 INTP142
P117 INTP143
µ
PD70F3003A, 70F3025A, 70F3003A(A)
9
Data Sheet U13189EJ5V0DS
2.2 Non-Port Pins
(1/2)
Pin Name I/O Function Alternate Function
TO110 Output Pulse signal output from timers 11 to 14 P00
TO111 P01
TO120 P10
TO121 P11
TO130 P30
TO131 P31
TO140 P110
TO141 P111
TCLR11 Input External clear signal input for timers 11 to 14 P02
TCLR12 P12
TCLR13 P32
TCLR14 P112
TI11 Input External count clock input for timers 11 to 14 P03
TI12 P13
TI13 P33
TI14 P113
INTP110 Input External maskable interrupt request input and external capture P04
INTP111 trigger input for timer 11 P05
INTP112 P06
INTP113 P07/ADTRG
INTP120 Input External maskable interrupt request input and external capture P14
INTP121 trigger input for timer 12 P15/SO2
INTP122 P16/S12
INTP123 P17/SCK2
INTP130 Input External maskable interrupt request input and external capture P34
INTP131 trigger input for timer 13 P35/SO3
INTP132 P36/SI3
INTP133 P37/SCK3
INTP140 Input External maskable interrupt request input and external capture P114
INTP141 trigger input for timer 14 P115
INTP142 P116
INTP143 P117
SO0 Output Serial transmit data output for CSI0 to CSI3 (3-wire) P22/TXD0
SO1 P25/TXD1
SO2 P15/INTP121
SO3 P35/INTP131
SI0 Input Serial receive data output for CSI0 to CSI3 (3-wire) P23/RXD0
SI1 P26/RXD1
SI2 P16/INTP122
SI3 P36/INTP132
µ
PD70F3003A, 70F3025A, 70F3003A(A)
10 Data Sheet U13189EJ5V0DS
(2/2)
Pin Name I/O Function Alternate Function
SCK0 I/O Serial clock I/O for CSI0 to CSI3 (3-wire) P24
SCK1 P27
SCK2 P17/INTP123
SCK3 P37/INTP133
TXD0 Output Serial transmit data output of UART0 to UART1 P22/SO0
TXD1 P25/SO1
RXD0 Input Serial receive data input of UART0 to UART1 P23/SI0
RXD1 P26/SI1
PWM0 Output Pulse signal output of PWM P20
PWM1 P21
AD0 to AD7 I/O 16-bit multiplexed address/data bus when external memory is connected P40 to P47
AD8 to AD15 P50 to P57
A16 to A19 Output Higher address bus when external memory is connected P60 to P63
LBEN Output Lower byte enable signal output of external data bus P90
UBEN Higher byte enable signal output of external data bus P91
R/W Output External read/write status output P92
DSTB External data strobe signal output P93
ASTB External address strobe signal output P94
HLDAK Output Bus hold acknowledge output P95
HLDRQ Input Bus hold request input P96
ANI0 to ANI7 Input Analog input to A/D converter P70 to P77
ANO0, ANO1 Output Analog output of D/A converter —
NMI Input Non-maskable interrupt request input —
CLKOUT Output System clock output —
CKSEL Input Input specifying operation mode of clock generator CVDD
WAIT Input Control signal input inserting wait state in bus cycle —
MODE Input Operation mode specification —
RESET Input System reset input —
X1 Input System clock resonator connection. Input external clock to X1 to —
X2 — supply external clock. —
ADTRG Input A/D converter external trigger input P07/INTP113
AVREF1 Input Reference voltage input for A/D converter —
AVREF2 Input Reference voltage input for D/A converter —
AVREF3 —
AVDD — Positive power supply for A/D converter —
AVSS — Ground potential for A/D converter —
CVDD — Positive power supply for internal clock generator CKSEL
CVSS — Ground potential for internal clock generator —
VDD — Positive power supply —
VSS — Ground potential —
VPP — High voltage application pin when program is written/verified —
µ
PD70F3003A, 70F3025A, 70F3003A(A)
11
Data Sheet U13189EJ5V0DS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure
2-1 shows a partially simplified diagram of each circuit.
It is recommended that 1 to 10 kΩ resistors be used when connecting to VDD or VSS via a resistor.
Table 2-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2)
Pin Name I/O Circuit Type Recommended Connection of Unused Pins
P00/TO110, P01/TO111 5 Input: Independently connect to VDD or VSS via a resistor.
P02/TCLR11, P03/TI11, 8 Output: Leave open.
P04/INTP110 to P07/INTP113/ADTRG
P10 to TO120, P11/TO121 5
P12/TCLR12, P13/TI12 8
P14/INTP120
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
P20/PWM0, P21/PWM1 5
P22/TXD0/SO0
P23/RXD0/SI0, P24/SCK0 8
P25/TXD1/SO1 5
P26/RXD1/SI1, P27/SCK1 8
P30/TO130, P31/TO131 5
P32/TCLR13, P33/TI13 8
P34/INTP130
P35/INTP131/SO3 10-A
P36/INTP132/SI3
P37/INTP133/SCK3
P40/AD0 to P47/AD7 5
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7 9 Directly connect to VSS.
P90/LBEN 5 Input: Independently connect to VDD or VSS via a resistor.
P91/UBEN Output: Leave open.
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14 8
P114/INTP140 to P117/INTP143
µ
PD70F3003A, 70F3025A, 70F3003A(A)
12 Data Sheet U13189EJ5V0DS
Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name I/O Circuit Type Recommended Connection of Unused Pins
ANO0, ANO1 12 Leave open.
NMI 2 Directly connect to VSS.
CLKOUT 3 Leave open.
WAIT 1 Directly connect to VDD.
MODE 2 —
RESET
CVDD/CKSEL —
AVREF1 to AVREF3, AVSS — Directly connect to VSS.
AVDD — Directly connect to VDD.
VPP — Connect to VSS.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
13
Data Sheet U13189EJ5V0DS
Figure 2-1. Pins I/O Circuits
Type 1
Type 5
Type 2
Type 8
Type 3
P-ch
N-ch
IN
VDD
IN
Schmitt trigger input with hysteresis characteristics
P-ch
N-ch
VDD
OUT
P-ch
N-ch
VDD
IN/OUT
Data
Output
disable
Input
enable
P-ch
N-ch
VDD
IN/OUT
Data
Output
disable
Type 9
Type 10-A
Type 12
+
–
N-ch
P-ch
Comparator
VREF (Threshold voltage)
Input enable
IN
P-ch
N-ch
VDD
IN/OUT
P-ch
VDD
Data
Pull-up
enable
Output disable
Open drain
Analog output voltage OUT
P-ch
N-ch
µ
PD70F3003A, 70F3025A, 70F3003A(A)
14 Data Sheet U13189EJ5V0DS
3. ELECTRICAL SPECIFICATIONS
3.1 Normal Operation Mode
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply voltage VDD VDD pin –0.5 to +7.0 V
CVDD CVDD pin –0.5 to VDD + 0.3Note 1 V
CVSS CVSS pin –0.5 to +0.5 V
AVDD AVDD pin –0.5 to VDD + 0.3Note 1 V
AVSS AVSS pin –0.5 to +0.5 V
Input voltage VI1 Note 2, VDD = 5.0 V ±10% –0.5 to VDD + 0.3Note 1 V
VI2 VPP pin in flash memory programming mode, –0.5 to +11.0 V
VDD = 5.0 V ±10%
Clock input voltage VKX1 pin, VDD = 5.0 V ±10% –0.5 to VDD + 1.0Note 1 V
Output current, low ICL 1 pin 4.0 mA
Total of all pins 100 mA
Output current, high ICH 1 pin –4.0 mA
Total of all pins –100 mA
Output voltage VOVDD = 5.0 V ±10% –0.5 to VDD + 0.3Note 1 V
Analog input voltage VIAN P70/ANI0 to P77/ANI7 AVDD > VDD –0.5 to VDD + 0.3Note 1 V
VDD ≥ AVDD –0.5 to AVDD + 0.3Note 1 V
Analog reference input voltage AVREF AVREF1 to AVREF3 AVDD > VDD –0.5 to VDD + 0.3Note 1 V
VDD ≥ AVDD –0.5 to AVDD + 0.3Note 1 V
Operating ambient temperature TA–40 to +85 °C
Storage temperature Tstg –65 to +125 °C
Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
2. X1, P70 to P77, AVREF1 to AVREF3, and their alternate-function pins are excluded.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC
and GND. However, direct connections among open-drain and open-collector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output conflict with pins that become high-impedance.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The normal operating ranges of ratings and conditions in which the quality of the product
is guaranteed are specified in the following DC Characteristics and AC Characteristics.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
15
Data Sheet U13189EJ5V0DS
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CIfc = 1 MHz 15 pF
I/O capacitance CIO Pins other than tested pin: 0 V 15 pF
Output capacitance CO15 pF
Operating Conditions
Operation Mode Internal System Clock Frequency (
φ
) Operating Temperature (TA) Supply Voltage (VDD)
Direct mode, 2 to 33 MHzNote 1 –40 to +85°C 5.0 V ±10%
PLL mode 5 to 33 MHzNote 2 –40 to +85°C 5.0 V ±10%
Notes 1. When A/D converter not used.
2. When A/D converter used.
Recommended Oscillator
Caution For the resonator selection and oscillator constant of the
µ
PD70F3003A(A), customers are
requested to apply to the resonator manufacturer for evaluation.
(1) Ceramic resonator connection (TA = –40 to +85°C)
(a)
µ
PD70F3003A
X1 X2
C1 C2
Rd
Manufacturer Part Number Oscillation Recommended Oscillation Oscillation
Frequency Circuit Constant Voltage Range Stabilization Time
fXX (MHz) C1 (pF) C2 (pF) Rd (W) MIN. (V) MAX. (V) (MAX.) TOST (ms)
Kyocera PBRC4.00HR 4.0 On-chip On-chip —4.5 5.5 0.10
Corporation PBRC5.00HR 5.0 On-chip On-chip —4.5 5.5 0.08
PBRC6.00HR 6.0 On-chip On-chip —4.5 5.5 0.08
PBRC6.60HR 6.6 On-chip On-chip —4.5 5.5 0.08
TDK FCR4.0MC5 4.0 On-chip On-chip —4.5 5.5 0.14
FCR5.0MC5 5.0 On-chip On-chip —4.5 5.5 0.14
FCR6.0MC5 6.0 On-chip On-chip —4.5 5.5 0.11
Murata Mfg. CSTS0400MG06 4.0 On-chip On-chip —4.5 5.5 0.12
Co., Ltd CSTCR4M00G05 4.0 On-chip On-chip —4.5 5.5 0.14
CSTS0600MG06 6.0 On-chip On-chip —4.5 5.5 0.14
CSTCR6M00G55-R0 6.0 On-chip On-chip —4.5 5.5 0.18
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the
µ
PD70F3003A and the resonator.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
16 Data Sheet U13189EJ5V0DS
(b)
µ
PD70F3025A
X1 X2
C1 C2
Rd
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the
µ
PD70F3025A and the resonator.
(2) External clock input
X1
High-speed CMOS inverter
External clock
X2
Open
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pins as possible.
2. Sufficiently evaluate the matching between the
µ
PD70F3003A, 70F3025A, or 70F3003A(A),
and the high-speed CMOS inverter.
Manufacturer Part Number Oscillation Recommended Oscillation Oscillation
Frequency Circuit Constant Voltage Range Stabilization Time
fXX (MHz) C1 (pF) C2 (pF) Rd (W) MIN. (V) MAX. (V) (MAX.) TOST (ms)
Kyocera PBRC4.00HR 4.0 On-chip On-chip —4.5 5.5 0.12
Corporation PBRC5.00HR 5.0 On-chip On-chip —4.5 5.5 0.04
PBRC6.00HR 6.0 On-chip On-chip —4.5 5.5 0.04
PBRC6.60HR 6.6 On-chip On-chip —4.5 5.5 0.04
TDK FCR4.0MC5 4.0 On-chip On-chip —4.5 5.5 0.14
FCR5.0MC5 5.0 On-chip On-chip —4.5 5.5 0.13
FCR6.0MC5 6.0 On-chip On-chip —4.5 5.5 0.13
Murata Mfg. CSTS0400MG06 4.0 On-chip On-chip —4.5 5.5 0.12
Co., Ltd CSTCR4M00G55-R0 4.0 On-chip On-chip —4.5 5.5 0.14
CSTS0600MG06 6.0 On-chip On-chip —4.5 5.5 0.16
CSTCR6M00G55-R0 6.0 On-chip On-chip —4.5 5.5 0.19
µ
PD70F3003A, 70F3025A, 70F3003A(A)
17
Data Sheet U13189EJ5V0DS
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
(1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH
Except X1 and Note
2.2 VDD + 0.3 V
Note 0.8VDD VDD + 0.3 V
Input voltage, low VIL
Except X1 and Note
–0.5 +0.8 V
Note –0.5 0.2VDD V
Clock input voltage, high VXH X1 0.8VDD VDD + 0.5 V
Clock input voltage, low VXL X1 –0.5 0.6 V
Schmitt trigger input threshold voltage VT
+Note, rising 3.0 V
VT
–Note, falling 2.0 V
Schmitt trigger input hysteresis width VT
+ – VT
–Note 0.5 V
Output voltage, high VOH IOH = –2.5 mA 0.7VDD V
IOH = –100
µ
AVDD – 0.4 V
Output voltage, low VOL IOC = 2.5 mA 0.45 V
Input leakage current, high ILIH VI = VDD 10
µ
A
Input leakage current, low ILIL VI = 0 V –10
µ
A
Output leakage current, high ILOH VO = VDD 10
µ
A
Output leakage current, low ILOL VO = 0 V –10
µ
A
Software pull-up resistor R
P35/INTP131/SO3,
15 40 90 kΩ
P36/INTP132/SI3,
P37/INTP133/SCK3
Note P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and their
alternate-function pins.
Remark TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
18 Data Sheet U13189EJ5V0DS
(2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
µ
PD70F3003A,
Operating IDD1 Direct mode 2.2 ×
φ
+ 7.5 2.5 ×
φ
+ 22 mA
current 70F3003A(A) PLL mode 2.3 ×
φ
+ 9.5 2.6 ×
φ
+ 25 mA
In HALT mode
IDD2 Direct mode 1.2 ×
φ
+ 7.5 1.3 ×
φ
+ 15 mA
PLL mode 1.3 ×
φ
+ 9.5 1.4 ×
φ
+ 17 mA
In IDLE mode IDD3 Direct mode 8 ×
φ
+ 300 10 ×
φ
+ 500
µ
A
PLL mode 0.1 ×
φ
+ 2 0.2 ×
φ
+ 3 mA
In STOP mode
IDD4
CESEL = 0, Note 1
250
µ
A
CESEL = 0, Note 2
2 200
µ
A
CESEL = 1, Note 1
30 200
µ
A
CESEL = 1, Note 2
30 500
µ
A
µ
PD70F3025A
Operating IDD1 Direct mode 2.5 ×
φ
+ 8 2.8 ×
φ
+ 22.5 mA
PLL mode 2.6 ×
φ
+ 10 2.9 ×
φ
+ 25.5 mA
In HALT mode
IDD2 Direct mode 1.3 ×
φ
+ 7.5 1.4 ×
φ
+ 15 mA
PLL mode 1.3 ×
φ
+ 12.5 1.4 ×
φ
+ 20 mA
In IDLE mode IDD3 Direct mode 8 ×
φ
+ 300 10 ×
φ
+ 500
µ
A
PLL mode 0.1 ×
φ
+ 2 0.2 ×
φ
+ 3 mA
In STOP mode
IDD4
CESEL = 0, Note 1
250
µ
A
CESEL = 0, Note 2
2 200
µ
A
CESEL = 1, Note 1
60 300
µ
A
CESEL = 1, Note 2
60 500
µ
A
Notes 1. –40°C ≤ TA ≤ +50°C
2. 50°C < TA ≤ 85°C
Remarks 1. TYP. values are reference values for when TA = 25°C (except for the conditions in Note 2) and VDD
= 5.0 V. The power supply current does not include AVREF1 to AVREF3 or the current that flows through
software pull-up resistors.
2.
φ
: Internal system clock frequency
µ
PD70F3003A, 70F3025A, 70F3003A(A)
19
Data Sheet U13189EJ5V0DS
Data Retention Characteristics (TA = –40 to +85°C, VDD = VDDDR)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data hold voltage VDDDR STOP mode 1.5 5.5 V
Data hold current IDDDR
µ
PD70F3003A,
CESEL = 0, Note 1 0.4VDDDR 50
µ
A
70F3003A(A)
CESEL = 0, Note 2 0.4VDDDR 200
µ
A
CESEL = 1, Note 1 6VDDDR 200
µ
A
CESEL = 1, Note 2 6VDDDR 500
µ
A
µ
PD70F3025A
CESEL = 0, Note 1 0.4VDDDR 50
µ
A
CESEL = 0, Note 2 0.4VDDDR 200
µ
A
CESEL = 1, Note 1 12VDDDR 300
µ
A
CESEL = 1, Note 2 12VDDDR 500
µ
A
Supply voltage rise time tRVD 200
µ
s
Supply voltage fall time tFVD 200
µ
s
Supply voltage hold time tHVD 0ms
(vs. STOP mode setting)
STOP mode release signal input time tDREL 0ns
Data hold input voltage, high VIHDR Note 3 0.9VDDDR VDDDR V
Data hold input voltage, low VILDR Note 3 0 0.1VDDDR V
Notes 1. –40°C
≤
TA
≤
+50°C
2. 50°C <TA
≤
85°C
3. P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins.
Remark TYP. values are reference values for when TA = 25°C (except for the conditions in Note 2) and VDD =
5.0 V.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
20 Data Sheet U13189EJ5V0DS
t
HVD
V
DD
V
DD
t
FVD
t
RVD
t
DREL
V
DD
V
DDDR
RESET (input) V
IHDR
NMI (input)
(Release by falling edge) V
IHDR
V
ILDR
NMI (input)
(Release by rising edge)
STOP mode is set (at fifth clock after PSC register has been set).
µ
PD70F3003A, 70F3025A, 70F3003A(A)
21
Data Sheet U13189EJ5V0DS
AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
AC test input test points
(a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and
their alternate-function pins
(b) Other than (a)
AC test output test points
Load condition
C
L
= 50 pF
DUT
(tested device)
Caution If the load capacitance exceeds 50 pF due to the circuit configuration,
decrease the load capacitance of this device to less then 50 pF by using a buffer.
Test points
0.8VDD
0.2VDD
0.8VDD
0.2VDD
VDD
0 V
Test points
2.2 V
0.8 V
2.2 V
0.8 V
2.4 V
0.4 V
Test points
2.2 V
0.8 V
2.2 V
0.8 V
µ
PD70F3003A, 70F3025A, 70F3003A(A)
22 Data Sheet U13189EJ5V0DS
(1) Clock timing
Parameter Symbol Conditions MIN. MAX. Unit
X1 input cycle <1> tCYX Direct mode 15 Note 1 ns
PLL mode 151Note 2 Note 3 ns
(PLL lock status)
X1 input width, high <2> tWXH Direct mode 6 ns
PLL mode 60 ns
X1 input width, low <3> tWXL Direct mode 6 ns
PLL mode 60 ns
X1 input rise time <4> tXR Direct mode 7 ns
PLL mode 10 ns
X1 input fall time <5> tXF Direct mode 7 ns
PLL mode 10 ns
CPU operating frequency —
φ
Note 4 33 MHz
CLKOUT output cycle <6> tCYK 30 Note 5 ns
CLKOUT width, high <7> tWKH 0.5 T – 5ns
CLKOUT width, low <8> tWKL 0.5 T – 5ns
CLKOUT rise time <9> tXR 5 ns
CLKOUT fall time <10> tXF 5 ns
X1 ↓→ CLKOUT delay time <11> tDXK Direct mode 3 17 ns
Notes 1. When A/D converter used: 100 ns
When A/D converter not used: 250 ns
2. When using A/D converter: The value when
φ
= 5 × fXX and
φ
= fXX are set. Setting
φ
= 1/2 × fXX is
prohibited.
When not using A/D converter: The value when
φ
= 5 × fXX,
φ
= fXX, and
φ
= 1/2 × fXX are set.
3. When using A/D converter: 250 ns (when
φ
= 5 × fXX is set) and 200 ns (when
φ
= fXX is set). Setting
φ
= 1/2 × fXX is prohibited.
When not using A/D converter: 250 ns (when
φ
= 5 × fXX,
φ
= fXX, and
φ
= 1/2 × fXX are set).
4. When A/D converter used: 5 MHz
When A/D converter not used: 2 MHz
5. When A/D converter used: 200 ns
When A/D converter not used: 500 ns
Remark T = tCYK
<1>
<2>
<4>
<11>
<5> <6>
<7>
<9> <10>
<8>
<3>
X1 (input)
CLKOUT (output)
<11>
µ
PD70F3003A, 70F3025A, 70F3003A(A)
23
Data Sheet U13189EJ5V0DS
(2) Input wave
(a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and their
alternate-function pins
Parameter Symbol Conditions MIN. MAX. Unit
Input rise time <12> tIR2 20 ns
Input fall time <13> tIF2 20 ns
(b) Other than (a)
Parameter Symbol Conditions MIN. MAX. Unit
Input rise time <14> tIR1 10 ns
Input fall time <15> tIF1 10 ns
2.2 V
0.8 V
2.2 V
0.8 V
2.4 V
0.4 V
Input signal
< 15 > < 14 >
0.8V
DD
0.2V
DD
0.8V
DD
0.2V
DD
V
DD
0 V
Input signal
< 13 > < 12 >
µ
PD70F3003A, 70F3025A, 70F3003A(A)
24 Data Sheet U13189EJ5V0DS
(3) Output wave (other than CLKOUT)
Parameter Symbol Conditions MIN. MAX. Unit
Output rise time <16> tOR 10 ns
Output fall time <17> tOF 10 ns
(4) Reset timing
Parameter Symbol Conditions MIN. MAX. Unit
RESET width, high <18> tWRSH 500 ns
RESET width, low <19> tWRSL On power appli- 500 + TOST ns
cation, or on
releasing STOP
mode
Except on power 500 ns
application, or
except on releas-
ing STOP mode
Remark TOST: Oscillation stabilization time
0.8 V
2.2 V
Output signal
< 16 > < 17 >
2.2 V
0.8 V
RESET (input)
< 18 > < 19 >
µ
PD70F3003A, 70F3025A, 70F3003A(A)
25
Data Sheet U13189EJ5V0DS
(5) Read timing (1/2)
Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address
<20> tDKA 3 20 ns
Delay time from CLKOUT↑ to R/W, UBEN, LBEN
<78> tDKA2 –2 +13 ns
Delay time from CLKOUT↑ to address float
<21> tFKA 3 15 ns
Delay time from CLKOUT↓ to ASTB
<22> tDKST 3 15 ns
Delay time from CLKOUT↓ to DSTB
<23> tDKD 3 15 ns
Data input setup time (to CLKOUT↑)
<24> tSIDK 5 ns
Data input hold time (from CLKOUT↑)
<25> tHKID 5 ns
WAIT setup time (to CLKOUT↓) <26> tSWTK 5 ns
WAIT hold time (from CLKOUT↓) <27> tHKWT 5 ns
Address hold time (from CLKOUT↑)
<28> tHKA 0 ns
Address setup time (to ASTB↓) <29> tSAST
–40°C ≤ TA ≤ +70°C
0.5 T – 10 ns
70°C < TA ≤ 85°C
0.5 T – 12 ns
Address hold time (from ASTB↓) <30> tHSTA 0.5 T – 10 ns
Delay time from DSTB↓ to address float
<31> tFDA 0 ns
Data input setup time (to address) <32> tSAID
–40°C ≤ TA ≤ +70°C
(2 + n) T – 22 ns
70°C < TA ≤ 85°C
(2 + n) T – 25 ns
Data input setup time (to DSTB↓) <33> tSDID
–40°C ≤ TA ≤ +70°C
(1 + n) T – 20 ns
70°C < TA ≤ 85°C
(1 + n) T – 24 ns
Delay time from ASTB↓ to DSTB↓<34> tDSTD 0.5 T – 10 ns
Data input hold time (from DSTB↑) <35> tHDID 0 ns
Delay time from DSTB↑ to address output
<36> tDDA (1 + i) T ns
Delay time from DSTB↑ to ASTB↑<37> tDDSTH 0.5 T – 10 ns
Delay time from DSTB↑ to ASTB↓<38> tDDSTL (1.5 + i) T – 10 ns
DSTB low-level width <39> tWDL
–40°C ≤ TA ≤ +70°C
(1 + n) T – 10 ns
70°C < TA ≤ 85°C
(1 + n) T – 13 ns
ASTB high-level width <40> tWSTH T – 10 ns
WAIT setup time (to address) <41> tSAWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
1.5 T – 20 ns
n ≥ 1, 70°C < TA ≤ 85°C
1.5 T – 24 ns
<42> tSAWT2
n ≥ 1, –40°C ≤ TA ≤ +70°C
(1.5 + n) T – 20 ns
n ≥ 1, 70°C < TA ≤ 85°C
(1.5 + n) T – 24 ns
WAIT hold time (from address) <43> tHAWT1 n ≥ 1 (0.5 + n) T ns
<44> tHAWT2 n ≥ 1 (1.5 + n) T ns
WAIT setup time (to ASTB↓) <45> tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
T – 18 ns
n ≥ 1, 70°C < TA ≤ 85°C
T – 20 ns
<46> tSSTWT2 n ≥ 1 (1 + n) T – 15 ns
WAIT hold time (from ASTB↓) <47> tHSTWT1 n ≥ 1 nT ns
<48> tHSTWT2 n ≥ 1 (1 + n) T ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle.
4. Be sure to observe at least one of data input hold times tHKID (<25>) and tHDID (<35>).
µ
PD70F3003A, 70F3025A, 70F3003A(A)
26 Data Sheet U13189EJ5V0DS
(5) Read Timing (2/2): 1 wait
T1 T2 TW T3
CLKOUT (output)
A16 to A19 (output)
AD0-AD15 (I/O)
ASTB (output)
DSTB (output)
WAIT (input)
< 32 >
< 20 >
< 78 >
< 28 >
R/W (output)
UBEN (output)
LBEN (output)
< 25 >< 24 >< 21 >
A0 to A15 (output) D0 to D15 (input)
< 22 >
< 29 > < 30 > < 22 >
< 35 >
< 37 >
< 36 >< 23 >
< 31 >
< 23 >< 40>
< 33 >< 34 >
< 39 >
< 38 >
< 26 > < 27 >< 26 >
< 47 >
< 46 >
< 48 >
< 27 >< 45 >
< 41 >
< 44 >
< 43 >
< 42 >
Remark Broken line indicates high-impedance.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
27
Data Sheet U13189EJ5V0DS
(6) Write timing (1/2)
Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address
<20> tDKA 3 20 ns
Delay time from CLKOUT↑ to R/W, UBEN, LBEN
<78> tDKA2 –2 +13 ns
Delay time from CLKOUT↓ to ASTB
<22> tDKST 3 15 ns
Delay time from CLKOUT↑ to DSTB
<23> tDKD 3 15 ns
WAIT setup time (to CLKOUT↓) <26> tSWTK 5 ns
WAIT hold time (from CLKOUT↓) <27> tHKWT 5 ns
Address hold time (from CLKOUT↑)
<28> tHKA 0 ns
Address setup time (to ASTB↓) <29> tSAST
–40°C ≤ TA ≤ +70°C
0.5 T – 10 ns
70°C < TA ≤ 85°C
0.5 T – 12 ns
Address hold time (from ASTB↓) <30> tHSTA 0.5 T – 10 ns
Delay time from ASTB↓ to DSTB↓<34> tDSTD 0.5 T – 10 ns
Delay time from DSTB
↑
to ASTB
↑
<37> tDDSTH 0.5 T – 10 ns
DSTB low-level width <39> tWDL
–40°C ≤ TA ≤ +70°C
(1 + n) T – 10 ns
70°C < TA ≤ 85°C
(1 + n) T – 13 ns
ASTB high-level width <40> tWSTH T – 10 ns
WAIT setup time (to address) <41> tSAWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
1.5 T – 20 ns
n ≥ 1, 70°C < TA ≤ 85°C
1.5 T – 24 ns
<42> tSAWT2
n ≥ 1, –40°C ≤ TA ≤ +70°C
(1.5 + n) T – 20 ns
n ≥ 1, 70°C < TA ≤ 85°C
(1.5 + n) T – 24 ns
WAIT hold time (from address) <43> tHAWT1 n ≥ 1 (0.5 + n) T ns
<44> tHAWT2 n ≥ 1 (1.5 + n) T ns
WAIT setup time (to ASTB↓) <45> tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
T – 18 ns
n ≥ 1, 70°C < TA ≤ 85°C
T – 20 ns
<46> tSSTWT2 n ≥ 1
(1 + n) T – 15 ns
WAIT hold time (from ASTB↓) <47> tHSTWT1 n ≥ 1 nT ns
<48> tHSTWT2 n ≥ 1 (1 + n) T ns
Address hold time (from CLKOUT↑)
<49> tDKOD
–40°C ≤ TA ≤ +70°C
20 ns
70°C < TA ≤ 85°C
23 ns
Delay time from DSTB↓ to data output
<50> tDDOD 10 ns
Data output hold time (from CLKOUT↑)
<51> tHKOD 0 ns
Data output setup time (to DSTB↑) <52> tSODD
(1 + n) T – 15 ns
Data output hold time (from DSTB↑)
<53> tHDOD T – 10 ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
28 Data Sheet U13189EJ5V0DS
(6) Write timing (2/2): 1 wait
T1 T2 TW T3
CLKOUT (output)
A16 to A19 (output)
AD0-AD15 (I/O)
ASTB (output)
DSTB (output)
WAIT (input)
< 20 > < 28 >
R/W (output)
UBEN (output)
LBEN (output)
< 78 >
< 49 >
A0 to A15 (output)
D0 to D15 (output)
< 22 >
< 29 > < 30 > < 22 >
< 37 >
< 53 >
< 23 >
< 23 >
< 40 >
< 52 >< 34 >
< 39 >
< 26 > < 27 >< 26 >
< 47 >
< 46 >
< 48 >
< 27 >< 45 >
< 41 >
< 44 >
< 43 >
< 42 >
< 51 >
Remark Broken line indicates high-impedance.
< 50 >
µ
PD70F3003A, 70F3025A, 70F3003A(A)
29
Data Sheet U13189EJ5V0DS
(7) Bus hold timing (1/2)
Parameter Symbol Conditions MIN. MAX. Unit
HLDRQ setup time (to CLKOUT↓) <54> tSHOK 5 ns
HLDRQ hold time (from CLKOUT↓) <55> tHKHQ 5 ns
Delay time from HLDAK to CLKOUT↑
<56> tDKHA 20 ns
HLDRQ high-level width <57> tWHQH T + 10 ns
HLDAK low-level width <58> tWHAL
–40°C ≤ TA ≤ +70°C
T – 10 ns
70°C < TA ≤ 85°C
T – 12 ns
Delay time from CLKOUT↑ to bus float
<59> tDKF 20 ns
Delay time from HLDAK↑ to bus output
<60> tDHAC –3ns
Delay time from HLDRQ↓ to HLDAK↓
<61> tDHQHA1
(2 n + 7.5) T + 20 ns
Delay time from HLDRQ↑ to HLDAK↑
<62> tDHQHA2 0.5 T 1.5 T + 20 ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when
the programmable wait state is inserted.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
30 Data Sheet U13189EJ5V0DS
(7) Bus hold timing (2/2)
TH TH TH TITH
CLKOUT (output)
HLDAK (output)
DSTB (output)
HLDRQ (input)
ASTB (output)
AD0 to AD15 (I/O)
D0 to D15
(input or output)
< 55 >
< 61 > < 62 >
< 57 >
< 54 >
< 54 >
< 56 >
< 58 >
< 56 >
< 60 >
Note UBEN (output), LBEN (output)
Remark Broken line indicates high-impedance.
A16 to A19 (output)
Note
< 59 >
R/W (output)
µ
PD70F3003A, 70F3025A, 70F3003A(A)
31
Data Sheet U13189EJ5V0DS
(8) Interrupt timing
Parameter Symbol Conditions MIN. MAX. Unit
NMI width, high <63> tWNIH 500 ns
NMI width, low <64> tWNIL 500 ns
INTPn width, high <65> tWITH n = 110 to 113, 3 T + 10 ns
120 to 123, 130
to 133, 140 to 143
INTPn width, low <66> tWITL n = 110 to 113, 3 T + 10 ns
120 to 123, 130
to 133, 140 to 143
Remark T = tCYK
NMI (input)
< 63 > < 64 >
INTPn (input)
< 65 > < 66>
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
µ
PD70F3003A, 70F3025A, 70F3003A(A)
32 Data Sheet U13189EJ5V0DS
(9) CSI timing (1/2)
(a) Master mode
(i) CSI0 to CSI2 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCKn cycle <67> tCYSK1 Output 120 ns
SCKn high-level width <68> tWSKH1 Output 0.5 tCYSK1 – 20 ns
SCKn low-level width <69> tWSKL1 Output 0.5 tCYSK1 – 20 ns
SIn setup time (to SCKn↑)<70> tSSISK1 30 ns
SIn hold time (from SCKn↑)<71> tHSKSI1 0 ns
SOn output delay time (from SCKn↓)
<72> tDSKSO1 18 ns
SOn output hold time (from SCKn↑)
<73> tHSKSO1 0.5 tCYSK1 – 5ns
Remark n = 0 to 2
(ii) CSI3 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCK3 cycle <67> tCYSK3 Output 500 ns
SCK3 high-level width <68> tWSKH3 Output
0.5 tCYSK3 – 70 ns
SCK3 low-level width <69> tWSKL3 Output
0.5 tCYSK3 – 70 ns
SI3 setup time (to SCK3↑) <70> tSSISK3 100 ns
SI3 hold time (from SCK3↑) <71> tHSKSI3 50 ns
SO3 output delay time (from SCK3↓)
<72> tDSKSO3 RL = 1.5 KΩ 150 ns
CL = 50 pF
SO3 output hold time (from SCK3↑)
<73> tHSKSO3 0.5 tCYSK3 – 5ns
Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
(b) Slave mode
(i) CSI0 to CSI2 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCKn cycle <67> tCYSK2 Input 120 ns
SCKn high-level width <68> tWSKH2 Input 30 ns
SCKn low-level width <69> tWSKL2 Input 30 ns
SIn setup time (to SCKn↑) <70> tSSISK2 10 ns
SIn hold time (from SCKn↑) <71> tHSKSI2 10 ns
SOn output delay time (from SCKn↓)
<72> tDSKSO2 30 ns
SOn output hold time (from SCKn↑)
<73> tHSKSO2 tWSKH2 ns
Remark n = 0 to 2
RL = 1.5
kΩ
CL = 50
pF
µ
PD70F3003A, 70F3025A, 70F3003A(A)
33
Data Sheet U13189EJ5V0DS
(9) CSI timing (2/2)
(ii) CSI3 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCK3 cycle <67> tCYSK4 Input 500 ns
SCK3 high-level width <68> tWSKH4 Input 180 ns
SCK3 low-level width <69> tWSKL4 Input 180 ns
SI3 setup time (to SCK3↑) <70> tSSISK4 100 ns
SI3 hold time (from SCK3↑) <71> tHSKSI4 50 ns
SO3 output delay time (from SCK3↓)
<72> tDSKSO4 RL = 1.5 kΩ 150 ns
SO3 output hold time (from SCK3↑)
<73> tHSKSO4 CL = 50 pF tWSKH4 ns
Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
SCKn (I/O)
SIn (input)
SOn (output)
< 67 >
< 69 > < 68 >
< 70 > < 71 >
< 72 >
< 73 >
Input data
Output data
Remark 1. The broken line indicates the high-impedance state.
2. n = 0 to 3
µ
PD70F3003A, 70F3025A, 70F3003A(A)
34 Data Sheet U13189EJ5V0DS
(10) RPU timing
Parameter Symbol Conditions MIN. MAX. Unit
TI1n high-level width <74> tWTIH 3 T + 10 ns
TI1n low-level width <75> tWTIL 3 T + 10 ns
TCLR1n high-level width <76> tWTCH 3 T + 10 ns
TCLR1n low-level width <77> tWTCL 3 T + 10 ns
Remark T = tCYK
TI1n (input)
<74> <75>
TCLR1n (input)
<76> <77>
Remark n = 1 to 4
µ
PD70F3003A, 70F3025A, 70F3003A(A)
35
Data Sheet U13189EJ5V0DS
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution — 10 10 10 bit
Overall errorNote 1 —4.5 V ≤ AVREF1 ≤ AVDD ±0.4 %FSR
—3.5 V ≤ AVREF1 ≤ AVDD ±0.7 %FSR
Quantization error — ±1/2 LSB
Conversion time tCONV 4.5 V ≤ AVREF1 ≤ AVDD 60 tCYK
3.5 V ≤ AVREF1 ≤ AVDD 60 tCYK
Sampling time tSAMP 4.5 V ≤ AVREF1 ≤ AVDD 10 tCYK
3.5 V ≤ AVREF1 ≤ AVDD 10 tCYK
Zero-scale errorNote 1 —4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±3.5 LSB
—3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 LSB
Full-scale errorNote 1 —4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±2.5 LSB
—3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 LSB
Non-linearity errorNote 1 —4.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±2.5 LSB
—3.5 V ≤ AVREF1 ≤ AVDD ±1.5 ±4.5 LSB
Analog input VIAN –0.3 AVDD + 0.3 V
voltageNote 2
Reference voltage AVREF1 3.5 AVDD V
AVREF1 current AIREF1 1.2 3.0 mA
AVDD supply current AIDD 2.3 6.0 mA
Notes 1. Except quantization error.
2. The conversion result is 000H when VIAN = 0.
Converted with 10-bit resolution when 0 < VIAN < AVREF1.
The conversion result is 3FFH when AVREF1 ≤ VIAN ≤ AVDD.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
36 Data Sheet U13189EJ5V0DS
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution — 8 8 8 bit
Overall error —Load conditions: 2 MΩ, 30 pF 0.8 %
AVREF2 = VDD
AVREF3 = 0
—Load conditions: 2 MΩ, 30 pF 1.0 %
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
—Load conditions: 4 MΩ, 30 pF 0.6 %
AVREF2 = VDD
AVREF3 = 0
—Load conditions: 4 MΩ, 30 pF 0.8 %
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
Settling time —Load conditions: 2 MΩ, 30 pF 10
µ
s
Output resistance RO 8 kΩ
AVREF2 input voltage AVREF2
0.75VDD VDD V
AVREF3 input voltage AVREF3 0
0.25VDD V
Resistance between RAIREF DACS0, DACS1 = 55H 2 4 kΩ
AVREF2 and AVREF3
µ
PD70F3003A, 70F3025A, 70F3003A(A)
37
Data Sheet U13189EJ5V0DS
3.2 Flash Memory Programming Mode
Basic Characteristics (TA = 10 to 40°C (when rewriting), TA = –40 to +85°C (when not rewriting), VDD = AVDD
= 5 V ±10%, VSS = AVSS = 0 V))
(1)
µ
PD70F3003A (all ranks), 70F3025A (except K, E, P, X rank)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating frequency
φ
10 33 MHz
VPP supply voltage VPP1
During flash memory programming
9.7 10.3 10.6 V
VPPL VPP low-level detection –0.5 0.2VDD V
VPPM VPP, VDD level detection 0.8VDD 1.2VDD V
VPPH VPP high-voltage level detection 9.7 10.3 10.6 V
VDD supply current IDO VPP = VPP1
3.0 ×
φ
+ 25
mA
VPP supply current IPP VPP = 10.3 V 200 mA
Step erase time tER Note 1 0.2 s
Overall erase time per area tERA
When the step erase time = 0.2 s, Note 2
40 s/area
Write-back time tWB Note 3 5ms
Number of write-backs per CWB When the write-back time 50
Count/write-
write-back command = 5 ms, Note 4
back command
Number of erase/write-backs CERWB 16 Count
Step writing time tWT Note 5 50
µ
s
Overall writing time per word tWTW When the step writing time = 50 50 500
µ
s/word
µ
s (1 word = 4 bytes), Note 6
Number of rewrites per area CERWR 1 erase + 1 write after erase 20
Count/area
= 1 rewrite, Note 7
Notes 1. The recommended setting value of the step erase time is 0.2 s.
2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included.
3. The recommended setting value of the step erase time is 5 ms.
4. Write-back is executed once by the issuance of the write-back command. Therefore, the retry count
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step writing time is 50
µ
s.
6. 100
µ
s is added to the actual writing time per word. The internal verify time during and after the writing
is not included.
7. When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and “write
only”.
Example (P: Write, E: Erase)
Shipped product → P→ E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
µ
PD70F3003A, 70F3025A, 70F3003A(A)
38 Data Sheet U13189EJ5V0DS
Cautions 1. VPP pull-down resistance value (RVPP) is recommended to be in the range 5 kΩ to 15 kΩ.
2. Set the transfer rate between programmer and device as follows.
CSI0: 0.2 to 1 MHz
UART0: 4,800 to 76,800 bps
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter
files is automatically set. Do not change the settings unless otherwise specified.
2. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH (area 1 is provided in the
µ
PD70F3025A
only)
3. The rank is indicated by the 5th character from the left in the lot number.
4. The I rank applies to engineering samples (ES) only. The operation of an ES is not guaranteed.
5.
φ
: Internal system clock frequency
µ
PD70F3003A, 70F3025A, 70F3003A(A)
39
Data Sheet U13189EJ5V0DS
(2)
µ
PD70F3025A (X rank)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operating frequency
φ
Note 1 10 33 MHz
VPP supply voltage VPP1
During flash memory programming
9.7 10.3 10.6 V
VPPL VPP low-level detection –0.5 0.2VDD V
VPPM VPP, VDD level detection 0.8VDD 1.2VDD V
VPPH VPP high-voltage level detection 9.7 10.3 10.6 V
VDD supply current IDD VPP= VPP1
3.0 ×
φ
+ 25
mA
VPP supply current IPP VPP= 10.3 V 200 mA
Step erase time tER Note 1 2s
Overall erase time per area tERA
When the step erase time = 2 s, Note 2
40 s/area
Step writing time tWT Note 3 200
µ
s
Overall writing time per word tWTW
When the step writing time = 200
200 2000
µ
s/word
µ
s (1 word = 4 bytes), Note 4
Number of rewrites per area CERWR 1 erase + 1 write after erase 20
Count/area
= 1 rewrite, Note 5
Notes 1. The recommended setting value of the step erase time is 2 s.
2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included.
3. The recommended setting value of the step writing time is 200
µ
s.
4. 100
µ
s is added to the actual writing time per word. The internal verify time during and after the writing
is not included.
5. When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and “write
only”.
Example (P: Write, E: Erase)
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
Cautions 1. VPP pull-down resistance value (RVPP) is recommended to be in the range 5 kΩ to 15 kΩ.
2. Set the transfer rate between programmer and device as follows.
CSI0: 0.2 to 1 MHz
UART0: 4,800 to 76,800 bps
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter
files is automatically set. Do not change the settings unless otherwise specified.
2. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH
3. The rank is indicated by the 5th character from the left in the lot number.
4. The K, E, P, and X rank products do not support handshake mode. The I rank applies to engineering
samples (ES) only. The operation of an ES is not guaranteed.
5.
φ
: Internal system clock frequency
µ
PD70F3003A, 70F3025A, 70F3003A(A)
40 Data Sheet U13189EJ5V0DS
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
16.00±0.20
14.00±0.20
0.50 (T.P.)
1.00
J
16.00±0.20
K
C 14.00±0.20
I 0.08
1.00±0.20
L0.50±0.20
F 1.00
N
P
Q
0.08
1.40±0.05
0.10±0.05
S100GC-50-8EU, 8EA-2
S 1.60 MAX.
H 0.22+0.05
−0.04
M 0.17+0.03
−0.07
R3°+7°
−3°
125
26
50
100
76
75 51
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
µ
PD70F3003A, 70F3025A, 70F3003A(A)
41
Data Sheet U13189EJ5V0DS
5. RECOMMENDED SOLDERING CONDITIONS
The
µ
PD70F3003A, 70F3025A, and 70F3003A(A) should be soldered and mounted under the following
recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 5-1. Soldering Mounting Type Soldering Conditions
(1)
µ
PD70F3003AGC-33-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
µ
PD70F3025AGC-33-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-103-3
(at 210°C or higher), Count: Three times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72
hours)
VPS Package peak temperature: 215°C, Time: 25 to 40 seconds VP15-103-3
(at 200°C or higher), Count: Three times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72
hours)
Partial heating Pin temperature: 300°C max., Time 3 seconds max. —
(per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. IR35-103-2
(at 210°C or higher), Count: Two times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72
hours)
VPS Package peak temperature: 215°C, Time: 25 to 40 seconds VP15-103-2
(at 200°C or higher), Count: Two times or less, Exposure
limit: 3 daysNote (after that, prebake at 125°C for 10 to 72
hours)
Partial heating Pin temperature: 300°C max., Time 3 seconds max. —
(per pin row)
(2)
µ
PD70F3003AGC(A)-33-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
µ
PD70F3003A, 70F3025A, 70F3003A(A)
42 Data Sheet U13189EJ5V0DS
APPENDIX NOTES ON TARGET SYSTEM DESIGN
The following shows a diagram of the connection conditions between the in-circuit emulator option board
and conversion connector. Design your system making allowances for conditions such as the form of parts
mounted on the target system as shown below.
Target system
Note YQSOCKET100SDN (included with IE-703002-MC) can be inserted here to adjust the height (height: 3.2 mm).
NQPACK100SD
YQPACK100SD
132.24 mm
Note
In-circuit emulator option board
Conversion connector
IE-703003-MC-EM1
Side view
Top view
Connection
condition diagram
In-circuit emulator
IE-703002-MC
YQGUIDE
Target system
YQPACK100SD, NQPACK100SD,
YQGUIDE
IE-703003-MC-EM1
IE-703002-MC
Pin 1 position
13.3 mm
24 mm 21.58 mm
15.24 mm
75 mm
31.84 mm
Target system
NQPACK100SD
YQPACK100SD
IE-703003-MC-EM1
Connect to
IE-703002-MC.
YQGUIDE
Pin 1 position
µ
PD70F3003A, 70F3025A, 70F3003A(A)
43
Data Sheet U13189EJ5V0DS
[MEMO]
µ
PD70F3003A, 70F3025A, 70F3003A(A)
44 Data Sheet U13189EJ5V0DS
[MEMO]
µ
PD70F3003A, 70F3025A, 70F3003A(A)
45
Data Sheet U13189EJ5V0DS
[MEMO]
µ
PD70F3003A, 70F3025A, 70F3003A(A)
46 Data Sheet U13189EJ5V0DS
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Related document:
µ
PD703003A, 703004A, 703025A, 703003A(A), 703025A(A) Data Sheet (U13188E)
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850 Series and V853 are trademarks of NEC Corporation.
µ
PD70F3003A, 70F3025A, 70F3003A(A)
47
Data Sheet U13189EJ5V0DS
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.12
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
•
Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
•
Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana S.R.L.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (France) S.A.
Vélizy-Villacoublay, France
Tel: 01-3067-58-00
Fax: 01-3067-58-99
NEC Electronics (France) S.A.
Representación en España
Madrid, Spain
Tel: 091-504-27-87
Fax: 091-504-28-60
µ
PD70F3003A, 70F3025A, 70F3003A(A)
M8E 00. 4
The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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