AX88170L - ASIX Electronics Corporation

ASIX ELECTRONICS CORPORATION Frist Released Date : Sep/11/2000

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.

TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw

AX88170 L

USB to Fast Ethernet/HomePNA Controller

Document No.: AX170-12 / V1.2 / Apr. 11 ’01

Features

• Single chip USB to 10/100Mbps Fast Ethernet and

1/10Mbps HomePNA Network Controller

• Compliant with USB specification 1.0 and 1.1

• Full Speed USB Device with bus power capability

• USB Communication Class Spec 1.0 Compliant

• Support 4 endpoints on USB

• IEEE 802.3u 100BASE-T, TX, and T4 Compatible

• Embedded 5K*16 bit SRAM

• Support both full-duplex or half-duplex operation on

Fast Ethernet

• Provides a MII port for both Ethernet and

HomePNA PHY interface

• Supports suspended mode and remote wakeup

(link_up or magic packet)

• Optional PHY power down mode for power saving

• Provides optional MII/RMII interface with PHY

mode for multiple ports USB-to-USB bridge

application.

• Support 256/512 bytes serial EEPROM (used for

saving USB Descriptors)

• Support automatic loading of Ethernet ID, USB

Descriptors and Adapter Configuration from

EEPROM on power-on initialization

• External PHY loop-back diagnostic capability

• Small form factor 64-pin LQFP package

• 48MHz and 25MHz Operation, pure 3.3V operation

with I/O 5V tolerance

*IEEE is a registered trademark of the Institute of Electrical and

Electronic Engineers, Inc.

*All other trademarks and registered trademark are the property of

their respective holders.

Product description

The AX88170 USB to Fast Ethernet/HomePNA Controller is a high performance and highly integrated Controller with

embedded 5K*16 bit SRAM. The AX88170 contains a USB interface to host CPU and compliant with USB Standard V1.0 and

V1.1. The interface between AX88170 and PC Host is compliant with USB Communication Class Specification 1.0. The

AX88170 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and

1M/10M HomePNA standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to

simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII

interface with PHY mode, combine with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge

application.

System Block Diagram

Always contact ASIX for possible updates before starting a design.

This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without

notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

AX88170

10/100 Mbps Ethernet

PHY/TxRx

MAGNETIC

RJ45

USB I/F

EEPROM

1/10 Mbps

Home LAN PHY

MAGNETIC

RJ11

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CONTENTS

1.0 INTRODUCTION...........................................................................................................................................................................4

1.1 GENERAL DESCRIPTION:............................................................................................................................................................4

1.2 AX88170 BLOCK DIAGRAM:......................................................................................................................................................4

1.3 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE ...........................................................................................5

1.4 AX88170 PIN CONNECTION DIAGRAM WITH RMII INTERFACE.........................................................................................6

2.0 SIGNAL DESCRIPTION...............................................................................................................................................................7

2.1 USB BUS INTERFACE SIGNALS GROUP ....................................................................................................................................7

2.2 EEPROM SIGNALS GROUP .........................................................................................................................................................7

2.3A MII INTERFACE SIGNALS GROUP (MAC MODE)..................................................................................................................7

2.3B MII INTERFACE SIGNALS GROUP (PHY MODE).....................................................................................................................8

2.4 RMII INTERFACE SIGNAL PINS (PHY MODE)..........................................................................................................................9

2.5 MISCELLANEOUS PINS GROUP...................................................................................................................................................9

3.0 EEPROM MEMORY MAPPING...............................................................................................................................................11

4.0 USB COMMANDS.......................................................................................................................................................................12

4.1 USB STANDARD COMMANDS...................................................................................................................................................12

4.2 USB COMMUNICATION CLASS COMMANDS.........................................................................................................................13

4.3 USB VENDOR COMMANDS.......................................................................................................................................................14

5.0 USB CONFIGURATION STRUCTURE...................................................................................................................................16

5.1 USB CONFIGURATION..............................................................................................................................................................16

5.2 USB INTERFACE CLASS............................................................................................................................................................16

5.3 USB ENDPOINTS........................................................................................................................................................................16

6.0 ELECTRICAL SPECIFICATION AND TIMINGS.................................................................................................................17

6.1 ABSOLUTE MAXIMUM RATINGS............................................................................................................................................17

6.2 GENERAL OPERATION CONDITIONS......................................................................................................................................17

6.3 DC CHARACTERISTICS..............................................................................................................................................................17

6.4 A.C. TIMING CHARACTERISTICS.............................................................................................................................................18

6.4.1 25M_XIN............................................................................................................................................................................18

6.4.2 48M_XIN............................................................................................................................................................................18

6.4.3 Reset Timing......................................................................................................................................................................18

6.4.4 MII Timing of MAC mode................................................................................................................................................20

6.4.5 MII Timing of PHY mode.................................................................................................................................................21

6.4.6 RMII Interface Timing of PHY Mode.............................................................................................................................22

6.4.7 STATION MANAGEMENT TIMING..............................................................................................................................23

6.4.8 SERIAL EEPROM TIMING.............................................................................................................................................24

7.0 PACKAGE INFORMATION.......................................................................................................................................................25

APPENDIX A: SYSTEM APPLICATIONS....................................................................................................................................26

A.1 USB TO FAST ETHERNET CONVERTER................................................................................................................................26

A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION................................................................................27

A.3 USB-TO-USB OR USB-TO-ETHERNET BRIDGE THROUGH ETHERNET REPEATER CONTROLLER............................28

A.4 USB-TO-USB OR USB-TO-ETHERNET BRIDGE THROUGH ETHERNET SWITCH CONTROLLER.................................28

DEMONSTRATION CIRCUIT A: AX88170 + ETHERNET PHY.............................................................................................29

DEMONSTRATION CIRCUIT B: AX88170 + HOMEPNA 1M8 PHY....................................................................................31

DEMONSTRATION CIRCUIT C: 4 USB PORTS + 1 ETHERNET PORT BRIDGE AP.....................................................33

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FIGURES

FIG - 1 AX88170 BLOCK DIAGRAM.....................................................................................................................................................4

FIG - 2 AX88170 PIN CONNECTION DIAGRAM WITH MII INTERFACE .........................................................................................5

FIG - 3 AX88170 PIN CONNECTION DIAGRAM RMII INTERFACE..................................................................................................6

TABLES

TAB - 1 USB BUS INTERFACE SIGNALS GROUP ..................................................................................................................................7

TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP .........................................................................................................................7

TAB - 3 MII INTERFACE SIGNALS GROUP (MAC MODE).................................................................................................................8

TAB - 4 MII INTERFACE SIGNALS GROUP (PHY MODE)...................................................................................................................8

TAB - 5 RMII INTERFACE SIGNAL PINS (PHY MODE).......................................................................................................................9

TAB - 6 MISCELLANEOUS PINS GROUP .............................................................................................................................................10

TAB - 7 EEPROM MEMORY MAPPING.............................................................................................................................................11

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1.0 Introduction

1.1 General Description:

The AX88170 USB to Fast Ethernet Controller is a high performance and highly integrated USB bus Ethernet Controller with

embedded 5K* 16 bit SRAM. The AX88170 contains a full speed USB interface to host CPU and compliant with USB

Communication Class Spec. 1.0. The AX88170 implements both 10Mbps and 100Mbps Ethernet function based on

IEEE802.3 / IEEE802.3u LAN standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII)

interface to simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional

MII/RMII interface with PHY mode, combines with Ethernet repeater or switch IC can build a multiple ports USB-to-USB

bridge application.

AX88170 uses 64-pin LQFP low profile package, 48MHz operation for USB and 25MHz operation for Ethernet, CMOS

process with pure 3.3V operation and 5 Volt I/O tolerance.

1.2 AX88170 Block Diagram:

Fig – 1 AX88170 Block Diagram

MAC

Core

Memory Arbiter

USB to

Ethernet

Bridge

USB Core and Interface

STA

SEEPROM

Loader I/F

D-/D+

MII I/F

Or

RMII I/F

SMDC

SMDIO

EECS

EECK

EEDI

EEDO

5K* 16

SRAM

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1.3 AX88170 Pin Connection Diagram with MII Interface

The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 2 AX88170 Pin Connection

Diagram.

Fig – 2 AX88170 Pin Connection Diagram with MII Interface

1

5

6

4

7

2

3

8

9

10

11

12

13

14

15

16

30

29

28

24

23

25

27

26

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18

17

19

31

21

20

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

64

63

61

62

60

59

58

57

56

55

54

50

49

COL

TEST0

VSS

VDD

/RST

VSS

VDD

VSS

VDD

VSS

RXD0

RXD1

RXD2

RXD3

RX_ER

RX_DV

TXD0

TXD1

TXD2

TXD3

CRS

TX_CLK

25M_XIN

VSS

VDD

52

53

51

VSS

D+

/S_RMII

/S_MAC

/S_FDPX

SPD_UP

EECS

AX88170 RX_CLK

TX_EN

TEST1

TEST2

D-

MDC

MDIO

/PHY_RST

25M_CLKO

25M_XOUT

48M_XIN

48M_XOUT

EECK

EEDI

EEDO

VSS

VDD

VSS

TEST3

LD_RDY

TEST_OUT

VDD

S_EXT

ACT/LINK

TEST4 (MII Interface)

GPIO0

GPIO1

/HomeLink

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1.4 AX88170 Pin Connection Diagram with RMII Interface

The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 3 AX88170 Pin Connection

Diagram RMII Interface.

Fig – 3 AX88170 Pin Connection Diagram RMII Interface

1

5

6

4

7

2

3

8

9

10

11

12

13

14

15

16

30

29

28

24

23

25

27

26

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18

17

19

31

21

20

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

64

63

61

62

60

59

58

57

56

55

54

50

49

COL

TEST0

VSS

VDD

/RST

VSS

VDD

VSS

VDD

VSS

RXD0

RXD1

NC

TXD0

TXD1

NC

CRS_DV

REF_CLK

25M_XIN

VSS

VDD

52

53

51

VSS

D+

/S_RMII

/S_MAC

/S_FDPX

SPD_UP

EECS

AX88170 NC

TX_EN

TEST1

TEST2

D-

MDC

MDIO

/PHY_RST

25M_CLKO

25M_XOUT

48M_XIN

48M_XOUT

EECK

EEDI

EEDO

VSS

VDD

VSS

TEST3

LD_RDY

TEST_OUT

VDD

S_EXT

ACT/LINK

TEST4 (RMII Interface)

GPIO0

GPIO1

/HomeLink

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2.0 Signal Description

The following terms describe the AX88170 pin-out:

All pin names with the “/” suffix are asserted low.

The following abbreviations are used in following Tables.

I Input PU Pull Up

O Output PD Pull Down

I/O Input/Output P Power Pin

OD Open Drain

2.1 USB Bus Interface Signals Group

SIGNAL TYPE PIN NO. DESCRIPTION

D+ I/O 1 USB Data Plus Pin

D- I/O 2 USB Data Minus Pin

Tab – 1 USB bus interface signals group

2.2 EEPROM Signals Group

SIGNAL TYPE PIN NO. DESCRIPTION

EECS O 45 EEPROM Chip Select : EEPROM chip select signal.

EECK O 46 EEPROM Clock : Signal connected to EEPROM clock pin.

EEDI O 47 EEPROM Data In : Signal connected to EEPROM data input pin.

EEDO I/PU 48 EEPROM Data Out : Signal connected to EEPROM data output pin.

Tab – 2 EEPROM bus interface signals group

2.3a MII interface signals group (MAC mode)

When /S_RMII=1 and /S_MAC=0

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[3:0]

I/PU 29, 28

27, 26

Receive Data: RXD[3:0] is driven by the PHY synchronously with respect

to RX_CLK.

CRS I/PD 15

Carrier Sense: Asynchronous signal CRS is asserted by the PHY when

either the transmit or receive medium is non-idle.

RX_DV I/PD 32 Rece

ive Data Valid: RX_DV is driven by the PHY synchronously with

respect to RX_CLK. Asserted high when valid data is present on RXD

[3:0].

RX_ER I/PD 31

Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is

asserted for one or more RX_CLK per

iods to indicate to the port that an

error has detected.

RX_CLK I/PU 24

Receive Clock: RX_CLK is a continuous clock that provides the timing

reference for the transfer of the RX_DV,RXD[3:0] and RX_ER signals from

the PHY to the MII port of the MAC.

COL I/PD 13 Collision: this signal is driven by PHY when collision is detected.

TX_EN O 22

Transmit Enable: TX_EN is transition synchronously with respect to the

rising edge of TX_CLK. TX_EN indicates that the port is presenting

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SIGNAL TYPE PIN NO. DESCRIPTION

nibbles on TXD [3:0] for transmission.

TXD[3:0] O 21, 20

19, 18

Transmit Data: TXD[3:0] is transition synchronously with respect to the

rising edge of TX_CLK. For each TX_CLK period in which TX_EN is

asserted ,TXD[3:0] are accepted for transmission by the PHY.

TX_CLK I 16 Transmit Cl

ock: TX_CLK is a continuous clock from PHY. It provides the

timing reference for the transfer of the TX_EN and TXD[3:0] signals from

the MII port to the PHY.

MDC O 12

Station Management Data Clock: The timing reference for MDIO. All data

transfers on MDIO

are synchronized to the rising edge of this clock. MDC

is a 2.5MHz frequency clock output.

MDIO I/O/PU 14

Station Management Data Input/Output: Serial data input/output transfers

from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII

specification.

Tab – 3 MII interface signals group (MAC mode)

2.3b MII interface signals group (PHY mode)

When /S_RMII=1 and /S_MAC=1

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[3:0]

O 29, 28

27, 26 Receive Data: Basically RXD[3:0] is tran

sformed from TXD[3:0] of MAC

mode of MII interface.

CRS O 15

Carrier Sense: Basically CRS is transformed from TX_EN of MAC mode of

MII interface.

RX_DV O 32

Receive Data Valid: Basically RX_DV is transformed from TX_EN of MAC

mode of MII interface.

RX_ER O 31 Receive Error: No used

RX_CLK O 24

Receive Clock: Basically RX_CLK is sourced from internal 25MHz local

clock.

COL O 13 Collision: this signal is generated by internal logic

when collision is

detected.

TX_EN I/PD 22 Transmit Enable: Basical

ly TX_EN is simulation from RX_DV of MAC

mode of MII interface.

TXD[3:0] I/PU 21, 20

19, 18

Transmit Data: Basically TXD[3:0] is simulation from RXD[3:0] of MAC

mode of MII interface.

TX_CLK O 16 Transmit Clock: Basically TX_CLK is sourced from inter

nal 25MHz local

clock.

Tab – 4 MII interface signals group (PHY mode)

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2.4 RMII interface signal pins (PHY mode)

When /S_RMII=0 and /S_MAC=1

SIGNAL TYPE PIN NO. DESCRIPTION

RXD[1:0]

O 27, 26 Receive Data : Basically RXD[1:0] is

transformed from TXD[1:0] of MAC

mode of RMII interface.

CRS_DV O 15 Carrier Sense _ Data Valid : Basically CRS_DV is

transformed of TX_EN

from MAC mode of RMII interface.

TXD[1:0]

I/PU

19, 18 Transmit Data : Basically TXD[1:0] is transformed from RX

D[1:0] of MAC

mode of RMII interface.

TX_EN

I/PD

22 Transmit Enable :

Basically TX_EN is transformed from RX_DV from MAC

mode of RMII interface.

REF_CLK I 16 Reference clock : The input is a continue clock at 50Mhz for

timing

reference with RMII interface.

Tab – 5 RMII interface signal pins (PHY mode)

2.5 Miscellaneous pins group

SIGNAL TYPE PIN NO. DESCRIPTION

25M_XIN I 35 CMOS Local Clock : Typical a 25Mhz clock, +/- 100 ppm, 40% -

60% duty

cycle. ( See application note also )

Crystal Oscillator Input : Typical a 25Mhz crystal, +/-

25 ppm can be

connected across 25M_XIN and 25M_XOUT.

25M_XOUT O 36 Crystal Oscillator Output : Typical a 25Mhz crystal, +/-

25 ppm can be

connected across 25M_XIN and 25M_XOUT. If a single -ended ex

ternal

clock is connected to 25M_XIN, the crystal output pin should be left

floating.

48M_XIN I 52 48Mhz CMOS Clock In : Typical a 48Mhz clock, +/- 500 ppm, 40%-

60% duty

cycle. ( See application note also )

48Mhz Crystal Oscillator Input: Typical a 48Mhz crystal, +/-

100 ppm can be

connected across 48M_XIN and 48M_XOUT.

48M_XOUT O 51 48Mhz Crystal Oscillator Output: Typical a 48Mhz crystal, +/-

100 ppm can

be connected across 48M_XIN and 48M_XOUT. If a single-

ended external

clock is connected to 48M_XIN,

the crystal output pin should be left

floating.

25M_CLKO O 33 Clock Output : This clock is source from 25M_XIN.

/RST I/PD 4 Reset:

Reset is active low

then place AX88170 into reset mode immediately.

During Rising edge the AX88170 loads the EEPROM data.

/S_RMII I/PU 43 Set to RMII mode:

0: RMII mode is selected.

1: MII mode is selected. (default)

/S_MAC I/PD 9 Set MII/RMII interface to MAC mode:

0: MAC mode is selected. (default)

1: PHY mode is selected.

/S_FDPX I/PD 8 Set duplex mode when PHY mode is

selected or When S_EXT is set and

MAC mode is selected:

0: full-duplex mode is selected. (default)

1: half-duplex mode is selected.

S_EXT I/PD 7 Select where duplex mode is sourced from when MAC mode:

0: duplex mode depands on internal register. (default)

1: duplex mode depands on external signal /S_FDPX

SPD_UP ID 6 The setting is enable speed up test mode:

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0: Normal operation mode.

1: Speed up test mode enable.

TEST0 I/PD 55 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST1 I/PD 56 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST2 I 57 Test Pin: This pin for test purpose only.

Pull down the pin for normal operation.

TEST3 I/PD 58 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST4 I/PD 61 Test Pin: This pin for test purpose only.

Pull down the pin or keep no connection for normal operation.

TEST_OUT O 60 Test Output Pin: This pin for test purpose only.

LDRDY O 62 Load EEPROM data completed indicator. Active high.

ACT/LINK O 63

LED indicator: When link fail, drives logic high always. When link OK, the

pin drives logic low and will drives high a period when line has activity

(data transfer).

/PHY_RST O 39 PHY Reset: This pin is used to reset PHY and is an active low signal.

GPIO0 B/PD 38 General Purpose I/O 0: Refer to section 4.3 USB Vendor Commands

GPIO1 B/PD 40 General Purpose I/O 1: Refer to section 4.3 USB Vendor Commands

/HOMELINK I/PU 41 Link Status: For external HomePHY link state input active low

VDD P 3, 10, 23, 30

37, 44, 50

54,59

Power Supply: +3.3V DC.

VSS P 5, 11

17, 25, 34

42, 49, 53

64

Power Supply: +0V DC or Ground Power.

Tab - 6 Miscellaneous pins group

MII/RMII interface Cross Reference Table

MII RMII

RXD[0] RXD[0]

RXD[1] RXD[1]

RXD[2]

RXD[3]

CRS CRS_DV

RX_DV

RX_CLK

RX_ER

TX_EN TX_EN

TX_CLK REF_CLK (50MHz)

TXD[0] TXD[0]

TXD[1] TXD[1]

TXD[2]

TXD[3]

COL

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3.0 EEPROM Memory Mapping

EEPROM

OFFSET HIGH BYTE LOW BYTE

00H RESERVED WORD COUNT FOR PRELOAD

01H *FLAG

02H LENGTH OF DEVICE DESCRIPTOR (BYTE) EEPROM OFFSET OF DEVICE

DESCRIPTOR

03H LENGTH OF CONFIGURATION DESCRIPTOR

(BYTE) EEPROM OFFSET OF CONFIGURATION

DESCRIPTOR

04H NODE ID 1 NODE ID 0

05H NODE ID 3 NODE ID 2

06H NODE ID 5 NODE ID 4

07H LANGUAGE ID HIGH BYTE LANGUAGE ID LOW BYTE

08H LENGTH OF STRING INDEX 1 EEPROM OFFSET OF STRING INDEX 1

09H LENGTH OF STRING INDEX 2 EEPROM OFFSET OF STRING INDEX 2

0AH LENGTH OF STRING INDEX 3 EEPROM OFFSET OF STRING INDEX 3

0BH LENGTH OF STRING INDEX 4 EEPROM OFFSET OF STRING INDEX 4

0CH LENGTH OF STRING INDEX 5 EEPROM OFFSET OF STRING INDEX 5

0DH LENGTH OF STRING INDEX 6 EEPROM OFFSET OF STRING INDEX 6

0EH LENGTH OF STRING INDEX 7 EEPROM OFFSET OF STRING INDEX 7

0FH LENGTH OF STRING INDEX 8 EEPROM OFFSET OF STRING INDEX 8 (19H)

10H MAX PACKETSIZE HIGH BYTE MAX PACKET LOW BYTE

11H HOMEPNA PHY ID ETHERNET PHY ID

12H PAUSE PACKET HIGH WATER LEVEL PAUSE PACKET LOW WATER LEVEL

13H-18H RESERVED

19H 03H 0CH

1AH BYTE 2 OF UNICODE MAC ADDRESS **BYTE 1 OF UNICODE MAC ADDRESS

1BH BYTE 4 OF UNICODE MAC ADDRESS BYTE 3 OF UNICODE MAC ADDRESS

1CH BYTE 6 OF UNICODE MAC ADDRESS BYTE 5 OF UNICODE MAC ADDRESS

1DH BYTE 8 OF UNICODE MAC ADDRESS BYTE 7 OF UNICODE MAC ADDRESS

1EH BYTE 10 OF UNICODE MAC ADDRESS BYTE 9 OF UNICODE MAC ADDRESS

1FH BYTE 12 OF UNICODE MAC ADDRESS BYTE 11 OF UNICODE MAC ADDRESS

20H-4FH DEVICE /CONFIGURATION /INTERFACE /ENDPOINT DESCRIPTOR

50H-FFH STRINGS

Tab - 7 EEPROM Memory Mapping

Note:

*Flag: Bit 0 è Self Powered (for USB GetStatus) Bit 1 è Bus Powered (Reserved)

Bit 2 è Remote Wakeup (for USB GetStatus) Bit 3 è Interrupt Endpoint Enaable (Reserved)

Bit 4 è ClkNoStop (for Self Power only) Bit 5 è Reserved

Bit 6 è Reserved Bit 7 è Reserved

Bit 8 è Capture Effective Mode Bit 9 è Flow Control selector (1: software, o: read from PHY)

Bit A – F è Reserved

Bit 4 also effect LED display, if high then LED display USB active only otherwise display USB link and activity.

(In Self power mode Bit_4 set to high)

**Unicode MAC Address:

If the MAC’s NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, … NODE ID5 Then

the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC ADDRESS- BYTE

2 OF UNICODE MAC ADDRESS, … -BYTE 12 OF UNICODE MAC ADDRESS.

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4.0 USB Commands

There are three command groups for Endpoint 0 in AX88170:

l The USB standard commands

l USB Communication Class commands

l USB vendor commands.

4.1 USB standard commands

** The Language ID is 0x0904 for English

** PPLL means buffer length

** CC means configuration number

** I I means Interface number

SETUP COMMAND DATA IN/OUT DESCRIPTION

80 06 00 01 00 00 LL PP Data PPLL bytes Get Device Descriptor

80 06 00 02 00 00 LL PP Data PPLL bytes Get Configuration Descriptor

80 06 00 03 00 00 LL PP Data 2 bytes Get Supported Language ID

80 06 01 03 09 04 LL PP Data PPLL bytes Get Manufacture String

80 06 02 03 09 04 LL PP Data PPLL bytes Get Product String

80 06 03 03 09 04 LL PP Data PPLL bytes Get Serial Number String

80 06 04 03 09 04 LL PP Data PPLL bytes Get Configuration String

80 06 05 03 09 04 LL PP Data PPLL bytes Get Interface 0 String

80 06 06 03 09 04 LL PP Data PPLL bytes Get Interface 1/0 String

80 06 07 03 09 04 LL PP Data PPLL bytes Get Interface 1/1 Stirng

80 06 08 03 09 04 LL PP Data 12 bytes Get Ethernet Address String

80 08 00 00 00 00 01 00 Data 1 bytes Get Configuration

00 09 CC 00 00 00 00 00 No Data Set Configuration

81 0A 00 00 I I 00 01 00 Data 1 byte Get Interface

01 0B AS 00 01 00 00 00 No Data Set Interface

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4.2 USB Communication Class Commands

** NN: number of multicast addresses

** BBAA: Ethernet Packet Filter

** TTSS: Number of Ethernet Statics

SETUP COMMAND DATA IN/OUT DESCRIPTION

21 40 NN 00 00 00 6*N 00 Data 6*N bytes Set Ethernet Multicast Filters

21 41 00 00 00 00 10 00 Data 16 bytes Set Ethernet Power Management Pattern

A1 42 00 00 00 00 02 00 Data 2 bytes Get Ethernet Power Management Pattern

21 43 AA BB 00 00 00 00 No Data Set Ethernet Packet Filter (AA BB)

Description of Ethernet Packet Filter (AA BB) Bitmap

BB = [D15:D8]

AA = [D7:D0]

Bit position DESCRIPTION

D15..D5 RESERVED (Reset to Zero)

D4 PACKET_TYPE_MULTICAST

1: All multicast packets enumerated in the device’s multicast address list are

forwarded up to the host.

0: Disabled.

D3 PACKET_TYPE_BROADCAST

1: All broadcast packet packets received by the networking device are forwarded

up to the host.

0: Disable.

D2 PACKET_TYPE_DIRECTED

1: Directed packets received containing a destination address equal to the MAC

address of the networking device are forwarded up to the host.

0: Always not set to Zero.

D1 PACKET_TYPE_ALL_MULTICAST

1 : ALL multicast frames received by the networking device are forwarded up to

the host, not just the ones enumerated in the device’s multicast address list.

0: Disabled.

D0 PACKET_TYPE_PROMISCUOUS

1: ALL frames received by the networking device are forwarded up to the host.

0: Disabled.

Tab - 9 Ethernet Packet Filter Bitmap

ASIX ELECTRONICS CORPORATION 14

CONFIDENTIAL

AX88170 PRELIMINARY

4.3 USB Vendor Commands

SETUP COMMAND DATA IN/OUT DESCRIPTION

C0 02 XX YY 00 0M 02 00 Data 2 bytes Read Rx/Tx SRAM

M = 0 : Rx, M=1 : Tx

40 03 XX YY PP QQ 00 00 No Data Write Rx SRAM

40 04 XX YY PP QQ 00 00 No Data Write Tx SRAM

40 06 00 00 00 00 00 00 No Data Disable H/W MII Operation

C0 07 PI 00 RG 00 02 00 Data 2 Bytes Read MII Register

40 08 PI 00 RG 00 02 00 Data 2 Bytes Write MII Register

C0 09 00 00 00 00 01 00 Data 1 Bytes Read MII Operation Mode

40 0A 00 00 00 00 00 00 No Data Enable H/W MII Operation

C0 0B DR 00 00 00 02 00 Data 2 Bytes Read SROM

40 0C DR 00 MM SS 00 00 No Data Write SROM

40 0D 00 00 00 00 00 00 No Data Write SROM Enable

40 0E 00 00 00 00 00 00 No Data Write SROM Disable

C0 0F 00 00 00 00 02 00 Data 2 Bytes Read Rx Control Register

40 10 RR 00 00 00 00 00 No Data Write Rx Control Register

C0 11 00 00 00 00 03 00 Data 3 Bytes Read IPG/IPG1/IPG2 Register

40 12 II 00 00 00 00 00 No Data Write IPG Register

40 13 II 00 00 00 00 00 No Data Write IPG1 Register

40 14 II 00 00 00 00 00 No Data Write IPG2 Register

C0 15 00 00 00 00 08 00 Data 8 Bytes Read Multi-Filter Array

40 16 00 00 00 00 08 00 Data 8 Bytes Write Multi-Filter Array

C0 17 00 00 00 00 06 00 Data 6 Bytes Read Node ID

C0 19 00 00 00 00 02 00 Data 2 Bytes Read Ethernet/HomePNA PhyID

C0 1A 00 00 00 00 01 00 Data 1 Byte Read Medium Status(*)

40 1B MM 00 00 00 00 00 No Data Write Medium Mode(*)

C0 1C 00 00 00 00 01 00 Data 1 Byte Get Monitor Mode Status(**)

40 1D MM 00 00 00 00 00 No Data Set Monitor Mode On/Off(**)

Notes:

* Read / Write Medium status

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Read GPI1 X GPI0 X Home_Link 100MHz Full_Duplex Link

Write GPO1 GPO1EN GPO0 GPO0EN FRBI 100MHz Full_Duplex Link

** Read / Write Monitor Mode

Bit7-5 Bit4 Bit3 Bit2 Bit1 Bit0

Read Reserved

(Hardware_Version

for ASIX only)

Flow_Contron_En

X Magic_Packet_En

Link_UP_Wake Monitor_Mode

Write X Flow_Contron_En

X Magic_Packet_En

Link_UP_Wake Monitor_Mode

ASIX ELECTRONICS CORPORATION 15

CONFIDENTIAL

AX88170 PRELIMINARY

Interrupt Endpoint report link status format

Byte Number

Byte 0 A1 Fixed value

Byte 1 00 Fixed value

Byte 2 NN Bit_0 : Ethernet Link state, Bit_1 : Home PHY Link state (active high)

Byte 3 00 Fixed value

Byte 4 NN Bit_0 : 100MHz speed detect

Byte 5 NN Reserved (Hardware version for ASIX only)

Byte 6 NN Bit_0 : Full Duplex

Byte 7 00 Fixed value

ASIX ELECTRONICS CORPORATION 16

CONFIDENTIAL

AX88170 PRELIMINARY

5.0 USB Configuration Structure

5.1 USB Configuration.

The AX88170 supports 1 Configuration only.

5.2 USB Interface Class.

The AX88170 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.

5.3 USB Endpoints.

The AX88170 supports 4 endpoints.

Endpoint 0 è Control endpoint, it is for configuring device.

Endpoint 1 è (optional) Interrupt endpoint, it is for reporting status change

Endpoint 2è Bulk Out endpoint, it is for Transmitting Ethernet Packet.

Endpoint 3 è Bulk In endpoint, it is for Receiving Ethernet Packet.

ASIX ELECTRONICS CORPORATION 17

CONFIDENTIAL

AX88170 PRELIMINARY

6.0 Electrical Specification and Timings

6.1 Absolute Maximum Ratings

Description SYM Min Max Units

Operating Temperature Ta 0 +85 °C

Storage Temperature Ts -55 +150 °C

Supply Voltage Vdd -0.3 +3.6 V

Input Voltage Vin -0.3 Vdd+0.3 V

Output Voltage Vout -0.3 Vdd+0.3 V

Lead Temperature (soldering 10 seconds maximum) Tl -55 +240 °C

Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to

Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.

6.2 General Operation Conditions

Description SYM Min Tpy Max Units

Operating Temperature Ta 0 25 +70 °C

Supply Voltage Vdd +3.0 +3.30 +3.6 V

6.3 DC Characteristics

(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C)

Description SYM Min Tpy Max Units

Low Input Voltage Vil - 0.3*Vdd V

High Input Voltage Vih 0.7*Vdd - V

Low Output Voltage Vol - 0.4 V

High Output Voltage Voh 2.4 - V

Input Leakage Current Iil -1 +1 uA

Output Leakage Current Iol -10 +10 uA

Input Pull-up / down resistance Ri 75 K ohm

Description SYM Min Tpy Max Units

Power Consumption (3.3V) SPt3v 40 mA

ASIX ELECTRONICS CORPORATION 18

CONFIDENTIAL

AX88170 PRELIMINARY

6.4 A.C. Timing Characteristics

6.4.1 25M_XIN

25M_XIN

Tr Tf Tlow

25M_CLKO Tod

Symbol Description Min Typ. Max Units

Tcyc CYCLE TIME 40 ns

Thigh CLK HIGH TIME 16 20 24 ns

Tlow CLK LOW TIME 16 20 24 ns

Tr/Tf CLK SLEW RATE 1 - 4 ns

Tod LCLK/XTALIN TO 25M_CLKO OUT DELAY 8 29 ns

6.4.2 48M_XIN

48M_XIN

Tr Tf Tlow

Symbol Description Min Typ. Max Units

Tcyc CYCLE TIME 20.83 ns

Thigh CLK HIGH TIME 8.3 10.42 12.5 ns

Tlow CLK LOW TIME 8.3 10.42 12.5 ns

Tr/Tf CLK SLEW RATE 1 - 4 ns

6.4.3 Reset Timing

25M_XIN

/RST

Symbol Description Min Typ. Max Units

Trst Reset pulse width 100 - - 25M

_XIN

Tcyc

Thigh

Tcyc

Thigh

ASIX ELECTRONICS CORPORATION 19

CONFIDENTIAL

AX88170 PRELIMINARY

ASIX ELECTRONICS CORPORATION 20

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.4 MII Timing of MAC mode

Ttclk Ttch Ttcl

TXCLK(in)

Ttv Tth

TXD<3:0>(out)

TXEN(out)

Trclk Trch Trcl

RXCLK(in)

Trs Trh

RXD<3:0>(in)

RXDV(in)

Trs1

RXER(in)

CRS(in)

Symbol Description Min Typ. Max Units

Ttclk Cycle time(100Mbps) - 40 - ns

Ttclk Cycle time(10Mbps) - 400 - ns

Ttch high time(100Mbps) 14 - 26 ns

Ttch high time(10Mbps) 140 - 260 ns

Trch low time(100Mbps) 14 - 26 ns

Trch low time(10Mbps) 140 - 260 ns

Ttv Clock to data valid - - 20 ns

Tth Data output hold time 5 - - ns

Trclk Cycle time(100Mbps) - 40 - ns

Trclk Cycle time(10Mbps) - 400 - ns

Trch high time(100Mbps) 14 - 26 ns

Trch high time(10Mbps) 140 - 260 ns

Trcl low time(100Mbps) 14 - 26 ns

Trcl low time(10Mbps) 140 - 260 ns

Trs data setup time 6 - - ns

Trh data hold time 10 - - ns

Trs1 RXER data setup time 10 - - ns

ASIX ELECTRONICS CORPORATION 21

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.5 MII Timing of PHY mode

Ttclk Ttch Ttcl

TXCLK(out)

Tts Tth

TXD<3:0>(in)

TXEN(in)

Trclk Trch Trcl

RXCLK(out)

Trs Trh

RXD<3:0>(out)

RXDV(out)

Tcrsh

CRS(out)

Symbol Description Min Typ. Max Units

Ttclk Cycle time(100Mbps) - 40 - ns

Ttclk Cycle time(10Mbps) - 400 - ns

Ttch high time(100Mbps) 14 - 26 ns

Ttch high time(10Mbps) 140 - 260 ns

Trch low time(100Mbps) 14 - 26 ns

Trch low time(10Mbps) 140 - 260 ns

Tts TXD, TXEN setup to TXCLK high 15 - - ns

Tth TXD, TXEN hold to TXCLK high 0 - - ns

Trclk Cycle time(100Mbps) - 40 - ns

Trclk Cycle time(10Mbps) - 400 - ns

Trch high time(100Mbps) 14 - 26 ns

Trch high time(10Mbps) 140 - 260 ns

Trcl low time(100Mbps) 14 - 26 ns

Trcl low time(10Mbps) 140 - 260 ns

Trv RXD, RXDV valid to RXCLK high 10 - - ns

Trh RXCLK high to RXD, RXDV invalid 10 - - ns

Tcrsh RXCLK high to CRS invalid 10 - - ns

ASIX ELECTRONICS CORPORATION 22

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.6 RMII Interface Timing of PHY Mode

Tclk Tch Tcl

REF_CLK

Ts Th

TX_EN

(in)

TXD

(in)

CRS_DV

(out)

Tod Tod

RXD

(out)

Symbol Description Min Typ. Max Units

Tclk REF_CLK Clock Cycle Time 19.998 20 20.002 ns

Tch REF_CLK Clock High Time 7 10 13 ns

Tcl REF_CLK Clock Low Time 7 10 13 ns

Ts TXEN and TXD data setup to REF_CLK high 4 ns

Th TXEN and TXD data hold from REF_CLK high 2 ns

Tod REF_CLK rising edge to CRS_DV, RXD delay 4 ns

ASIX ELECTRONICS CORPORATION 23

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.7 STATION MANAGEMENT TIMING

MDC

MDIO

(output)

MDIO

(input)

Symbol Description Min Typ. Max Units

Tclk MDC Clock Cycle Time 2560 ns

Tch MDC Clock High Time 1280 ns

Tcl MDC Clock Low Time 1280 ns

Tod Clock Falling Edge to Output Valid Delay 2 9 ns

Ts Data In Setup Time 10 ns

Th Data In Hold Time 100 ns

Tod

Tclk

Ts

Th

Tch Tcl

ASIX ELECTRONICS CORPORATION 24

CONFIDENTIAL

AX88170 PRELIMINARY

6.4.8 SERIAL EEPROM TIMING

EECK

EEDI

(output)

EECS

EEDO

(input)

Symbol Description Min Typ. Max Units

Tclk EECK Clock Cycle Time 5120 ns

Tch EECK Clock High Time 2500 9 ns

Tcl EECK Clock Low Time 2500 9 ns

Tdv EEDI Data Valid Output to EECK High Time 500 ns

Tod EECK High to EEDI Data Output Delay Time 500 ns

Tscs EECS Valid to EECK High Time 300 ns

Thcs EECK Low to EECS Invalid Time 0 ns

Tlcs Minimum EECS Low Time 2500 ns

Ts Data Input Setup Time 10 ns

Th Data Input Hold Time 100 ns

Tch

Tclk

Tcl

VALID VALID

Tdv Tod

Tsc

s

Thcs Tlcs

Th

DATA VALID

Ts

ASIX ELECTRONICS CORPORATION 25

CONFIDENTIAL

AX88170 PRELIMINARY

7.0 Package Information

be

D

Hd

E

He

pin 1

A2 A1

L

L1

θ

A

ASIX ELECTRONICS CORPORATION 26

CONFIDENTIAL

AX88170 PRELIMINARY

MILIMETER SYMBOL

MIN. NOM MAX

A1 0.05 0.1 0.15

A2 1.35 1.40 1.45

A 1.60

b 0.17 0.22 0.27

D 10.00

E 10.00

e 0.5

Hd 12.00

He 12.00

L 0.45 0.60 0.75

L1 1.00

θ 0° 3.5° 7°

Appendix A: System Applications

Some typical applications for AX88170 are illustrated bellow.

A.1 USB to Fast Ethernet Converter

AX88170

10/100 PHY/TxRx

MAGNETIC

RJ45

USB I/F

EEPROM

ASIX ELECTRONICS CORPORATION 27

CONFIDENTIAL

AX88170 PRELIMINARY

A.2 USB to Fast Ethernet and/or HomeLAN Combo solution

AX88170

10/100 Mbps

Ethernet PHY/TxRx

MAGNETIC

RJ45

USB I/F

EEPROM

1/10 Mbps

Home LAN PHY

MAGNETIC

RJ11

ASIX ELECTRONICS CORPORATION 28

CONFIDENTIAL

AX88170 PRELIMINARY

A.3 USB-to-USB or USB-to-Ethernet Bridge through Ethernet Repeater Controller

Note : Using AX88871 for 8-port or less then 8-port solutions.

A.4 USB-to-USB or USB-to-Ethernet Bridge through Ethernet Switch Controller

AX88875

Repeater Controller

AX88170

Ethernet PHY for

Up-link

AX88170

Client

PC A

Client

PC B

Client

PC C

Client

PC D

MII I/F MII I/F MII I/F MII I/F

MII I/F

To Ethernet Backend

USB I/F

AX88615

Switch Controller

AX88170

Ethernet PHY for

Up-link

AX88170

Client

PC A

Client

PC B

Client

PC C

Client

PC D

MII I/F MII I/F MII I/F MII I/F

MII I/F

To Ethernet Backend

USB I/F

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 29

Demonstration Circuit A: AX88170 + Ethernet PHY

TXD1

R6 18

L2

FUSE

ACT/LINK#

COL

EEDI

L4

F.B.

VDD3

RST#

D-

VDD3

C1

8p

C13

0.1u

R1 20K

Y2

25M

12

4 3

J1 USB-CON

1

2

3

4

GND

VDD5

D+

D-

S S

C6

20P

*1 USB Port Link/Act LED

25MHZ

RXD2

EEDI

EECS

TXD0

AX88710 L Application for

10BASE-T/100BASE-TX

CRS

R5

1.5K

C14

0.47u

TXEN

RXDV

RXD0

C5

22p U1

AX88170 L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D+

D-

VDD

/RST

VSS

SPD_UP

S_EXT

/S_FDPX

/S_MAC

VDD

VSS

MDC

COL

MDIO

CRS

TX_CLK

VSS

TXD0

TXD1

TXD2

TXD3

TX_EN

VDD

RX_CLK

VSS

RXD0

RXD1

RXD2

RXD3

VDD

RX_ER

RX_DV

25M_CLKO

VSS

25M_XIN

25M_XOUT

VDD

GPIO0

/PHY_RST

GPIO1

/HOMELINK

VSS /S_RMII

VDD

EECS

EECK

EEDI

EEDO

VSS

VDD

48M_XOUT

48M_XIN

VSS

VDD

TEST0

TEST1

TEST2

/EP78DIS TEST3

VDD

TEST_OUT

TEST4

LEERDY

ACT/LINK

VSS

C11

0.1u

TXEN

VDD3

R8 4.7K

PRST#

RXCLK

C9

0.1u

*2 RC reset (option)

TXD3

GND

RXD3

C4

20P

RXCLK

MDC

U3

93C56R

1

2

3

4 5

6

7

8

CS

SK

DI

DO GND

NC

VCC

R3

0

MDIO

RXER

C17

0.1u

+

C15

10u/16V

25MHZ

25M_XOUT

U4

AMS1117 - 3.3

32

1

VIN VOUT

ADJ/GND

RST#

RXD0

GND

C12

0.1u

R4 330

TXD1

EEDO

D1 LED

VDD3

25M_XIN

VDD3

D+

C3

20P

C7

20P

EECK

PRST#

48M_XOUT

25M_XOUT

TXD2

RXD1

GND

VDD3

C19

1000P

48M_XIN

170AP1A.SCH 2.0

AX88170

ASIX ELECTRONIC CORPORATION

B

1 2Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

R2 1M

L1

2.2uH

RXDV

RXD2

Y1

48M

VDD3

R9

10K

TXD0

VDD3

MDIO

48M_XOUT

VDD3

D2

1N4148

EEDO

EECS

+

C16

10u/16V

TXD2 TXD3

R7 18

L3

F.B.

MDC

RXD1

EECK

TXCLK

C18

0.01u

VDD3

C2

8p

C10

0.1u

C8

0.01u

48M_XIN

COL

RXER

25M_XIN

RST#

CRS

RXD3

5V

U2

V6300C

1

2

3

VCC

RESET#

GND

TXCLK

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 30

TDP

GND

C40

0.1u

L5

F.B.

C30

0.1u

VDD3 C27

0.1u

ACTIVITY LED

SPDLED

MDIO

TXD0 R15 4.7K

TXEN

D4LED

RX-

R19

75

R35 510

R16

49.9

VDD3

R32 510

RXDV

R25 2K

TXD3

C23

0.01u

TDN

25MHZ

R20

75

VDD3

RXER J2

RJ45

2

1

3

6

4

5

7

8

SS

R21

75

R17

49.9

CRS

TX+

R18

75

R31 4.7K

VDD3

L6

F.B.

VDD3

R24 4.7K

R28 4.65K

VDD3

GND

R12 4.7K

R26 4.7K

GND

C35

0.1u D6 LED

FULL DUPLEX LED

TX-

D3LED

R23 4.7K

+

C37

4.7u/16V

FULLED

VDD3

C26

1000P

C39

0.1u

C33

0.1u

VDD3

C34

0.1u

RXD1

GND

D5 LED

RXD3

VDD3

C42

0.1u

R11

49.9

TXCLK

GND

C22

0.01u/2KV

PRST#

VDD3

C29

1000P

R34 510

COL

C20

0.01u

R33 510

LINK LED

ACTLED

RXD2

+

C25

4.7u/16V

GND

RXD0

ACTLED

C31

0.1u

RX+

FULLED

VDD3

U5

LU3X31T-T64

1

2

3

4

5

6

7

89

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

RESV

100FDEN

GND9

AUTONEN

TPTXTR

EQGND1

EQVDD1

RESVRSTZ

PHY[0]

100HDEN

PHY[1]

VDD5

GND1

VDD1

MDIOINTZ/PHY[2]

LEDSP/10FDEN

RXDV

RXER

RXD3

RXD2

RXD1

RXD0

RXCLK

VDD8

GND8

TXEN

TXER

TXD3

TXD2

TXD1

TXD0

RXVDD2

RXGND2

TPRX-

TPRX+

RXGND1

RXVDD1

CSVDD

CSGND

TXVDD2

TPTX-

TPTX+

TXGND1

TXVDD1

REF100

REF10

XOUT

XIN

XTLVDD

MDC

LNKLED/BPALIGN

LEDFD/10HDEN

LEDCOL/BP4B5B

LEDTX/ACTLED/BPSCR

LEDRX

COL/PHY[4]

VDD6

VDD4

GND4

MDIO

CRS/PHY[3]

TXCLK

R10

49.9

VDD3

C24

0.01u

C32

0.1u

R13 4.7K

R22 4.7K

RDN

+

C41

4.7u/16V

C36

0.1u LNKLED

VDD3

RXCLK

Set PHY Address to 00010：

SPDLED R14 4.7K

U6

TS6121A

1

2

3

6

7

8 9

10

11

14

15

16

1

2

3

6

7

8 9

10

11

14

15

16

R27 301

C21

0.01u

+

C28

4.7u/16V

R29 1

LNKLED

VDD3

SPEED LED

170AP1A1.SCH 2.0

LU3X31

ASIX ELECTRONIC CORPORATION

B

2 2Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

TXD2

TXD1

VDD3

R30 4.7K

C38

1000P

RDP

MDC

TX 1:1

RX 1:1

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 31

Demonstration Circuit B: AX88170 + HomePNA 1M8 PHY

COL

VDD3

R19 1M

C32

0.01u

48M_XOUT

25MHZ

C31

0.1u

TXD1

PRST#

C20

20P

R29

10K

C28

0.47u

EECS

EEDI

25M_XIN

RXD3

R22

1.5K

C23

0.1u

CRS

R21 330

VDD3

RXDV

C15

8p

U6

AMS1117

32

1

VIN VOUT

ADJ/GND

C22

0.01u

VDD3

EECK

D-

+C29

47u/16V

C18

20P

RXD1

TXD2

C25

0.1u

R25 18

GND

R27

4.7K

GND

PRST#

C33

1000P

12

4 3

J2 USB-CON

1

2

3

4

GND

VDD5

D+

D-

S S

EECS

VDD3

RXD3

C17

20P

L4

F.B.

RXDV

RXD0

48M_XOUT

U4

V6300C

1

2

3

VCC

RESET#

GND

MDIO

VDD3

25M_XOUT

EEDI

VDD3

D+

U3

AX88170 L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D+

D-

VDD

/RST

VSS

SPD_UP

S_EXT

/S_FDPX

/S_MAC

VDD

VSS

MDC

COL

MDIO

CRS

TX_CLK

VSS

TXD0

TXD1

TXD2

TXD3

TX_EN

VDD

RX_CLK

VSS

RXD0

RXD1

RXD2

RXD3

VDD

RX_ER

RX_DV

25M_CLKO

VSS

25M_XIN

25M_XOUT

VDD

PHY_RST

/PHY_RST

PHY_PWN

/PHY_PWN

VSS /S_RMII

VDD

EECS

EECK

EEDI

EEDO

VSS

VDD

48M_XOUT

48M_XIN

VSS

VDD

TEST0

TEST1

TEST2

/EP78DIS TEST3

VDD

TEST_OUT

TEST4

LEERDY

ACT/LINK

VSS

U5

93C56R

1

2

3

4 5

6

7

8

CS

SK

DI

DO GND

NC

VCC

TXCLK

COL

RXCLK

C27

0.1u

48M_XIN

25M_XOUT

RST# *2 RC reset (option)

+C30

47u/16V

L3

2.2uH

ACT/LINK#

*1 USB Port Link/Act LED

VDD3

TXEN

L5

F.B.

EEDO

GND

RXD1

MDIO

C16

8p

MDC

VDD3

Y2

25M

C24

0.1u

C19

22pF

R26 4.7K TXD3

Y1

48M

C26

0.1u

R18 20k

5V

TXCLK

R24 18

AX88710 Application for 1M8 HomePNA

EECK

RST#

TXEN

VDD3

25M_XIN

R20

0

25MHZ

RXD0

TXD1

RXD2

VDD3

C21

20P

VDD3

MDC

VDD3

RXCLK

VDD3

R28

4.7K

RXD2

F1

FUSE

TXD3

TXD2

D6

1N4148

TXD0

170AP2A.SCH 2.0

AX88170

ASIX ELECTRONIC CORPORATION

B

2 2Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

TXD0

CRS

VDD3

D5 LED

R23

4.7K

EEDO

48M_XIN

RST#

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 32

TXD2

RXDV

RING

VDD3

TXEN

R13 10K

VDD3

C3

0.1u

R14

49.9

TXD3

TXEN R4

20

+

C10

47u/16V

TXD0

TIP

25MHZ

R6 10K

170AP2A1.SCH 2.0

HOMENET PHY C.K.T.

B

1 2Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

MDIO

TXCLK

C8

0.01u

COL RXD0

VDD3

POWERLED#

TXCLK

COLLED#

POWERLED#

R2

4.7K

C14

0.1u

C4

0.1u

TXCLK

R7 20

VDD3

CRS

RXD2

TXD3

R15

49.9

U2

HR002

5

4

3

2

1

7

8

612

13

14

15

16

11

10

9

NC

GND

-

+

NC

NC NC

NC

TIP

RING

RXD3

SPEEDLED# R8 330

+

C1

47u/16V

TXD0

C7

0.01u

RXCLK

RXD0

CRS

RXD3

COL

MDC

ACTLED#

RXCLK

AVDD3_1

R9

4.7K

U1

DP83851C

36

35

34

33

32

31

23

24

25

26

27

28

37

38

21

22

45

46

19

29

39

5

11

20

7

8

4

17

18

16

15

44

14

42

43

48

30

40

41

47

3

6

10

1

2

9

12

13

TXD3

TXD2

TXD1

TXD0/TXD

TX_EN

TX_CLK

RXD3/PHYAD0

RXD2/CMDDIS#

RXD1/HI_POWER_EN#

RXD0/RXD/LOW_SPEED_EN#

RX_DV/GPSI_SEL#

RX_CLK

COL/MDIO_INT_EN#

CRS/PIN_INTRP_EN#

MDIO

MDC

X1

X2

IO_VDD1

IO_VDD2

CORE_VDD

ANA_VDD2

ANA_VDD3

IO_GND1

TIP

RING

RBIAS

LED_COL/PHYAD2

LED_ACT/PHYAD1

LED_SPEED/PHYAD3

LED_POWER/PHYAD4

RESET#

RESERVED

ANA_VDD1

IO_GND2

CORE_GND

CORE_SUB(0V)

ANA_GND1

ANA_GND2

ANA_GND3

ANA_GND4

SUB_GND1

SUB_GND2

SUB_GND3

RESERVED

D3

YELLOW LED

TXD3

AVDD3_2

TXD1

R11 330

D1

GREEN LED

R17

0

SPEEDLED#

TXEN

RXCLK

MDC

GND

R16 4.7K

PRST#

MDC

CRS

D2

YELLOW LED

R3 10K

GND

RXD3

VDD3

L1

F.B.

C13

0.01u

J1

RJ11

1

2

3

4

5

6

NC

A1

TIP

RING

A2

NC

RXD1

+

C5

47u/16V

RXD1

C12

0.01u

RXD1

ACTLED#

TXD2

VDD3

25MHZ

TXD0

COL

TXD1

+

C6

47u/16V

25MHZ

R5 330

+

C11

47u/16V

MDIO D4

RED LED

MDIO

VDD3

RXDV

PRST#

R12

9.31K

1%

C2

0.01u

TIP

C9

0.1u

RXD2

R1 330

L2

F.B.

RXD2

TXD2

TXD1

RXDV

R10 10K

Set PHY Address TO 00001 and LED DISPLAY C.K.T.

：

PRST#

RXD0

COLLED#

RING

VDD3

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 33

Demonstration Circuit C: 4 USB Ports + 1 Ethernet Port Bridge AP

U4C

74HC04

5 6

(POWER IN: 5V/3A)

C12

0.1u

25M_PHY

RST_USB#

25M_USB1

U5

OSC 25MHZ

5

48 OUT

GNDVCC

GND

+C1

200u/16V

RST_USB#

25M_USB0

*2 R9 & R10 : Adjust DM9191F

LCLK to AX88875AP LCLK

C5

1000p

L3

F.B.

VDD5

25M_USB3

VDD5

25MHZ

25M_USB3

C7

1000p

U4A

74HC04

1 2

U2D

74LV04

9 8

GND

L2

F.B.

AX88170 L PHY mode application (MII Interface)

U2A

74LV04

1 2

R5 20

25M_PHY

U2C

74LV04

5 6

L1

F.B.

GND5

R3 20

25M_USB2

VDD5

25M_USB0

VDD5

VDD3

U6C

74F04

5 6

RST_EN#

R10 20

C11

0.1u

JP1

POWER CONNECTOR

4

3

2

1

VDD3

R6 20

C9

0.1u

U1

AMS1084-3.3V

32

1

VIN VOUT

ADJ/GND

RST_EN#

U2B

74LV04

3 4

R4 51

VDD5

25M_USB2

R2 20 U4B

74HC04

3 4

*1 R7 & R8 : Adjust ax88875AP

LCLK to AX88170 L TXCLK

25M_USB1

R1

10K

GND

RST_EN#

+C3

47u/16V

U3

V6300F

1

2

3

VCC

RESET#

GND

R9 20

VDD5

+C2

200u/16V

VDD5

25M_REP

U2E

74LV04

11 10

25M_USB0

C4

0.1u

25M_USB2

+C8

47u/16V

25M_USB1

C6

0.1u

R7 20

U6A

74F04

1 2

25M_USB3

RST_USB#

VDD3

C13

1000p

C10

0.01u

+5V

GND

R8 20

GND

170AP5A.SCH 2.0

POWER & RESET C.K.T.

B

1 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

25M_REP

25M_PHY

U6B

74F04

3 4

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 34

R18 10K

RXD03

TXD0 TXD00

Y1

48M

D-

VDD3

ALDONE

170AP5A1.SCH 2.0

AX88170 CIRCUIT 1

ASIX ELECTRONIC CORPORATION

B

2 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

C23

8p

D1 LED

GND

48M_XOUT

R12 330

TXD02

GND

12

4 3

J1 USB-CON

1

2

3

4

GND

VDD5

D+

D-

S S

TXD1

RXD2

*3 USB Port Link/Act LED

RXD1

RST#

R13

1.5K

VDD3

R16 4.7K

R15 18

EECS

TXEN

EEDO

C21

0.1u

VDD3

48M_XIN

C15

20P

RXD02

C16

0.01u

TXD01

C24

22pF

VDD3

RXDV0

VDD3

L4 F.B.

VDD3

TXEN0

U8

93C56R

1

2

3

4 5

6

7

8

CS

SK

DI

DO GND

NC

VCC

RST_USB#

C19

0.1u

VDD3

C22

8p

Q1

2SC2412K

U7

AX88170 L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D+

D-

VDD

/RST

VSS

SPD_UP

S_EXT

/S_FDPX

/S_MAC

VDD

VSS

MDC

COL

MDIO

CRS

TX_CLK

VSS

TXD0

TXD1

TXD2

TXD3

TX_EN

VDD

RX_CLK

VSS

RXD0

RXD1

RXD2

RXD3

VDD

RX_ER

RX_DV

25M_CLKO

VSS

25M_XIN

25M_XOUT

VDD

GPIO0

/PHY_RST

GPIO1

/HOMELINK

VSS /S_RMII

VDD

EECS

EECK

EEDI

EEDO

VSS

VDD

48M_XOUT

48M_XIN

VSS

VDD

TEST0

TEST1

TEST2

/EP78DIS TEST3

VDD

TEST_OUT

TEST4

LEERDY

ACT/LINK

VSS

TXD2

TXD3

R14 18

VDD3

TXD03

RXD00

EEDO

C18

0.1u

48M_XIN

RXCLK

R11

1K

L5

2.2uH

R20

0

VDD3

RXD01

CRS0

VDD3

D+

VDD3

RXDV

C17

0.1u

ACT/LINK#

25M_USB0

VDD3

CRS

R19 10K

EECK

RXD0

C14

20P

R17 20k EECS

C20

0.1u

EEDI

EECK

RXD3

48M_XOUT

RXCLK0

EEDI

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 35

L6 F.B.

170AP5A2.SCH 2.0

AX88170 CIRCUIT 2

ASIX ELECTRONIC CORPORATION

B

3 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

EEDI

RST#

TXEN

R30

0

ACT/LINK#

RXD1

C35

22pF

RXD3

48M_XOUT

RXD0

RXD2

*4 USB Port Link/Act LED

RXCLK1

RXDV1

EECK

GND

VDD3

D+

RXDV

VDD3

Y2

48M

48M_XIN

ALDONE

RXCLK

48M_XIN

D2 LED

CRS1

C29

0.1u

R26 4.7KC26

20P

C28

0.1u

C34

8p

EECS

CRS

RST_USB#

TXD12

VDD3

RXD11

TXD1

VDD3

EEDO

TXEN1

L7

2.2uH

R23

1.5K

VDD3

C30

0.1u

C31

0.1u

C33

8p

VDD3

R27 20k

TXD0

EEDI

48M_XOUT

C27

0.01u

C25

20P

VDD3

EECK

R29 10K

R22 330

RXD13

TXD2

12

4 3

J2 USB-CON

1

2

3

4

GND

VDD5

D+

D-

S S

U10

93C56R

1

2

3

4 5

6

7

8

CS

SK

DI

DO GND

NC

VCC

Q2

2SC2412K

TXD3

D-

U9

AX88170 L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D+

D-

VDD

/RST

VSS

SPD_UP

S_EXT

/S_FDPX

/S_MAC

VDD

VSS

MDC

COL

MDIO

CRS

TX_CLK

VSS

TXD0

TXD1

TXD2

TXD3

TX_EN

VDD

RX_CLK

VSS

RXD0

RXD1

RXD2

RXD3

VDD

RX_ER

RX_DV

25M_CLKO

VSS

25M_XIN

25M_XOUT

VDD

GPIO0

/PHY_RST

GPIO1

/HOMELINK

VSS /S_RMII

VDD

EECS

EECK

EEDI

EEDO

VSS

VDD

48M_XOUT

48M_XIN

VSS

VDD

TEST0

TEST1

TEST2

/EP78DIS TEST3

VDD

TEST_OUT

TEST4

LEERDY

ACT/LINK

VSS

C32

0.1u

VDD3

R28 10K

25M_USB1

EECS

R21

1K

TXD10

VDD3

RXD10

TXD11

RXD12

R24 18

R25 18

TXD13

GND

EEDO

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 36

VDD3

48M_XIN

R35 18

R36 4.7K

RXCLK

U11

AX88170 L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D+

D-

VDD

/RST

VSS

SPD_UP

S_EXT

/S_FDPX

/S_MAC

VDD

VSS

MDC

COL

MDIO

CRS

TX_CLK

VSS

TXD0

TXD1

TXD2

TXD3

TX_EN

VDD

RX_CLK

VSS

RXD0

RXD1

RXD2

RXD3

VDD

RX_ER

RX_DV

25M_CLKO

VSS

25M_XIN

25M_XOUT

VDD

GPIO0

/PHY_RST

GPIO1

/HOMELINK

VSS /S_RMII

VDD

EECS

EECK

EEDI

EEDO

VSS

VDD

48M_XOUT

48M_XIN

VSS

VDD

TEST0

TEST1

TEST2

/EP78DIS TEST3

VDD

TEST_OUT

TEST4

LEERDY

ACT/LINK

VSS

VDD3

RST#

170AP5A3.SCH 2.0

AX88170 CIRCUIT 3

ASIX ELECTRONIC CORPORATION

B

4 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

VDD3

GND

48M_XIN

TXD3

ACT/LINK#

RXCLK2

EECS

VDD3

C40

0.1u

VDD3

R33

1.5K

12

4 3

J3 USB-CON

1

2

3

4

GND

VDD5

D+

D-

S S

RXD0

TXD2

ALDONE

RST_USB#

C42

0.1u

EEDO

U12

93C56R

1

2

3

4 5

6

7

8

CS

SK

DI

DO GND

NC

VCC

EECK

RXDV2

EEDI

C44

8p

R38 10K

TXD21

D-

48M_XOUT

VDD3

TXD0

CRS2

VDD3

R32 330

EECK

CRS

TXD23

R40

0

R31

1K

Y3

48M

RXD2

C43

0.1u

C41

0.1u

L9

2.2uH

TXEN

EEDO

D+

VDD3

C37

20P

VDD3

RXD1

RXDV

RXD20

R39 10K

RXD3

R34 18 RXD21

*5 USB Port Link/Act LED

C36

20P

R37 20k

L8 F.B.

GND

TXD1

VDD3

EEDI

TXEN2

RXD23

48M_XOUT

TXD20

RXD22

D3 LED

EECS

25M_USB2

C39

0.1u

Q3

2SC2412K

VDD3

C46

22pF

TXD22

C45

8p

C38

0.01u

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 37

RXDV3

RXD0

TXD0

VDD3

R46 4.7K

VDD3

TXD1

RXD33

TXD2

R49 10K

EECS

CRS3

C52

0.1u

L10 F.B.

R41

1K

TXD33

EECS

EECK

C55

8p

EEDO

TXD32

RXDV

25M_USB3

D4 LED

RST_USB#

TXD31

R44 18

VDD3

RST#

RXD30

TXEN

48M_XOUT

C57

22pF

C50

0.1u

R48 10K

D- RXD31

RXD1

VDD3

R43

1.5K

U13

AX88170 L

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42 43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D+

D-

VDD

/RST

VSS

SPD_UP

S_EXT

/S_FDPX

/S_MAC

VDD

VSS

MDC

COL

MDIO

CRS

TX_CLK

VSS

TXD0

TXD1

TXD2

TXD3

TX_EN

VDD

RX_CLK

VSS

RXD0

RXD1

RXD2

RXD3

VDD

RX_ER

RX_DV

25M_CLKO

VSS

25M_XIN

25M_XOUT

VDD

GPIO0

/PHY_RST

GPIO1

/HOMELINK

VSS /S_RMII

VDD

EECS

EECK

EEDI

EEDO

VSS

VDD

48M_XOUT

48M_XIN

VSS

VDD

TEST0

TEST1

TEST2

/EP78DIS TEST3

VDD

TEST_OUT

TEST4

LEERDY

ACT/LINK

VSS

VDD3

Y4

48M

C48

20P

C51

0.1u

RXD3

C49

0.01u

CRS

C47

20P

R45 18

VDD3

C56

8p

VDD3

D+

TXD3

RXD32

*6 USB Port Link/Act LED

TXD30

ALDONE

L11

2.2uH

GND

VDD3

RXD2

VDD3

RXCLK

R42 330

48M_XIN

ACT/LINK#

48M_XIN

170AP5A4.SCH 2.0

AX88170 CIRCUIT 4

ASIX ELECTRONIC CORPORATION

B

5 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

12

4 3

J4 USB-CON

1

2

3

4

GND

VDD5

D+

D-

S S

RXCLK3

VDD3

R47 20k

48M_XOUT

EEDO

C53

0.1u EEDI

Q4

2SC2412K

EEDI

R50

0

VDD3

EECK

GND

TXEN3

U14

93C56R

1

2

3

4 5

6

7

8

CS

SK

DI

DO GND

NC

VCC

C54

0.1u

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 38

RXCLK4

R59 10K

TXEN1

MODE0

RXDV1

MD3 C60

0.1u

TXD02

VDD5

R66 20

R51 20

C70

0.1u

MEMS1

MD0

C63

0.1u

RXCLK1

RXD21

MA11

GND

COL10#

RXD01

MA7

R71

510

RXD10

RXDV3

TXD32

CRS3

DISFC#

TXD30

+

C58

100u/16V

TXD13

*10 settingt to mode 0

MA0

GND

VDD5

MA6

TXER4

D6 LED

R67 10K

R56 10K

R57 10K

GND

DISFC#

TXD03

TXD01

TXD31 GND

RXD22 VDD5

TXD42

MA0

COL100#

MD7

MD2

MD3

GND

MA16

R53 10K

RXD43

RXD03

VDD5

TXD10

MA16

GND

RXCLK0

RXD12

VDD5

R72 10K

MD1

VDD5

ST_FW

MA11

U16

HSRAM128*8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

N.C.

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

VSS

VCC

A15

CS2

WE_#

A13

A8

A9

A11

OE_#

A10

CS1_#

I/O8

I/O7

I/O6

I/O5

I/O4

GND

MD4

C61

0.1u

TXD20

RXDV0

RXD41

RXD00

MA1

COL100#

RXD20

R52 10K

C66

0.1u

VDD5

TXD33

LLED4

GND

TXD40

TXD43

MA3

*9 LOW: DIS_FLOW-CONTROL

TXD23

CRS0

100 GLOBAL COLLISION

GND

MD2

MD6

MODE0

LCLK

R65 10K

ENTRY

GND

RST#

TXEN0

GND

TXD21

TXEN3

RXD23

MA14

VDD5

RXD33

ENTRY

RXD40

RXD42

MWR#

C65

0.1u

R60 20

R62 10K

VDD5

GND

C67

0.1u

MA15

MA14

10 GLOBAL COLLISION

MA7

MA5

VDD5

U15

AX88875AP

1

2

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

VDD

RXD<1><2>

TXD<3><1>

TXD<3><2>

TXD<3><3>

TXER3<3> COL<3>

VSS

PULL_DN

EN_FLOW-CTL

MODE

TXE_DELAY

VDD

RXER<4>

RXDV<4>

CRS<4>

VSS

VDD

RXCLK<4>

RXD<4><0>

RXD<4><1>

RXD<4><2>

RXD<4><3>

TXEN<4>

TXD<4><0> MEM_SIZE<0>

TXD<4><1> MEM_SIZE<1>

TXD<4><2> ENTRIES

TXD<4><3> ST_FW

TXER<4> COL<4>

COL_O<4>

VSS

/LCOL100

MDC

MDO

MCLK

/BMA<15>

/LUTI<0>

/LUTI<1>

/LUTI<2>

/LUTI<3>

/BMWR /IR_ACT_EN

BMA<8>

BMA<9>

/LPART<4>

VSS

/LACT<4>

NC

/LACT<2>

/LACT<3>

VDD

NC

/LACT<0>

/LACT<1>

NC

TEST1

/RST

VSS

LCLK

/HALF10

VDD

PULL_DN

VDD

VSS

RXER<0>

RXDV<0>

CRS<0>

RXCLK<0>

RXD<0><0>

RXD<0><1>

RXD<0><2>

RXD<0><3>

VSS

TXEN<0>

TXD<0><0>

TXD<0><1>

TXD<0><2>

TXD<0><3>

COL<0> TXER<0>

RXER<1>

RXDV<1>

CRS<1>

RXCLK<1>

RXD<1><0>

RXD<1><1>

RXD<1><3>

TXEN<1>

TXD<1><0>

TXD<1><1>

TXD<1><2>

TXD<1><3>

TXER<1> COL<1>

VSS

PULL_DN

VDD

VSS

RXER<2>

RXDV<2>

CRS<2>

RXCLK<2>

RXD<2><0>

RXD<2><1>

RXD<2><2>

RXD<2><3>

TXEN<2>

TXD<2><0>

TXD<2><1>

TXD<2><2>

TXD<2><3>

TXER<2> COL<2>

VSS

RXER<3>

RXDV<3>

CRS<3>

RXCLK<3>

RXD<3><0>

RXD<3><1>

RXD<3><2>

RXD<3><3>

VDD

TXEN<3>

TXD<3><0>

VDD

BMA<10>

BMA<11>

BMA<12>

BMA<13>

BMA<14>

BMA<15>

BMA<16>

VSS

BMD<0>

BMD<1>

BMD<2>

BMD<3>

BMD<4>

BMD<5>

BMD<6>

BMD<7>

VSS

BMA<0>

BMA<1>

BMA<2>

BMA<3>

VDD

BMA<4>

BMA<5>

BMA<6>

BMA<7>

VSS

VDD

/LSEL10

/LCOL10

/LUTI<5>

/LUTI<4>

/TEST2

/LPART<0>

/LPART<1>

/LPART<2>

LPART<3>

TXD22

MD6

VDD5

TXD00

25M_REP

MA13

MA3

MA9

C69

0.1u

RXCLK2

MD0

MA4

MWR#

D5 LED

R54 10K

GND

RXDV2

MD1

R58 10K

RXCLK3

COL10#

GND

*7 Set memory size to 128KB

MA2 MA10

MA1

MA12

CRS1

MD7

MA8

R55 10K

CRS2

RXD32

170AP5A5.SCH 2.0

AX88875 AP C.K.T.

B

6 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

MD5

VDD5

GND

RXD31

RXDV4

*8 ENTRIES Setting : High : 256

Low : 1024

R68 10K

GND

MD4

R64 10K

MA8

MA9

MA10

C68

0.1u

MA15

C62

0.1u

C71

0.1u

MA13

MA4

R69

510

R61 20

R70 20

C64

0.1u

MA6

MEMS1

C59

0.1u

TXD11

TXD12

RXD13

RST_EN#

MEMS0

VDD5

MA2

RXD11

RXD02

RXD30

MD5

R63 10K

MA5

TXEN2

TXEN4

CRS4

RXER4

GND

MA12

TXD41

AX88170 USB to Fast Ethernet/HomePNA Controller

ASIX ELECTRONICS CORPORATION 39

RXD0

LLED

C92

0.1u

C81

0.1u

TXER

C79

1000p

C91

0.1u

AGND

TXD43

TDN

R75

49.9

L12

F.B.

GND

CRS

C83

0.1u

RXD41

RJ03

C82

0.1u

RJ03

RXCLK

GND

C87

0.1u

TXD1

C74

0.1u

TXER

VDD5

GND

RXER

GND

RXD43

AVDD5

R79

75

CRS4

RDP

RDN

C73

0.01u/2KV

AVDD5

GND

RXD1

AGND

170AP5A6.SCH 2.0

EtherNet PHY C.K.T.

B

7 7Monday, February 26, 2001

Title

Size Document Number Rev

Date: Sheet of

TXD0

TDP

TXD2

TXD3

GND

R74

49.9

AGND

RXDV4

CRS

AVDD5

C78

1000p

TXD2

GND

RXER4

RXD2

GND

VDD5

+

C86

47u/16V

AGND

VDD5

AVDD5

GND

C76

0.01u

R80

75

R73

49.9

CHASSIS

JP3

RJ45

1

2

3

4

5

6

7

8

RXD0

VDD5

U17

DM9191F

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50 51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

AVCC

NC

AGND

AVCC

RXI-

RXI+

AGND

10TXO-

10TXO+

AVCC

AGND

NC

AVCC

AGND

100TXO-

100TXO+

AVCC

DVCC

OSC/X1

X2

DGND

OSC/XLT#

AVCC

AGND

BGRES

NC

DGND

AGND

AVCC

TRIDRV

UTP

SPEED10

RX_LOCK

DGND

NC

LINKSTS

CLK25M

DVCC

FDXLED# COLLED#

DGND

LINKLED#

RXLED#

TXLED#

TX_ER/TXD4

TXD3

TXD2

TXD1

TXD0

DGND

DVCC

TX_EN

TX_CLK

MDC

MDIO

DGND

DVCC

RXD3

RXD2

RXD1

RXD0

DGND

DVCC

RX_CLK

CRS

COL

RX_DV

RX_ER/RXD4

RX_EN

RESET#

TESTDOME

PHYAD0

PHYAD1

PHYAD2

DGND

DVCC

PHYAD3

PHYAD4

OPMODE0

OPMODE1

OPMODE2

OPMODE3

RPTR/NODE#

BPALIGN

BP4B5B

BPSCR

10BTSER

AGND

RJ02

(ETHERNET PORT)

VDD5

C84

0.1u

C80

0.1u

RST#

JP2

RJ45

1

2

3

4

5

6

7

8

GND_E

VDD5

+

C77

47u/16V

TDP

RDP

Ethernet Port Link/Act LED

VDD5

C93

0.1u

RJ06

GND

TDP

RST_EN#

AGND

VDD5

TXD3

TXD40

AVDD5

AGND

TXD41

TX 1CT:1CT

RX 1CT:1CT RJ02

RJ01

RJ03

RST#

RXD1

25M_PHY

AGND

TXEN

(1%)

GND

RDN

C90

0.1u

R82 510

VDD5

GND

VDD5

GND

RXD2

VDD5

LLED4 RJ06

RXD40 AGND

TXEN

RXCLK

AVDD5

RJ06

R78

75

C85

0.1u

(ETHERNET UPLINK POART)

AVDD5

C72

0.1u

VDD5

RXER

T1

16ST8515

16

14

15

1

3

2

10

12

11

7

5

6

16

14

15

1

3

2

10

12

11

7

5

6

RXD42

TXEN4

RJ02

AVDD5

LLED4

D7 GREEN LED

C89

0.1u

25M_PHY

TDN

TXER4 25M_PHY

GND

R81

6.2K

TXD0

AVDD5

C75

0.1u

RXD3

VDD5

C88

0.1u

GND

R76

49.9

RXCLK4

R77

75

RXDV

GND

LLED4

TDN

AGND

TXD42

TXD1

RJ01

VDD5

GND

RXDV

RJ01

RXD3