Preliminary Data Sheet
September 2001
L9216A/G
Short-Loop Ringing SLIC with Ground Start
Introduction
The Agere Systems Inc. L9216 is a subscriber line
interface circuit (SLIC) that is optimized for short-
loop, power-sensitive applications. This device pro-
vides the complete set of line interface functionality,
including power ringing needed to interface to a sub-
scriber loop. This device has the capability to operate
with a VCC supply of 3.3 V or 5 V and is designed to
minimize external components required at all device
interfaces.
Features
■Onboard ringing generation
■Three ringing input options:
— Sine wave
— PWM
— Logic level square wave
■Flexible VCC options:
— 5 V or 3.3 V VCC
— No –5 V required
■Battery switch to minimize off-hook power
■Eight operating states:
— Scan mode for minimal power dissipation
— Forward and reverse battery active
— On-hook transmission states
— Ground start (tip open)
— Ring mode
— Disconnect mode
■Ultralow on-hook power:
— 27 mW scan mode
— 41 mW active m ode
■Two SLIC gain options to minimal external compo-
nents in codec interface
■Loop start, ring trip, and ground start detectors
■Software-controllable dual current-limit option
■28-pin PLCC package
■48-pin MLCC package
Applications
■Voice over Internet Protocol (VoIP)
■Cable Modems
■Terminal Adapters (TA)
■Wireless Local Lo op (WLL)
■
Telcordia
Technologies
™ GR-9 09 Ac cess
■Network Termination (NT)
■Key Systems
Description
This device is optimized to provide battery feed, ring-
ing, and supervision on short-loop plain old tele-
phone service (POTS) loops.
This device provides po wer ring to the subs criber
loop through amplification of a low-voltage input. It
provides forward and reverse battery feed states, on-
hook transmission, a low-power scan state, ground
start (tip open), and a forward disconnect state.
The device re quire s a VCC and battery to operate.
VCC may be either a 5 V or a 3.3 V supply. The ring-
ing signal is derived from the high-voltage battery. A
battery switch is included to allow for use of a lower-
voltage battery in the off-hook mode, thus minimizing
short-loop off-hook power.
Loop closure, ring trip, and ground start detectors are
available. The loop closure detector has a fixed
threshold with hysteresis. The ring trip detector
requires a single-pole filter, thus minimizing external
components required.
The dc current limit is set and fixed by a logic control-
lable pin. Ground or open is applied to this pin set the
current limit at the low or high value.
The device is offered with two gain options. This
allows for an optimized codec interface, with minimal
external components regardless of whether a first-
generation or a programmable third-generation
codec is used.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
2 Agere Systems Inc.
Table of Contents
Contents Page
Introduction..................................................................1
Features....................................................................1
Applications...............................................................1
Description................................................................1
Features ......................................................................4
Description...................................................................4
Architecture Diagram...................................................7
Pin Information ............................................................8
Operating States ... ....... ...... ...... .................... ...... .......10
State Definitions ........................................................11
Forward Active........................................................11
Reverse Active........................................................11
Scan........................................................................11
On-Hook Transmission—Forward Battery..............11
On-Hook Transmission—Reverse Battery..............11
Disconnect..............................................................11
Ring.........................................................................11
Ground Start ...........................................................11
Thermal Shutdown..................................................12
Absolute Maximum Ratings (@ TA = 25 °C) ..............12
Electrical Characteristics...........................................13
Test Configurations ...................................................20
Applications...............................................................22
Power Control .........................................................22
dc Loop Current Limit..............................................23
Overhead Voltage...................................................23
Active Mode .........................................................23
Scan Mode...........................................................23
On-Hook Transmission Mode...............................23
Ring Mode............................................................24
Loop Range ............................................................24
Battery Reversal Rate.............................................24
Supervision................................................................24
Loop Closure...........................................................24
Ring Trip .................................................................24
Tip or Ring Ground Detector...................................24
Power Ring .............................................................25
Sine Wave Input Signal and Sine Wave
Power Ring Signal Output .................................26
PWM Input Signal and Sine Wave Power
Ring Signal Output.............................................28
5 V VCC Operation................................................29
3.3 V VCC Operation.............................................30
Square Wave Input Signal and Trapezoidal
Power Ring Signal Output .................................30
Contents Page
ac Applications ......................................................... 32
ac Parameters........................................................ 32
Codec Types.......................................................... 32
First-Generation Codecs..................................... 32
Third-Generation Codecs.................................... 32
ac Interface Network.............................................. 32
Design Ex amp le s... ...... ....... ...... .................... ...... ... 34
First-Generation Codec ac Interface
Network— Res istiv e Term in ati on ...... ....... ...... ... 34
Example 1, Real Termination.............................. 34
First-Generation Codec ac Interface
Network—Complex Termination....................... 37
Complex Termination Impedance Design
Example............................................................ 37
ac Interface Using First-Generation Codec......... 37
Transmit Gain................... ...... ....... ...... ....... ...... ... 38
Receive Gain.......................... .................... ...... ... 39
Hybrid Balance.................................................... 39
Blocking Capacitors ............................................ 40
Third-Generation Codec ac Interface
Network—Complex Termination....................... 42
Outline Diagrams...................................................... 44
28-Pin PLCC.......................................................... 44
48-Pin MLCC.......................................................... 45
48-Pin MLCC, JEDEC MO-220 VKKD-2................ 46
Ordering Information ................................................ 47
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC w/ Ground Start
L9216A/G
Agere Systems Inc. 3
Table of Contents (continued)
Figures Page
Figure 1. Architecture Diagram ...................................7
Figure 2. 28-Pin PLCC ...............................................8
Figure 3. 48-Pin MLCC................................................8
Figure 4. Basic Test Circuit ......................................20
Figure 5. Metallic PSRR ...........................................21
Figure 6. Longitudinal PSRR ....................................21
Figure 7. Longitudinal Balance .................................21
Figure 8. ac Gains ....................................................21
Figure 9. Ringing Waveform Crest Factor = 1.6 .......25
Figure 10. Ringing Waveform Crest Factor = 1.2 .....25
Figure 11. Ring Mode Typical Operation ..................26
Figure 12. RINGIN Op erati on ............................. ....... 27
Figure 13. L9215/16 Ringing Input Circuit Selection
Table for Square Wave and PWM
Inputs ................ ...... ....... ...... ....... ...... ....... 28
Figure 14. Modulation Waveforms ............................29
Figure 15. 5 V PWM Signal Amplitude .....................29
Figure 16. Ringing Output on RING, with
VCC = 5 V .................................................29
Figure 17. 3.3 V PWM Signal Amplitude ..................30
Figure 18. Ringing Output on RING, with
VCC = 3.1 V ..............................................30
Figure 19. Square Wave Input Signal and
Trapezoidal Power Ring Signal Output ...30
Figure 20. Crest Factor vs. Battery Voltage .............31
Figure 21. Crest Factor vs. R (kΩ) ...........................31
Figure 22. ac Equivalent Circuit ................................35
Figure 23. Agere T7504 First-Generation Codec
Resistive Termination ..............................35
Figure 24. Interface Circuit Using First-Generation
Codec (Blocking Capacitors Not
Shown) ....................................................38
Figure 25. ac Interface Using First-Generation Codec
(Including Blocking Capacitors) for
Complex Termination Impedance ...........40
Figure 26. Agere T7504 First-Generation Codec
Complex Termination ..............................40
Figure 27. Third-Generation Codec ac Interface
Network; Complex Termination ...............42
Tables Page
Table 1. Pin Descriptions .......................................... 9
Table 2. Control States............................................. 10
Table 3. Supervision Coding ................................... 10
Table 4. Recommended Operating
Characteris tics ....... ...... ....... ................... ... 12
Table 5. Thermal Characteristics.............................. 12
Table 6. Environmental Characteristics.................... 13
Table 7. 5 V Supply Currents ................................... 13
Table 8. 5 V Powering .............................................. 13
Table 9. 3.3 V Supply Currents ............................... 14
Table 10. 3.3 V Powering ......................................... 14
Table 11. 2-Wire Port .............................................. 15
Table 12. Analog Pin Characteristics ..................... 16
Table 13. ac Feed Characteristics .......................... 17
Table 14. Logic Inputs and Outputs (VCC = 5 V) ..... 18
Table 15. Logic Inputs and Outputs (VCC = 3.3 V) .. 18
Table 16. Ground Start ............................................ 18
Table 17. Ringing Specifications ............................. 19
Table 18. Ring Trip .................................................. 19
Table 19. Typical Active Mode On- to Off-Hook
Tip/Ring Current-Limit Transient
Response ................................................ 23
Table 20. FB1 and FB2 Values vs. Typical Ramp
Time ......................................................... 24
Table 21. Onset of Power Ringing Clipping
VCC = 5 V, Cinput = 0.47 µF ................... 27
Table 22. Onset of Power Ringing Clipping
VCC = 3.1 V, Cinput = 0.47 µF ................ 27
Table 23. Signal and Component Selection Chart ... 28
Table 24. Parts List L9216; Agere T7504 First-
Generati on Codec Res is tiv e Ter min ati on;
Nonmeter Pulse Application ................... 36
Table 25. Parts List L9216; Agere T7504 First-
Generation Codec Complex Termination;
Meter Pulse Appl ic ati on ........... ....... ......... 41
Table 26. Parts List L9216; Agere T8536
Third-Generation Codec ac and
dc Parameters; Fully Programmable ...... 43
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
4 Agere Systems Inc.
Features
■Onboard balanced ringing generation:
— No ring relay
— No bulk ring generator required
— 15 Hz to 70 Hz ring frequency supported
— Sine wave input-sine wave output
— PWM input-sine wave output
— Square wave input-trapezoidal output
■Power supplies requirements:
— VCC talk battery and ringing batt ery req uire d
— No –5 V supply required
— No high-voltage positive supply required
■Flexible Vcc options:
— 5 V or 3.3 V VCC operation
— 5 V or 3.3 V VCC interchangeable and transparent
to users
■Battery switch via logic control:
— Minimize off-hook power dissipation
■Minimal external components required
■Eight operating states:
— Fo rward active, VBAT2 applied
— Polarity reversal active, VBAT2 applied
— On-hook transmission, VBAT1 applie d
— On-hook transmission polarity reversal, VBAT1
applied
— Ground start
— Scan
— Forward disconnect
— Ring mode
■Unlatched parallel data control interface
■Ultralow SLI C power :
— Scan 37 mW (VCC = 5 V)
— Fo rward/reverse active 54 mW (VCC = 5 V)
— Scan 27 mW (VCC = 3.3 V)
— Fo rward/reverse active 41 mW (VCC = 3.3 V)
■Supervision:
— Loop start, fixed threshold with hysteresis
— Ring trip, single-pole ring trip filtering, fixed thresh-
old as a function of battery voltage
— Ring current for ground start applications, user-
adjustable thr eshold
■Adjustable current limit:
— 25 mA or 40 mA via ground or open to control
input
■Overhe ad vo ltage:
— Clamped typically <51 V differentially
— Clamped maximum <56.5 V single-ended
■Thermal shutdown protection with hysteresis
■Longitudinal balance:
—
Telcordia
Technologies
GR-909 balance
■ac interface:
— Two SLIC gain options to minimize external com-
ponents required for interface to first- or third-gen-
eration codecs
— Sufficient dynamic range for direct coupling to
codec output
■28-pin PLCC/48-pin MLCC package
■90 V CBIC-S technology
Description
The L9216 is designed to provide battery feed, ringing,
and supervision functions on short plain old telephone
service (POTS) loops. This device is designed for
ultralow power in all operating states.
The L9216 offers eight operating states. The device
ass um e s us es of a l ow e r -v ol tage t alk batte r y, a high e r-
voltage ringing battery, and a VCC supply.
The L9216 requires only a positive VCC supply. No
–5 V supply is needed. The L9216 can operate with a
VCC of either 5 V or 3.3 V, allowing for greater user flex-
ibility. The choice of VCC voltage is transparent to the
user; the device will function with either supply voltage
connected.
Two batteries are used:
1. A high-voltage ring battery (VBAT1).
VBAT1 is a maximum –75 V. VBAT1 is used for power
ring signal amp li fic ation and for scan, on- hoo k
transmission, and ground start modes. This supply
is current limited to approximately the maximum
power ringing current, typically 50 mA.
2. A lower-voltage talk battery (VBAT2).
VBAT2 is used for active mode powering.
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 5
Description (continued)
Forward and reverse battery active modes are used for
off-hook conditions. Since this device is designed for
short-loop applications, the lower-voltage VBAT2 is
applied during the forward and reverse active states.
Battery reversal is quiet, without breaking the ac path.
Rate of battery reversal may be ramped to control
switching time.
The magnitude of the overhead voltage in the forward
and reverse active modes has a typical default value of
6.0 V, allowing for an undistorted signal of 3.14 dBm
into 900 Ω. This overhead is fixed. The ring trip detec-
tor is turned off during active modes to conserve power .
Because on-hook transmission is not allowed in the
scan mode, an on-hook transmission mode is defined.
This mode is functionally similar to the active mode,
except the tip ring voltage is derived from the higher
VBAT1 rather than VBAT2.
In the on-hook transmission modes with a primary
battery whose magnitude is greater than a nominal
51 V, the magnitude of the tip to ground and ring to
ground voltage is clamped at less than 56.5 V.
To minimize on-hook power , a low-power scan mode is
available. In this mode, all functions except off-hook
supervision are turned off to conserve power. On-hook
transmission is not allowed in the scan mode.
In the scan mode with a primary battery whose magni-
tude is greater than a nominal 51 V, the magnitude of
the tip to ground and ring to ground voltage is clamped
at less than 56.5 V.
A forward disconnect mode is provided, where all cir-
cuits are turned off and power is denied to the loop.
The device offers a ring mode, in which a power ring
signal is provided to the tip/ring pair. During the ring
mode, a user-supplied low-voltage ring signal (ac-cou-
pled) is input to the device’s RINGIN input. This signal is
amplified to produce the power ring signal. This signal
may be a sine wave or filtered square wave to produce
a sine wave on trapezoidal output. Ring trip detector
and common-mode current detector are active during
the ring mode.
This feature eliminates the need for a separate external
ring relay, associated external circuitry, and a bulk ring-
ing generator . See the Applications section of this data
sheet for more information.
The device offers a ground start mode. In this mode,
the t ip dr iv e ampli fie r is turn ed o ff . The devi ce pr es ent s
a high impedance (>100 kΩ) to PT and a current-lim-
ited battery (VBAT1) to PR. VBAT1 is clamped to less than
56.5 V in this mode as PR. A ring current detector for
ring ground detection is included for ground start appli-
cations. The threshold is user programmable via exter-
nal resistors. See the Applications section of this data
sheet for more information on supervision functions.
Output pin RGDET indicates current flowing in the ring
lead.
Both the ring trip and loop closure supervision func-
tions are included. The loop closure has a fixed typical
10.5 mA on- to off-hook threshold in the active mode
and a fixed 11.5 mA on- to off-hook threshold from the
scan mode. In either case, there is a 2 mA hysteresis.
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. The ring
trip threshold at a given battery voltage is fixed. T ypical
ring trip threshold is 42.5 mA for a –70 V VBAT1.
Upon reaching the thermal shutdown temperature, the
device will enter an all-off mode. Upon cooling, the
device will re-enter the state it was in prior to thermal
shutdown. Hysteresis is built in to prevent oscillation.
Longitudinal balance is consistent with North American
GR-909 requirements. S pecifications are given in Table
12.
Data control is via a parallel unlatched control scheme.
The dc current limit is fixed to either 25 mA or 40 mA
depending if ground or open is applied to the VPROG
current-limit programming pin. Programming accuracy
is ±8%.
Circuitry is added to the L9216 to minimize the inrush
of current from the VCC supply and to the battery supply
during an on- to off-hook transition, thus saving in
power supply design cost. See the Applications section
of this data sheet for more information.
Overhead in the active modes (VBAT2 applied) is fixed
to approximately 6.0 V is achieved. This is adequate
for a 3.14 dBm overload into 900 Ω.
Transmit and receive gains have been chosen to mini-
mize the number of external components required in
the SLIC-codec ac interface, regardless of the choice
of co dec.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
6 Agere Systems Inc.
Description (continued)
The L9216 uses a voltage feed-current sense architec-
ture; thus, the transmit gain is a transconductance. The
L9216 transconductance is set via a single external
resistor, and this device is designed for optimal perfor-
mance with a transconductance set at 300 V/A.
The L9216 offers an option for a single-ended to differ-
ential receive gain of either 8 or 2. These options are
mask programmable at the factory and are selected by
choice of code.
A receive gain of 8 is more appropriate when choosing
a first-generation type codec where termination imped-
ance, hybrid balance, and overall gains are set by
external analog filters. The higher gain is typically
required for synthesization of complex termination
impedance.
A receive gain of 2 is more appropriate when choosing
a third-generation type codec. Third-generation codecs
will synthesize termination impedance and set hybrid
balance and overall gains. To accomplish these func-
tions, third-generation codecs typically have both ana-
log and digital gain filters. For optimal signal to noise
performance, it is best to operate the codec at a higher
gain level. If the SLIC then provides a high gain, the
SLIC output may be saturate d causing clipping distor-
tion of the signal at tip and ring. To avoid this situation,
with a higher gain SLIC, external resistor dividers are
used. These external components are not necessary
with the lower gain offered by the L9216. See the Appli-
cations section of this data sheet for more information.
The L9216 is internally referenced to 1.5 V. This refer-
ence voltage is output at the VREF output of the device.
The SLIC output VITR is also referenced to 1.5 V;
therefore, it must be ac coupled to the codec input.
However, the SLIC inputs RCVP/RCVN are floating
inputs. If there is not feedback from RCVP/RCVN to
VITR, RCVP/RCVN may be directly coupled to the
codec output. If there is feedback from RCVP/RCVN to
VITR, RCVP/RCVN must be ac coupled to the codec
output.
The L9216 is packaged in a 28-pin PLCC package and
an ultrasmall 48-pin MLCC package. Use L9216A for
gain of eight applications and L9216G for gain of two
applications.
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 7
Architecture Diagram
12-3530.E (F)
Figure 1. Architecture Diagram
VREF
VITR
TXI
ITR
VTX
PT
PR
ICM
RGDET
CF2
CF1
FB2
FB1
POWER
AGND VCC BGND VBAT2 VBAT1 VPROG NSTAT RTFLT DCOUT
1.5 V
BAND-GAP
REFERENCE
AAC
B = 20
OUT (ITR/306)
TIP/RING
CURRENT
SENSE
+1
ITR
ITR
RFT
18 Ω
RFR
18 Ω
VREG
–1
VREG
RINGING
27.5x PARALLEL
DATA
INTERFACE
RINGIN B0 B1 B2
X1
X1
RCVN
RCVP
CURRENT
LIMIT
AND
INRUSH
CONTROL
RING
LOOP
RECTIFIERVTX
COMMON-
MODE
CURRENT
DETECTOR
TRIP
CLOSURE
VREF
–
+
9216A GAIN = 4
+
–
+
–
–
+
GAIN
AX
9216G GAIN = 1
ac INTERFACE
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
8 Agere Systems Inc.
Pin Information
12-3558.d (F)
Figure 2. 28-Pin PLCC
Figure 3. 48-Pin MLCC
B0
B1
B2
PR
PT
FB1
DCOUT
CF2
CF1
RTFLT
5
6
7
8
9
10
11
42128273
12 14 15 16 17 1813
25
24
23
22
21
20
19
NSTATVBAT2
AGND
ICM
RGDET
VBAT1
VCC
BGND
VPROG
RINGIN
VREF FB2
VTX
TXI
VITR
RCVP
RCVN
26
ITR
L9216 PR
28-PIN PLCC
1
3
4
6
7
8
9
10
11
12
2
48 46 45 44 43 42 41 40 38 3747
13 16 17 18 19 20 21 22 23 2414
36
33
32
31
30
29
28
27
26
25
35
B2
PT
FB1
AGND
RINGIN
PR
RCVN
NSTAT
RCVP
TXI
ITR
FB2
BGND
VREF
VBAT2
VITR
34
VTX
39
15
5
DCOUT
CF2
CF1
RTFLT
VCC
VBAT1
ICM
B1
B035
L9216A/G
48-PIN ML CC
RGDET
NC
NC
NC
NC
VPROG
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 9
Pin Information (continued)
Table 1. Pin Descriptions
28-Pin
PLCC 48-Pin
MLCC Symbol Type Name/Function
143NSTATOLoop Closure Detector Output—Ring Trip Detector Output.
When low, this logic output indicates that an off-hook condition
exists or ringing is tripped.
245VITROTransmit ac Output Voltage. Output of internal AAC amplifier.
This output is a voltage that is directly proportional to the differen-
tial ac tip/ring current.
3 47 RCVP I Receive ac Signal Input (Noninverting). This high-impedance
input controls the ac differential voltage on tip and ring. This node
is a floating input.
448RCVNIReceive ac Signal Input (Inverting). This high- impedance inpu t
controls the ac differential voltage on tip and ring. This node is a
floating inp ut.
51RING
IN IPower Ring Signal Input. ac-couple to a sine wave or lower crest
factor low-voltage ring signal. The input here is amplified to pro-
vide the full power ring signal at tip and ring. This signal may be
applied continuously, even during nonringing states.
66DCOUTOdc Output Voltage. This output is a voltage that is directly propor-
tional to the absolute value of the differential tip/ring current. This
is used to set ring trip threshold.
77V
PROG ICurrent-Limit Program Input. Connect ground to this pin to set
current-limit to 25 mA, float to this pin to set current limit to 40 mA.
89CF2—Filter Capacitor. Connect a capacitor from this node to ground.
910CF1—Filter Capacitor. Connect a capacitor from this node to CF2.
10 12 RTFLT — Ring Trip Filter . Connect this lead to DCOUT via a resistor and to
AGND with a capacitor to filter the ring trip circuit to prevent spuri-
ous responses. A single-pole filter is needed.
11 13 VREF OSLIC Internal Reference Voltage. Output of internal 1.5 V refer-
ence voltage.
12 15 AGND GND Analog Signal Ground.
13 16 VCC PWR Analog Power Supply. User choice of 5 V or 3.3 V nominal power
or supply.
14 19 VBAT1 PWR Battery Supply 1. High-voltage battery.
15 20 VBAT2 PWR Battery Supply 2. Lowe r-v oltage batte ry.
16 22 BGND GND Battery Ground. Ground return for the battery supplies.
— 2, 3, 4, 5, 8,
11, 14, 17,
18, 21, 27,
28, 30, 32,
36, 37, 39,
42, 44, 46
NC — No Connection.
17 23 RGDET O Ring Ground Detect. When high, this open collector output indi-
cates the presence of a ring ground or a tip ground. This supervi-
sion output may be used in ground key, ground start or common-
mode fault detection applications.
18 24 ICM I Common-Mode Current Sense. To program tip or ring ground
sense threshold, connect a resistor to VCC and connect a capacitor
to AGND to filter 50/60 Hz. If unused, the pin is connected to
ground.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
10 Agere Systems Inc.
Pin Information (continued)
Table 1. Pin Descriptions (continued)
Operating States
Table 2. Control States
Table 3. Supervision Coding
28-Pin
PLCC 48-Pin
MLCC Symbol Type Name/Function
19 25 FB2 —Polarity Reversal Slowdown Capacitor. Connect a capacitor from
this node to ground for controlling rate of battery reversal. If ramped
battery reversal is not desired, this pin is left open.
20 26 FB1 — Polarity Reversal Slowdown Capacitor. Connect a capacitor from
this node to ground for controlling rate of battery reversal. If ramped
battery reversal is not desired, this pin is left open.
21 29 PT I/O Protected Tip. The output drive of the tip amplifier and input to the
loop sensing circuit. Connect to loop through overvoltage and overcur-
rent protection.
22 31 PR I/O Protected Ring. The output drive of the ring amplifier and input to the
loop sensing circuit. Connect to loop through overvoltage and overcur-
rent protection.
23 33 B2 IdState Control Input. These pins have an internal 110 kΩ pull-down.
24 34 B1 Id
25 35 B0 Id
26 38 ITR I Transmit Gain. Input to AX amplifier. Connect a 4.75 kΩ resistor from
this node to VTX to set transmit gain. Gain shaping for termination
impedance with a first-generation codec is also achieved with a net-
work from this node to VTX.
27 40 VTX O ac Outp ut Voltage. Output of internal AX amplifier. The voltage at this
pin is directly proportional to the differential tip/ring current.
28 41 TXI I ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1 µF
capacitor from this pin to VTX.
B0 B1 B2 State
1 1 0 Forward active
1 0 0 Reverse active
1 1 1 On-hook transmission forward battery
1 0 1 On-hook transmission reverse battery
0 0 1 Ground start
011Scan
0 0 0 Disconnect, device will power up in this state
010Ring
NSTAT RGDET
0 = off-hook or ring trip or TSD.
1 = on-hook and no ring trip and no TSD or DISCONNECT state. 0 = no ring or tip ground.
1 = ring or tip ground.
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 11
State Definition s
Forward Active
■Pin PT is positive with respect to PR.
■VBAT2 is applied to tip/ring drive amplifiers.
■Loop closure and common-mode detect are active.
■Ring trip detector is turned off to conserve power.
■Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω.
Reverse Active
■Pin PR is positive with respect to PT.
■VBAT2 is applied to tip/ring drive amplifiers.
■Loop closure and common-mode detect are active.
■Ring trip detector is turned off to conserve power.
■Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900 Ω.
Scan
■Except for loop closure, all circuits (including ring trip
and common-mode detector) are powered down.
■On-hook transmission is disabled.
■Pin PT is positive with respect to PR, and VBAT1 is
applied to tip/ring.
■The tip to ring on-hook differential voltage will be typ-
icallybetween –44 V and –51 V with a –70 V primary
battery.
On-Hook Transmission—Forward Battery
■Pin PT is positive with respect to PR.
■VBAT1 is applied to tip/ring drive amplifiers.
■Supervision circuits, loop closure, and common-
mode detect are active.
■Ring trip detector is turned off to conserve power.
■On-hook transmission is allowed.
■The tip-to-ring on-hook differential voltage will be typ-
ically between –41 V and –49 V with a –70 V primary
battery.
On-Hook Transmission—Rever se Battery
■Pin PR is positive with respect to PT.
■VBAT1 is applied to tip/ring drive amplifiers.
■Supervision circuits, loop closure, and common-
mode detect are active.
■Ring trip detector is turned off to conserve power.
■On-hook transmission is allowed.
■The tip-to-ring on-hook differential voltage will be typ-
ically between –41 V and –49 V with a –70 V primary
battery.
Disconnect
■The tip/ring amplifiers and all supervision are turned
off.
■The SLIC goes into a high-impedance state.
■NSTAT is forced high (on-hook).
■Device will power up in this state.
Ring
■Power ring signal is applied to tip and ring.
■Input waveform at RINGIN is amplified.
■Ring trip supervision and common-mode current
supervision are active; loop closure is inactive.
■Overhead voltage is reduced to typically 4 V.
■Current is limited by saturation current of the amplifi-
ers themselves, typically 100 mA at 125 °C.
Ground St art
■Tip drive amplifer is turned off.
■Device presents a high impedance (>100 kΩ) to pin
PT.
■Device presents a clamped (<56.5 V) current-limited
battery (VBAT1) to PR.
■Output pin RGDET indicates current flowing in the
ring lead.
Thermal Shutdown
■Not controlled via truth table inputs.
■NSTAT is forced low (off-hook) during this state.
■This mode is caused by excessive heating of the
device, such as may be encountered in an extended
power cross situation.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
12 Agere Systems Inc.
Absolute Maximum Ratings (@ TA = 25 °C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when
powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor t o cause a destructive overvoltage.
Table 4. Recommended Operating Characteristics
Table 5. Thermal Characteristics
1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
Parameter Symbol Min Typ Max Unit
dc Supply (VCC) — –0.5 — 7.0 V
Battery Supply (VBAT1) ———–80V
Battery Supply (VBAT2) ———VBAT1 V
Logic Input Voltage — –0.5 — VCC + 0.5 V
Logic Output Voltage — –0.5 — VCC + 0.5 V
Operating Temperature Range — –40 — 125 °C
Storage Temperature Range — –40 — 150 °C
Relative Humidity Range — 5 — 95 %
PT or PR Fault Voltage (dc) VPT, VPR VBAT – 5 — 3 V
PT or PR Fault Voltage (10 x 1000 µs) VPT, VPR VBAT – 15 — 15 V
Ground Potential Difference (BGND to AGND) — — — ±1 V
Parameter Min Typ Max Unit
5 V dc Supplies (VCC)—5.05.25V
3 V dc Supplies (VCC)3.133.3—V
High Office Battery Supply (VBAT1) –60 –70 –75 V
Auxiliary Office Battery Supply (VBAT2) –12 — VBAT1 V
Operating Temperature Range –40 25 85 °C
Parameter Min Typ Max Unit
Thermal Protection Shutdown (Tjc)1150 165 — °C
28-pin PLCC Thermal Resistance Junction to Ambient (θJA)2:
Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board
—
—
—
—
35.5
50.5
31.5
42.5
—
—
—
—
°C/W
°C/W
°C/W
°C/W
48-pin MLCC Thermal Resistance Junction to Ambient (θJA)1, 2 —38—°C/W
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 13
Electrical Characteristics
Table 6. Environmental Characteristics
1. Not to exceed 26 grams of water per kilogram of dry air.
Table 7. 5 V Supply Currents
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 5 V.
Table 8. 5 V Powering
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 5 V.
Parameter Min Typ Max Unit
Temperature Range –40 — 85 °C
Humidi ty Rang e15—95
1%RH
Parameter Min Typ Max Unit
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
4.30
0.24
3
4.80
0.35
6
mA
mA
µA
Supply Currents (forward/reverse active; no loop current, with or without PPM,
VBAT2 applie d) :
IVCC
IVBAT1
IVBAT2
—
—
—
5.95
25
1.2
7.0
85
1.40
mA
µA
mA
Supply Currents (on-hook transmission mode; no loop current, with or without
PPM, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
6.0
1.5
1.5
7.0
1.9
6
mA
mA
µA
Supp ly Curr en ts (disconne ct mode):
IVCC
IVBAT1
IVBAT2
—
—
—
2.7
15
3.5
3.75
110
25
mA
µA
µA
Supply Currents (ground start mode, no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
4.0
0.24
2
—
—
—
mA
mA
µA
Supply Currents (ring mode; no load):
IVCC
IVBAT1
IVBAT2
—
—
—
5.9
1.8
2
6.5
2.2
6
mA
mA
µA
Parameter Min Typ Max Unit
Power Dissipation (scan state; no loop cur rent) — 38 46 mW
Power Dissipation (forward/reverse active; no loop current, VBAT2 applied) — 57 64 mW
Power Dissipation (on-hook transmission mode; no loop current, VBAT1 applied) — 135 165 mW
Power Dissipation (disconnect mode) — 14 23 mW
Power Dissipation (ground start mode) — 37 — mW
Power Dissipation (ring mode; no load) — 156 184 mW
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
14 Agere Systems Inc.
Electrical Characteristics (continued)
Table 9. 3.3 V Supply currents
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.
Table 10. 3.3 V Powering
VBAT1 = –70 V, VBAT2 = –21 V, VCC = 3.3 V.
Parameter Min Typ Max Unit
Supply Currents (scan state; no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
3.2
0.24
3
3.6
0.35
6
mA
mA
µA
Supply Currents (forward/reverse active; no loop current, VBAT2 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.8
25
1.2
5.7
85
1.4
mA
µA
mA
Supply Currents (on-hook transmission mode; no loop current, VBAT1 applied):
IVCC
IVBAT1
IVBAT2
—
—
—
4.9
1.5
1.5
5.7
1.9
6
mA
mA
µA
Supply Currents (disconnect mode):
IVCC
IVBAT1
IVBAT2
—
—
—
1.8
8
2
2.5
110
25
mA
µA
µA
Supply Currents (ground start mode, no loop current):
IVCC
IVBAT1
IVBAT2
—
—
—
3.1
0.24
2
—
—
—
mA
mA
µA
Supply Currents (ring mode; no load):
IVCC
IVBAT1
IVBAT2
—
—
—
4.70
1.8
2
5.4
2.2
6
mA
mA
µA
Parameter Min Typ Max Unit
Power Dissipation (scan state; no loop current) — 27 36.5 mW
Power Dissipation (forward/reverse active; no loop current, VBAT2 applied) — 42 53 mW
Power Dissipation (on-hook transmission mode; no loop current, VBAT1 applie d) — 121 151 mW
Power Dissipation (disconnect mode) — 6.5 15 mW
Power Dissipation (ground start mode) — 27 — mW
Power Dissipation (ring mode; no loop current) — 141 172 mW
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 15
Electrical Characteristics (continued)
Table 11. 2-Wire Port
Parameter Min Typ Max Unit
Tip or Ring Drive Current = dc + Longitudinal + Signal Currents 105 —— mAp
Tip or Ring Drive Current = Ringing + Longitudinal 65 — — mAp
Signal Current 10 — — mArms
Longitudinal Current Capability per Wire (Longitudinal current is indepen-
dent of dc loop current.) 8.5 15 — mArms
Ringing Current (RLOAD = 1386 Ω + 40 µF) 29 — — mArms
Ringing Current Limit (RLOAD = 100 Ω)——50mAp
dc Loop Current —ILIM (VBAT2 applied, RLOOP = 100 Ω):
VPROG = 0
VPROG = Open —
—25
40 —
—mA
mA
dc Current Variation — — ±8 %
dc Feed Resistance (does not include protection resistors) — 50 — Ω
Open Loop Voltages:
Scan Mode:
|VBAT1| > 51 V |V TIP| – |VRING|
PR to Battery Ground
PT to Battery Ground
OHT Mode:
|VBAT1| > 51 V |V TIP| – |VRING|
PR to Battery Ground
PT to Battery Ground
Active Mode:
|PT – PR| – |VBAT2|
Ring Mode:
|PT – PR| – |VBAT1|
44
—
—
41
—
—
5.75
—
51
—
—
49
—
—
6.25
4
—
56.5
56.5
—
56.5
56.5
6.75
—
V
V
V
V
V
V
V
V
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
16 Agere Systems Inc.
Electrical Characteristics (continued)
Table 11. 2-Wire Port ( conti nu ed)
Table 12. Analog Pin Characteristics
Parameter Min Typ Max Unit
Loop Closure Threshold:
Active/On-hook Transmission Modes
Scan Mode —
—10.5
11.5 —
—mA
mA
Loop Closure Threshold Hysteresis:
VCC = 5 V Active Mode
VCC = 3.3 V Active Mode
VCC = 5 V Ground Start Mode
VCC = 3.3 V Ground Start Mode
—
—
—
—
2
1
6
5
—
—
—
—
mA
mA
mA
mA
Longitudinal to Metallic Balance at PT/PR
Test Method: Q552 (11/96) Section 2.1.2 and
IEEE
® 455:
300 Hz to 600 Hz
600 Hz to 3.4 kHz 52
52 —
——
—dB
dB
Metallic to Longitudinal (harm) Balance:
200 Hz to 1000 Hz
100 Hz to 4000 Hz 40
40 —
——
—dB
dB
PSRR 500 Hz—3000 Hz:
VBAT1, VBAT2
VCC (5 V operation) 45
35 —
——
—dB
dB
Parameter Min Typ Max Unit
TXI (input impedance) — 100 — kΩ
Output Offset (VTX)
Output Offset (VITR)
Output Drive Current (VTX)
Output Drive Current (VITR)
Output Voltage Swing:
Maximum (VTX, VITR)
Minimum (VTX)
Minimum (VITR)
Output Short-circuit Current
Output Load Resistance
Output Load Capacitance
—
—
±300
±10
AGND
AGND + 0.25
AGND + 0.35
—
10
—
—
—
—
—
—
—
—
—
—
20
±10
100
—
—
VCC
VCC – 0.5
VCC – 0.4
±50
—
—
mV
mV
µA
µA
V
V
V
mA
kΩ
pF
RCVN and RCVP:
Input Voltage Range (VCC = 5 V)
Input Voltage Range (VCC = 3.3 V)
Input Bias Current
0
0
—
—
—
0.05
VCC – 0.5
VCC – 0.3
—
V
V
µA
Differential PT/PR Current Sense (DCOUT):
Gain (PT/PR to DCOUT)
Offset Voltage at ILOOP = 0 —
–20 67
——
20 V/A
mV
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 17
Electrical Characteristics (continued)
Table 13. ac Feed Characteristics
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between
150 Ω and 1400 Ω can be synthesized.
2. This parameter is not tested in produc tion. It is guaranteed by design and dev ice characterization.
3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 Ω, the recommended value. Positive cur-
rent is defined as the differential current flowing from PT to PR.
Parameter Min Typ Max Unit
ac Termination Impedance1150 600 1400 Ω
Total Harmonic Distortion (200 Hz—4 kHz)2:
Off-hook
On-hook —
——
—0.3
1.0 %
%
Transmit Gain (f = 1004 Hz, 1020 Hz, current limit)3:
PT/PR Current to VITR 300 – 3% 300 300 + 3% V/A
Receive Gain, f = 1004 Hz, 1020 Hz Open Loop:
RCVP or RCVN to PT—PR (gain of 8 option, L9216A)
RCVP or RCVN to PT—PR (gain of 2 option, L9216G) 7.76
1.94 8
28.24
2.06 —
—
Gain vs. Frequency (transmit and receive)2 600 Ω Termination,
1004 Hz, 1020 Hz Reference:
200 Hz—300 Hz
300 Hz—3.4 kHz
3.4 kHz—20 kHz
20 kHz—266 kHz
–0.3
–0.05
–3.0
—
0
0
0
—
0.05
0.05
0.05
2.0
dB
dB
dB
dB
Gain vs. Level (transmit and receive)2 0 dBV Reference:
–55 dB to +3.0 dB –0.05 0 0.05 dB
Idle-channel Noise (tip/ring) 600 Ω Termination:
Psophometric
C-Message
3 kHz F l at
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
Idle-channel Noise (VTX) 600 Ω Termination:
Psophometric
C-Message
3 kHz F l at
—
—
—
–82
8
—
–77
13
20
dBmp
dBrnC
dBrn
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
18 Agere Systems Inc.
Electrical Characteristics (continued)
Table 14. Logic Inputs and Outputs (VCC = 5 V)
Table 15. Logic Inputs and Outputs (VCC = 3.3 V)
Table 16. Ground Start
Parameter Symbol Min Typ Max Unit
Input Voltages:
Low Level
High Level
VIL
VIH –0.5
2.0 0.4
2.4 0.7
VCC V
V
Input Current:
Low Level (VCC = 5.25 V, VI = 0.4 V)
High Level (VCC = 5.25 V, VI = 2.4 V) IIL
IIH —
——
—±50
±50 µA
µA
Output Voltages (open collector with internal pull-up resistor):
Low Level (VCC = 4.75 V, IOL = 200 µA)
High Level (VCC = 4.75 V, IOH = –20 µA) VOL
VOH 0
2.4 0.2
—0.4
VCC V
V
Parameter Symbol Min Typ Max Unit
Input Voltages:
Low Level
High Level
VIL
VIH –0.5
2.0 0.2
2.5 0.5
VCC V
V
Input Current:
Low Level (VCC = 3.46 V, VI = 0.4 V)
High Level (VCC = 3.46 V, VI = 2.4 V) IIL
IIH —
——
—±50
±50 µA
µA
Output V oltages (open collector with internal 60 kΩ pull-up resi stor):
Low Level (VCC = 3.13 V, IOL = 200 µA)
High Level (VCC = 3.13 V, IOH = –5 µA) VOL
VOH 0
2.2 0.2
—0.5
VCC V
V
Parameter Min Typ Max Unit
Tip Open Mode:
Tip Input Impedance 150 — — kΩ
Detector Accuracy — — 20 %
Detection 50 — — ms
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 19
Electrical Characteristics (continued)
Table 17. Ringing Specifications
Table 18. Ring Trip
Ringing will not be tripped by the following loads:
■10 kΩ resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
■100 Ω resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
Parameter Min Typ Max Unit
RINGIN (This input is ac coupled through 0.47 µF.):
Input V oltage Swing
Input Impedance 0
——
100 VCC
—V
kΩ
Ring Signal Isolation:
PT/PR to VITR
Ring Mode
—60—dB
Ring Signal Isolation:
RINGIN to PT/PR
Nonring Mode
—80—dB
Ringing Voltage (5 REN 1380 Ω + 40 µF load, 100 Ω loop, 2 x 50 Ω protection
resistor s, –70 V batt ery) 40 — — Vrms
Ringing Voltage (3 REN 2310 Ω + 24 µF load, 250 Ω loop, 2 x 50 Ω protection
resistor s, –70 V batt ery) 40 — — Vrms
Ring Signal Distortion:
5 REN 1380 Ω, 40 µF Load, 100 Ω Loop
3 REN 2310 Ω, 24 µF Load, 250 Ω Loop —
—3
3—
—%
%
Differential Gain:
RINGIN to PT/PR—No Load — 55 — —
Parameter Min Typ Max Unit
Ring Trip (NSTAT = 0): Loop Resistance (total) High Battery 100 — 600 Ω
Ring Trip (NSTAT = 1): Loop Resistance (total) High Battery — — 10 kΩ
Trip Time (f = 20 Hz) — — 100 ms
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
20 Agere Systems Inc.
Test Configurations
12-3531.h (F)
Figure 4. Basic Test Circuit
VBAT2 VBAT1 BGND VCC AGND ICM RGDET
0.1 µF
0.1 µF
0.1 µF
RTFLT
DCOUT
PR
PT
VPROG
VREF
0.1 µF
383 kΩ
30 Ω
30 Ω
CF1
CF2
B0
B1
B2
0.1 µF
RINGIN
VITR
RCVP
RCVN
ITR
VTX
TXI
VBAT2 VBAT1 VCC
0.47 µF
RLOOP
100 Ω/600 Ω
TIP
RING
FB2
FB1
0.1 µF
L9216
NSTAT
B0
B1
B2
4750 Ω
0.1 µF
VITR
RCV
RINGIN
114 kΩ
0.1 µF
60.4 kΩ
0.1 µF
26.7 kΩ
69.8 kΩRCV
VCC
BASIC
TEST
CIRCUIT
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 21
Test Configurations (continued)
12-2582.c (F)
Figure 5. Metallic PSRR
12-2583.b (F)
Figure 6. Longitudinal PSRR
12-2584.c (F)
Figure 7. Longitudinal Balance
12-2587.G (F)
Figure 8. ac Gains
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
VT/R
VBAT OR VCC
TIP
RING
BASIC
TEST CIRCUIT
+
–
PSRR = 20log VS
VT/R
600 Ω
BYPASS CAPACITOR
VS
4.7 µF
100 Ω
VBAT OR
VCC
DISCONNECT
BYPASS CAPACITOR
56.3 Ω
VBAT OR VCC
TIP
RING
BASIC
TEST CIRCUIT
PSRR = 20log VS
VM
67.5 Ω
10 µF
10 µF
67.5 Ω
VM
+
–
TIP
RING
BASIC
TEST CIRCUIT
LONGITUDINAL BALANCE = 20log VS
VM
368 Ω
100 µF
100 µF
368 Ω
VM
+
–
VS
PT
PR
BASIC
TEST CIRCUIT
600 ΩVT/R
+
–
GXMT =VXMT
VT/R
GRCV =VT/R
VRCV
RCV
VS
VITR
RCV
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
22 Agere Systems Inc.
Applications
Power Con t ro l
Under normal device operating conditions, power dissi-
pation on the device must be controlled to prevent the
device temperature from rising above the thermal shut-
down and causing the device to shut down. Power dis-
sipation is highest with higher battery voltages, higher
current limit, and under shorter dc loop conditions.
Additionally, higher ambient temperature will also
reduce thermal margin.
To support required power ringing voltages, this device
is meant to operate with a high-voltage primary battery
(–65 V to –75 V typically). Thus, power control is nor-
mally achieved by use of the battery switch and an aux-
iliary lower absolute voltage battery. Operating
temperature range, maximum current limit, maximum
battery voltage, minimum dc loop length and protection
resistor values, airflow , and number of PC board layers
will influence the overall thermal performance. The fol-
lowing example illustrates typical thermal design con-
siderations.
The thermal resistance of the 28-pin PLCC package is
typi ca lly 35 . 5 °C/ W, whic h i s r epresent a t ive of t h e n at u-
ral airflow as seen in a typical switch cabinet with a
multilayer board.
The L9216 will enter thermal shutdown at a tempera-
ture of 150 °C. The thermal design should ensure that
the SLIC does not reach this temperature under normal
operating conditions.
For this example, assume a maximum ambient operat-
ing temperature of 85 °C, a maxi mum current limit of
30 mA, a maximum battery of –75 V, and an auxiliary
battery of –21 V. Assume a (worst-case) minimum dc
loop of 20 Ω of wire resistance, 30 Ω protection resis-
tors, and 200 Ω for the handset. Additionally, include
the effects of parameter tolerance.
1. TTSD – TAMBIENT(max) = allowed thermal rise.
150 °C – 85 °C = 65 °C.
2. Allowed thermal rise = package thermal
impedance • SLIC power dissipation.
65 °C = 35.5 °C/W • SLIC power dissipation
SLIC power dissipation (PD) = 1.83 W.
Thus, if the total power dissipated in the SLIC is less
than 1.83 W, it will not enter the thermal shutdown
state. Total SLIC power is calculated as:
Total PD = maximum batter y • maximum current
limit + SLIC quiescent power.
For the L9216, the worst-case SLIC on-hook active
power is 75 mW. Thus,
Total off-hook power = (ILOOP)(current-limit
tolerance)*(VBATAPPLIED) + SLIC on-hook power
Total off-hook power = (0. 030 A)( 1.08 ) * (21 ) +
75 mW
Total off-hook power = 755.4 mW
The power dissipated in the SLIC is the total power dis-
sipation less the power that is dissipated in the loop.
SLIC PD = total power – loop power
Loop off-hook power = (ILOOP * 1.08)2 • (RLOOP(dc)
min + 2RHANDSET)
Loop off-hook power = (0.030 A)(1.08)2 • (20 Ω +
60 Ω + 200 Ω)
Loop off-hook power = 293.9 mW
SLIC off-hook power = Total off-hook power – loop
off-hook power
SLIC off-hook power = 755.4 mW – 293.9 mW
SLIC off-hook power = 461.5 mW < 1.83 W
Thus, under the operating conditions of this example,
the thermal design, using the auxiliary, is adequate to
ensure the device is not driven into thermal shutdown
under worst-case operating conditions.
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 23
Applications (continued)
dc Loop Current Limit
Current limit may be chosen from two discrete values,
25 mA or 40 mA, depending on if VPROG is grounded
(25 mA) or left floating (40 mA). Note that there is a
12.5 kΩ slope to the I/V characteristic in the current-
limit region; thus, once in current limit, the actual loop
current will increase slightly, as loop length decreases.
The above describes the active mode steady-state cur-
rent-limit response. There will be a transient response
of the current-limit circuit upon an on- to off-hook transi-
tion. Typical active mode transient current-limit
response is given in Table 19.
Table 19. Typical Active Mode On- to Off-Hook Tip/
Ring Current-Limit Transient Response
Overhead Voltage
Active Mode
Overhead is fixed to a nominal 6.0 V , which is adequate
for on-hook transmission of 3.14 dBm into 900 Ω.
Scan Mode
If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 44 V and
51 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 4 V to 6 V less
than battery. In the scan mode, overhead is unaffected
by VOVH.
On Hook Transmission Mode
If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 41 V and
49 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 6 V to 8 V less
than battery. In the scan mode, overhead is unaffected
by VOVH.
Parameter Value Unit
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 5 ms
ILIM + 60 mA
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 50 ms
ILIM + 20 mA
dc Loop Current:
Active Mode
RLOOP = 100 Ω On- to Off-hook
Transition t < 300 ms
ILIM mA
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
24 Agere Systems Inc.
Applications (continued)
Overhead Voltag e (continued)
Ring Mode
In the ring mode, to maximize ringing loop length, the
overhead is decreased to the saturation of the tip ring
drive amplifiers, a nominal 4 V. The tip to ground volt-
age is 1 V, and the ring to VBAT1 voltage is 3 V.
During the ring mode, to conserve power, the receive
input at RCVN/RCVP is deactivated. During the ring
mode, to conserve power, the AAC amplifier in the
transmit direction at VITR is deactivated. However, if
the AX amplifier at VTX is active during the ring mode,
differential ring current may be sensed at VTX during
the ring mode.
Loop Range
The dc loop range is calculated using:
RL = – 2RP – RDC
VBAT2 is typically applied under off-hook conditions for
power conservation and SLIC thermal considerations.
The L9216 is intended for short-loop applications and,
therefore, will always be in current limit during off-hook
conditions. However, note that the ringing loop length
rather than the dc loop length, will be the factor to
determine operating loop length.
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by
capacitors FB1 and FB2. Table 20 below shows FB1
and FB2 values vs. typical ramp time. Leave FB1 and
FB2 open if it is not desired to ramp the rate of battery
reversal.
Table 20. FB1 and FB2 Values vs. Typical Ramp
Time
Supervision
The L9216 offers the loop closure and ring trip supervi-
sion functions. Internal to the device, the outputs of
these detectors are multiplexed into a single package
output, NSTAT. Additionally, a common-mode current
detector for tip or ring ground detection is included for
ground key applications.
Loop Closure
The loop closure has a fixed typical 10.5 mA on- to off-
hook threshold in the active mode and a fixed 11.5 mA
on- to off-hook threshold from the scan mode. In either
case, there is a 2 mA hysteresis with VCC = 5 V and a
1 mA hysteresis with VCC = 3.3 V.
Ring Trip
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. An R/C
combination of 383 kΩ and 0.1 µF, for a filter pole at
5.15 Hz, is recommended.
The ring trip threshold is internally fixed as a function of
battery voltage and is given by:
RT (mA) = 67 * {(0.0045 * VBAT1) + 0.317}
where:
RT is ring trip current in mA.
VBAT1 is the magnitude of the ring battery in V.
There is a 6 mA to 8 mA hysteresis.
Tip or Ring Ground Detecto r
In the ground key or ground start applications, a com-
mon-mode current detector is used to indicate either a
tip- or ring-ground has occurred (ground key) or an off-
hook has occurred (ground start).
For ground start applications detection may be seen at
the output of the common mode current detector
(RGDET) or the loop closure detector (NSTAT).
If ICM is used, the detection threshold is set by con-
necting a resistor from ICM to VCC.
205 x VCC/RICM (kΩ) = ITH (mA)
Additionally, a filter capacitor across RICM will set the
time constant of the detector. No hysteresis is associ-
ated with this detector. The RC filter at ICM gives
immunity to longitudinal currents.
CFB1 and CFB2 Transition Time
0.01 µF 20 ms
0.1 µF 2 20 ms
0.22 µF 440 ms
0.47 µF 900 ms
1.0 µF 1.8 s
1.22 µF2.25 s
1.3 µF 2.5 s
1.4 µF 2.7 s
1.6 µF 3.2 s
VBAT2 VOH–
ILIMIT
--------------------------------------
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 25
Supervision (continued)
Tip or Ring Ground Detector (continued)
Also in the ground start mode, the fixed loop current
thr eshol d as soci ate d w ith the N STAT de tec tor outp ut i s
internally adjusted to account for common-mode cur-
rent detection in ground start mode (as opposed to dif-
ferential current in loop start mode) maintain the
detector at 10 mA. Thus, NSTAT may also be used for
loop closure detion in ground start. However, the detec-
tor at NSTAT is not filtered against longitudinal cur-
rents, which may or may not be an issue in short loop
applications. Using NSTAT will also save components
at ICM.
Power Ring
The device offers a ring mode, in which a balanced
power ring signal is provided to the tip/ring pair. During
the ring mode, a user-supplied low-voltage ring signal
is input to the device’s RINGIN input. This signal is
amplified to produce the balanced power ring signal.
The user may supply a sine wave input, PWM input, or
a square wave to produce sinusoidal or trapezoidal
ringing at tip and ring.
Various crest factors are shown for illustrative pur-
poses.
12-3346a (F)
Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms ;
period = 50 ms.
Figure 9. Ringing Waveform Crest Factor = 1.6
12-3347a (F)
Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms ;
period = 50 ms.
Figure 10. Ringing W avefo rm Crest Factor = 1.2
Voltage applied to the load may be increased by using
a filtered square wave input to produce a lower crest
factor trapezoidal power ring signal at tip and ring.
TIME (s)
–80
–60
–40
–20
0
20
40
60
80
0.00
0.02 0.06
0.04 0.08
0.10
0.12
0.14
0.16
0.18
0.20
VOLTS (V)
TIME (s)
–80
–60
–40
–20
0
20
40
60
80
0.00
0.02 0.06
0.04 0.08
0.10
0.12
0.14
0.16
0.18
0.20
VOLTS (V)
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
26 Agere Systems Inc.
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring
Signal Output
The low-voltage sine wave input is applied to the L9216
at pin RINGIN. This signal should be ac-coupled
through 0.47 µF. During the ring mode, the signal at
RINGIN is amplified and presented to the subscriber
loop. The differential gain from RINGIN to tip and ring is
a nominal 55.
When the device enters the ring mode, the tip/ring
overhead set at OVH and the scan clamp circuit is dis-
abled, allowing the voltage magnitude of the power ring
signal to be maximized. Additionally, in the ring mode,
the loop current limit is increased 2.5X the value set by
the VPROG voltage.
The magnitude of the power ring voltage will be a func-
tion of the gain of the ring amplifier, the high voltage
battery , and the input signal at RINGIN. The input range
of the signal at RINGIN is 0 V to Vcc. As the input volt-
age at RINGIN is increased, the magnitude of the power
ring voltage at tip and ring will increase linearly, per the
differential gain of 55, until the tip and ring drive amplifi-
ers begin to saturate. Once the tip and ring amplifiers
reach saturation, further increases of the input signal
will cause clipping distortion of the power ring signal
at tip and ring. The ring signal will appear balanced on
tip and ring. That is, the power ring signal is applied
to both tip and ring, with the signal on tip 180°
(180 degrees) out of phase from the signal on ring.
Figure 11 shows typical operation of the ring mode,
prior to saturation of the tip and ring drive amplifiers. A
–70 V battery is used with a 100 Ω loop and a 1 REN
load. The input signal is 1 V through a 0.47 µF capaci-
tor at RINGIN, (the input circuit is shown in Figure 12).
This produces a voltage swing from –34 V to –60 V
on ring and from –8 V to –34 V on tip, as shown in
Figu re 11. Thus , the t ota l volt age swing is 52 V (6 0 V to
8 V) for a 1 V input, which is approximately the differen-
tial gain of the device. Note that the tip and ring power
ring signals will swing around VBATTERY divided by two.
In this case, there is a –70 V battery so tip and ring
swing around –34 V.
12-3573F
12-3574F
Figure 11. Ring Mode Typical Operation
0
–600.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78
TIME
0.80
–20
–40
VRING VTIP
1.0
–1.00.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 0.76 0.78
TIME
0.80
0.5
0.0
–0.5
VRINGIN
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 27
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)
It is recommended that the input level at RINGIN be adjusted so that the power ring signal at tip and ring is just at
the edge or slightly clipping. This gives maximum power transfer with minimal distortion of the sine wave. The tip
side will saturate at a nominal 1 V above ground. The ring side will saturate at a nominal 3 V above battery. The
input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in Figure 12.
12-3532J
Figure 12. RINGIN Operation
The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the
input capacitor at RINGIN, and the input signal at RINGIN and Vcc. Typical characteristic conditions showing the
onset of clipping are given below .
Table 21. Onset of Power Ringing Clipping VCC = 5 V, Cinput = 0.47 µF
Table 22. Onset of Power Ringing Clipping VCC = 3.1 V, Cinput = 0.47 µF
Input T/R
VBAT1 (V) Vrms (mV) Vrms (V) Gain
–70.15 891 46.88 52.62
–68.06 858 45.11 52.58
–66.00 833 43.69 52.45
–64.08 814 42.57 52.30
–62.04 789 41.21 52.23
–60.05 747 39.11 52.36
Input T/R
VBAT1 (V) Vrms (mV) Vrms (V) Gain
–70.12 894 47.15 52.74
–68.07 855 45.11 52.76
–66.06 824 43.38 52.65
–64.01 799 41.95 52.5
–62.00 780 40.79 52.29
–60.00 749 39.09 52.19
GND
VBAT
PT +1
TR
27.5x
RINGIN 0.47 µFINPUT
L9216
VTIP
VRING
–1
3 V
100 kΩ
1 V
VBAT = –75 V
71 V
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
28 Agere Systems Inc.
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)
During nonring modes, the sinusoidal ringing waveform may be left on at RINGIN. Via the state table, the ring signal
will be removed from tip and ring even if the low- voltage input is still present at RINGIN. There are certain timing
considerations that should be made with respect to state changes which are detailed in the
Switching Behavior of
L9215/6 Ringing SLIC
Application Note.
PWM Input Signal a nd Sine Wave Power Ring Signal Output
A pulse-width modulated (PWM) signal may be used to provide the ringing input to RINGIN. The signal is applied
through a low-pass filter and ac-coupled into RINGIN as shown in Figure 13 below. This approach gives a sine
wave output at tip and ring.
12-3578bF
Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs
Table 23. Signal and Component Selection Chart
VBAT VCC Input R1 C1 C2 CF Typical 5 REN Ringing Voltage RMS
70 V 5 V 5 V Square 12 kΩ1 µF0.47 µF 1.3 48 V
70 V 3 V 3 V Square 7 kΩ1 µF0.47 µF 1.3 49 V
70 V 5 V 10 kHz PWM 5 V 10 kΩ0.22 µF0.47 µFsine 42 V
70 V 3 V 10 kHz PWM 3 V 10 kΩ0.22 µF0.47 µFsine 42 V
70 V 5 V 90 kHz PWM 5 V 7 kΩ0.1 µF0.47 µFsine 42 V
70 V 3 V 90 kHz PWM 3 V 7 kΩ0.1 µF0.47 µFsine 42 V
85 V 5 V 5 V Square 10 kΩ1 µF0.47 µF 1.3 59 V
85 V 3 V 3 V Square 7 kΩ1 µF0.47 µF 1.3 51 V
85 V 5 V 10 kHz PWM 5 V 10 kΩ0.22 µF0.47 µFsine 51 V
85 V 3 V 10 kHz PWM 3 V 4 kΩ0.22 µF0.47 µFsine 47 V
85 V 5 V 90 kHz PWM 5 V 4 kΩ0.1 µF0.47 µFsine 51 V
85 V 3 V 90 kHz PWM 3 V 4 kΩ0.1 µF0.47 µFsine 49 V
INPUT R1
C1
C2RINGIN
L9215/16
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 29
Supervision (continued)
Power Ring (continued)
PWM Input Signal and Sine Wave Power Ring Sig-
nal Output (continued)
Modulation waveforms showing PWM are in Figure 14
below.
Figure 14. Modulation Waveforms
5 V VCC Operation
A PWM signal was generated with an
HP
™ 8116
Function Generator modulated with a 20 Hz signal. The
optimal frequency used was 10 kHz. The PWM signal
amplitude was 5.0 V (0 V to 5 V). This signal is shown
in Figure 15.
12-3575F
Figure 15. 5 V PWM Signal Amplitude
This input produced 44.96 Vrms ringing signal on
tip/ring under open-loop conditions and 42.0 V rms was
delivered to 5 REN load. The ringing output on ring,
with VCC = 5 V, is shown in Figure 16.
1660
Notes:
The modulating 20 Hz signal THD was measured at 1.3%.
The tip/ring 20 Hz signal THD was measured at 1%.
VBAT1 = –70.6 V, VBAT2 = –26.5 V, VCC = 5.019 V.
PWM input 10 kHz, 5.0 Vp-p.
R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.
Figure 16. Ringing Output on RING, with VCC = 5 V
12-3381(F)
A. Upper = Pwm Signal Centered at 10 kHz
Lower = Modulation Signal
12-3380(F)
B. Same as A but Expanded
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
30 Agere Systems Inc.
Supervision (continued)
Power Ring (continued)
3.3 V VCC Operation
A PWM signal was generated with an
HP
8116 Func-
tion Generator modulated with a 20 Hz signal. The opti-
mal frequency used was 10 kHz. The PWM signal
amplitude was 3.10 V (0 V to 3.10 V). This input signal
is shown in Figure 17.
12-3571F
Figure 17. 3.3 V PWM Signal Amplitude
This produced 44.96 Vrms ringing signal on tip/ring
under open-loop conditions and 42.0 Vrms was deliv-
ered to 5 REN load. The ringing output on ring with VCC
= 3.1 V is shown in Figure 18.
1660
Notes:
The modulating 20 Hz signal THD was measured at 1.3%.
The tip/ring 20 Hz signal THD was measured at 1%.
VBAT1 = –70.6 V, VBA T2 = –26.5 V, VCC = 3.10 V.
PWM input 10 kHz, 3.1 Vp-p.
R1 = 10 kΩ, C1 = 0.22 µF, C2 = 0.47 µF.
Figure 18. Ringing Output on RING, with VCC = 3.1 V
During nonring modes, the PWM waveform may be left
on at RINGIN. Via the state table, the ring signal will be
removed from tip and ring even if the low-voltage input
is still present at RINGIN. There are certain timing con-
siderations that should be made with respect to state
changes which are detailed in the
Switchi ng Beh av ior
of L9215/6 Ringing SLIC
Application N ote.
Square Wave Input Signal and Trapezoidal Power
Ring Signal Output
A low-voltage square wave signal may be used to pro-
vide the ringing input to RINGIN. The signal is applied
through a low-pass filter and ac-coupled into RINGIN as
shown in Figure 13 and Table 23. This approach gives
a trapezoidal wave output at tip and ring.
Using this approach, a trapezoidal waveform can be
achieved at tip and ring. This has the advantage of
increasing the power transfer to the load for a given
battery voltage, thus increasing the effective ringing
loop length as compared to a sine wave. The actual
crest factor achieved is a function of the magnitude of
the battery, the magnitude of the input voltage, fre-
quency, and R1.
12-3572F
Notes:
CH1—CMOS Input (5 V) at RINGIN.
CH2—Filtered input at RINGIN.
CH3—Tip.
CH4—Ring.
R1 = 14 kΩ, C1 = 1.0 µF, C2 = 0.47 µF.
VBAT1 = –70 V, Vrms = 51 V, Vp-p = 67 V, frequency = 20 Hz, Crest
Factor = 1.3.
Figure 19. Square Wave Input Signal and Trapezoi-
dal Power Ring Signal Output
CH1
CH2
CH3
CH4
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 31
Supervision (continued)
Power Ring (continued)
Square Wave Input Signal and Trapezoidal Power Ring Signal Output (continued)
Figure 20 and Figure 21 provide some guidance to the relationship between crest factor, battery voltage, and R1
value.
12-3576F
Figure 20. Crest Factor vs. Battery Voltage
12-3577F
Figure 21. Crest Factor vs. R (kΩ)
During nonring modes, the square wave input may be left on or removed from RINGIN. Via the state table, the ring
signal will be removed from tip and ring even if the low-voltage input is still present at RINGIN. However, removing
the waveform has certain advantages in terms of the timing of state. These advantages are detailed in the
Switch-
ing Behavior of L9215/16 Ringing SLIC
Applic ation Note.
1.36
58 BAT V
CF
60 62 64 66 68 70 72
1.35
1.34
1.33
1.32
1.31
1.3
1.29
1.28
1.27
1.26
1.5
1.45
10 R (kΩ)
CF
1.4
1.35
1.3
1.25 10.5 11 11.5 12 12.5 13 13.5 14
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
32 Agere Systems Inc.
ac Applications
ac Parameters
There are four key ac design parameters. Termination
impedance is the impedance looking into the 2-wire
port of the line card. It is set to match the impedance of
the telephone loop in order to minimize echo return to
the telephone set. T ransmit gain is measured from the
2-wire port to the PCM highway, while receive gain is
done from the PCM highway to the transmit port.
Transmit and receive gains may be specified in terms
of an actual gain, or in terms of a transmission level
point (TLP), that is the actual ac transmission level
in dBm. Finally, the hybrid balance network cancels
the unwanted amount of the receive signal that
appears at the transmit port.
Codec Types
At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. Below is a brief codec
feature summary.
First-Generation Codecs
These perform the basic filtering, A/D (transmit), D/A
(receive), and µ-law/A-law companding. They all have
an op amp in front of the A/D converter for transmit
gain setting and hybrid balance (cancellation at the
summing node). Depending on the type, some have
differential analog input stages, differential analog out-
put stages, 5 V only or ±5 V operation, and µ-law/A-law
selectability. These are available in single and quad
designs. This type of codec requires continuous time
analog filtering via external resistor/capacitor networks
to set the ac design parameters. An example of this
type of codec is the Agere T7504 quad 5 V only codec.
This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Further ac parameters are fixed by the external R/C
network so software control of ac parameters is diffi-
cult.
Third-Generation Codecs
This class of devices includes all ac parameters set
digitally under microprocessor control. Depending on
the device, it may or may not have data control latches.
Additional functionality sometimes offered includes
tone plant generation and reception, PPM generation,
test algorithms, and echo cancellation. Again, this type
of codec may be 3.3 V, 5 V only, or ±5 V operation, sin-
gle quad or multichannel, and µ-law/A-law or 16-bit lin-
ear coding selectable. Examples of this type of codec
are the Agere T8535/6 (5 V only, quad, standard fea-
tures), T8537/8 (3.3 V only, quad, standard features),
T8533/4 (5 V only, quad with echo cancellation), and
the T8531/32 (5 V only multichannel).
ac Interface Network
The ac interface network between the L9216 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9216 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set dig-
itally, internal to the codec; thus, the interface between
the L9216 and this type of codec is designed to avoid
overload at the codec input in the transmit direction
and to optimize signal to noise ratio (S/N) in the receive
direction.
Because the design requirements are very different
with a first- or third-generation codec, the L9216 is
offered with two different receive gains. Each receiv e
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9216
and codec.
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 33
ac Applications (continued)
ac Interface Network (continued)
With a first-generation codec, the termination imped-
ance is set by providing gain shaping through a feed-
back network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9216 provides a transcon-
ductance from T/R to VITR in the transmit direction and
a single-ended to differential gain from either RCVN or
RCVP to T/R in the receive direction. Assuming a short
from VITR to RCVN or RCVP, the maximum imped-
ance that is seen looking into the SLIC is the product of
the SLIC transconductance multiplied by the SLIC
receive gain, plus the protection resistors. The various
specified termination impedances can range over the
voiceba nd as low as 300 Ω up to over 1000 Ω. Thus, if
the SLIC gains are too low , it will be impossible to syn-
thesize the higher termination impedances. Further, the
termination that is achieved will be far less than what is
calculated by assuming a short for SLIC output to SLIC
input. In the receive direction, in order to control echo,
the gain is typically a loss, which requires a loss net-
work at the SLIC RCVN/RCVP inputs, which will
reduce the amount of gain that is available for termina-
tion impedance. For this reason, a high-gain SLIC is
required with a first-generation codec.
With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination imped-
ance, hybrid balances, and transmission level point
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voiceband frequency, must ensure the
codec is not overloaded. With a given TLP and a given
SLIC gain, if the signal will cause a codec overload, the
designer must insert some sort of loss, typically a resis-
tor divider, between the SLIC output and codec input.
Note also that some third-generation codecs require
the designer to provide an inherent resistive termina-
tion via external networks. The codec will then provide
gain shaping, as a function of frequency, to meet the
return loss requirements. This feedback will increase
the signal at the codec input and increase the likeli-
hood that a resistor divider is needed in the transmit
direction. Further stability issues may add external
components or excessive ground plane requirements
to the design.
In the receive direction, the issue is to optimize the
S/N. Again, the designer must consider all the consid-
ered TLPs. The idea, for all desired TLPs, is to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember, noise floor is
constant, so the hotter the signal from the codec, the
better the S/N. The problem is if the codec is feeding a
high gain SLIC, either an external resistor divider is
needed to knock the gain down to meet the TLP
requirements, or the codec is not operated near maxi-
mum signal levels, thus compromising the S/N.
Thus, it appears that the solution is to have a SLIC with
a low gain, especially in the receive direction. This will
allow the codec to operate near its maximum output
signal (to optimize S/N), without an external resistor
divider (to minimize cost).
To meet the unique requirements of both types of
codecs, the L9216 offers two receive gain choices.
These receive gains are mask-programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9216 is
offered with a receive gain of 8. For interface with a
third-generation codec, the L9216 is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction or the transmit gain is 300 Ω.
These receive gain options afford the designer the flex-
ibility to maximize performance and minimize external
components, regardless of the type of codec chosen.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
34 Agere Systems Inc.
ac Applications (continued)
Design Examples
First-Generation Codec ac Interface Network—
Resistive Te rmination
The reference circuit in Figure 23 shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for a resistive termination imped-
ance. For this example, the ac interface was designed
for a 600 Ω resistiv e ter min ati on and hy br id bal ance
with transmit gain and receive gain set to 0 dBm.
This is a lower feature application example and uses
single battery operation, fixed overhead, current limit,
and loop closure threshold.
Resisto r RGN is optional. It compensates for any mis-
match of input bias voltage at the RCVN/RCVP inputs.
If it is not used, there may be a slight offset at tip and
ring due to mismatch of input bias voltage at the
RCVN/RCVP inputs. It is very common to simply tie
RCVN directly to ground in this particular mode of oper-
ation. If used, to calculate RGN, the impedance from
RCVN to ac ground should equal the impedance from
RCVP to ac ground.
Example 1, Real Termination
The following design equations refer to the circuit in
Figure 22. Use these to synthesize real termination
impedance.
Termination Impedance:
zT =
Receive Gain:
Transmit Gain:
Hybrid Balance:
hbal = 20l og
hbal = 20log
To optimize the hybrid balance, the sum of the currents
at the VFX input of the codec op amp should be set to
0. The expression for ZHB becomes the following:
VT/R
IT/R–
------------
zT50 Ω2+RP2400
1RT1
RGP
---------RT1
RRCV
------------
++
-----------------------------------
+=
grcv VT/R
VFR
------------
=
grcv 8
1RRCV
RT1
----------- RRCV
RGP
------------
++
1ZT
ZT/R
---------
+
------------------------------------------------------------------
=
gtx VGSX
VT/R
-----------
=
gtx RX–
RT2
--------- 300
ZT/R
---------
×
=
RX
RHB
------------gtx–grcv×
VGSX
VFR
---------------
RHB kΩ() RX
gtx grcv×
-------------------
=
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 35
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
0586 (F)
Figure 22. ac Equivalent Circuit
Figure 23. Agere T7504 First-Generation Codec Resistive Termination
RP
ZT+
–
RP
VT/R
IT/R
VS
ZT/R
+
–
RING AV = –1
AV = 1
VITR
CURRENT
SENSE
TIP
+
–
RT1
RRCV
RHB1
RT2
RCVN
RCVP
RXVGSX
VFXIN
VFR
1/4 T7504 CODEC
RGP
+2.4 V
–0.300 V/mA
AV = 4
L9216
VFXIP
18 Ω
18 Ω
+
–
+
–
VBAT1 BGND VBAT2 VCC AGND ICM RGDET
CBAT1
0.1 µF
CBAT2
0.1 µF
CCC
0.1 µF
RTFLT
DCOUT
PR
PT
VREF
CRT
0.1 µF
RRT
383 kΩ
AGERE
L7591
VBAT1
FUSIBLE OR PTC
30 Ω
30 Ω
CF1 CF2
rate of battery
reversal not
ramped
FB1 FB2 NSTATB2B1B0
CF1
0.22 µFCF2
0.1 µF
RINGIN
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4750 Ω
VBAT1
DBAT1
VBAT2 VCC
CTX
0.1 µF
C2
0.47 µF
1/4 T7504
CODEC
RT6 CC1
RX
GSX
+2.4 V
RHB1 VFXIN
RRCV
RT3
RGP
CC2 VFRO
DX
DR
FSE
FSEP
MCLK
ASEL CONTROL
INPUTS
SYNC
AND
PCM
HIGHWAY
CLOCK
RN2
–
+
49.9 kΩ
100 kΩ
100 kΩ
60.4 kΩ0.1 µF
17.65 kΩ
26.7 kΩ
69.8 kΩ
0.1 µF
L9216A
FUSIBLE OR PTC
VPROG
VREF
VREF
R1
12 kΩ
C1
1.0 µF
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
36 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
Table 24. Part s List L9216; Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse
Application
Notes:
Term ination Impedance = 600 Ω.
Hybrid Balance = 600 Ω.
Tx = 0 dBm.
Rx = 0 dBm.
Name Value Tolerance Rating Function
Fault Protection
RPT 30 Ω1% Fusible or PTC Protection resistor.
RPR 30 Ω1% Fusible or PTC Protection resistor.
Protector Agere L7591 — — Secondary protection.
Power Supply
CBAT1 0.1 µF20% 100 V VBAT filter capacitor.
CBAT2 0.1 µF20% 50 V VBAT filter capacitor. |VBAT2| < |VBAT1|.
DBAT1 1N4004 — — Reverse current.
CCC 0.1 µF20% 10 V VCC filter capacitor.
CF1 0.22 µF20% 100 V Filter capacitor.
CF2 0.1 µF20% 100 V Filter capacitor.
Ring/Ring Trip
C11.0 µF20% 10 V Ring filter for square wave.
C20.47 µF20% 10 V ac-couple input ring si gna l.
R112 kΩ1% 1/16 W Ring filter for square wave.
CRT 0.1 µF20% 10 V Ring trip filter capacitor.
RRT 383 kΩ1% 1/16 W Ring trip filter resistor.
ac Interface
RGX 4750 Ω1% 1/16 W Sets T/R to VITR transconductance.
CTX 0.1 µF20% 10 V ac/dc separatio n.
CC1 0.1 µF20% 10 V dc blocking capacitor.
CC2 0.1 µF20% 10 V dc blocking capacitor.
RT3 69.8 kΩ1% 1/16 W With RGP and RRCV, sets termination impedance
and receive gain.
RT6 49.9 kΩ1% 1/16 W With RX, sets transmit gain.
RX100 kΩ1% 1/16 W With RT6, sets transmit gain.
RHB1 100 kΩ1% 1/16 W With RX, sets hybrid balance.
RRCV 60.4 kΩ1% 1/16 W With RGP and RT3, sets termination impedance
and receive gain.
RGP 26.7 kΩ1% 1/16 W With RRCV and RT3, sets termination impedance
and receive gain.
RGN Optional 17.6 kΩ1% 1/16 W Optional. Compensates for input offset at
RCVN/RCVP.
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 37
ac Applications (continued)
Design Examples (continued)
First-Generation Codec ac Interface Network—
Complex Termination
The reference circuit in Figure 26 shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for the German complex termination
impedance. For this example, the ac interface was
designed for a 220 Ω + (820 Ω || 115 nF) complex
termination and hybrid balance with transmit gain and
receive gain set to 0 dBm. For illustration purposes,
1 Vrms PPM injection was assumed in this example.
This implies the overhead voltage is increased to
7.24 V and no meter pulse rejection is required. Also,
this example illustrates the device using fixed overhead
and current limit.
Complex Termination Impedance Design Example
The gain shaping necessary for a complex termination
impedance may be done by shaping across the AX
amplifier at nodes ITR and VTX.
Complex termination is specified in the form:
5-6396(F)
To work with this application, convert termination to the
form:
5-6398(F)
where:
R1´ = R1 + R2
R2´ = (R1 + R2)
C´ = C
ac Interface Using First-Genera tion Codec
RGX/RTGS/CGS (ZTG): these components give gain shap-
ing to get good gain flatness. These components are a
scaled version of the specified complex termination
impedance.
Note for pure (600 Ω) resistive terminations, compo-
nents RTGS and CGS are not used. Resistor RGX is us ed
and is still 4750 Ω.
RX/RT6: with other components set, the trans mit gain
(for complex and resistive terminations) RX and RT6 are
varied to give specified transmit gain.
RT3/RRCV/RGP: for both complex and resistive termina-
tions, the ratio of these resistors sets the receive gain.
For resistive terminations, the ratio of these resistors
sets the return loss characteristic. For complex termi-
nations, the ratio of these resistors sets the low-fre-
quency re turn loss cha r act eris tic .
CN/RN1/RN2: for complex terminations, these compo-
nents provide high-frequency compensation to the
return loss characteristic.
For resistive terminations, these components are not
used and RCVN is connected to ground via a resistor.
RHB: sets hybrid balance for all terminations.
Set Z TG—Gain Shaping:
ZTG = RGX || RTGS + CGS which is a scaled version of
ZT/R (the specified termination resistance) in the
R1´ || R2´ + C´ form.
RGX must be 4750 Ω to set SLIC transconductance to
300 V/A.
RGX = 4750 Ω
At dc, CGS and C´ are open.
RGX = M x R1´
where M is the scale factor.
M =
It can be shown:
RTGS = M x R2´
and
CTGS =
R2
C
R1
R1´
C´R2´
R1
R2
-------
R2
R1R2+
---------------------
2
4750
R1′
--------------
C′
M
------
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
38 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
Transmit Gain
Transmit gain will be specified as a gain from T/R to
PCM, TX (dB). Since PCM is referenced to 600 Ω and
assumed to be 0 dB, and in the case of T/R being refer-
enced to some complex impedance other than 600 Ω
resistive, the effects of the impedance transformation
must be taken into account.
Again, specified complex termination impedance at T/R
is of the form:
5-6396(F)
First, calculate the equivalent resistance of this network
at the midband frequency of 1000 Hz.
REQ =
Using REQ, calculate the desired transmit gain, taking
into account the impedance transformation:
TX (dB) = TX (specifi ed[dB]) + 20log
TX (s pecif ied[dB ]) is the specified transmit gain. 600 Ω is the
impedance at the PCM, and REQ is the impedance at
tip and ring. 20log represents the power
loss/gain due to the impedance transformation.
Note that in the case of a 600 Ω pure resistive termina-
tion
at T/R 20log = 20log = 0.
Thus, there is no power loss/gain due to impedance
transformation and TX (dB) = TX (spe cified [dB ]).
Finally, convert TX (dB) to a ratio, gTX:
TX (dB) = 20log gTX
The ratio of RX/RT6 is used to set the transmit gain:
= gTX • • with a quad Agere codec
such as T7504:
RX < 200 kΩ
R2
C
R1
2πf()
2C12R1R22R1R2++
12πf()
2R22C12
+
-----------------------------------------------------------------------------
22πfR22C1
12πf()
2R22C12
+
---------------------------------------------------
2
+
600
REQ
-----------
600
REQ
-----------
600
REQ
-----------600
600
----------
RX
RT6
---------- 318.25
20
------------------1
M
-----
5-6400.P (F)
Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)
0.1 µF
RTGS
VTX
RGX = 4750 Ω
TXI VITR
RT6
Rx
RT3 RHB
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
20
CN
RN1
RN2 RGP
RRCV
–IT/R
318.25
CGS
RCVN
RCVP
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 39
ac Applications (continued)
Design Examples (continued)
Receive Gain
Ratios of RRCV, R T3, RGP will set both the low-frequency
termination and receive gain for the complex case. In
the complex case, additional high-frequency compen-
sation, via CN, RN1, and RN2, is needed for the return
loss characteristic. For resistive termination, CN, RN1,
and RN2 are not used and RCVN is tied to ground via a
resistor.
Determine the receive gain, gRCV, taking into account
the impedance transformation in a manner similar to
transmit gain.
RX (dB) = RX (specified[dB]) + 20log
RX (dB) = 20log gRCV
Then:
gRCV =
and low-frequency termination
ZTER(low) = + 2RP + 50 Ω
ZTER(low) is the specified termination impedance assum-
ing low frequency (C or C´ is open).
RP is the series protection resistor.
50 Ω is the typical internal feed resistance.
These two equations are best solved using a computer
spreadsheet.
Next, solve for the high-frequency return loss compen-
sation circuit, CN, RN1, and RN2:
CNRN2 = CG RTGP
RN1 = RN2
There is an input offset voltage associated with nodes
RCVN and RCVP. To minimize the effect of mismatch
of this voltage at T/R, the equivalent resistance to ac
ground at RCVN should be approximately equal to that
at RCVP. Refer to Figure 25 (with dc blocking capaci-
tors). To meet this requirement, RN2 = RGP || RT3.
Hybrid Balance
Set the hybrid cancellation via RHB.
RHB =
If a 5 V only codec such as the Agere T7504 is used,
dc blocking capacitors must be added as shown in
Figure 25. This is because the codec is referenced to
2.5 V and the SLIC to ground—with the ac coupling, a
dc bias at T/R is eliminated and power associated with
this bias is not consumed.
Typically, values of 0.1 µF to 0.47 µF capacitors are
used for dc blocking. The addition of blocking capaci-
tors will cause a shift in the return loss and hybrid bal-
ance frequency response toward higher frequencies,
degrading the lower-frequency response. The lower
the value of the blocking capacitor, the more pro-
nounced the effect is, but the cost of the capacitor is
lower. It may be necessary to scale resistor values
higher to compensate for the low-frequency response.
This eff ect is bes t evalua ted via simulat ion. A
PSPICE
®
model for the L9216 is available.
Design equation calculations seldom yield standard
component values. Conversion from the calculated
value to standard value may have an effect on the ac
parameters. This effect should be evaluated and opti-
mized via simulation.
REQ
600
-----------
4
1RRCV
RT3
--------------- RRCV
RGP
---------------
++
------------------------------------------------
2400
1RT3
RGP
------------RT3
RRCV
---------------
++
--------------------------------------------
2RP
2400
-------------
2400
2RP
-------------RTGS
RTGP
--------------
1–
RX
gRCV gTX×
-------------------------------
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
40 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors
5-6401.M (F)
Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termi-
nation Impedance
Figure 26. Agere T7504 First-Generation Codec Complex Termination
0.1 µF
RTGS
VTX
RGX = 4750 Ω
TXI VITR
RT6
Rx
RT3 RHB
CODEC
OUTPUT
DRIVE
AMP
CODEC
OP AMP
–
+
20
CN
RN1
RN2 RGP
RRCV
–IT/R
318.25
CGS
CB1
2.5 V
CB2
RCVN
RCVP
VBAT1 BGND VBAT2 VCC AGND ICM RGDET
ground key
not used
CBAT1
0.1 µF
CBAT2
0.1 µF
CCC
0.1 µF
RTFLT
DCOUT
PR
PT
CRT
0.1 µF
RRT
383 kΩ
AGERE
L7591
V
BAT1
FUSIBLE
30 Ω
rate of battery
reversal not
ramped
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4750 ΩRTGS 1.74 kΩ
CGS 12 nF
VBAT1
DBAT1
VBAT2 VCC
CTX
0.1 µF
RT6
RHB1
RT3
RRCV
CN
RGP
RN2
30 Ω
CC2
L9216A
CC1
CF1 CF2 FB1 FB2 NSTAT B2 B1 B0
CF1
0.22 µFCF2
0.1 µF
RINGIN
CRING
0.47 µF
FROM/TO CONTROL
RING
FUSIBLE
47.5 kΩ
54.9 kΩ
127
RN1
kΩ
59.0 kΩ
49.9 kΩ113 kΩ
120 pF
0.1 µF
0.1 µF
40.6 kΩ
VREF
OR PTC
OR PTC
RX
VFXIN DX
+2.4
–
+
GSX
VFRO
1/4 T7504
CODEC
PCM
HIGHWA
Y
SYNC
AND
CLOCK
CONTRO
L
INPUTS
DR
FSE
FSEP
MCLK
ASEL
VPROG
VREF
VREF
115 kΩ
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 41
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors (continued)
Table 25. Parts List L9216; Agere T7504 First-Generation Codec Complex Termination; Meter Pulse
Application
Termination impedance = 220 Ω + (820 Ω || 115 nF), hybrid balance = 220 Ω + (820 Ω || 115 nF) Tx = 0 dBm,
Rx = 0 dBm.
Name Value Tolerance Rating Function
Fault Protection
RPT 30 Ω1% Fusible or PTC Protection resistor.
RPR 30 Ω1% Fusible or PTC Protection resistor.
Protector Agere
L7591 — — Secondary protection.
Power Supply
CBAT1 0.1 µF20% 100 V VBAT filter cap acitor.
CBAT2 0.1 µF20% 50 V VBAT filter capacitor. |VBAT2| < |VBAT1|.
DBAT1 1N4004 — — Reverse current.
CCC 0.1 µF20% 10 V VCC filter capacitor.
CF1 0.22 µF20% 100 V Filter capacitor.
CF2 0.1 µF20% 100 V Filter capacitor.
Ring/Ring Trip
CRING 0.47 µF20% 10 V ac-couple input ring si gna l.
CRT 0.1 µF20% 10 V Ring trip filter capacitor.
RRT 383 kΩ1% 1/16 W Ring trip filter resistor.
ac Interface
RGX 4750 Ω1% 1/16 W Sets T/R to VITR transconductance.
RTGS 1.74 k Ω1% 1/16 W Gain shaping for complex termination.
CGS 12 nF 5% 10 V Gain shaping for complex termination.
CTX 0.1 µF20% 10 V ac/dc separatio n.
CC1 0.1 µF20% 10 V dc blocking capacitor .
CC2 0.1 µF20% 10 V dc blocking capacitor .
RT3 49.9 kΩ1% 1/16 W With RGP and RRCV, sets termination imp eda nc e and recei ve
gain.
RT6 40.2 kΩ1% 1/16 W With RX, sets transmit gain.
RX115 kΩ1% 1/16 W With RT6, sets transmit gain.
RHB1 113 kΩ1% 1/16 W With RX, sets hybrid balance.
RRCV 59.0 k Ω1% 1/16 W With RGP and RT3, sets termination impedance and receive
gain.
RGP 54.9 kΩ1% 1/16 W With RRCV and RT3, sets termination impedance and receive
gain.
CN120 pF 20% 10 V High frequency compensation.
RN1 127 kΩ1% 1/16 W High frequency compensation.
RN2 47.5 kΩ1% 1/16 W High frequency compensation, compensate for dc offset at
RCVP/RCVN.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
42 Agere Systems Inc.
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination
The following reference circuit, Figure 27, shows the complete SLIC schematic for interface to the Agere T8536
third-generation codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that
no external components are required in the ac interface to provide a dc termination impedance or for stability. For
illustration purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used.
Also, this example illustrates the device using programmable overhead and current limit. Please see the T8535/6
data sheet for information on coefficient programming.
Figure 27. Third-Generation Codec ac Interface Network; Complex Termination
VBAT1 BGND VBAT2 VCC AGND ICM RGDET
ground key
not used
CBAT1
0.1 µF
CBAT2
0.1 µF
CCC
0.1 µF
RTFLT
DCOUT
PR
PT
VPROG
VREF
CRT
0.1 µF
RRT
383 kΩ
AGERE
L7591
VBAT1
FUSIBLE OR PTC
50 Ω
50 Ω
CF1 CF2
rate of battery
reversal not
ramped
FB1 FB2 NSTAT B2 B1 B0
CF1
0.22 µFCF2
0.1 µF
RINGIN
VITR
RCVP
RCVN
ITR
VTX
TXI
RGX
4750 Ω
VBAT1
DBAT1
VBAT2 VCC
CTX
0.1 µF
CRING
0.47 µF
CC1
PCM
HIGHWAY
DX0
DR0
DX1
DR1
FS
BCLK
DGND
VDD
SYNC
AND
VDD
VFXI
VFROP
VFRON
SLIC4a
SLIC3a
SLIC2a
SLIC0a
CLOCK
L9216G
FROM/TO
CONTROL
B2
B1
NSTAT
B0
0.1 µF
FUSIBLE OR PTC
RCIN
20 MΩ
1/4
T8536/8
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 43
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network—Complex Termination (continued)
Table 26. Parts List L9216; Agere T8536 Third-Generation Codec ac and dc Parameters; Fully
Programmable
* For loop stability, increase to 50 Ω minimum if synthesizing 900 Ω or 900 Ω + 2.16 µF termination impedance.
Name Value Tolerance Rating Function
Fault Protection
RPT 50 Ω1% Fusible or PTC Protection resistor*.
RPR 50 Ω1% Fusible or PTC Protection resistor*.
Protector Agere L7591 — — Secondary protection.
Power Supply
CBAT1 0.1 µF20% 100 V VBAT filter capacitor.
CBAT2 0.1 µF20% 50 V VBAT filter capacitor. |VBAT2| < |VBAT1|.
DBAT1 1N4004 — — Reverse current.
CCC 0.1 µF20% 10 V VCC filter capacitor.
CF1 0.22 µF20% 100 V Filter capacitor.
CF2 0.1 µF20% 100 V Filter capacitor.
Ring/Ring Trip
CRING 0.47 µF20% 10 V ac-couple input ring signal.
CRT 0.1 µF20% 10 V Ring trip filter capacitor.
RRT 383 kΩ1% 1/16 W Ring trip filter resistor.
ac Interface
RGX 4750 Ω1% 1/16 W Sets T/R to VITR transconductance.
RCIN 20 MΩ5% 1/16 W dc bia s.
CTX 0.1 µF20% 10 V ac/dc separation.
CC1 0.1 µF20% 10 V dc blocking capacitor.
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
44 Agere Systems Inc.
Outline Diagrams
28-Pin PLCC
Dimensions are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
5-2506r.8(F)
1.27 TYP
0.330/0.533
0.10
SEATING PLA NE
0.51 MIN
TYP
4.572
MAX
12 18
11
5
4126
25
19
12.446 ± 0.127
PIN #1 IDENTIFIER
ZONE
11.506 ± 0.076
11.506
± 0.076
12.446
± 0.127
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 45
Outline Diagrams (continued)
48-Pin MLCC
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
0195mod
PIN #1
IDENTIFIE R ZONE
1
7.00
6.75
SEATING PLANE
0.08
0.65/0.80
0.20 REF
DETAIL A
7.00
5.10
± 0.15
3
3.50
3.375
6.75
0.00/0.05
SECTION C–C
11 SP ACES @
0.50 = 5.50
0.50 BSC
0.18/0.30
0.30/0.45
0.01/0.05
1.00 MAX
12°
0.18/0.30
0.24/0.60
0.24/0.60
2
1
3
2
0.50 BSC
DETAIL A
CC
VIEW FOR EVEN TERMINAL/SIDE
CL
EXPOSED PAD
Prel iminary Data Sheet
September 2001
Short-Loop Ringing SLIC with Ground Start
L9216A/G
46 Agere Systems Inc.
Outline Diagrams (continued)
48-Pin MLCC, JEDEC MO-220 VKKD-2
Dimensions are in millimeters.
Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schemat-
ics to assist your design efforts, please contact your Agere Sales Representative.
The exposed pad on the bottom of the package will be at VBAT1 potential.
0195a
INDEX AREA
7.00
3.50
SEATI N G PLA N E
0.08
0.20 REF
DETAIL A
7.00
5.00/5.25
3.50
11 SPACES @
0.50 = 5.50
0.50 BSC
0.18/0.30
0.02/0.05
1.00 MAX 0.23
0.30/0.50
1
3
2
(7.00/2 x 7.00/2)
PIN #1
IDEN TI FIER ZO N E
TOP VIEW
SIDE VIEW DETAIL B
0.23
0.18
0.18
BOTTOM VIEW
2.50/2.625
EXPOSED PAD
DETAIL B
0.50 BSC
DETAIL A
VIEW FOR EVEN TERMINAL/SIDE
CL
Preliminary Data Sheet
September 2001 Short-Loop Ringing SLIC with Ground Start
L9216A/G
Agere Systems Inc. 47
Ordering Information
Device Part No. Description Package Comcode
LUCL9216AGF-D SLIC Gain = 8 28-Pin PLCC
Dry-bagged 108876723
LUCL9216AGF-DT SLIC Gain = 8 28-Pin PLCC
Tape & Reel, Dry-bagged 108876731
LUCL9216GGF-D SLIC Gain = 2 28-Pin PLCC
Tape & Reel 108876780
LUCL9216GGF-DT SLIC Gain = 2 28-Pin PLCC
Tape & Reel, Dry-bagged 108876798
LUCL9216ARG-D SLIC Gain = 8 48-Pin MLCC
Dry-bagged 108955477
LUCL9216GRG-D SLIC Gain = 2 48-Pin MLCC
Dry-bagged 108955469
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September 2001
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