ps CYP En a. iat, aa EE, Ls ana ees 2 EEE ee a Features e 512x9 and IK x9 FIFO buffer memory Dual-port RAM cell Asynchronous read/write e High-speed 66.6-MHz read/write independent of depth/width 10-ns access time Half Full flag in standalone Empty and Full flags Retransmit in standalone mode Expandable in width and depth Parallel cascade minimizes bubbie-through 5V > 10% supply 300-mii 28-pin DIP and 32-pin PLCC packaging RESS SEMICONDUCTOR PRELIMINARY CY7C421A CY7C425A @ TTL compatible e Three-state outputs e Pin compatible and functional equivalent to IDT7201 and IDT7202 Functional Description The CY7C421A and CY7C425A are first- in first-out (FIFO) memories. They are,re- spectively, 512 and 1,024 words by 9-bits wide. Each FIFO memory is organized such that the data is read in the same se- quential order that it was written. Full and Empty flags are provided to prevent over- run and underrun. Three additional pins are also provided to facilitate unlimited ex- pansion in width, depth, or both. The depth expansion technique steers the con- trol signals from one device to another in parallel, thus eliminating the serial addi- tion of propagation delays, so that throughput is not reduced. Data is steered in a similar manner. High-Speed Cascadable 512 x 9 FIFO 1K x 9 FIFO The read and write operations may be asynchronous; each can occur at a rate of 66.6 MHz. The write operation occurs when the write signal is LOW. Read accurs when read (R) goes LOW. The nine data outputs go to the high-impedance state when R is HIGH. A Half Full (HF) output flag is provided thatis valid in the standalone and width ex- pansion configurations. In the depth ex- pansion configuration, this pin provides the expansion out (KO) information that is used to tell the next FIFO that it will be ac- tivated. In the standalone and width expansion configurations, a LOW on the retransmit input causes the FIFOs toretransmit the data. Read enable (R)andwrite enable (W) must both be HIGH during retrans- mit, and then R is used to access the data. Logic Block Diagram Pin Configurations DATA INPUTS PLCC DIP (Do- Dg) Top View Top View rrr oes 2 soe WRITE 4 3 2%, 323130 w CONTROL wt RAM ARRAY WRITE 512x9 READ POINTER 40249 POINTER 23 7C421A 7C421A 7C425A Ly 764254" b TLL ae STATE BUFFERS 13 a Lh 14 15 1617 181920 DATA OUTPUTS 99ir y eee & Fe 3 eo Reset p> MR 421A READ LOGIG fa FLAT Re) CONTROL T FLAG tr LoGiC a EXPANSION Aria x ~| loac f* > OFFCYPRESS SEMICONDUCTOR PRELIMINARY CY7C421A CY7C425A Selection Guide Maximum Access Time (ns Maximum Current 7C421A-10 7C425A~10 66.6 10 Commercial 7C421A15 7C425A15 40 Maximum Rating (Above which the useful life may be impaired. For user guidelines, not tested.) Power Dissipation ............. 000.00 cee c cece Output Current, into Outputs (LOW) ............-. 20 mA Storage Temperature ................. - 65C to +150C Static Discharge voltage nan >2001V Ambient Temperature with (per MIL-STD-883, Method 3015) Power Applied ..........-.--..220005 55Cto+125C = Latch UpCurrent ............ 0.6.0.0... sees >200 mA Supply Voltage to Ground Potential ....... -0.5Vto+7.0V Operating Range fig Peta en cee 0.5V to +7.0V Range Temperataret! Vee DC Input Voltage ................02.00. 0.5V to +7.0V Commercial O'Cto + 10C 5V + 10% w Electrical Characteristics Over the Operating Rangel?! ra 7C421A10 | 7C421A~15 u 7C425A-10 | 7C0425A15 Parameter Description Test Conditions Min, | Max. | Min. | Max. | Unit Vou Output HIGH Voltage Voc = Min. lon = 2.0mA 24 2.4 Vv VoL Output LOW Voltage Vcc = Min., Io, = 8.0mA 0.4 0.4 Vv Vin Input HIGH Voltage | Com! 2.0 | Voc | 2.0 | Vcc Vv VIL Input LOW Voltage -0.5 ] 08 | -05 | 08 Vv Ix Input Leakage Current GND < V; < Vcc, Vcc = Max. -1 +1 -1 +1 uA loz Output Leakage Current R> VinGND < Vo < Vcc, Vcc = Max. | 10 | +10 J 10 | +10 | yA Icc Operating Current Vec = Max, Com! 180 120 | mA Your = 9 mA Ispi Standby Current All Inputs = Viy Min. Com! 15 15 mA Isp2 Power-Down Current All Inputs > Vcc - 0.2V. | Com 5 5 mA los Output Short Voc = Max., Vout = GND 90 -90 | mA Circuit Current!3) Capacitance! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ts = 25C,f= 1 MHz 5 pF Cout Output Capacitance 7 pF Notes: 1. Ty is the instant on case temperature. 2. See the last page of this specification for Group A subgroup testing in- formation. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Tested initially and after any design or process changes that may affect these parameters.CY7C421A Sa fies PRELIMINARY CY7C425A SEMICONDUCTOR AC Test Loads and Waveforms ALL INPUT PULSES sv $$vr ome 5.0v Equivalent to: THEVENIN EQUIVALENT 183Q 30 pF T ge GND OUTPUT One 2V INCLUDING IG ANE = = 421A4 Switching Characteristics Over the Operating Rangel>-l 7C421A-10 7C421A~-15 7C425A10 7C425A-15 Parameter Description Min. Max. Min. Max. Unit trc Read Cycle Time 15 25 ns ta Access Time 10 15 ns tre Read Recovery Time 5 10 ns tpr Read Pulse Width 10 15 ns tovel! Data Valid After Read HIGH 5 5 ns tuzRl/] Read HIGH to High Z, 15 15 ns twc Write Cycle Time 15 25 ns tpw Write Pulse Width 10 15 ns twr Write Recovery Time 5 10 ns tsp Data Set-Up Time 8 10 ns typ Data Hold Time 0 0 ns trsc MR Cycle Time 15 25 ns tPMR MR Pulse Width 10 15 ns trMR MR Recovery Time 5 10 ns trTc Retransmit Cycle Time 15 25 ns tert Retransmit Pulse Width 10 15 ns trTR Retransmit Recovery Time 5 10 ns ter. MR to EF LOW 10 15 ns HEH MR to HF HIGH 10 15 ns trFH MR to FF HIGH 10 15 ns trEF Read LOW to EF LOW 10 1s ns trrF Read HIGH to FF HIGH 10 15 ns twEr Write HIGH to EF HIGH 10 15 ns twFF Write LOW to FF LOW 10 15 ns twHr Write LOW to HF LOW 10 15 Bs trur Read HIGH to HF HIGH 10 15 ns txoL Expansion Out LOW Delay from Clock 12 15 ns txon Expansion Out HIGH Delay from Clock 12 15 ns trzR Read LOW to Low Z 1 1 ns tuwz Write HIGH to Low Z 5 5 ns trpw Read HIGH to MR HIGH 10 15 ns twew Write HIGH to MR HIGH 10 15 ns tRAE Effective Read from Write HIGH 10 15 ns tRPE Effective Read Pulse Width After FF HIGH 10 15 ns twaF Effective Write from Read HIGH 10 15 ns twee Effective Read Pulse Width After FF HIGH 10 15 nsCY7C421A ge ence PRELIMINARY CY7C425A SEMICONDUCTOR Switching Waveforms Asynchronous Read and Write tac tpn t, > tan >t# ty a aa + ti2zR tovr\ tuzA Qp~Qg K DATA VALID DATA VALID Xr twe tpw twr we RCS tsp >** td Do-Dg DATA VALID DATA VALID S21A6 5 Master Reset vs tuasc!l Le tpmR MA FR, WE EF tHFH AF FR LLLLLLLLLLLLLLLLLL LL FF 4218-7 Half-Full Flag HALF FULL HALF FULL +1 HALF FULL WwW a tee = R ___ L twHe AF fv 42108 Notes: 5. Test conditions assume signal transition time of 5 ns or less, timingref- 7. tyyzR transition ismeasured al +500mV from Vo_and 5U0mV from erence levels of 1.5V and output loading of the specified Ip, /Ioy and Vou. tpve transition is measured at the 1.5V level. tywz and ttzx 30 pF load capacitance, as in AC Test Load and Waveforms, unless transition is measured at +100 mV from the steady state. otherwise specified. 8. Wand R > Vyq around the rising edge of MR. 6. see the last page of this specification for Group Asubgrouptestingin- 9, tmrsc = tpMR + tRMR- formation.CY7C421A Syis PRELIMINARY CY7C425A SEMICONDUCTOR Switching Waveforms (continued) Last Write to First Read Full Flag ADDITIONAL LAST WRITE FIRST READ READS FIRST WRITE , \_f \_/ Ww WEF ltnrr to \_S | Last Read to First Write Empty Flag 4214-9 ADDITIONAL LAST READ FIRST WRITE WRITES FIRST READ " \_43 r \__/| " \_f twee . | "F V Y DATA OUT X) VALID (X) 4214-10 Retransmit!!) taro!!!) tprt UR Y r a RW y rf rr tatR 421A-11 Notes: 10. EF, HF and FF maychange state during retransmit asa result of the off- set of the read and write pointers, but flags will be valid at tarc. 11. terc = tprr + terre.CY7C421A =, a PRELIMINARY CY7C425A SEMICONDUCTOR Switching Waveforms (continued) Empty Flag and Empty Boundary Timing Diagram DATA IN x Tt \ ff mw trac > * AMAA NL = twer 7 tuwz DATA OUT XXX vara vaio XXX) ta FIFOs | 421A-12 Full Flag and Full Boundary Timing Diagram R v A | w VR tarF | twee fF > tub DATAIN DATA VAUD ma ta r+ tsp >| oxraouT KK ware vaio XXX 4214-13 5-49PRELIMINARY CY7C421A CY7C425A Switching Waveforms (continued) Expansion Timing Diagrams WRITE TO LAST PHYSICAL LOCATION OF DEVICE 1 Ww txor XO (XI) (21 v2 KXXXXRKERRRRERK SAE) READ FROM LAST PHYSICAL LOCATION OF DEVICE 1 XO, (ig) (121 XK WRITE TO FIRST PHYSICAL LOCATION OF DEVICE 2 tub DATA VALID 4214-14 READ FROM FIRST PHYSICAL LOCATION OF DEVICE 2 Qo-Qg XAXAXAAXK ls AXA) ef, A21A-15 Note: 12. Expansion pe of device 1 (XO) is connected to Expansion In of de- vice 2PRELIMINARY CY7C421A CY7C425A 7 CYPRESS SEMICONDUCTOR Architecture The CY7C421A/425A FIFOs consist of an array of 512/1024 words of 9 bits each (implemented by an array of Guat pon RAM cells) a read pointer, awrite pointer, control signals (W, R, XT, XO, FL, RT, MR), and Full, Half Full, and Empty flags. Dual-Port RAM The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write opera- tions to be independent of each other, which isnecessary to achieve asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment the read and write pointers is much less than the time that would be required for data propagation through the memory, which would be the case if the memory were implemented using the conventional register array architecture. Resetting the FIFO Upon power-up, the FIFO mustbe reset with a Master Reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (HF) and Full flags (Fe ) being HIGH. Read (R) and write (W) must be HIGH trpw/twrw before and trap after the rising edge of MR for a valid reset cycle. If reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. Writing Data to the FIFO The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data ap- pearing at the inputs (Dg - Dg) tsp before and typ after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs twer after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW twur after the falling edge of W following the FIFO actually being Half Full. Therefore, the HF is active once the FIFO is filled to half its capacity plus one word, HF will remain LO W while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tpyr after the rising edge of R when the FIFO goes from half full +1 to half full. HF is available in stand- alone and width expansion modes. FF goes LOW twee after the falling edge of W, during the cycle in which the last available loca- tion is filled. Internal logic prevents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not in- cremented. FF goes HIGH trer after a read from a full FIFO. Reading Data from the FIFO The falling edge of R initiates a read cycle if the EF is not LOW. Data outputs (Qg- Qs) are in a high-impedance condition between read operations (R HIGH) when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of R initiates a HIGH-to-LOW transition of EF When the FIFO is empty, the outputs are in a high-impedance state. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read twer after a valid write. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the re- ceiver and retransmitted if necessary. The Retransmit (RT) inputis active in the standalone and width ex- pansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last MR cycle. A LOW pulse on RF resets the internal read pointer to the first physical location of the FIFO. R and W must both be HIGH while and terp after retransmit is LOW. With every read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are up- dated during a retransmit cycle. Data written to the FIFO after ac- tivation of RT are transmitted also. The full depth of the FIFO can be repeatedly transmitted. Standalone/Width Expansion Modes Standalone and width expansion modes are set by grounding Ex- pansion In (XT) and tying First Load (FL) to Vcc, FIFOs can be expanded in width to provide word widths greater than nine in in- crements of nine. During width expansion mode, all control line in- puts ate common to ail devices, and flag outputs from any device can be monitored. Depth Expansion Mode (see Figure /) Depth expansion mode isenteredwhen, duringa MR cycle, - sion Out (XO) of one device is connected to Expansion In oth of the next device, with KO of the last device connected to XI of the first device. In the depth expansion mode the First Load (FT) in- put, when grounded, indicates that this partis the first to be loaded. All other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and pulsed LOW again when the last physical location is read. Only one FIFO is enabled for read and one for write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a com- posite EF is created by ORing the EFs together. HF and RT fune- tions are not available in depth expansion mode. FIFOs |CY7C421A ay ce PRELIMINARY CY7C425A SEMICONDUCTOR CY7C421A CY7C425A CY7C421A CY7C425A CY7C421A CY7C425A * FIRST DEVICE 4210-18 Figure 1. Depth Expansion Ordering Information Speed Package | Operating (ms) Ordering Code Type Range 10 CY7C421A-10JC J65 Commercial CY7C421A10PC P21 15 CY7C421A- 15JC J65 Commercial CY7C421A 15PC P21 Speed Package | Operating (ns) Ordering Code Type Range 10 CY7C425A10JC J65 Commercial CY7C425A10PC P21 15 CY7C425A15IC J65 Commerciai CY7C425A-15PC P21 Document #: 3800248