Single (TSZ121)
Dual (TSZ122)
Quad (TSZ124)
SC70-5 SOT23-5
DFN8 2x2 MiniSO8 SO8
QFN16 3x3 TSSOP14
Features
• Very high accuracy and stability: offset voltage 5 µV max at 25 °C, 8 µV over full
temperature range (-40 °C to 125 °C)
• Rail-to-rail input and output
• Low supply voltage: 1.8 - 5.5 V
• Low power consumption: 40 µA max. at 5 V
• Gain bandwidth product: 400 kHz
• High tolerance to ESD: 4 kV HBM
• Extended temperature range: -40 to 125 °C
• Micro-packages: SC70-5, DFN8 2x2, and QFN16 3x3
Applications
• Battery-powered applications
• Portable devices
• Signal conditioning
• Medical instrumentation
Description
The TSZ12x series of high precision operational amplifiers offer very low input offset
voltages with virtually zero drift.
TSZ121 is the single version, TSZ122 the dual version, and TSZ124 the quad
version, with pinouts compatible with industry standards.
The TSZ12x series offers rail-to-rail input and output, excellent speed/power
consumption ratio, and 400 kHz gain bandwidth product, while consuming less than
40 µA at 5 V. The devices also feature an ultra-low input bias current.
These features make the TSZ12x family ideal for sensor interfaces, battery-powered
applications and portable applications.
Maturity status link
TSZ121
TSZ122
TSZ124
Related products
TSV711 Continuous-time
precision amplifiers
TSV731
TSZ181 Zero drift 3 MHz
amplifiers
TSZ182
Benefits
Higher accuracy without calibration
Accuracy virtually unaffected by
temperature change
Very high accuracy (5 µV) zero drift micropower 5 V operational amplifiers
TSZ121, TSZ122, TSZ124
Datasheet
DS9216 - Rev 10 - February 2019
For further information contact your local STMicroelectronics sales office. www.st.com
1Package pin connections
Figure 1. Pin connections for each package (top view)
SC70-5 SOT23-5
DFN8 2x2 MiniSO8 and SO8
QFN16 3x3 TSSOP14
1. The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating.
TSZ121, TSZ122, TSZ124
Package pin connections
DS9216 - Rev 10 page 2/38
2Absolute maximum ratings and operating conditions
Table 1. Absolute maximum ratings (AMR)
Symbol Parameter Value Unit
VCC Supply voltage (1) 6
V
Vid Differential input voltage (2) ±VCC
Vin Input voltage (3) (VCC-) - 0.2 to
(VCC+) + 0.2
Iin Input current (4) 10 mA
Tstg Storage temperature -65 to 150 °C
TjMaximum junction temperature 150
Rthja Thermal resistance junction to ambient (5) (6)
SC70-5 205
°C/W
SOT23-5 250
DFN8 2x2 57
MiniSO8 190
SO8 125
QFN16 3x3 39
TSSOP14 100
ESD
HBM: human body model (7) 4 kV
MM: machine model (8) 300 V
CDM: charged device model (9) 1.5 kV
Latch-up immunity 200 mA
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. Vcc - Vin must not exceed 6 V, Vin must not exceed 6 V
4. Input current must be limited by a resistor in series with the inputs.
5. Rth are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin
combinations with other pins floating.
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device
with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating.
9. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to
ground.
Table 2. Operating conditions
Symbol Parameter Value Unit
VCC Supply voltage 1.8 to 5.5 V
Vicm Common mode input voltage range (VCC -) - 0.1 to (VCC +) + 0.1
Toper Operating free air temperature range -40 to 125 °C
TSZ121, TSZ122, TSZ124
Absolute maximum ratings and operating conditions
DS9216 - Rev 10 page 3/38
3Electrical characteristics
Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage T = 25 °C 1 5 μV
-40 °C < T < 125 °C 8
ΔVio/ΔT Input offset voltage drift (1) -40 °C < T < 125 °C 10 30 nV/°C
Iib Input bias current (Vout = VCC/2) T = 25 °C 50 200 (2)
pA
-40 °C < T < 125 °C 300 (2)
Iio Input offset current (Vout = VCC/2) T = 25 °C 100 400 (2)
-40 °C < T < 125 °C 600 (2)
CMR
Common mode rejection ratio, 20
log (ΔVicm/ΔVio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
T = 25 °C 110 122
dB
-40 °C < T < 125 °C 110
Avd Large signal voltage gain, Vout =
0.5 V to (VCC - 0.5 V)
T = 25 °C 118 135
-40 °C < T < 125 °C 110
VOH High-level output voltage T = 25 °C 30
mV
-40 °C < T < 125 °C 70
VOL Low-level output voltage T = 25 °C 30
-40 °C < T < 125 °C 70
Iout
Isink (Vout = VCC)T = 25 °C 7 8
mA
-40 °C < T < 125 °C 6
Isource (Vout = 0 V) T = 25 °C 5 7
-40 °C < T < 125 °C 4
ICC Supply current (per amplifier, Vout =
VCC/2, RL > 1 MΩ)
T = 25 °C 28 40 μA
-40 °C < T < 125 °C 40
AC performance
GBP Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
400 kHz
FuUnity gain frequency 300
ɸm Phase margin 55 Degrees
GmGain margin 17 dB
SR Slew rate (3) 0.17 V/μs
tsSetting time To 0.1 %, Vin = 1 Vp-p, RL = 10 kΩ, CL =
100 pF 50 μs
enEquivalent input noise voltage f = 1 kHz 60 nV/√Hz
f = 10 kHz 60
∫enLow-frequency peak-to-peak input
noise Bandwidth, f = 0.1 to 10 Hz 1.1 µVpp
CsChannel separation f = 100 Hz 120 dB
TSZ121, TSZ122, TSZ124
Electrical characteristics
DS9216 - Rev 10 page 4/38
Symbol Parameter Conditions Min. Typ. Max. Unit
tinit Initialization time T = 25 °C 50 μs
-40 °C < T < 125 °C 100
1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on
x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. Slew rate value is calculated as the average between positive and negative slew rates.
Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage T = 25 °C 1 5 μV
-40 °C < T < 125 °C 8
ΔVio/ΔT Input offset voltage drift (1) -40 °C < T < 125 °C 10 30 nV/°C
Iib Input bias current (Vout = VCC/2) T = 25 °C 60 200 (2)
pA
-40 °C < T < 125 °C 300 (2)
Iio Input offset current (Vout = VCC/2) T = 25 °C 120 400 (2)
-40 °C < T < 125 °C 600 (2)
CMR
Common mode rejection ratio, 20
log (ΔVicm/ΔVio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
T = 25 °C 115 128
dB
-40 °C < T < 125 °C 115
Avd Large signal voltage gain, Vout =
0.5 V to (VCC - 0.5 V)
T = 25 °C 118 135
-40 °C < T < 125 °C 110
VOH High-level output voltage T = 25 °C 30
mV
-40 °C < T < 125 °C 70
VOL Low-level output voltage T = 25 °C 30
-40 °C < T < 125 °C 70
Iout
Isink (Vout = VCC)T = 25 °C 15 18
mA
-40 °C < T < 125 °C 12
Isource (Vout = 0 V) T = 25 °C 14 16
-40 °C < T < 125 °C 10
ICC Supply current (per amplifier, Vout =
VCC/2, RL > 1 MΩ)
T = 25 °C 29 40 μA
-40 °C < T < 125 °C 40
AC performance
GBP Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
400 kHz
FuUnity gain frequency 300
ɸm Phase margin 56 Degrees
GmGain margin 19 dB
SR Slew rate (3) 0.19 V/μs
tsSetting time To 0.1 %, Vin = 1 Vp-p, RL = 10 kΩ, CL =
100 pF 50 μs
TSZ121, TSZ122, TSZ124
Electrical characteristics
DS9216 - Rev 10 page 5/38
Symbol Parameter Conditions Min. Typ. Max. Unit
enEquivalent input noise voltage f = 1 kHz 40 nV/√Hz
f = 10 kHz 40
∫enLow-frequency peak-to-peak input
noise Bandwidth, f = 0.1 to 10 Hz 0.8 µVpp
CsChannel separation f = 100 Hz 120 dB
tinit Initialization time T = 25 °C 50 μs
-40 °C < T < 125 °C 100
1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on
x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. Slew rate value is calculated as the average between positive and negative slew rates.
Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified)
Symbol Parameter Conditions Min. Typ. Max. Unit
DC performance
Vio Input offset voltage T = 25 °C 1 5 μV
-40 °C < T < 125 °C 8
ΔVio/ΔT Input offset voltage drift (1) -40 °C < T < 125 °C 10 30 nV/°C
Iib Input bias current (Vout = VCC/2) T = 25 °C 70 200 (2)
pA
-40 °C < T < 125 °C 300 (2)
Iio Input offset current (Vout = VCC/2) T = 25 °C 140 400 (2)
-40 °C < T < 125 °C 600 (2)
CMR
Common mode rejection ratio, 20
log (ΔVicm/ΔVio), Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
T = 25 °C 115 136
dB
-40 °C < T < 125 °C 115
SVR
Supply voltage rejection ratio, 20
log (ΔVCC/ΔVio), VCC = 1.8 V to 5.5
V, Vout = VCC/2, RL > 1 MΩ
T = 25 °C 120 140
-40 °C < T < 125 °C 120
Avd Large signal voltage gain, Vout =
0.5 V to (VCC - 0.5 V)
T = 25 °C 120 135
-40 °C < T < 125 °C 110
EMIRR (3) EMI rejection rate = -20 log
(VRFpeak/ΔVio)
VRF = 100 mVp, f = 400 MHz 84
VRF = 100 mVp, f = 900 MHz 87
VRF = 100 mVp, f = 1800 MHz 90
VRF = 100 mVp, f = 2400 MHz 91
VOH High-level output voltage T = 25 °C 30
mV
-40 °C < T < 125 °C 70
VOL Low-level output voltage T = 25 °C 30
-40 °C < T < 125 °C 70
TSZ121, TSZ122, TSZ124
Electrical characteristics
DS9216 - Rev 10 page 6/38
Symbol Parameter Conditions Min. Typ. Max. Unit
Iout
Isink (Vout = VCC)T = 25 °C 15 18
mA
-40 °C < T < 125 °C 14
Isource (Vout = 0 V) T = 25 °C 14 17
-40 °C < T < 125 °C 12
ICC Supply current (per amplifier, Vout =
VCC/2, RL > 1 MΩ)
T = 25 °C 31 40 μA
-40 °C < T < 125 °C 40
AC performance
GBP Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
400 kHz
FuUnity gain frequency 300
ɸm Phase margin 53 Degrees
GmGain margin 19 dB
SR Slew rate (4) 0.19 V/μs
tsSetting time To 0.1 %, Vin = 100 mVp-p, RL = 10 kΩ, CL
= 100 pF 10 μs
enEquivalent input noise voltage f = 1 kHz 37 nV/√Hz
f = 10 kHz 37
∫enLow-frequency peak-to-peak input
noise Bandwidth, f = 0.1 to 10 Hz 0.75 µVpp
CsChannel separation f = 100 Hz 120 dB
tinit Initialization time T = 25 °C 50 μs
-40 °C < T < 125 °C 100
1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on
x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.
2. Guaranteed by design
3. Tested on SC70-5 package
4. Slew rate value is calculated as the average between positive and negative slew rates.
TSZ121, TSZ122, TSZ124
Electrical characteristics
DS9216 - Rev 10 page 7/38
4Electrical characteristic curves
Figure 2. Supply current vs. supply voltage
0.00.0 0.5 1.01.0 1.5 2.02.0 2.5 3.03.0 3.5 4.04.0 4.5 5.05.0 5.5
00
5
1010
15
2020
25
3030
35
4040
T=-40°C
VICM
=VCC
/2
T=125°C
T=25°C
Supply Current (µA)
Supply voltage (V)
Figure 3. Input offset voltage distribution at VCC = 5 V
-5 -4 -3 -2 -1 0 1 2 3 4 5
0
10
20
30
40
50
60
T=25°C
Vcc=5V,
Vicm=2.5V
Population
Input offset voltage (µV)
Figure 4. Input offset voltage distribution at VCC = 3.3 V
-5 -4 -3 -2 -1 0 1 2 3 4 5
0
10
20
30
40
50
60
T=25°C
Vcc=3.3V,
Vicm=1.65V
Population
Input offset voltage (µV)
Figure 5. Input offset voltage distribution at VCC = 1.8 V
-5 -4 -3 -2 -1 0 1 2 3 4 5
0
10
20
30
40
50
60
T=25°C
Vcc=1.8V,
Vicm=0.6V
Population
Input offset voltage (µV)
Figure 6. Vio temperature co-efficient distribution
(-40 °C to 25 °C)
-0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030
0
10
20
30
40
50
60
T=-40°C to 25°C
Vcc=5V,
Vicm=2.5V
Population
Input offset voltage drift [µV/°C]
Figure 7. Vio temperature co-efficient distribution
(25 °C to 125 °C)
-0.030 -0.025 -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0.025 0.030
0
10
20
30
40
50
60
T=25°C to 125°C
Vcc=5V,
Vicm=2.5V
Population
Input offset voltage drift [µV/°C]
TSZ121, TSZ122, TSZ124
Electrical characteristic curves
DS9216 - Rev 10 page 8/38
Figure 8. Input offset voltage vs. supply voltage
2.02.0 2.3 2.52.5 2.8 3.03.0 3.3 3.53.5 3.8 4.04.0 4.3 4.54.5 4.8 5.05.0
-5
-4-4
-3
-2-2
-1
00
1
22
3
44
5
T=25°C
T=-40°C
T=125°C
Vicm=Vcc/2
Vio (µV)
Vcc(V)
Figure 9. Input offset voltage vs. input common-mode at
VCC = 1.8 V
0.00.0 0.20.2 0.40.4 0.60.6 0.80.8 1.01.0 1.21.2 1.41.4 1.61.6 1.81.8
-5
-4-4
-3
-2-2
-1
00
1
22
3
44
5
T=25°C
T=-40°C
T=125°C
Vcc=1.8V
Vio (µV)
Vicm (V)
Figure 10. Input offset voltage vs. input common-mode at
VCC = 2.7 V
0.00.0 0.2 0.40.4 0.6 0.80.8 1.0 1.21.2 1.4 1.61.6 1.8 2.02.0 2.2 2.42.4 2.6 2.82.8
-5-5
-4
-3
-3
-2
-1
00
1
2
3
3
4
55
T=25°C
T=-40°C
T=125°C
Vcc=2.7V
Vio (µV)
Vicm (V)
Figure 11. Input offset voltage vs. input common-mode at
VCC = 5.5 V
0.00.0 0.4 0.80.8 1.2 1.61.6 2.0 2.42.4 2.8 3.23.2 3.6 4.04.0 4.4 4.84.8 5.2 5.65.6
-5-5
-4
-3
-3
-2
-1
00
1
2
3
3
4
55
T=25°C
T=-40°C
T=125°C
Vcc=5.5V
Vio (µV)
Vicm (V)
Figure 12. Input offset voltage vs. temperature
-40 -20 0 20 40 60 80 100 120
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input offset voltage (µV)
Temperature (°C)
Limit for TSZ121
Vcc=5V, Vicm=2.5V
Figure 13. VOH vs. supply voltage
1.8 2.02.0 2.2 2.42.4 2.6 2.82.8 3.0 3.23.2 3.4 3.63.6 3.8 4.04.0 4.2 4.44.4 4.6 4.84.8 5.0 5.25.2 5.4
00
3
55
8
1010
13
1515
18
2020
T=25°C
T=-40°C
T=125°C
Rl=10kΩ
Vicm=Vcc/2
Output swing (mV from Vcc+)
Vcc (V)
TSZ121, TSZ122, TSZ124
Electrical characteristic curves
DS9216 - Rev 10 page 9/38
Figure 14. VOL vs. supply voltage
1.8 2.02.0 2.2 2.42.4 2.6 2.82.8 3.0 3.23.2 3.4 3.63.6 3.8 4.04.0 4.2 4.44.4 4.6 4.84.8 5.0 5.25.2 5.4
00
3
55
8
1010
13
1515
18
2020
T=25°C
T=-40°C
T=125°C
Rl=10kΩ
Vicm=Vcc/2
Output swing (mV from Vcc-)
Vcc (V)
Figure 15. Output current vs. output voltage at VCC = 1.8 V
0.00.0 0.3 0.50.5 0.8 1.01.0 1.3 1.51.5 1.8
-30
-20-20
-10
00
10
2020
30
T=-40°C T=25°C
T=125°C
T=-40°C
Vcc=1.8V
T=125°C
T=25°C
Output Current (mA)
Output Voltage (V)
Figure 16. Output current vs. output voltage at VCC = 5.5 V
0.00.0 0.5 1.01.0 1.5 2.02.0 2.5 3.03.0 3.5 4.04.0 4.5 5.05.0 5.5
-30
-20-20
-10
00
10
2020
30
T=-40°C T=25°C
T=125°C
T=-40°C Vcc=5.5V
T=125°CT=25°C
Output Current (mA)
Output Voltage (V)
Figure 17. Input bias current vs. common mode at
VCC = 5 V
0.00.0 0.5 1.01.0 1.5 2.02.0 2.5 3.03.0 3.5 4.04.0 4.5 5.05.0
-100-100
-75
-50-50
-25
00
25
5050
75
100100
Vcc=5V
T=25°C
IiBn
IiBp
IiB (pA)
Common Mode Voltage (V)
Figure 18. Input bias current vs. common mode at
VCC = 1.8 V
0.00.0 0.3 0.50.5 0.8 1.01.0 1.3 1.51.5 1.8
-100-100
-75
-50-50
-25
00
25
5050
75
100100
Vcc=1.8V
T=25°C
IiBn
IiBp
IiB (pA)
Common Mode Voltage (V)
Figure 19. Input bias current vs. temperature at VCC = 5 V
-25 00 25 5050 75 100100 125
-100-100
-75
-50-50
-25
00
25
5050
75
100100
Vcc=5V
IiBp
IiBn
IiB (pA)
Temperature (°C)
TSZ121, TSZ122, TSZ124
Electrical characteristic curves
DS9216 - Rev 10 page 10/38
Figure 20. Bode diagram at VCC = 1.8 V
1 10 100 1000
-40
-20
0
20
40
-250
-200
-150
-100
-50
0
50
100
150
200
250
Gain (dB)
Frequency (kHz)
Gain
Phase
Vcc=1.8V, Vicm=0.9V, G=-100
Rl=10kΩ, Cl=100pF, Vrl=Vcc/2
T=125°C
T=-40°C
T=25°C
Phase (°)
Figure 21. Bode diagram at VCC = 2.7 V
1 10 100 1000
-40
-20
0
20
40
-250
-200
-150
-100
-50
0
50
100
150
200
250
Gain (dB)
Frequency (kHz)
Gain
Phase
Vcc=2.7V, Vicm=1.35V, G=-100
Rl=10kΩ, Cl=100pF, Vrl=Vcc/2
T=125°C
T=-40°C
T=25°C
Phase (°)
Figure 22. Bode diagram at VCC = 5.5 V
1 10 100 1000
-40
-20
0
20
40
-250
-200
-150
-100
-50
0
50
100
150
200
250
Gain (dB)
Frequency (kHz)
Gain
Phase
Vcc=5.5V, Vicm=2.75V, G=-100
Rl=10kΩ, Cl=100pF, Vrl=Vcc/2
T=125°C
T=-40°C
T=25°C
Phase (°)
Figure 23. Open loop gain vs. frequency
0.01 0.1 1 10 100 1000
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
Gain (dB)
Frequency (kHz)
Gain
Phase
Vcc=5V, Vicm=2.5V,
Rl=10k Ω, Cl=100pF
Phase (°)
Figure 24. Positive slew rate vs. supply voltage
2.02.0 2.52.5 3.03.0 3.53.5 4.04.0 4.54.5 5.05.0 5.55.5
0.00.0
0.10.1
0.20.2
0.30.3
Rl=10kΩ, Cl=100pF
Vin: from 0.3V to Vcc-0.3V
SR calculated from 10% to 90%
T=125°C
T=25°C
T=-40°C
Positive Slew Rate (V/µs)
Supply Voltage (V)
Figure 25. Negative slew rate vs. supply voltage
2.02.0 2.52.5 3.03.0 3.53.5 4.04.0 4.54.5 5.05.0 5.55.5
-0.3-0.3
-0.2-0.2
-0.1-0.1
0.00.0
Rl=10kΩ, Cl=100pF
Vin: from Vcc-0.3V to 0.3V
SR calculated from 10% to 90%
T=125°C
T=25°C
T=-40°C
Negative Slew Rate (V/µs)
Supply Voltage (V)
TSZ121, TSZ122, TSZ124
Electrical characteristic curves
DS9216 - Rev 10 page 11/38
Figure 26. 0.1 Hz to 10 Hz noise
100m 1 10
10
15
20
25
30
35
40
45
50
55
noise density (nV/√Hz)
Frequency (Hz)
Vcc = 5.5V
Vicm=Vcc/2
T=25°C Noise 0.1Hz_10Hz
equivalent to 0.75 µVpp
Figure 27. Noise vs. frequency
100 1k 10k
20
40
60
80
100
120
140
160
180
200
Equivalent Input Voltage Noise (nV/√Hz)
Frequency (Hz)
Vcc=1.8V
Vcc=3.3V
Vcc=5.5V
Vicm=Vcc/2
Tamb=25°C
Figure 28. Noise vs. frequency and temperature
100 1k 10k
20
40
60
80
100
120
140
160
180
200
Equivalent Input Voltage Noise (nV/√Hz)
Frequency (Hz)
125°C
25°C
-40°C
Vicm=Vcc/2
Vcc=5.5V
Figure 29. Output overshoot vs. load capacitance
10 100 1000
00
5
1010
15
2020
25
3030
35
4040
Vcc=5.5V
100mVpp
Rl=10kΩ
Overshoot (%)
Load capacitance (pF)
Figure 30. Small signal
-10 0 10 20 30
-0.10
-0.05
0.00
0.05
0.10
Vcc = 5.5V
Rl=10kΩ
Cl=100pF
T=25°C
Output Voltage (V)
Time (µs)
Figure 31. Large signal
-100 0 100 200 300 400 500 600
-2.00
0.00
2.00
Vcc = 5.5V
Rl=10kΩ
Cl=100pF
T=25°C
Output Voltage (V)
Time (µs)
TSZ121, TSZ122, TSZ124
Electrical characteristic curves
DS9216 - Rev 10 page 12/38
Figure 32. Positive overvoltage recovery at VCC = 1.8 V
-100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
-0.20
-0.15
-0.10
-0.05
0.00
Vout (V)
Time (s)
Vout
Vin
Vcc=1.8V, Vicm=0.9V, G=101
Rl=10kΩ, Cl=100pF
Vin (V)
Figure 33. Positive overvoltage recovery at VCC = 5 V
-100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
-0.20
-0.15
-0.10
-0.05
0.00
Vout (V)
Time (s)
Vout
Vin
Vcc=5.5V, Vicm=2.75V, G=101
Rl=10kΩ, Cl=100pF
Vin (V)
Figure 34. Negative overvoltage recovery at VCC = 1.8 V
-100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ
-1.0
-0.5
0.0
0.5
1.0
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
Vout (V)
Time (s)
Vout
Vin
Vcc=1.8V, Vicm=0.9V, G=101
Rl=10kΩ, Cl=100pF
Vin (V)
Figure 35. Negative overvoltage recovery at VCC = 5 V
-100µ -50µ 0 50µ 100µ 150µ 200µ 250µ 300µ 350µ 400µ
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
Vout (V)
Time (s)
Vout
Vin
Vcc=5.5V, Vicm=2.75V, G=101
Rl=10kΩ, Cl=100pF
Vin (V)
Figure 36. PSRR vs. frequency
10 100 1000 10000 100000 1000000
0
-20
-40
-60
-80
-100
-PSRR
+PSRR
Vcc=5.5V, Vicm=2.75V, G=1
Rl=10kΩ, Cl=100pF, Vripple=100mVpp
PSRR (dB)
Frequency (Hz)
Figure 37. Output impedance vs. frequency
100 1k 10k 100k 1M
200
400
600
800
1000
1200
1400
1600
1800
2000
Vcc=2.7V to 5.5V
Osc level=30mVRMS
G=1
Ta=25°C
Output Impedance (Ω)
Frequency (Hz)
TSZ121, TSZ122, TSZ124
Electrical characteristic curves
DS9216 - Rev 10 page 13/38
5Application information
5.1 Operation theory
The TSZ121, TSZ122, and TSZ124 are high precision CMOS devices. They achieve a low offset drift and no 1/f
noise thanks to their chopper architecture. Chopper-stabilized amps constantly correct low-frequency errors
across the inputs of the amplifier.
Chopper-stabilized amplifiers can be explained with respect to:
• Time domain
• Frequency domain
5.1.1 Time domain
The basis of the chopper amplifier is realized in two steps. These steps are synchronized thanks to a clock
running at 400 kHz.
Figure 38. Block diagram in the time domain (step 1)
Vout
A1(f) Filter
A2(f)
V
V
Chop 1 Chop 2
inp
inn
Figure 39. Block diagram in the time domain (step 2)
V
o ut
A1(f) Filter
A2 (f)
V
V
Chop 1 Chop 2
inp
inn
Figure 38. Block diagram in the time domain (step 1) shows step 1, the first clock cycle, where Vio is amplified in
the normal way.
Figure 39. Block diagram in the time domain (step 2) shows step 2, the second clock cycle, where Chop1 and
Chop2 swap paths. At this time, the Vio is amplified in a reverse way as compared to step 1.
At the end of these two steps, the average Vio is close to zero.
The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input offset and is
consequently divided by A1(f).
In the time domain, the offset part of the output signal before filtering is shown in Figure 40. Vio cancellation
principle.
TSZ121, TSZ122, TSZ124
Application information
DS9216 - Rev 10 page 14/38
Figure 40. Vio cancellation principle
Step 1 Step 1 S tep 1
Step 2 Step 2 S te p 2
V
io
Time
V
io
The low pass filter averages the output value resulting in the cancellation of the Vio offset.
The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio, thanks to the chopper
technique.
5.1.2 Frequency domain
The frequency domain gives a more accurate vision of chopper-stabilized amplifier architecture.
Figure 41. Block diagram in the frequency domain
Vinn
Vinp
Vos + Vn
Chop1 A(f) Chop 2 Filter
A(f) Vout
1 2 3 4
The modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and
demodulate it back after amplification.
1. According to Figure 41. Block diagram in the frequency domain, the input signal Vin is modulated once
(Chop1) so all the input signal is transposed to the high frequency domain.
2. The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise)) to this modulated
signal.
3. This signal is then demodulated (Chop2), but since the noise and the offset are modulated only once, they
are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low
frequency noise. Consequently, the input signal is amplified with a very low offset and 1/f noise.
4. To get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented.
To further suppress the remaining ripple down to a desired level, another low pass filter may be added externally
on the output of the TSZ121, TSZ122, or TSZ124 device.
5.2 Operating voltages
TSZ121, TSZ122, and TSZ124 devices can operate from 1.8 to 5.5 V. The parameters are fully specified for 1.8
V, 3.3 V, and 5 V power supplies. However, the parameters are very stable in the full VCC range and several
characterization curves show the TSZ121, TSZ122, and TSZ124 device characteristics at 1.8 V and 5.5 V.
Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 ° C.
5.3 Input pin voltage ranges
TSZ121, TSZ122, and TSZ124 devices have internal ESD diode protection on the inputs. These diodes are
connected between the input and each supply rail to protect the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this over current can damage the device.
TSZ121, TSZ122, TSZ124
Operating voltages
DS9216 - Rev 10 page 15/38
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in
Figure 42. Input current limitation.
Figure 42. Input current limitation
Vin
R
5 V
TSZ121, TSZ122, TSZ124
Vout
+
+
-
-
5.4 Rail-to-rail input
TSZ121, TSZ122, and TSZ124 devices have a rail-to-rail input, and the input common mode range is extended
from (VCC -) - 0.1 V to (VCC+) + 0.1 V.
5.5 Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
∆Tmax Vio T( ) Vio 25
()–
T 25 °C–
=°C
Where T = -40 °C and 125 °C.
The TSZ121, TSZ122, and TSZ124 datasheet maximum value is guaranteed by measurements on a
representative sample size ensuring a Cpk (process capability index) greater than 1.3.
5.6 Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 30 mV above and below the rail
when connected to a 10 kΩ resistive load to VCC/2.
5.7 Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.
Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a serial resistor
at VDD = 1.8 V show the serial resistor that must be added to the output, to make a system stable. Figure 45. Test
configuration for Riso shows the test configuration using an isolation resistor, Riso.
TSZ121, TSZ122, TSZ124
Rail-to-rail input
DS9216 - Rev 10 page 16/38
Figure 43. Stability criteria with a serial resistor at
VDD = 5 V
Figure 44. Stability criteria with a serial resistor at
VDD = 1.8 V
Figure 45. Test configuration for Riso
Cload
VIN +
-
+VCC
Riso
10 kΩ
-VCC
VOUT
5.8 PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. Good practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.
5.9 Optimized application recommendation
TSZ121, TSZ122, and TSZ124 devices are based on chopper architecture. As they are switched devices, it is
strongly recommended to place a 0.1 µF capacitor as close as possible to the supply pins.
A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic
interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small
ripple that may appear on the output.
TSZ121, TSZ122, and TSZ124 devices have been optimized for use with 10 kΩ in the feedback loop. With this, or
a higher value of resistance, these devices offer the best performance.
5.10 EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF
signal rectification.
The TSZ121, TSZ122, and TSZ124 have been specially designed to minimize susceptibility to EMIRR and show
an extremely good sensitivity. Figure 46. EMIRR on IN+ pin shows the EMIRR IN+ of the TSZ121, TSZ122, and
TSZ124 measured from 10 MHz up to 2.4 GHz.
TSZ121, TSZ122, TSZ124
PCB layout recommendations
DS9216 - Rev 10 page 17/38
Figure 46. EMIRR on IN+ pin
10 100 1000
0
20
40
60
80
100
120
Vcc=5.5V, G=1
Prf=-10dBm
EMIRR In+(dB)
Frequency (MHz)
5.11 Application examples
5.11.1 Oxygen sensor
The electrochemical sensor creates a current proportional to the concentration of the gas being measured. This
current is converted into voltage thanks to R resistance. This voltage is then amplified by TSZ121, TSZ122, and
TSZ124 devices (see Figure 47. Oxygen sensor principle schematic).
Figure 47. Oxygen sensor principle schematic
-
+
+
-
O2_ sensor
R1 R2
VCC
TSZ121, TSZ122, TSZ124
Vout
I
The output voltage is calculated using Equation 2:
Equation 2
Vou t I(R Vio )R2
R1
1+×–×=
As the current delivered by the O2 sensor is extremely low, the impact of the Vio can become significant with a
traditional operational amplifier. The use of the chopper amplifier of the TSZ121, TSZ122, or TSZ124 is perfect for
this application.
In addition, using TSZ121, TSZ122, or TSZ124 devices for the O2 sensor application ensures that the
measurement of O2 concentration is stable even at different temperature thanks to a very good ΔVio/ΔT.
5.11.2 Precision instrumentation amplifier
The instrumentation amplifier uses three op amps. The circuit, shown in Figure 48. Precision instrumentation
amplifier schematic, exhibits high input impedance, so that the source impedance of the connected sensor has no
impact on the amplification.
TSZ121, TSZ122, TSZ124
Application examples
DS9216 - Rev 10 page 18/38
Figure 48. Precision instrumentation amplifier schematic
TSZ12x
V1
V2
Rg
Rf
Rf
R2 R4
R1 R3
TSZ12x
V
out
TSZ12x
+
-
-
+
-
+
The gain is set by tuning the Rg resistor. With R1 = R2 and R3 = R4, the output is given by
Section 5.11.2 Equation 3.
Equation 3
Vout =V2− V1
R4
R2⋅2Rf
Rg+ 1
The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection ratio (CMR).
5.11.3 Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting
applications. The low-side current sensing method consists of placing a sense resistor between the load and the
circuit ground. The resulting voltage drop is amplified using TSZ121, TSZ122, and TSZ124 devices (see
Figure 49. Low-side current sensing schematic).
Figure 49. Low-side current sensing schematic
-
+
+
-
R
shunt
Rg1
Rg2
C1
Rf1
5 V
Vout
Rf2
TSZ121, TSZ122, TSZ124
IIn
Ip
Vout can be expressed as follows:
Equation 4
Vou t Rshun t I 1 Rg2
Rg2 Rf2
+1Rf1
Rg1
–
×Ip
Rg2 Rf2
Rg2 Rf2
1Rf1
Rg1
lnRf1 Vio 1Rf1
Rg1
+––+=+ + ×
×
+×
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 4 can be simplified as follows:
Equation 5
Vout Rshunt IRf
Rg
× Vio 1Rf
Rg
–RfIio
×+= +
TSZ121, TSZ122, TSZ124
Application examples
DS9216 - Rev 10 page 19/38
The main advantage of using the chopper of the TSZ121, TSZ122, and TSZ124, for a low-side current sensing, is
that the errors due to Vio and Iio are extremely low and may be neglected.
Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power
dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the
accuracy of the measurement.
TSZ121, TSZ122, TSZ124
Application examples
DS9216 - Rev 10 page 20/38
6Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
TSZ121, TSZ122, TSZ124
Package information
DS9216 - Rev 10 page 21/38
6.1 SC70-5 (or SOT323-5) package information
Figure 50. SC70-5 (or SOT323-5) package outline
SEATING PLANE
GAUGE PLANE
DIMENSIONS IN MM
SIDE VIEW
TOP VIEW
COPLANAR LEADS
Table 6. SC70-5 (or SOT323-5) mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.80 1.10 0.032 0.043
A1 0.10 0.004
A2 0.80 0.90 1.00 0.032 0.035 0.039
b 0.15 0.30 0.006 0.012
c 0.10 0.22 0.004 0.009
D 1.80 2.00 2.20 0.071 0.079 0.087
E 1.80 2.10 2.40 0.071 0.083 0.094
E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 0.025
e1 1.30 0.051
L 0.26 0.36 0.46 0.010 0.014 0.018
< 0° 8° 0° 8°
TSZ121, TSZ122, TSZ124
SC70-5 (or SOT323-5) package information
DS9216 - Rev 10 page 22/38
6.2 SOT23-5 package information
Figure 51. SOT23-5 package outline
Table 7. SOT23-5 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.90 1.20 1.45 0.035 0.047 0.057
A1 0.15 0.006
A2 0.90 1.05 1.30 0.035 0.041 0.051
B 0.35 0.40 0.50 0.014 0.016 0.020
C 0.09 0.15 0.20 0.004 0.006 0.008
D 2.80 2.90 3.00 0.110 0.114 0.118
D1 1.90 0.075
e 0.95 0.037
E 2.60 2.80 3.00 0.102 0.110 0.118
F 1.50 1.60 1.75 0.059 0.063 0.069
L 0.10 0.35 0.60 0.004 0.014 0.024
K 0 degrees 10 degrees 0 degrees 10 degrees
TSZ121, TSZ122, TSZ124
SOT23-5 package information
DS9216 - Rev 10 page 23/38
6.3 DFN8 2 x 2 package information
Figure 52. DFN8 2 x 2 package outline
Table 8. DFN8 2 x 2 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.51 0.55 0.60 0.020 0.022 0.024
A1 0.05 0.002
A3 0.15 0.006
b 0.18 0.25 0.30 0.007 0.010 0.012
D 1.85 2.00 2.15 0.073 0.079 0.085
D2 1.45 1.60 1.70 0.057 0.063 0.067
E 1.85 2.00 2.15 0.073 0.079 0.085
E2 0.75 0.90 1.00 0.030 0.035 0.039
e 0.50 0.020
L 0.225 0.325 0.425 0.009 0.013 0.017
ddd 0.08 0.003
TSZ121, TSZ122, TSZ124
DFN8 2 x 2 package information
DS9216 - Rev 10 page 24/38
Figure 53. DFN8 2 x 2 recommended footprint
TSZ121, TSZ122, TSZ124
DFN8 2 x 2 package information
DS9216 - Rev 10 page 25/38
6.4 MiniSO8 package information
Figure 54. MiniSO8 package outline
Table 9. MiniSO8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.1 0.043
A1 0 0.15 0 0.0006
A2 0.75 0.85 0.95 0.030 0.033 0.037
b 0.22 0.40 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.80 3.00 3.20 0.11 0.118 0.126
E 4.65 4.90 5.15 0.183 0.193 0.203
E1 2.80 3.00 3.10 0.11 0.118 0.122
e 0.65 0.026
L 0.40 0.60 0.80 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.010
k 0° 8° 0° 8°
ccc 0.10 0.004
TSZ121, TSZ122, TSZ124
MiniSO8 package information
DS9216 - Rev 10 page 26/38
6.5 SO8 package information
Figure 55. SO8 package outline
Table 10. SO8 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
E 5.80 6.00 6.20 0.228 0.236 0.244
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
L1 1.04 0.040
k 0° 8° 0° 8°
ccc 0.10 0.004
TSZ121, TSZ122, TSZ124
SO8 package information
DS9216 - Rev 10 page 27/38
6.6 QFN16 3x3 package information
Figure 56. QFN16 3x3 package outline
TSZ121, TSZ122, TSZ124
QFN16 3x3 package information
DS9216 - Rev 10 page 28/38
Table 11. QFN16 3x3 mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0 0.05 0 0.002
A3 0.20 0.008
b 0.18 0.30 0.007 0.012
D 2.90 3.00 3.10 0.114 0.118 0.122
D2 1.50 1.80 0.059 0.071
E 2.90 3.00 3.10 0.114 0.118 0.122
E2 1.50 1.80 0.059 0.071
e 0.50 0.020
L 0.30 0.50 0.012 0.020
Figure 57. QFN16 3x3 recommended footprint
TSZ121, TSZ122, TSZ124
QFN16 3x3 package information
DS9216 - Rev 10 page 29/38
6.7 TSSOP14 package information
Figure 58. TSSOP14 package outline
aaa
Table 12. TSSOP14 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.20 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0089
D 4.90 5.00 5.10 0.193 0.197 0.201
E 6.20 6.40 6.60 0.244 0.252 0.260
E1 4.30 4.40 4.50 0.169 0.173 0.176
e 0.65 0.0256
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
k 0° 8° 0° 8°
aaa 0.10 0.004
TSZ121, TSZ122, TSZ124
TSSOP14 package information
DS9216 - Rev 10 page 30/38
7Ordering information
Table 13. Order codes
Order code Temperature range Package Packaging Marking
TSZ121ICT
-40 to 125 °C
SC70-5
Tape and reel
K44
TSZ121ILT SΟΤ23-5 K143
TSZ122IQ2T DFN8 2x2 K33
TSZ122IST MiniSO8 K208
TSZ122IDT SO8 TSZ122I
TSZ124IQ4T QFN16 3x3 K193
TSZ124IPT TSSOP14 TSZ124I
TSZ121IYLT (1)
-40 to 125 °C automotive grade
SΟΤ23-5 K192
TSZ122IYDT (1) SO8 K192D
TSZ122IYST (1) MiniSO8 K192
TSZ124IYPT (1) TSSOP14 TSZ124IY
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 &
Q002 or equivalent.
TSZ121, TSZ122, TSZ124
Ordering information
DS9216 - Rev 10 page 31/38
Revision history
Table 14. Document revision history
Date Revision Changes
16-Aug-2012 1 Initial release.
25-Apr-2013 2
Added dual and quad products (TSZ122 and TSZ124 respectively)
Updated title
Added following packages: DFN8 2x2, MiniSO8, QFN16 3x3, TSSOP14
Updated Features
Added Benefits and Related products
Updated Description
Updated Table 1 (Rthja, ESD)
Updated Table 3 (Vio, ∆Vio/∆T, CMR, Avd, ICC, en, and Cs)
Updated Table 4 (Vio, ∆Vio/∆T, CMR, ICC, en, and Cs)
Updated Table 5 (Vio, ∆Vio/∆T, CMR, SVR, EMIRR, ICC, ts, en, and Cs)
Updated curves of Section 3: Electrical characteristics
Added Section 4.7: Capacitive load
Small update Section 4.9: Optimized application recommendation (capacitor)
Added Section 4.10: EMI rejection ration (EMIRR)
Updated Table 10: Order codes
11-Sep-2013 3
Added SO8 package for commercial part number TSZ122IDT
Related products: added hyperlinks for TSV71x and TSV73x products
Table 1: updated CDM information
Figure 6, Figure 7: updated X-axes titles
Figure 12: updated X-axis and Y-axis titles
Figure 19: updated title
Figure 26: updated X-axis (logarithmic scale)
Figure 27 and Figure 28: updated Y-axis titles
23-May-2014 4
Table 1: updated ESD information
Table 5: added footnote 3
Table 10: Order codes: added automotive qualification footnotes 1 and 2; updated marking of TSZ122IST.
Updated disclaimer
09-May-2016 5
Updated document layout
Table 13: "Order codes": added new automotive grade order code TSZ122IYD, updated footnotes of other
automotive grade order codes.
07-Feb-2017 6 Table 3, Table 4, and Table 5: added parameter "Low-frequency peak-to-peak input noise" (∫en). Figure 26:
"0.1 Hz to 10 Hz noise": updated legend (0.75 μVpp instead of 0.2 μVpp)
12-Apr-2017 7 Updated footnote related to TSZ122IYDT in Table 13: "Order codes". Minor changes throughout the
document.
18-May-2017 8 Updated package outline drawing and mechanical data in Section 6.2: SOT23-5 package information.
12-Nov-2018 9 Updated Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a
serial resistor at VDD = 1.8 V
26-Feb-2019 10 Updated Figure 43. Stability criteria with a serial resistor at VDD = 5 V and Figure 44. Stability criteria with a
serial resistor at VDD = 1.8 V
TSZ121, TSZ122, TSZ124
DS9216 - Rev 10 page 32/38
Contents
1Package pin connections ..........................................................2
2Absolute maximum ratings and operating conditions ..............................3
3Electrical characteristics...........................................................4
4Electrical characteristic curves ....................................................8
5Application information...........................................................14
5.1 Operation theory ..............................................................14
5.1.1 Time domain ...........................................................14
5.1.2 Frequency domain ......................................................15
5.2 Operating voltages ............................................................15
5.3 Input pin voltage ranges ........................................................15
5.4 Rail-to-rail input ...............................................................16
5.5 Input offset voltage drift over temperature .........................................16
5.6 Rail-to-rail output..............................................................16
5.7 Capacitive load ...............................................................16
5.8 PCB layout recommendations ...................................................17
5.9 Optimized application recommendation ...........................................17
5.10 EMI rejection ration (EMIRR)....................................................17
5.11 Application examples ..........................................................18
5.11.1 Oxygen sensor .........................................................18
5.11.2 Precision instrumentation amplifier ..........................................18
5.11.3 Low-side current sensing .................................................19
6Package information..............................................................21
6.1 SC70-5 (or SOT323-5) package information .......................................22
6.2 SOT23-5 package information...................................................22
6.3 DFN8 2 x 2 package information.................................................23
6.4 MiniSO8 package information ...................................................26
6.5 SO8 package information.......................................................26
6.6 QFN16 3x3 package information.................................................27
6.7 TSSOP14 package information..................................................29
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Contents
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7Ordering information .............................................................31
Revision history .......................................................................32
Contents ..............................................................................33
List of tables ..........................................................................35
List of figures..........................................................................36
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Contents
DS9216 - Rev 10 page 34/38
List of tables
Table 1. Absolute maximum ratings (AMR) ........................................................3
Table 2. Operating conditions .................................................................3
Table 3. Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified) ........................................................4
Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified) ........................................................5
Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C, and RL = 10 kΩ connected to
VCC/2 (unless otherwise specified) ........................................................6
Table 6. SC70-5 (or SOT323-5) mechanical data ...................................................22
Table 7. SOT23-5 mechanical data............................................................. 23
Table 8. DFN8 2 x 2 mechanical data ........................................................... 24
Table 9. MiniSO8 package mechanical data ......................................................26
Table 10. SO8 package mechanical data .........................................................27
Table 11. QFN16 3x3 mechanical data ...........................................................29
Table 12. TSSOP14 package mechanical data ..................................................... 30
Table 13. Order codes ...................................................................... 31
Table 14. Document revision history ............................................................. 32
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List of tables
DS9216 - Rev 10 page 35/38
List of figures
Figure 1. Pin connections for each package (top view) ...............................................2
Figure 2. Supply current vs. supply voltage .......................................................8
Figure 3. Input offset voltage distribution at VCC = 5 V................................................8
Figure 4. Input offset voltage distribution at VCC = 3.3 V ..............................................8
Figure 5. Input offset voltage distribution at VCC = 1.8 V ..............................................8
Figure 6. Vio temperature co-efficient distribution (-40 °C to 25 °C) .......................................8
Figure 7. Vio temperature co-efficient distribution (25 °C to 125 °C) ......................................8
Figure 8. Input offset voltage vs. supply voltage ....................................................9
Figure 9. Input offset voltage vs. input common-mode at VCC = 1.8 V .....................................9
Figure 10. Input offset voltage vs. input common-mode at VCC = 2.7 V .....................................9
Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V .....................................9
Figure 12. Input offset voltage vs. temperature......................................................9
Figure 13. VOH vs. supply voltage ..............................................................9
Figure 14. VOL vs. supply voltage..............................................................10
Figure 15. Output current vs. output voltage at VCC = 1.8 V ............................................ 10
Figure 16. Output current vs. output voltage at VCC = 5.5 V ............................................ 10
Figure 17. Input bias current vs. common mode at VCC = 5 V........................................... 10
Figure 18. Input bias current vs. common mode at VCC = 1.8 V ......................................... 10
Figure 19. Input bias current vs. temperature at VCC = 5 V ............................................10
Figure 20. Bode diagram at VCC = 1.8 V ......................................................... 11
Figure 21. Bode diagram at VCC = 2.7 V ......................................................... 11
Figure 22. Bode diagram at VCC = 5.5 V ......................................................... 11
Figure 23. Open loop gain vs. frequency ......................................................... 11
Figure 24. Positive slew rate vs. supply voltage .................................................... 11
Figure 25. Negative slew rate vs. supply voltage ................................................... 11
Figure 26. 0.1 Hz to 10 Hz noise ..............................................................12
Figure 27. Noise vs. frequency................................................................ 12
Figure 28. Noise vs. frequency and temperature ...................................................12
Figure 29. Output overshoot vs. load capacitance .................................................. 12
Figure 30. Small signal .....................................................................12
Figure 31. Large signal ..................................................................... 12
Figure 32. Positive overvoltage recovery at VCC = 1.8 V ..............................................13
Figure 33. Positive overvoltage recovery at VCC = 5 V ...............................................13
Figure 34. Negative overvoltage recovery at VCC = 1.8 V ............................................. 13
Figure 35. Negative overvoltage recovery at VCC = 5 V ............................................... 13
Figure 36. PSRR vs. frequency ...............................................................13
Figure 37. Output impedance vs. frequency....................................................... 13
Figure 38. Block diagram in the time domain (step 1) ................................................14
Figure 39. Block diagram in the time domain (step 2) ................................................14
Figure 40. Vio cancellation principle ............................................................ 15
Figure 41. Block diagram in the frequency domain .................................................. 15
Figure 42. Input current limitation ..............................................................16
Figure 43. Stability criteria with a serial resistor at VDD = 5 V ........................................... 17
Figure 44. Stability criteria with a serial resistor at VDD = 1.8 V.......................................... 17
Figure 45. Test configuration for Riso ........................................................... 17
Figure 46. EMIRR on IN+ pin................................................................. 18
Figure 47. Oxygen sensor principle schematic .....................................................18
Figure 48. Precision instrumentation amplifier schematic.............................................. 19
Figure 49. Low-side current sensing schematic .................................................... 19
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List of figures
DS9216 - Rev 10 page 36/38
Figure 50. SC70-5 (or SOT323-5) package outline ..................................................22
Figure 51. SOT23-5 package outline ........................................................... 23
Figure 52. DFN8 2 x 2 package outline .......................................................... 24
Figure 53. DFN8 2 x 2 recommended footprint..................................................... 25
Figure 54. MiniSO8 package outline ............................................................ 26
Figure 55. SO8 package outline ...............................................................27
Figure 56. QFN16 3x3 package outline ..........................................................28
Figure 57. QFN16 3x3 recommended footprint..................................................... 29
Figure 58. TSSOP14 package outline ........................................................... 30
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List of figures
DS9216 - Rev 10 page 37/38
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