02095-DSH-001-E Mindspeed Technologies®August 2007
Mindspeed Proprietary and Confidential
M02095/6
3.3/5V Laser Driver / Limiting Amplifier
for Operation to 2.5 Gbps
Applications
• 2.5 Gbps STM-16/OC-48 SDH/SONET (M02096)
• 1.06 and 2.12 Gbps Fibre Channel (M02095/6)
• 1.25 Gbps Ethernet (M02095/6)
• 1.25 Gbps SDH/SONET (M02095/6)
• 2.67 Gbps SDH/SONET with FEC (M02096)
• SDH/SONET 155 Mbps Transceivers
• FTTx and Media Converters
Features
• High speed operation; suitable for applications to 2.5 Gbps. 55 ps
typical rise/fall time into 25Ω
• Independently programmable bias and modulation currents
Modulation current to 85 mA and bias current to 100 mA
The M02095 and M02096 are integrated laser drivers and limiting amplifiers for applications to 1.25 Gbps and
2.5 Gbps, respectively. The laser driver modulation output can be AC or DC coupled to an FP/DFB laser. The
devices can operate from a 3.3V or 5V supply.
The devices include monitors for bias and laser power. Integrated safety circuitry provides latched bias and
modulation current shutdown if a fault condition is detected and provides an internal VCC switch.
The limiting amplifier also includes a programmable signal-level detector, allowing the user to set thresholds at
which the logic outputs are enabled. PECL or CML outputs are available on the limiting amplifier.
Configuration logic provides flexibility in setting data path polarity, safety logic configuration, and LOS behavior.
M02095/6 Typical Applications Diagram
V
CC
3T
SV
CC
OUT+
OUT-
GND
0
IPIN
IB
OUT
Input
Buffer
D
IN
-
D
IN
+
TX
Disable
FAIL
DIS
RESET
V
CC
T
GND
BIAS_Mon
TxPwrMon
3.3V Regulator
with Bypass
To Safety
Logic
To Safety
Logic
V
CC
V
CC3
Laser
Driver
MODSET
APCSET
Laser Power Control
BIAS
MON
TxPwr
MON
Threshold
Setting
Circuit
Biasing
RxOUTp
Regulator
RxOUTm
RSSI
LOS-ST
RxINm
Iref
RxINp
V
CC
RSTSET
Offset Cancel
DCR_Disable
Limiting
Amplifier
SCB
Safety
Circuitry with
Latched Fault
Output
Buffer
Tx_Polarity
Rx_Polarity
CONFIG_2 Tx_Polarity
Rx_Polarity
CONFIG_3
CONFIG_1
DCR_Disable
C
APC
TC
SLOPE
TC
START
LOS-to-JAM
CONFIG_4 LOS-to-JAM
LOS-ST_sel
LOS-ST_sel
Vttr
Analog
MUX
LOS
Level
Detect
Comparator
V
CC
3R
Configuration
Logic
Modulation
Control
2kΩ
2kΩ
4kΩ
4kΩ
Vttx
Output
Buffer
V
CC
3T
DeMux
Output
Configuration
Control
(V
CC
, GND
or Float)
V
CC
Photodiode
AC-Coupled
to TIA
M0201x
V
CC
3R
AC or DC Coupled
(as described in
Applications Information)
Clock Data
Recovery
Unit
V
CC
Features (con’t)
• Integrated power supply switch for redundant shutdown under a
fault condition
• Temperature compensation for modulation current
• Automatic Power Control
• SFP compliant safety circuitry (configurable)
• 3.3 mV typical input limiting amp sensitivity at 2.5 Gbps
• CML or PECL limiting amplifier outputs
• Limiting amplifier includes integrated DC offset cancellation circuit
• Polarity Control for both the driver and limiting amplifier data paths
• Operates with 3.3V or 5V supply with an internal auto-sensing
regulator that enables with 5V supplies and is bypassed with 3.3V
supplies
• Powers 3.3V ROSAs from its Receiver Regulator output enabling
true 3.3/5V designs using all 3.3V Mindspeed TIAs
02095-DSH-001-E Mindspeed Technologies®2
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M02096 2.5 Gbps Laser Driver Eye Diagram M02095/6 Pin Configuration
Ordering Information
Part Number Package Operating Temperature
M02095G-XX* QFN32 –40°C to 95°C
M02096G-XX* QFN32 –40°C to 95°C
* The letter “G” designator after the part number indicates that the device is RoHS-compliant. Refer to www.mindspeed.com for additional
information.
Revision History
Revision Level Date ASIC
Revision Description
E Release August 2007 -12 Finalize limiting amplifier jitter specifications, combine laser driver and limiting
amplifier supply current together in Table 1-3.
D Preliminary May 2007 -12 Add TxPwrMon and BIASMON pins to device. Update DC specifications, Functional
Description and Applications Information.
C Preliminary November 2006 -11 Reflect current device pinout.
B Advance August 2006 -11 Update several specifications based on initial device evaluation.
A Advance June 2006 NA Initial Release.
GND
RxINp
RxINm
Config1
Config2
Config3
Config4
LOS-ST
IREF
CAPC
VCC3T
APCSET
TxPwrMON
BIASMON
MODSET
DIS
FAIL
RxOUTm
RxOUTp
VCC R
VCC T
TC
SLOPE
TCSTART
DINp
DINm
VCC 3R
STSET
SVCC
OUTN
OUTP
GNDO
IBOUT
IPIN
1
2
3
4
5
7
6
8
12
1110
916151413
20
19
18
17
24
23
22
21
28 27 26 2532 31 30 29
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1.0 Product Specification
1.1 Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged.
Reliable operation at these extremes for any length of time is not implied.
1.2 Recommended Operating Conditions
Table 1-1. Absolute Maximum Ratings
Symbol Parameter Rating Units
VCC Power supply voltage -0.4 to +6.0 V
VCC3 3.3V power supply voltage (when VCC3 is connected to VCC) -0.4 to +4.0 V
TSTG Storage temperature -65 to +150 °C
IBOUT_MAX Maximum bias output current at IBOUT 140 mA
IMOD_MAX Maximum modulation current 120 mA
Table 1-2. Recommended Operating Conditions
Parameter Rating Units
Power supply: (VCC-GND) (apply no potential to VCC3) or
(VCC3-GND) (connect VCC to same potential as VCC3)
+4.7 to 5.5V or
+3.3V ± 7.5%
V
Junction temperature -40 to +125 °C
Operating ambient -40 to +95 °C
Product Specification
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1.3 DC Characteristics
1.3.1 Device Power
VCC = 3.05 to 3.55V or 4.7 to 5.5V, TA = -40°C to +95°C, unless otherwise noted.
Typical values are VCC = 3.3V, IBOUT = 20 mA, IMOD = 30 mA.
1.3.2 DC Electrical Characteristics - Laser Driver
VCC = 3.05 to 3.55V or 4.7 to 5.5V, TA = -40°C to +95°C, unless otherwise noted.
Typical values are VCC = 3.3V, IBOUT = 20 mA, IMOD = 30 mA.
Table 1-3. Device Power
Symbol Parameter Conditions Minimum Typical Maximum Units
ICC VCC (sum of VCCT and VCCR)
supply current
Using external 3.3V supply VCC = 3.3V (1)
With CML Outputs (M02096)
With PECL Outputs (M02095 - includes PECL
load)
Additional current when operating from 5V
supply (2)
–
–
–
68
93
4
96
108
–
mA
NOTES:
1. Excludes bias and modulation currents delivered to the laser. Maximum supply current based on maximum settings for bias and modulation.
2. Bias and modulation currents add directly to power supply current in 5V applications; additional supply current noted excludes these currents.
Table 1-4. DC Electrical Characteristics - Laser Driver
Symbol Parameter Conditions Minimum Typical Maximum Units
VCC3THL 3.3V supply detection (low
voltage) threshold (1)
2.5 2.8 3.05 V
VCC3HH 3.3V supply detection (high
voltage) threshold (1)
3.65 3.95 4.2 V
VCC5THL 5V supply detection (low
voltage) threshold
3.9 4.35 4.7 V
VCC5THH 5V supply detection (high
voltage) threshold
5.5 – – V
VMODSET Modulation current ref. Voltage reference for MODSET 1.1 1.25 1.4 V
VAPCSET Automatic power control loop
voltage reference
Voltage at APCSET with APC loop operational 0.90 1.20 1.4 V
VFAULTL Low fault voltage detection
threshold (IBOUT, OUTP, CAPC,
IPIN, MODSET, APCSET)
Fault condition occurs when voltage drops
below this level
– 100 200 mV
VFAULTH High fault voltage detection
threshold (IPIN)
Fault condition occurs when voltage goes above
this level (2)
VCC3T - 0.2 VCC3T
- 0.1
–V
VSELFL Self-biased voltage for IBOUT and
OUTP
During disable condition 0.5 1.65 2.0 V
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IBIAS Bias current adjust range At IBOUT. VIBOUT > 0.7V 1 – 100 mA
IBIAS(OFF) Bias current with output disabled DIS = high
VIBOUT = VCC3
– – 150 µA
Ratio of bias output current to
APCSET current
= IBIAS / IAPCSET in open loop operation – 90 – A/A
Ratio of bias current to BIASMON
current
= IBIAS / IBIASMON 79 89 99 A/A
VMD Monitor diode reverse bias
voltage
1.5 2 – V
IMD Monitor diode current
adjustment range
For stable APC loop operation in closed loop
mode
10 – 1500 µA
Ratio of TxPwrMON current to
monitor diode current
Across range of IMD 0.8 1 1.2 A/A
CMDMAX Maximum monitor photodiode
capacitance
For loop stability; includes any additional
parasitic capacitance
– – 100 pF
VIH_DIS TTL/CMOS input high voltage
(DIS)
2.0 – – V
VIL_DIS TTL/CMOS input low voltage
(DIS)
––0.8V
VIH_CFG Configuration logic input high
voltage (Config1 - 4) (2)
VCC3T - 0.5 – – V
VIL_CFG Configuration logic input low
voltage (Config1 - 4) (2)
––0.5V
VOH_FAIL Logic output high voltage (FAIL) With external 10 kΩ pull-up to VCC VCC - 0.6 – – V
VOL_FAIL Logic output low voltage (FAIL) IOL = 0.8 mA – – 0.4 V
RIN Differential input resistance Transmitter Data inputs – 7.5 – kΩ
VCMSELF Self-biased common mode input
voltage
Data inputs floating – VCC3T
- 1.3
–V
VINCM Common-mode input
compliance voltage
Transmitter Data inputs VCC3T - 1.5 – VCC3T
- VIN(Diff)/4
V
VIN(Diff) Differential input voltage = 2*(DINpHIGH – DINpLOW) 200 – 2400 mV
NOTES:
1. VCC3 supply okay circuitry monitors internally regulated voltage when only the +5V supply is used (VCC = 5V).
2. Input is 3.3V tolerant logic.
Table 1-4. DC Electrical Characteristics - Laser Driver
Symbol Parameter Conditions Minimum Typical Maximum Units
Product Specification
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1.3.3 DC Electrical Characteristics - Limiting Amplifier
VCCR = 3.05 to 3.55V or 4.7 to 5.5V, TA = -40°C to +95°C, unless otherwise noted.
Typical values are VCC = 3.3V, 25°C.
1.4 AC Characteristics
1.4.1 AC Electrical Characteristics - Laser Driver
VCCT = 3.05 to 3.55V or 4.7 to 5.5V, TA = -40°C to +95°C, unless otherwise noted.
Typical values are VCC = 3.3V, IBOUT = 20 mA, IMOD = 30 mA.
Table 1-5. DC Electrical Characteristics - Limiting Amplifier
Symbol Parameter Conditions Minimum Typical Maximum Units
VAMP_CML CML Output Amplitude Single ended, 50Ω load to VCC;
10 mVPP input (M02096)
280 500 – mVPP
VOUTLPECL(1) PECL Output Low Voltage
(RxOUTm, RxOUTp)
Single ended; 50Ω load to VCC - 2V
(M02095) VCC - 1.88 VCC - 1.71 VCC - 1.60
V
VOUTHPECL(1) PECL Output High Voltage
(RxOUTm, RxOUTp)
Single ended; 50Ω load to VCC - 2V
(M02095) VCC - 1.09 VCC - 0.95 VCC - 0.88
V
VAMP_PECL PECL Output Amplitude Single ended; 50Ω load to VCC - 2V
(M02095)
– 740 – mVPP
RIN_DIFF Differential Input Resistance – 4.5 – kΩ
ROUT_DIFF Differential Output Resistance CML Outputs (M02096) 170 200 230 Ω
VOUTLLOS LOS Output High Voltage Open collector, 4.7 - 10 kΩ pull up to VCC 2.4 – VCC V
VOUTHLOS LOS Output Low Voltage IOL = 0.8 mA – – 0.4 V
NOTES:
1. PECL level requirements apply from 0°C to 95°C.
Table 1-6. AC Electrical Characteristics - Laser Driver
Symbol Parameter Conditions Minimum Typical Maximum Units
IMOD Modulation current adjust range To meet AC specifications (1, 2) 8–85mA
PP
IMOD(OFF) Modulation current with output
disabled
DIS = high – – 150 µA
Ratio of modulation current to
MODMON current (3)
–75–A/A
Ratio of modulation current to
MODSET current
– 110 – A/A
IMOD-TC Programmable range for
modulation current temperature
coefficient
Adjustable using TCSLOPE
0–10
4ppm/°C
TTCSTRT
Programmable temperature
range at which modulation
current TC compensation enables
Based on value set for TCSTART –0 (4) - 95 –°C
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1.4.2 AC Electrical Characteristics - Limiting Amplifier
VCCR = 3.05 to 3.55V or 4.7 to 5.5V, TA = -40°C to +95°C, unless otherwise noted.
tR / tFModulation output rise / fall times
20% to 80% into 25Ω load. Measured using
alternating 1111-0000 pattern at 2.5 Gbps
M02095; 25Ω load
M02096; 25Ω load
–
–
72
65
95
85
ps
OS Overshoot of modulation output
Into 25Ω load, off direction – 3 –
%
Into 25Ω load, on direction – 7 –
RJ Random jitter – 1.0 – psRMS
DJ Modulation output deterministic
jitter
into 25Ω load (includes pulse width distortion)
K28.5 pattern at 1.25 Gbps (M02095)
223 - 1 PRBS at 2.7 Gbps (M02096))
–
–
22
15
40
30
psPP
NOTES:
1. Minimum voltage at OUTP > 0.7 V; laser forward voltage and total series resistance must be considered if output is DC coupled to laser.
2. AC specifications apply across this range of mod current.
3. MODMON is accessible using Special Configuration 3 (SC3), see Table 4-3.
4. Default if TCSTART is floating.
Table 1-7. AC Electrical Characteristics - Limiting Amplifier
Symbol Parameter Conditions Minimum Typical Maximum Units
VIN(MIN) Minimum Differential Input
Sensitivity
BER < 10-12 at 2.5 Gbps with 223-1 PRBS
(M02096)
–3.36
mVPP
BER < 10-12 at 1.25 Gbps with K28.5 pattern
(M02095)
–24
VI(MAX) Input Overload
BER < 10-12, differential input 1200 – –
mVPP
BER < 10-12, single-ended input 600 – –
VNRMS Input Referred Noise
M02096 – – 425
µVRMS
M02095 – – 285
VLOS LOS Programmable Range
Differential inputs,
6.04 kΩ ≤ RSTSET ≤ 8.06 kΩ (M02096)
6.04 kΩ ≤ RSTSET ≤ 8.25 kΩ (M02095)
–8 - 60
7 - 60
–mV
HYS Signal Detect Hysteresis (electrical); signal detect level set to 20 mVPP 246dB
RSSIpp Peak-to-peak received signal
strength indicator range
4–100mV
BWLF Small-Signal -3dB Low
Frequency Cutoff.
Excluding AC coupling capacitors – 4 – kHz
DJ Deterministic Jitter
Differential, 10 mVPP input, 215-1 PRBS
2.5 Gbps (M02096)
1.25 Gbps (M02095)
–
–
20
20
48
70
ps
Table 1-6. AC Electrical Characteristics - Laser Driver
Symbol Parameter Conditions Minimum Typical Maximum Units
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1.5 Safety Logic Timing
VCC = 3.05 to 3.55V or 4.7 to 5.5V, TA = -40°C to +95°C, unless otherwise noted.
Typical values are VCC = 3.3V, IBOUT = 20 mA, IMOD = 30 mA.
RJ Random Jitter 10 mVPP input – 3.8 – psRMS
tr / tf2.5G Data Output Rise and Fall Times
M02096
20% to 80%; outputs terminated into 50Ω;
10 mVPP input
– 90 150 ps
tr / tf1.25G Data Output Rise and Fall Times
M02095
20% to 80%; outputs terminated into 50Ω;
10 mVPP input
– 160 250 ps
TLOS_ON Time from LOS state until LOS
output is asserted
LOS assert time after 1 VPP input signal is turned
off; signal detect level set to 10 mV
2.3 – 80 µs
TLOS_OFF Time from non-LOS state until
LOS is deasserted
LOS deassert time after input crosses signal
detect level; signal detect set to 10 mV with
applied input signal of 20 mVPP
2.3 – 80 µs
Table 1-8. Safety Logic Timing
Symbol Parameter Conditions Minimum Typical Maximum Units
t_off DIS assert time Rising edge of DIS to fall of output signal below
10% of nominal (1)
–110µs
t_on DIS negate time Falling edge of DIS to rise of output signal above
90% of nominal (1)
–0.41ms
t_init Time to initialize Includes reset of FAIL; from power on after
Supply_OK or from negation of DIS during reset
of FAIL condition
–4300ms
t_wc Window comparator hold-off
time
Time during which the status of the fault detect
comparators is ignored.
23–ms
t_fault Laser fault time -- from fault
condition to assertion of FAIL
From occurrence of fault condition or when
Supply_OK is beyond specified range
–16100µs
t_reset DIS time to start reset DIS pulse width required to initialize safety
circuitry or reset a latched fault
––10µs
tVCC_OK Supply okay delay time Delay between supply_OK condition and when
outputs are enabled
– 900 – µs
NOTE:
1. With CAPC = 47 nF.
Table 1-7. AC Electrical Characteristics - Limiting Amplifier
Symbol Parameter Conditions Minimum Typical Maximum Units
Product Specification
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Figure 1-1. Safety Logic Simplified Block Diagram
Table 1-9. Circuit Response to Single-Point Fault Conditions on Driver Pins
Pin Name Circuit Response to Over-voltage Condition or Short to
VCC
Circuit Response to Under-Voltage Condition or Short
to Ground
Config1-4 Does not affect output power (some conditions can selectively
enable/disable driver output).
Does not affect output power (some conditions can selectively
enable/disable driver output).
VCC Outputs are disabled if VCC exceeds the VCC_okay (high level)
threshold. If so, FAIL will be asserted. (1)
Outputs are disabled if VCC voltage is below the VCC_okay (low
level) threshold. If so, FAIL will be asserted. (1)
VCC3T Outputs are disabled if VCC3 exceeds the VCC3_okay (high level)
threshold. If so, FAIL will be asserted. (1)
Outputs are disabled if VCC3 voltage is below the VCC3_okay
(low level) threshold. If so, FAIL will be asserted. (1)
DINp, DINm The APC loop will attempt to compensate for the change in
output power. If the APC loop can not maintain the set average
power, a fault state occurs. (2,3)
The APC loop will attempt to compensate for the change in
output power. If the APC loop can not maintain the set average
power, a fault state occurs. (2,3)
CAPC A fault state occurs.(2) Laser bias current will be shut off, then a fault state occurs. (2)
FAIL Does not affect laser operation. Does not affect laser operation.
DIS Bias and modulation outputs are disabled and SVCC is opened. Does not affect laser power (normal condition for circuit
operation).
MODSET No modulation current. APC loop will adjust output power if DC
coupled to laser.
A fault state occurs. (2)
APCSET Laser output power is reduced (if the modulation outputs DC
coupled to laser) or turned off (if the modulation outputs AC
coupled to laser). A fault state may occur. (2)
A fault state occurs. (2)
TCSTART Modulation current may increase depending on operating
temperature and TCSLOPE setting. APC loop will adjust for change
in output power if modulation outputs are DC coupled to laser.
Modulation current may decrease depending on operating
temperature and TCSLOPE setting. APC loop will adjust for
change in output power if modulation outputs are DC coupled
to laser.
TCSLOPE Modulation current may decrease depending on operating
temperature and TCSTART setting. APC loop will adjust for change
in output power if modulation outputs are DC coupled to laser.
Modulation current may increase depending on operating
temperature and TCSTART setting. APC loop will adjust for
change in output power if modulation outputs are DC coupled
to laser.
DIS
Fault_OK
V
cc
3_ OK
V
cc
_OK
3.3V_ONLY
Q
Q
SET
CL R
S
R
~900
µ
s typical
FAIL
Output _ Enable
* Fault_OK indicates that no fault is detected at any of the fault sense nodes
~3 ms typical
Activate _Config_Settings
TC
SL O PE
Fault_OK
Normal
SCB
+
-
~2V
Configuration settings are not updated while TC
SLOPE
is
pulled high, but are updated when TC
SLOPE
is at normal level
Normal
SCB
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BIASMON,
TxPwrMON
Does not affect laser operation. Does not affect laser operation.
IPIN A fault state occurs. (2,4) A fault state occurs. (2,4)
IBOUT The laser is turned off and a fault state may occur. (2) A fault state occurs. (2)
OUTP Laser modulation is prevented; the APC loop will increase bias
current to compensate for the drop in laser power. If the set
output power can not be obtained, a fault state occurs. (2,3)
A fault state occurs. (2)
OUTN Does not affect laser operation. Does not affect laser operation.
GNDO Laser modulation is prevented and a fault state may occur. (2) Does not affect laser power.
SVCC Does not affect laser operation. The laser is turned off and a fault state occurs. (2)
NOTES:
1. In this case a fault state will assert the FAIL output, but it is not latched. While the fault condition remains, the bias and modulation outputs are
disabled and the switch at SVCC is open. No fault occurs if in Safety Circuit Bypass (SCB).
2. In this case a fault state will assert and latch the FAIL output, disable bias and modulation outputs and open the switch at SVCC. No fault occurs
if in Safety Circuit Bypass (SCB).
3. Does not affect laser power when the modulation output is AC coupled to the laser.
4. Does not affect laser power in open loop mode or when “Ignore IPIN” is selected.
Table 1-9. Circuit Response to Single-Point Fault Conditions on Driver Pins
Pin Name Circuit Response to Over-voltage Condition or Short to
VCC
Circuit Response to Under-Voltage Condition or Short
to Ground
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Figure 1-2. M02095/6 Safety Logic Timing Characteristics
Low
“OK”
Low
HOT PLUG (DIS Low)
t_init < 5 ms
(3 ms typ.)
Supply
(1)
FAIL
DIS
Laser
Output
Low
3.3V
Low
SLOW RAMPING 3.3V Operation (DIS Low)
3.3V
t_init < 5 ms
(3 ms typ.)
V
CC
FAIL
DIS
Laser
Output
V
CC
3
Low
5V
Low
SLOW RAMPING 5V Operation (DIS Low)
3.3V
t_init < 5 ms
(3 ms typ.)
V
CC
FAIL
DIS
Laser
Output
V
CC
3
Low
“OK”
FAIL
DIS Low
Laser
Output
High
TRANSMITTER ENABLE
t_on < 1 ms
(300 µs typ.)
Supply
(1)
Low
“OK”
Low
High
TRANSMITTER DISABLE
FAIL
DIS
Laser
Output
t_off < 10 µs
(1 µs typ.)
Supply (1)
Low
Low
RESPONSE TO FAULT
LowNormal
Fault Occurs
High
t_fault < 100 µs
(4 µs typ.)
FAIL
DIS
Laser
Output
Fault sense
node such
as IB
OUT
(2)
1. Supply “OK” means both VCC and VCC3 are within their defined operating windows.
2. A fault occurs when IPIN goes high or low; a fault at IPIN does not apply when “Ignore IPIN” configuration is selected.
NOTE: “Laser Output” is equivalent to bias current plus modulation current.
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Figure 1-3. M02095/6 Safety Logic Timing Characteristics (Continued)
Low
High
FAULT RECOVERY BEHAVIOR
Low Normal
t_reset
10 µs
Fault Removed
t_on < 1 ms
(300 µs typ.)
FAIL
DIS
Laser
Output
Fault sense
node such
as IB
OUT
(2)
FAULT RESET ATTEMPT
Low
(Does not turn on)
FAIL
DIS
Laser
Output
10 µs
10 - 20 µs
Fault sense
node such
as IB
OUT
(2)
FAIL
DIS
Laser
Output
FAULT RESET ATTEMPT
Low
t_init < 5 ms
(3 ms typ.)
10 µs
Fault sense
node such
as IB
OUT
(2)
1. Supply “OK” means both VCC and VCC3 are within their defined operating windows.
2. A fault occurs when IPIN goes high or low; a fault at IPIN does not apply when “Ignore IPIN” configuration is selected.
NOTE: “Laser Output” is equivalent to bias current plus modulation current.
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2.0 Pin Definitions
Table 2-1. M02095/6 Pin Descriptions (1 of 2)
QFN Pin
Number Pin Name Function
1 RxOUTm Limiting amplifier inverting data output (M02095 - PECL, M02096 - CML). Either output type is referenced to the
Rx supply input (VCCR).
2 RxOUTp Limiting amplifier non-inverting data output (M02095 - PECL, M02096 - CML). Either output type is referenced to
the Rx supply input (VCCR).
3V
CCR Power supply input for limiting amplifier circuitry (3.3V or 5V).
4V
CCT Power supply input for laser driver circuitry (3.3V or 5V).
5TC
SLOPE Modulation temperature compensation slope. A resistor to ground sets the level of temperature compensation
for the modulation current. Forcing this pin high (to 3.3V) causes the configuration logic to ignore configuration
logic settings until this pin is released to its normal level (~1.25V). Temperature compensation is disabled if this
pin is floating.
6TC
START A resistor to ground at this pin sets the temperature at which the modulation temperature compensation slope
becomes active. Letting this pin float results in a start temperature of ~0°C. Grounding this pin disables
temperature compensation.
7 DINp Transmitter positive Data Input. Internally terminated with 4 kΩ to self-bias voltage of approximately
VCC3T - 0.65V. Can be AC coupled.
8 DINm Transmitter negative Data Input. Internally terminated with 4 kΩ to self-bias voltage of approximately
VCC3T - 0.65V. Can be AC coupled.
9 FAIL Safety circuit fault indicator. Goes high when a safety logic fault is detected. The FAIL output is low when DIS is
high. Open collector; 4.7 kΩ to 10 kΩ external pull-up required. 5V compatible when using a 5V supply.
10 DIS Disable control (TTL compatible). When high or left floating, the bias and modulation outputs are disabled. Set
low for normal operation. 7 kΩ internal pull-up to VCCT.
11 MODSET Modulation Current Adjust. Connect a resistor between this pin and ground to set laser modulation current.
12 BIASMON Bias output current monitor. Terminate with a resistor to ground to set the desired full-scale voltage at maximum
bias current. Some internal functions can be muxed to this pin via the configuration logic. See configuration logic
table for more detail.
13 TxPwrMON Transmit power monitor. Provides a 1:1 mirror of the monitor photodiode current. Terminate with a resistor to
ground to set the desired full-scale voltage at maximum photodiode current.
14 APCSET A resistor connected from this pin to ground sets laser output power.
15 IPIN Monitor photodiode input. Connect this input to the monitor photodiode anode for automatic power control. The
monitor photodiode cathode should be connected to SVCC or VCC3T.
16 IBOUT Laser bias current output. Connect to laser cathode through a ferrite.
17 GNDO Ground for modulation output stage. Connect directly to ground or can connect to ground through an inductor.
Pin Definitions
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18 OUTP Transmitter positive modulation output. Draws current when DINp is high. Referenced to the SVCC (transmitter
regulator output) voltage.
19 OUTN Transmitter negative modulation output. Draws current when DINp is low. Referenced to the SVCC (transmitter
regulator output) voltage.
20 SVCC Internal power supply switch for laser. Provides redundant shutdown during a disable or fault condition.
21 VCC3T Internally regulated voltage for laser driver circuitry in 5V applications. Connect directly to supply to allow wider
power supply tolerance in 3.3V-only applications (internal regulator not in use). Do not connect to power supply
if VCC = 5V.
22 CAPC A capacitor at this pin sets the dominant pole for automatic power control. Connect a capacitor between this pin
and VCC3 if automatic power control is used. Can leave floating if using open loop configuration.
23 STSET Loss of signal threshold setting input. Connect a resistor between this pin and VCC3R to set loss of signal or
signal detect threshold.
24 VCC3R Internally regulated voltage for limiting amplifier circuitry in 5V applications. Connect directly to supply to allow
wider power supply tolerance in 3.3V-only applications (internal regulator not in use). Do not connect to power
supply if VCC = 5V.
25 RxINp Non-inverting limiting amplifier data input. Internally terminated with 2 kΩ to self-bias voltage of approximately
VCC3R - 0.5V.
26 RxINm Inverting limiting amplifier data input. Internally terminated with 2 kΩ to self-bias voltage of approximately
VCC3R - 0.5V.
27 Config1
Configuration logic input. These pins select laser driver and limiting amplifier configurations and test modes.
Refer to Configuration Logic table (Table 4-3) for more information. Three level logic where nominal level is mid-
range (VCC3T / 2) when floating.
28 Config2
29 Config3
30 Config4
31 LOS-ST Limiting amplifier LOS or ST (signal detect) output. Configuration logic selects whether output is to be LOS or ST.
5V compatible when using a 5V supply.
32 IREF Internal reference current. Must be connected to ground through a 12.4 kΩ 1% resistor.
Table 2-1. M02095/6 Pin Descriptions (2 of 2)
QFN Pin
Number Pin Name Function
Pin Definitions
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Figure 2-1. M02095/6 Package Pin-out (5x5mm MLF)
GND
RxINp
RxINm
Config1
Config2
Config3
Config4
LOS-ST
I
REF
C
APC
V
CC
3T
APC
SET
Tx Pwr
MON
BIAS
MON
MOD
SET
DIS
FAIL
RxOUTm
RxOUTp
V
CC
R
V
CC
T
TC
SLOPE
TC
START
DINp
DINm
V
CC
3R
ST
SET
SV
CC
OUTN
OUTP
GNDO
IB
OUT
I
PIN
1
2
3
4
5
7
6
8
12
1110
916151413
20
19
18
17
24
23
22
21
28 27 26 2532 31 30 29
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3.0 Functional Description
3.1 Overview
The M02095/6 devices are a highly integrated combined laser driver and limiting amplifier intended for applications
to 2.5 Gbps, depending on device type. The parts can be operated from a single 3.3V or 5V supply.
Many features are user-adjustable, including the APC loop bias control (via a monitor photodiode), modulation
current, temperature compensation control of modulation current, loss of signal threshold, using jam or not on the
Rx path and the Rx and Tx polarity.
Safety circuitry is also included to provide a latched shut-down of laser bias and modulation current if a fault
condition occurs. An internal VCC switch provides redundant shutdown of the laser current under a fault condition.
Figure 3-1. M02095/6 Block Diagram
V
CC
3T
SV
CC
OUT+
OUT-
GND
0
IPIN
IB
OUT
Input
Buffer
D
IN
-
D
IN
+
TX
Disable
FAIL
DIS
RESET
V
CC
T
GND
BIAS_Mon
TxPwrMon
3.3V Regulator
with Bypass
To Safety
Logic
To Safety
Logic
V
CC
V
CC3
Laser
Driver
MODSET
APCSET
Laser Power Control
BIAS
MON
TxPwr
MON
Threshold
Setting
Circuit
Biasing
RxOUTp
Regulator
RxOUTm
RSSI
LOS-ST
RxINm
Iref
RxINp
V
CC
RSTSET
Offset Cancel
DCR_Disable
Limiting
Amplifier
SCB
Safety
Circuitry with
Latched Fault
Output
Buffer
Tx_Polarity
Rx_Polarity
CONFIG_2
Tx_Polarity
Rx_Polarity
CONFIG_3
CONFIG_1
DCR_Disable
C
APC
TC
SLOPE
TC
START
LOS-to-JAM
CONFIG_4
LOS-to-JAM
LOS-ST_sel
LOS-ST_sel
Vttr
Analog
MUX
LOS
Level
Detect
Comparator
V
CC
3R
Configuration
Logic
Modulation
Control
2kΩ
2kΩ
4kΩ
4kΩ
Vttx
Output
Buffer
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3.2 General Description
The M02095 and M02096 integrate a laser driver and limiting amplifier in one highly configurable device for
applications to 1.25 Gbps and 2.5 Gbps respectively. The Tx and Rx paths are independently operated and
configurable using four three state configuration inputs allowing more than 80 user variations.
The laser driver supplies the bias and modulation current required to drive an edge emitting laser and incorporates
automatic power control, a power supply switch for redundant shutdown during a fault, user settable temperature
compensation of modulation current and SFP compliant safety circuitry. The limiting amplifier includes user
settable input signal level detection circuit and a fully integrated DC-offset cancellation loop that does not require
any external components.
Using the configuration logic, the limiting amplifier output can be jammed when loss of signal occurs and polarity
control is available for both the driver and limiting amplifier data paths. Finally, using an internal self selecting
regulator, the devices can operate from either a 3.3V or 5V supply with no changes to its configuration.
3.2.1 Internal Regulator
The M02095/96 contain an internal 3.3V regulator so high bit rate performance can be achieved with either a 5V or
3.3V power supply.
When operating from a 5V supply (VCC connected to +5V), an internal regulator provides a voltage of
approximately 3.3V to the majority of the on-chip circuitry. The on-chip regulator is internally compensated,
requiring no external components. When a 3.3V supply is used (VCC connected to 3.3V, or both VCC and VCC3
connected to 3.3V), internal logic configures the device for 3.3V operation and the regulator is switched to a low-
resistance mode. The device decides whether or not the internal regulator is enabled using internal sensing logic,
the sensing logic also determines whether the device safety circuitry needs to monitor for proper +5V supply
voltage.
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3.2.2 Configuration Logic
The four configuration pins allow the user to select over 80 configurations for the M02095/96. Each input has three
states: tied high, tied low or floating. When floating, the respective configuration pin internally is brought to
~VCC3T/2 and this is decoded separately from either a high or low state. See Figure 3-2.
Table 3-1. M02095/6 Configuration Logic Selections
Function Function
DIS/EN: The laser driver DIS pin is either active high “Tx_Disable” or active high “Tx_Enable”. Note that the DIS pin has an active
high pull-up regardless of its function.
SCB Safety Circuit Bypass. If SCB is selected, a Tx Fault condition will not be latched and the safety circuitry will not disable the
bias and modulation outputs. Fail will be asserted only while the fault is present.
LOS/ST Defines the limiting amplifier LOS-ST pin as either ST (goes high with signal detect) or LOS (goes high with LOS).
LOS=JAM / NO_JAM When “LOS=Jam” the limiting amplifier outputs are jammed when a loss of signal occurs. This is separate from whether
the LOS/ST pin is defined to be either LOS or ST.
TxPOL Defines the relationship between DIN+ and OUT+ in the Tx path.
RxPOL Defines the relationship between RxINp and RxOUTp in the Rx path.
Special Config Enables multiple specific configurations modes for the user. See Table 4-4 in Section 4.4 of this datasheet.
Figure 3-2. Configuration Pin Input
180Ω
~60 kΩ
V
CC
3T
V
CC
~60 kΩ
CONFIG_X
Functional Description
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3.3 Laser Driver Description
3.3.1 Driver Inputs
Inputs to the laser driver data buffer are self-biased through 4 kΩ resistors to an internal reference of approximately
VCC3T - 1.3V (Figure 3-3). (VCC3T is the internally regulated voltage for laser driver circuitry in 5V applications or is
the bypassed regulator output in 3.3V applications). Both CML and PECL input signals can be AC coupled to the
M02095/6.
In most applications the data inputs are AC coupled with controlled impedance pcb traces which will need to be
terminated externally with a 100Ω resistor between the DIN+ and DIN- inputs. AC coupling is recommended when
using the internal regulator (VCC = 5V), though external level-shifting may be used if DC coupling is desired with a
5V supply.
It is possible to invert the polarity of the driver inputs using the configuration logic (Ta bl e 4 - 3 ).
3.3.2 Driver Output Stage
The laser driver output stage (Figure 3-4) incorporates feedback to maintain performance over the range of laser
modulation current. The output stage is nominally configured to drive an approximate 25Ω output load. When DC
coupled, OUTP should be connected through a series resistor to the laser such that the total impedance seen at
the output is approximately 25Ω. This will result in the optimum pulse response while allowing the maximum
modulation current to be achieved.
The output can also be AC coupled to the laser. When AC coupled the dynamic resistance seen by OUTP should
still be 25Ω. In addition to a resistor in series with the laser, a capacitor is added in series and a ferrite is used to
pull up the collector at OUTP to VCC. When the laser is AC coupled, the OUTN pin is usually tied to the laser anode
through an AC coupled series resistor which matches the impedance seen by the OUTP pad. Laser modulation
current is controlled by adjusting current at MODSET (Figure 3-5).
Figure 3-3. Laser Driver Data Inputs
V
CC
3.75 kΩ
V
CC
3T - 1.3V
D
IN
Figure 3-4. Modulator Outputs
OUTP
80fF
0.75 nH OUTN
GNDO
(optional
external
inductance)
*
* Denotes bond
wire internal
inductance to
MLF package
0.75 nH
*
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The output stage also has a separate current path to GND labelled GNDO. This isolates the output switching
currents from the rest of the device.
3.3.3 Modulation Control
The modulation current amplitude is controlled by the MODSET input pin. The modulation current can be
temperature compensated by setting slope through the TCSLOPE pin and TCSTART (Figure 3-6) sets the
temperature at which the temperature compensation begins to operate. The temperature compensation is
independent of the modulation current setting.
Figure 3-5. APCSET, MODSET and TCSLOPE Input
190 Ω
MODSET,
APCSET,
or
TCSLOPE
VCC VCC3T
+
-
1.28V
Figure 3-6. TCSTART Input
TC
START
V
CC
4.2 kΩ
3.2 kΩ
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3.3.4 Bias Current Generator (Figure 3-7) and Automatic Power Control
The M02095/6 include circuitry to automatically maintain laser average output power with use of a monitor
photodiode. The monitor photodiode cathode is connected to VCC3 (or SVCC) and the anode is connected to IPIN
(Figure 3-8). A feedback loop maintains the monitor photodiode current set by the current at APCSET (Figure 3-5).
The monitor diode photo current is mirrored and an equivalent current is sourced from TxPwrMON (Figure 3-9).
A capacitor between CAPC (Figure 3-10) and VCC3 sets the dominant pole for APC loop stability.
The bias generator also includes a bias current monitor (BIASMON, Figure 3-9), whose output current is typically
1/90th of the bias current.
Figure 3-7. IBIASOUT
IBIAS
OUT
V
CC
26 kΩ
14 kΩ
14 kΩ
V
CC
3T
Figure 3-8. IPIN Input
30 Ω
I
PIN
V
CC
Figure 3-9. TxPwrMON and BIASMON Outputs
190 Ω
TxPwrMON
or
BIASMON
VCC3T
30 Ω
190 Ω
VCC
Figure 3-10. CAPC Input
190 Ω
C
APC
V
CC
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3.3.5 Fail Output
The M02095/96 has an open collector FAIL alarm output (Figure 3-11) which is compatible with the TX_FAULT
signalling requirements of common plugable module standards.
The Fail output is 5V compatible whether the M02095/96 is using a 5V or 3.3V supply. It requires an external 4.7kΩ
to 10 kΩ pull-up resistor so if the M02095/96 loses power the pull-up will signal a fail condition. In a simple static
protection scheme used by other ICs the protection diodes would clamp the FAIL signal to ground when the chip
loses power.
3.3.6 Tx Disable Control
The DIS (Figure 3-12) pin is used to disable the transmit signal (both the modulation and bias current are disabled
when DIS = high or is floating).
Depending on the configuration logic settings (Ta bl e 4 - 3 ), the DIS pin can redefined as an enable (EN) pin. In this
case, both the modulation and bias current are enabled when EN = high or is floating).
The DIS input is compatible with TTL levels regardless of whether VCC = 5V or VCC = 3.3V. The external 4.7 kΩ to
10 kΩ pull-up resistor required by most interface standards is not needed because this pin has an internal 7 kΩ
resistor to VCC.
3.3.7 Safety Circuitry
Comparators at APCSET
, MODSET
, IBOUT
, IPIN, OUTP, and CAPC will assert the FAIL (Figure 3-12) output, indicating
that a fault condition has occurred (see Ta bl e 1 - 9 ). This condition is latched and requires DIS (Figure 3-11) to be
toggled or power cycling before reset occurs. SVCC is opened during a fault or disable condition.
By setting DIS high, the bias and modulation output currents are disabled. DIS will disable laser bias and
modulation current if left floating. DIS must be forced to a low state to enable the outputs. When safety circuit
bypass (SCB) mode is enabled, FAIL will indicate a fault condition but is not latched and the outputs will not be
disabled. Only the DIS pin will shutdown the outputs when in SCB mode.
Figure 3-11. FAIL Output
FAIL
Figure 3-12. DIS (or EN) Input
80 k Ω
DIS
7 kΩ
V
CC
3T
V
CC
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3.3.8 Current Monitors
Output monitors are provided for transmit power (TxPwrMON) bias (BIASMON) and modulation current (MODMON).
MODMON has limited availability through a configuration logic setting (Ta bl e 4 - 3 ) for the M02095/6. These monitors
source current and should either feed into a current-input ADC or terminated with a resistor to ground that sets the
desired full-scale voltage.
Figure 3-13. MODMON Output
190 Ω
MOD
MON
V
CC
V
CC
3T
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3.4 Limit Amp Description
3.4.1 Inputs
The data inputs are internally connected to VTTR via 2 kΩ resistors and generally need to be AC coupled. Referring
to Figure 3-14, the nominal VTTR voltage is 2.85V because of the internal resistor divider to VCC3R, which means
this is the DC potential on the data inputs. See the applications information section for further details on choosing
the AC-coupling capacitor.
It is possible to invert the polarity of the limit amp inputs using the configuration logic (Ta bl e 4 - 3 ).
3.4.2 DC Offset Compensation
The M02095/96 contains an internal DC autozero circuit that can remove the effect of DC offsets without using
external components. This circuit is configured such that the feedback is effective only at frequencies well below
the lowest frequency of interest. The low frequency cut off is typically 4 kHz.
It is possible to reduce the DC servo cutoff frequency using an external capacitor or to disable the servo loop
completely using the configuration logic (Ta bl e 4 - 3 ). This is described in more detail in the applications section.
Figure 3-14. CML Data Inputs
V
CC
3R
RxINp
V
CC
3R – 0.45V
2.25kΩ
RxINm
8. 8kΩ
1. 4kΩ
V
CC
2. 2 5kΩ
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3.4.3 CML Outputs
The M02096 CML output configuration is shown in Figure 3-15. The outputs are internally terminated to VCC3R
through a 100Ω resistor and have a nominal amplitude of 260 mVPP
.
3.4.4 PECL Outputs
The M02095 features 100k/300k PECL swing compatible outputs as shown in Figure 3-16 that are referenced to
VCC3R. The outputs may be terminated using any standard AC or DC-coupling PECL termination technique. AC-
coupling is used in applications where the average DC content of the data is zero e.g. SONET. The advantage of
this approach is lower power consumption, no susceptibility to DC drive and compatibility with non-PECL
interfaces.
Figure 3-15. CML Data Outputs (M02096)
RxOUTp
RxOUTm
I
TAIL
V
CC
3R
100 Ω100 Ω
V
CC
Figure 3-16. PECL Data Outputs (M02095)
V
CC
RxOUTp
RxOUTm
V
CC
3R
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3.4.5 Loss of Signal/Signal Detect (LOS-ST)
The M02095/96 features input signal level detection over an extended range. Using an external resistor between
pin STSET (Figure 3-18) and VCC3R the user can program the input signal threshold. This function can be
programmed using the configuration logic (Ta bl e 4 - 3 ) to either represent signal detect (ST) or loss of signal (LOS).
For a given RST resistor setting, the difference between the ST and LOS threshold is a fixed hysteresis. The signal
detect status is indicated on the LOS-ST output pin shown in Figure 3-17. LOS is active when the signal is below
the threshold value, ST is active when the signal is above the threshold value. The signal detection circuitry has the
equivalent of 4 dB electrical hysteresis.
3.4.6 JAM Function (“Squelch”) (Special Configuration Mode)
When enabled through the configuration logic (Ta bl e 4 - 3 ), when LOS is asserted (ST is deasserted) an internal
connection between LOS and the output buffer forces the data outputs to a logic “one” state. This ensures that no
data is propagated through the system. The loss of signal detection circuit can be used to automatically force the
data outputs to a high state when the input signal falls below the LOS threshold. The function is normally used to
allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the
data outputs toggling due to noise when there is no signal present.
Figure 3-17. LOS-ST Output
LOS-ST
V
CC
80 kΩ
Figure 3-18. STSet Input
V
CC
3R
ST
SET
R
ST
V
STSET
V
CC
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3.4.7 Peak to Peak Received Signal Strength Indicator (RSSIPP) (Special
Configuration Mode)
When enabled through the configuration logic (Ta bl e 4 - 3 ), the RSSIPP output voltage is made available on the
TxPwrMON output pin. the RSSI voltage is logarithmically proportional to the peak to peak level of the input signal.
It is not necessary to connect an external capacitor to this output.
3.4.8 Reference Current Generation
The M095/96 contains an accurate on-chip bias circuit that requires an external 12.4 kΩ 1% resistor, RREF
, from pin
IREF to ground to set the LOS-ST threshold voltage at STSET precisely.
Figure 3-19. RSSIPP Output (when configured by the Configuration Logic)
RSSI
PP
V
CC
3R
I(RSSI
PP
)
4 kΩ
V
CC
Figure 3-20. Reference Current Generation
LOS
V
SET
V
Det
BG_Ref
V
CC
3R
R
ST
R
REF
ST
SET
I
REF
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4.0 Applications Information
4.1 General
• 2.5 Gbps STM-16/OC-48 SDH/SONET (M02096)
• 1.06 and 2.12 Gbps Fibre Channel (M02095/6)
• 1.25 Gbps Ethernet (M02095/6)
• 1.25 Gbps SDH/SONET (M02095/6)
• 2.67 Gbps SDH/SONET with FEC (M02096)
• SDH/SONET 155 Mbps Transceivers
• FTTx and Media Converters
Figure 4-1. Application Diagram, Laser AC Coupled Example
V
CC
3T
SV
CC
OUT+
OUT-
GND
0
IPIN
IB
OUT
Input
Buffer
D
IN
-
D
IN
+
TX
Disable
FAIL
DIS
RESET
V
CC
T
GND
BIAS_Mon
TxPwrMon
3.3V Regulator
with Bypass
To Safety
Logic
To Safety
Logic
V
CC
V
CC3
Laser
Driver
MODSET
APCSET
Laser Power Control
BIAS
MON
Tx Pw r
MON
Threshold
Setting
Circuit
Biasing
RxOUTp
Regulator
RxOUTm
RSSI
LOS-ST
RxINm
Iref
RxINp
V
CC
RSTSET
Offset Cancel
DCR_Disable
Limiting
Amplifier
SCB
Safety
Circuitry with
Latched Fault
Output
Buffer
Tx_Polarity
Rx_Polarity
CONFIG_2 Tx_Polarity
Rx_Polarity
CONFIG_3
CONFIG_1
DCR_Disable
C
APC
TC
SLOPE
TC
START
LOS-to-JAM
CONFIG_4 LOS-to-JAM
LOS-ST_sel
LOS-ST_sel
Vttr
Analog
MUX
LOS
Level
Detect
Comparator
V
CC
3R
Configuration
Logic
Modulation
Control
2kΩ
2kΩ
4kΩ
4kΩ
Vttx
Output
Buffer
V
CC
3T
DeMux
Output
Configuration
Control
(V
CC
, GND
or Float)
V
CC
Photodiode
AC-Coupled
to TIA
M0201x
V
CC
3R
AC or DC Coupled
(as described in
Applications Information )
Clock Data
Recovery
Unit
V
CC
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4.2 Laser Driver Connections
4.2.1 Configuring the Laser Driver Output
The laser driver output configuration needs to be optimized for the device type and configuration. Figure 4-2 shows
a typical schematic of the laser driver connections for both AC and DC coupling. Ta b l e 4 - 1 provides the
recommended starting component values for the two configurations.
Figure 4-2. Laser Driver Output and Typical Component Values
Table 4-1. Suggested Starting Component Values for Laser Driver Connections
Component AC Coupled Laser DC Coupled Laser
R88 0Ωopen
L1, 2 10 µH open
FB3, 4 Ferrite (1) open
FB1, 2, 8 Ferrite (1) Ferrite (1)
R89, 90 100 nF 0Ω
R92 (2) 68Ω68Ω
C45 (2) 2.7 pF 2.7 pF
R87 25Ω25Ω
R91 20Ω20Ω
CAPC
GND0
IBOUT
IPIN
OUTN
OUTP
RXINM
RXINP
STSET
SVCC
VCC3R
VCC3T
2
2
KPD
KLD
APD
TOSA
/ALD
3.3V2_T
100MA
FB8
IPIN_B
1
2
3
JP2
DNI
100MA
FB4
DNI
100MA
FB3
R87
0
1
2
3
LD1
DNI
DNI
0.001UF
C46
100MA
FB2
20
R91
100MA
FB1
68
R92
2.7PF
C45
24.9
R90
R89
0
DNI
10UH
L2
DNI
10UH
L1
DNI
R88
0
FB7
0
22
17
16
15
19
18
26
25
23
20
24
21
SVCC_B
OUTP_B
OUTN_B
IBOUT_B
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4.2.2 Modulation Control
There are programmable control lines for controlling the modulation current and its temperature compensation.
These inputs can be programmed simply with a resistor to ground.
The modulation current amplitude is controlled by the MODSET input pin. The modulation current is temperature
compensated by the TCSLOPE inputs. The temperature compensation is independent of the setting.
If the temperature compensation at TCSLOPE is disabled, the modulation output current is:
IMOD = 110 x (1.25V / RMODSET)
Where RMODSET is the resistance from pin MODSET to ground.
4.2.2.1 Setting Modulation Temperature Compensation
Temperature compensation involves setting two parameters: the temperature at which the compensation starts
TCSTART (°C) and the slope TCSLOPE (% compensation / °C).
Figure 4-3 graphically illustrates the selection of the resistor at the TCSTART pin (RTCSTART). For example, to have
the temperature compensation start at 30°C, chose RTCSTART = 15 kΩ. With TCSTART floating, the start
temperature defaults to ~0°C.
The percent change per degree C is set by the selection of RTCSLOPE at the TCSLOPE pin. The range varies from 0
to one percent of modulation current change per degree C. Note that the starting modulation current is the that set
by RMODSET when the temperature is below that of RTCSTART
. Figure 4-4 illustrates the behavior of the output
modulation current as the temperature increases for a range of resistors at the TCSLOPE pin. This is the most
accurate method for selecting RTCSLOPE.
However, you can also select RTCSLOPE using the following relationship:
RTCSLOPE = 19.5*(TC)-1.5, where TC is the desired slope of the modulation current from 25°C to 85°C in “%/°C”
and RTCSLOPE is in kΩ. If no temperature compensation is desired, leave RTCSLOPE open.
In any case, RTCSLOPE will have negligible effect at M02095/6 ambient temperatures below the TCSTART
temperature. For example:
Given a laser with a desired modulation current at low temperatures of 30mA and a temperature coefficient of -
0.5%/°C at high temperatures (which will require a laser driver temperature coefficient of +0.5%).
Choose RMODSET = 110 x (1.25V / 30mA) = 4.6 kΩ Choose RTCSLOPE =19.5*(0.5)-1.5 kΩ = 55 kΩ.
C46 open open
FB7 0Ω0Ω
NOTES:
1. Ferrite bead, 600Ω, 100 MHz, 100 mA typical. Similar to Murata BLM18HD601SN1.
2. C45 and R92 are compensation components for the laser TO can inductance. Actual values are
determined by experimentation but typically fall within 0 to 30 pF and 0 to 200Ω.
Table 4-1. Suggested Starting Component Values for Laser Driver Connections
Component AC Coupled Laser DC Coupled Laser
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Figure 4-3. Selecting RTCSTART for a Given Start Temperature
Figure 4-4. Effect of RTCSLOPE on IMOD vs. Temperature for RTCSTART = 25°C (25k
Ω
)
Temperature Compensation Start Temperature on the M02095/96
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0 102030405060708090
Desired Temperature Compensation Start Temperature (°C)
Rstart Value (k Ω)
M02095/M02096 Rslope Characteristics with Temperature
-20
-10
0
10
20
30
40
50
60
70
80
90
100
-40-30-20-100 102030405060708090
Ambient Temperature (°C)
Percent Change in Modulation Current
Relative to Programmed Start Temperature
24kΩ
30kΩ
39kΩ
51kΩ
62kΩ
91kΩ
150kΩ
300kΩ
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4.2.3 Setting Automatic Power Control
To maintain laser average output power the laser monitor photodiode cathode is connected to VCC3 (or SVCC) and
the anode is connected to IPIN. The current from the monitor photo diode mounted in the laser package is sunk at
IPIN. The APC loop adjusts the laser bias current so that the current into IPIN from the monitor photo diode equals
the current set at APCSET by the user selection of RAPCSET
.
RAPCSET = 1.25 V / IPIN
An internal feedback loop maintains the monitor photodiode current set by the current at APCSET
. The resulting
laser bias current is determined by the value of the external resistor RAPCSET (the external resistor connected
between the APCSET pin and ground) and the transfer efficiency between the laser and monitor photo diode.
The monitor diode photo current is mirrored and an equivalent current is sourced from TxPwrMON. TxPwrMON
can be connected directly to a current input ADC or through a resistor to ground. If this function is not needed this
pin can be left open.
A capacitor between CAPC and VCC3 sets the dominant pole for APC loop stability. The APC loop includes circuitry
allow for good t_on times, even with higher CAPC values. For example, a 47 nF capacitor can be used at CAPC,
providing a low-frequency cutoff typically around 1 kHz while still achieving a t_on < 1 ms. This makes it easy to
use the M02095/6 in low rate or multi-rate applications.
The bias current monitor (BIASMON) output current is typically 1/90th of the bias current. This pin can be connected
directly to a current input ADC or through a resistor to ground. If this function is not needed this pin can be left
open.
Open loop operation can also be achieved by connecting BIASMON to IPIN. The open loop bias current is set by
adjusting RAPCSET
. TxPwrMON effectively acts like a bias monitor (duplicate of BIASMON) in this configuration.
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4.3 Limiting Amplifier Connections
4.3.1 Reference Current Generation
The M02095/96 contain an accurate on-chip bias circuit that requires an external 12.4 kΩ 1% resistor, RREF
, from
pin IREF to ground to set the LOS threshold voltage at STSET precisely.
4.3.2 Input Matching and Choosing an Input AC-Coupling Capacitor
Depending on the intended data rate or data rates, the use of an 100Ω resistor in shunt across the limiting amplifier
inputs may be used to achieve good high frequency matching between the TIA output and the limiting amplifier
input. For applications above 1 Gbps, it is recommended that this resistor be used. The minimum value of AC
coupling between the TIA and limit amp depends on whether the limit amp input has this external shunt matching
resistance.
When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of
interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. For SONET
data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/(10,000) of the
input data rate. For Ethernet or Fibre Channel, there are less consecutive bits in the data, and the recommended
cut-off frequency is 1/(1,000) of the input data rate.
In all cases, a high quality coupling capacitor should be used as to pass undistorted the high frequency content of
the input data stream.
Figure 4-5. Reference Current Generation
LOS
V
SET
V
PP
_
LVL_Det
BG_Ref
V
CC
R
ST
R
REF
ST
SET
I
REF
12.4 kΩ
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4.3.2.1 Data Rates Greater than 1 Gbps
In this case a 100Ω resistor should be connected between RxINp and RxINm close to the limiting amplifier inputs to
achieve good match with properly designed 50Ω Zo transmission lines to the input. The value for the AC coupling
capacitor then depends on the actual datarate and whether the data is SONET or Ethernet/Fibre Channel based.
For example, for 2.5 Gbps SONET data, the coupling capacitor should be chosen as:
fCUTOFF ≤ (2.5x109 / 10x103) = 250x103
The -3 dB cutoff frequency of the low pass filter at the input is found as (assuming the TIA output is 50Ω single
ended):
f3dB = 1/ (2 π * 100Ω * CAC)
so solving for C where f3dB = fCUTOFF
CAC = 1/ (2 π * 100Ω * fCUTOFF) EQ.1
and in this case the minimum capacitor is 6.4 nF.
For 1.25 Gbps SONET data, the minimum capacitor is twice this or 12.8 nF.
In all cases, a capacitor larger than calculated above results in a lower cutoff frequency due to the ac coupling
between the TIA and the limiting amplifier inputs.
4.3.2.2 Applications below 1 Gbps
The M02095/96 limiting amplifier is ideally suited for low data rate operation because of its low DC servo cutoff
frequency and high input resistance. The low servo cutoff frequency improves low data rate performance in the
same way that having the AC coupling capacitor sized appropriately for the data rate and longest consecutive
string of ones or zeros. The high input resistance means that the AC coupling capacitor need not be nearly as large
as in the case of a device with a 50Ω input resistance. For 155 Mbps SONET data, the input coupling capacitor
needs to be large enough to pass 15 kHz (155x106/10,000) resulting in a minimum capacitor value of 5 nF and for
100 Mbps ethernet, the minimum capacitor is even smaller. In either case, a simple choice is the widely available
10 nF capacitor.
4.3.3 Setting the Signal Detect Level
Based on the configuration logic setting (see Ta bl e 4 - 3 ), the LOS-ST output is either configured to either go high
with signal detect (ST output) or to go high with the loss of signal (LOS). Figure 4-6 shows the relationship of the
LOS-ST output when defined as LOS across the range of RST resistors. When configured as an ST output, the
labels “Assert” and “Deassert” are interchanged. Ta bl e 4 - 2 lists the Assert and Deassert values for 1% resistors.
As shown in Figure 4-1, RST is connected between STSET and VCC3R. To minimize LOS-ST variation, it is
recommended that a 1% resistor be used for RST
. And as shown in Figure 4-5, the tolerance of the 12.4 kΩ resistor
at IREF also affects the LOS-ST accuracy.
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Table 4-2. Typical LOS Assert and De-assert Levels for Various 1% RST Resistor Values
RST (kΩ)
VIN (mVPP) differential
RST (kΩ)
VIN (mVPP) differential
LOS Assert/ST De-
Assert
LOS De-Assert/ST
Assert
LOS Assert/ST De-
Assert
LOS De-Assert/ST
Assert
6.04 62.0 93.0 7.15 20.0 30.2
6.19 52.6 79.1 7.32 17.4 26.2
6.34 44.6 68.1 7.50 14.4 22.4
6.49 37.3 58.8 7.68 11.9 19.3
6.65 31.6 49.6 7.87 10.0 16.2
6.81 27.2 42.0 8.06 8.2 13.6
6.98 23.6 35.6 8.25 (1) 6.9 11.3
NOTE:
1. M02095 Only.
Figure 4-6. Typical Loss of Signal Characteristic vs. RST (use 1% Resistor tolerance)
Typical Loss of Signal Characteristic
0
20
40
60
80
100
120
6.00 6.50 7.00 7.50 8.00
R
ST
(kΩ)
Threshold Level (mV
PP
)
DeAssert
A
ssert
M02096
maximum
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4.3.4 Using JAM
As shown in Figure 4-1, there is an optional internal connection between LOS and Jam. If this connection is
enabled via the configuration logic (), when LOS asserts the Jam function sets the data outputs to a fixed “one”
state (RxOUTp is held high and RxOUTm is held low). This is normally used to allow data to propagate only when
the signal is above the users' bit error rate (BER) requirement. It prevents the outputs from toggling due to noise
when no signal is present. The internal connection between LOS and Jam is independent of whether the LOS-ST
output is configured as a LOS output or an ST output.
4.3.5 PECL Output Termination (2095 Only)
The data outputs of the M02095 are PECL compatible and any standard AC or DC-coupling termination technique
can be used. Figure 4-7 and Figure 4-8 illustrate typical AC and DC terminations.
AC-coupling is used in applications where the limiting amplifier is connected to a non-PECL compatible load. In
addition to level shifting the signal to the common mode range of the load, the load receives the full PECL peak to
peak swing from the limiting amplifier.
DC-coupling can be used when driving PECL interfaces. In the case where the load does not contain PECL
termination, Figure 4-8 shows the proper termination for the M02095 PECL outputs. A Thevenin termination may
be substituted for the load when VCC-2V is not available and is shown in Figure 4-9.
Figure 4-7. Most Common AC-Coupled PECL Termination (Non-PECL load)
V
CC
M02095
RxOUTp
Z
o
= 50Ω
0.1µF
0.1µF
RxOUTm Z
o
150Ω150Ω
DeSerializer
100Ω
Z
o
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Figure 4-8. True PECL Termination (DC Coupled)
Figure 4-9. Thevenin Equivalent PECL Termination (DC Coupled)
V
CC
Z
o
Z
o
10 nF
V
CC
-2V
50Ω
50Ω
M02095
RxOUTp
RxOUTm
Z
o
= 50Ω
DeSerializer
V
CC
Z
o
Z
o
82Ω82Ω
M02095
RxOUTp
RxOUTm
Z
o
= 50Ω
DeSerializer
V
CC
130Ω
10 nF
130Ω
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4.4 M02095/6 Configuration Logic
Table 4-3. M02095/6 Configuration Logic
Config1 Config2 Config3 Config4 DIS/EN LOS=JAM/
NO_JAM LOS/ST SCB RxPOL TxPOL Special
Config.
0 0 0 0 0 0 0 0 0 0 none
0 0 0 M 0 0 0 0 0 1 none
0 0 M 0 0 0 0 0 1 0 none
0 0 M M 0 0 0 0 1 1 none
0 0 1 1 0 0 0 1 0 0 none
0 0 0 1 0 0 0 1 0 1 none
0 0 1 0 0 0 0 1 1 0 none
0 0 M 1 0 0 0 1 1 1 none
001M0 00000SC1
0 M 0 0 0 0 1 0 0 0 none
0 M 0 M 0 0 1 0 0 1 none
0 M M 0 0 0 1 0 1 0 none
0 M M M 0 0 1 0 1 1 none
0 M 1 1 0 0 1 1 0 0 none
0 M 0 1 0 0 1 1 0 1 none
0 M 1 0 0 0 1 1 1 0 none
0 M M 1 0 0 1 1 1 1 none
0M1M0 01000SC2
M 0 0 0 0 1 0 0 0 0 none
M 0 0 M 0 1 0 0 0 1 none
M 0 M 0 0 1 0 0 1 0 none
M 0 M M 0 1 0 0 1 1 none
M 0 1 1 0 1 0 1 0 0 none
M 0 0 1 0 1 0 1 0 1 none
M 0 1 0 0 1 0 1 1 0 none
M 0 M 1 0 1 0 1 1 1 none
M0 1M0 10000SC3
M M 0 0 0 1 1 0 0 0 none
M M 0 M 0 1 1 0 0 1 none
M M M 0 0 1 1 0 1 0 none
MMMM 0 1101 1none
M M 1 1 0 1 1 1 0 0 none
M M 0 1 0 1 1 1 0 1 none
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M M 1 0 0 1 1 1 1 0 none
M M M 1 0 1 1 1 1 1 none
MM 1 M 0 1100 0SC4
1 1 0 0 1 0 0 0 0 0 none
1 1 0 M 1 0 0 0 0 1 none
1 1 M 0 1 0 0 0 1 0 none
1 1 M M 1 0 0 0 1 1 none
1 1 1 1 1 0 0 1 0 0 none
1 1 0 1 1 0 0 1 0 1 none
1 1 1 0 1 0 0 1 1 0 none
1 1 M 1 1 0 0 1 1 1 none
111M1 00000SC5
0 1 0 0 1 0 1 0 0 0 none
0 1 0 M 1 0 1 0 0 1 none
0 1 M 0 1 0 1 0 1 0 none
0 1 M M 1 0 1 0 1 1 none
0 1 1 1 1 0 1 1 0 0 none
0 1 0 1 1 0 1 1 0 1 none
0 1 1 0 1 0 1 1 1 0 none
0 1 M 1 1 0 1 1 1 1 none
011M1 01000SC5
1 0 0 0 1 1 0 0 0 0 none
1 0 0 M 1 1 0 0 0 1 none
1 0 M 0 1 1 0 0 1 0 none
1 0 M M 1 1 0 0 1 1 none
1 0 1 1 1 1 0 1 0 0 none
1 0 0 1 1 1 0 1 0 1 none
1 0 1 0 1 1 0 1 1 0 none
1 0 M 1 1 1 0 1 1 1 none
101M1 10000SC6
M 1 0 0 1 1 1 0 0 0 none
1M0 0 1 11000SC7
M 1 0 M 1 1 1 0 0 1 none
1M0M1 11001SC8
M 1 M 0 1 1 1 0 1 0 none
Table 4-3. M02095/6 Configuration Logic
Config1 Config2 Config3 Config4 DIS/EN LOS=JAM/
NO_JAM LOS/ST SCB RxPOL TxPOL Special
Config.
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1MM0 1 11010SC9
M 1 M M 1 1 1 0 1 1 none
1 MMM 1 1101 1SC10
M 1 1 1 1 1 1 1 0 0 none
1M1 1 1 11100SC5
M 1 0 1 1 1 1 1 0 1 none
1M0 1 1 11101SC3
M 1 1 0 1 1 1 1 1 0 none
1 M 1 0 1 1 1 1 1 0 SC11
M 1 M 1 1 1 1 1 1 1 none
M 1 1 M 1 1 1 0 0 0 SC12
1 M M 1 1 1 1 1 1 1 SC13
1 M 1 M 1 1 1 0 0 0 SC14
KEY:
0, 1, M:0 = Logic low; 1 = Logic high; M = pin floating (pin goes to intermediate “mid-range” self-biased voltage
DIS/EN:0 = DIS pin acts as Tx_Disable; 1 = DIS pin becomes Tx_Enable
LOS=JAM / NO_JAM:0 = Jam outputs upon LOS; 1 = Do not jam outputs upon LOS
LOS/ST:0 = LOS-ST pin is ST (goes high with signal detect); 1 = LOS-ST pin is high with LOS
SCB:0=latched fault; 1=safety circuit bypass mode
TxPOL and RxPOL:0 = default polarity; 1 = inverted polarity
Special Config.:Refer to Special Configurations table for definition of special configuration modes
If Special Config = “none”, BIASMON, TxPwrMON and other functions operate as defined in the specification.
Table 4-3. M02095/6 Configuration Logic
Config1 Config2 Config3 Config4 DIS/EN LOS=JAM/
NO_JAM LOS/ST SCB RxPOL TxPOL Special
Config.
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Table 4-4. M02095/6 Special Configurations
Special
Config. #
Special Config.
Name Definition
SC1 Ignore_Ipin Safety logic ignores high/low faults on IPIN
SC2 Vdet-RSSI Vdet node in limiting amp is muxed to BIASMON; RSSIPP node of limiting amp is muxed to TxPwrMON
SC3 ModMon TxPwrMON output becomes MODMON output
SC4 Faultbits6 BIASMON output acts as fault status at VCCTHL; TxPwrMON output acts as fault status at VCCTHH
SC5 DCR_Filter
(CAZ)
The DC restore lowpass filter nodes are muxed to BIASMON and TxPwrMON; can add capacitance
between these nodes to reduce the LF cutoff of the limiting amplifier
SC6 Faultbits5 BIASMON output acts as fault status at VCC3THL; TxPwrMON output acts as fault status at VCC3THH
SC7 Faultbits1 BIASMON output acts as fault status at OUTP; TxPwrMON output acts as fault status at IBOUT
SC8 Faultbits2 BIASMON output acts as fault status at APCSET; TxPwrMON output acts as fault status at MODSET
SC9 Faultbits3 BIASMON output acts as fault status at CAPC; TxPwrMON is undefined status bit
SC10 Faultbits4 BIASMON output acts as fault status at Ipin_hi; TxPwrMON output acts as fault status at Ipin_lo
SC11 Test Mode 1 Internal Use Only; do not use
SC12 DCRDIS Disables the DC restore in the limiting amplifier. Can pass DC signal through limiting amp, but offset at
limiting amplifier input passes through to outputs.
SC13 Test Mode 2 Internal Use Only; do not use
SC14 Test Mode 3 Internal Use Only; do not use
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5.0 Package Specification
Figure 5-1. QFN32 Package Information
Note: View is for a 28 pin package. All dimensions in the
tables apply for the 32 pin package
3.30
3.30
3.45
3.45
3.15
3.15
0.70
0.90
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