The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD78F9328
8-BIT SINGLE-CHIP MICROCONTROLLER
Document No. U14411EJ1V0PM00 (1st edition)
Date Published November 1999 N CP(K)
Printed in Japan
PRELIMINARY PRODUCT INFORMATION
The
µ
PD78F9328 is a
µ
PD789327 Subseries (designed for remote controller with on-chip LCD) product in the
78K/0S Series, featuring expanded flash memory in place of the internal ROM of the
µ
PD789322, 789324, 789326,
and 789327.
Because flash memory allows the program to be written and erased with the device mounted on the target board,
this product is ideal for development trials, small-scale production, or for applications that require frequent upgrades.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µ
µµ
µ
PD789327, 789467 Subseries User’s Manual: To be prepared
78K/0S Series User’s Manual Instructions: U11047E
FEATURES
• Pin-compatible with mask ROM product (except VPP)
• Flash memory: 32 Kbytes
• Internal high-speed RAM: 512 bytes
• LCD display RAM: 24 bytes
• Variable minimum instruction execution time: High speed (0.4
µ
s: @5.0-MHz operation with main system clock),
low speed (1.6
µ
s: @5.0-MHz operation with main system clock), and ultra low speed (122
µ
s: @32.768-kHz
operation with subsystem clock)
• I/O ports: 21
• Serial interface (3-wire serial I/O mode): 1 channel
• LCD controller/driver
Segment signals: 24
Common signals: 4
• Timer: 4 channels
• Supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Remote-control devices, healthcare equipment, etc.
ORDERING INFORMATION
Part Number Package
µ
PD78F9328GB-8ET 52-pin plastic LQFP (10 mm × 10 mm)
Preliminary Product Information U14411EJ1V0PM00
2
µ
µµ
µ
PD78F9328
78K/0S SERIES LINEUP
The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products under development
Products in mass production
PD789014
42-/44-pin PD789014 with enhanced timer and expanded ROM, RAM
Small-scale, general-purpose applications
PD789146
PD789156
44-pin
RC oscillation version of the PD789197AY
PD789177 with on-chip EEPROM
TM
and SMB
78K/0S
Series
44-/48-pin
44-/48-pin
Small-scale, general-purpose applications + A/D
28-pin
44-pin PD789167 with enhanced A/D converter
PD789104A with enhanced timer
PD789124A with enhanced A/D converter
RC oscillation version of the PD789104A
PD789104A with enhanced A/D converter
PD789026 with added A/D, multiplier
On-chip UART. Capable of low-voltage (1.8 V) operation
PD789026
44-pin PD789046 PD789026 with internal subsystem clock
30-pin
30-pin
30-pin
30-pin
PD789124A
PD789134A
PD789
217AY
PD789
197AY
PD789177
PD789167
30-pin
30-pin
PD789104A
PD789114A
PD789104A with EEPROM
PD789146 with enhanced A/D converter
PD789427 with enhanced A/D converter
On-chip UART and dot LCD
80-pin
80-pin
LCD drive
88-pin
PD789447 with enhanced A/D converter
Inverter control
44-pin PD789842 On-chip inverter control circuit and UART
On-chip EEPROM, security circuit
5-pin PD789810
IC card
For keyless entry, on-chip POC and key return circuit
20-pin PD789860
PD789840 For key pad, on-chip POC
44-pin
ASSP
For PC keyboard, on-chip USB function
44-pin PD789800
20-pin PD789861 RC oscillation version of the PD789860
PD789457 with enhanced I/O
RC oscillation version of the PD789427
PD789447
PD789457
PD789437
PD789407A with enhanced A/D converter
PD789417A
PD789830
PD789407A
PD789427
PD789306
PD789316 PD789306 with A/D converter
RC oscillation version of the PD789306
Basic subseries for LCD drive
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
Preliminary Product Information U14411EJ1V0PM00 3
µ
µµ
µ
PD78F9328
The major functional differences among the subseries are listed below.
TimerFunction
Subseries Name
ROM
Capacity 8-Bit 16-Bit Watch WDT
8-Bit
A/D 10-Bit
A/D Serial Interface I/O VDD Min.
Value Remarks
µ
PD789046 16 K 1 ch
µ
PD789026 4 K to 16 K
1 ch 1 ch 34
Small-
scale,
general-
purpose
applications
µ
PD789014 2 K to 4 K 2 ch −
−
1 ch −−
1 ch (UART: 1 c h)
22
1.8 V −
µ
PD789217AY
RC oscillation
version,
on-chip
EEPROM
µ
PD789197AY
2 ch UART: 1ch
SMB : 1ch
On-chip
EEPROM
µ
PD789177
−8 ch
µ
PD789167
16 K to 24 K 3 ch 1 ch
8 ch −
31
−
µ
PD789156 −4 ch
µ
PD789146
8 K to 16 K
4 ch −
On-chip
EEPROM
µ
PD789134A −4 ch
µ
PD789124A
4 ch −
RC oscillation
version
µ
PD789114A
−4 ch
Small-
scale,
general-
purpose
applications
+ A/D
µ
PD789104A
2 K to 8 K
1 ch
1 ch
−
1 ch
4 ch −
1 ch (UART: 1 ch)
20
1.8 V
−
Inverter
control
µ
PD789842 8 K t o 16 K 3 ch Note 1 ch 1 ch 8 ch −1 ch (UART: 1 ch) 30 4.0 V −
µ
PD789830 24 K 1 ch −30 2.7 V
µ
PD789417A
−
7 ch 43 1.8 V
µ
PD789407A
12 K to 24 K 3 ch
7 ch −
1 ch (UART: 1 ch) −
µ
PD789457 −4 ch
µ
PD789447 4 ch −
RC oscillation
version
µ
PD789437 −4 ch
µ
PD789427
16 K to 24 K
4 ch
25
−
µ
PD789316 RC oscillation
version
LCD drive
µ
PD789306
8 K to 16 K
2 ch
1 ch 1 ch 1 ch
−
−
2 ch (UART: 1 ch)
23
−
µ
PD789800 −2 ch (USB: 1 ch) 31 4.0 V
µ
PD789840
8 K 1 ch
4 ch 1 ch 29 2.8 V
−
µ
PD789861 RC oscillation
version
ASSP
µ
PD789860
4 K
2 ch
−
−1 ch
−
−
−14 1.8 V
−
IC card
µ
PD789810 6 K −−−
1 ch −− − 1 2.7 V On-chip
EEPROM
Note 10-bit timer: 1 channel
Preliminary Product Information U14411EJ1V0PM00
4
µ
µµ
µ
PD78F9328
OVERVIEW OF FUNCTIONS
Item Description
Flash memory 32 Kbytes
High-speed RAM 512 bytes
Internal memory
LCD display RAM 24 bytes
Main system clock
(oscillati on f requency) Ceramic/ crystal resonat or (1.0 to 5.0 M Hz)
Subsystem clock
(oscillati on f requency) Cryst al res onator (32.768 kHz)
0.4
µ
s/1.6
µ
s (@5.0-MHz operation wit h m ai n system clock)Minimum i nstruction exec ution tim e
122
µ
s (@32.768-k Hz operation with subsystem clock)
General-purpose regis ters 8 bits × 8 regi sters
Instruction set •16-bit operati ons
• Bit m ani pul at i on (set, reset, test) etc.
I/O ports Total: 21
CMOS I/O: 21
Timers • 8-bit tim er: 2 channels
•Watch ti mer: 1 channel
• Watchdog ti mer: 1 channel
Timer outputs 1
Serial int erface 3-wire serial I/O mode: 1 channel
LCD controll e r/ driver • Segment signal outputs: 24
•Common signal outputs: 4
Maskabl e Internal: 6, External: 2Vectored i nterrupt
sources Non-maskable Internal: 1
Reset • Reset by RESET signal input
•Internal res et by watchdog tim er
• Reset v i a power-on-clear circuit
Supply v ol tage VDD = 1.8 to 5.5 V
Operating ambient temperat ure TA = −40 to +85°C
Package 52-pin plastic LQFP (10 mm × 10 m m )
Preliminary Product Information U14411EJ1V0PM00 5
µ
µµ
µ
PD78F9328
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................7
2. BLOCK DIAGRAM.................................................................................................................................8
3. PIN FUNCTIONS....................................................................................................................................9
3.1 Port Pins......................................................................................................................................... 9
3.2 Non-Port Pins .............................................................................................................................. 10
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins..........................................11
4. CPU ARCHITECTURE.........................................................................................................................13
4.1 Memory Space.............................................................................................................................13
4.2 Data Memory Addressing........................................................................................................... 14
4.3 Processor Registers ................................................................................................................... 15
4.3.1 Control registers...............................................................................................................................15
4.3.2 General-purpose registers................................................................................................................16
4.3.3 Special function registers (SFRs).....................................................................................................17
5. PERIPHERAL HARDWARE FUNCTIONS ......................................................................................... 19
5.1 Ports............................................................................................................................................. 19
5.1.1 Port functions....................................................................................................................................19
5.1.2 Port configuration .............................................................................................................................21
5.1.3 Port function control registers...........................................................................................................22
5.2 Clock Generator .......................................................................................................................... 25
5.2.1 Clock generator function...................................................................................................................25
5.2.2 Clock generator configuration...........................................................................................................25
5.2.3 Clock generator control registers......................................................................................................27
5.3 8-Bit Timer 30, 40 ........................................................................................................................ 30
5.3.1 Functions of 8-bit timer 30, 40..........................................................................................................30
5.3.2 Configuration of 8-bit timer 30, 40....................................................................................................31
5.3.3 8-bit timer 30, 40 control registers....................................................................................................36
5.4 Watch Timer................................................................................................................................. 40
5.4.1 Watch timer functions.......................................................................................................................40
5.4.2 Watch timer configuration.................................................................................................................41
5.4.3 Watch timer control register..............................................................................................................42
5.5 Watchdog Timer..........................................................................................................................43
5.5.1 Watchdog timer functions.................................................................................................................43
5.5.2 Watchdog timer configuration...........................................................................................................43
5.5.3 Watchdog timer control register........................................................................................................44
5.6 Serial Interface 10........................................................................................................................ 45
5.6.1 Functions of serial interface 10 ........................................................................................................45
5.6.2 Configuration of serial interface 10...................................................................................................45
5.6.3 Control register for serial interface 10 ..............................................................................................47
5.7 LCD Controller/Driver ................................................................................................................. 49
5.7.1 LCD controller/driver functions.........................................................................................................49
5.7.2 LCD controller/driver configuration...................................................................................................49
Preliminary Product Information U14411EJ1V0PM00
6
µ
µµ
µ
PD78F9328
5.7.3 LCD controller/driver control registers..............................................................................................52
6. INTERRUPT FUNCTION......................................................................................................................55
6.1 Interrupt Types ............................................................................................................................55
6.2 Interrupt Sources and Configuration ........................................................................................55
6.3 Interrupt Function Control Registers........................................................................................58
7. STANDBY FUNCTION.........................................................................................................................64
7.1 Standby Function........................................................................................................................64
7.2 Standby Function Control Register...........................................................................................66
8. RESET FUNCTION...............................................................................................................................67
8.1 Reset Function ............................................................................................................................67
8.2 Power Failure Detection Function.............................................................................................69
9. FLASH MEMORY PROGRAMMING...................................................................................................70
9.1 Selection of Communication Mode ...........................................................................................70
9.2 Flash Memory Programming Functions....................................................................................71
9.3 Flashpro III Connection Example...............................................................................................71
9.4 Setting Example Using Flashpro III (PG-FP3)...........................................................................72
10. INSTRUCTION SET OVERVIEW......................................................................................................73
10.1 Conventions...............................................................................................................................73
10.1.1 Operand formats and descriptions..................................................................................................73
10.1.2 Operation field definitions...............................................................................................................74
10.1.3 Flag operation field definitions........................................................................................................74
10.2 Operations..................................................................................................................................75
11. ELECTRICAL SPECIFICATIONS......................................................................................................80
APPENDIX A. DIFFERENCES BETWEEN
µ
µµ
µ
PD78F9328 AND MASK ROM VERSIONS................91
APPENDIX B. DEVELOPMENT TOOLS ................................................................................................92
APPENDIX C. RELATED DOCUMENTS................................................................................................94
Preliminary Product Information U14411EJ1V0PM00 7
µ
µµ
µ
PD78F9328
1. PIN CONFIGURATION (TOP VIEW)
52-pin plastic LQFP (10 mm ×
××
× 10 mm)
µ
µµ
µ
PD78F9328GB-8ET
RESET
P60/TO40
P43/KR03
P42/KR02
P41/KR01
P40/KR00
P03
P02
P01
P00
INT/P61
X1
X2
VDD
VSS
XT2
XT1
VPP
P20/SCK10
P21/SO10
P22/SI10
VLC0
52 51 50 49 48 47 46 45 44 43 42
14 15 16 17 18 19 20 21 21 23 24
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
31
30
29
P11
P10
P81/S21
P82/S20
P83/S19
P84/S18
P85/S17
S16
S15
S14
S13
S12
S11
S10
S9
COM0
COM1
COM2
COM3
S0
S1
S2
S3
S4
S5
S6
S7
S8
S23
P80/S22
12
13 28
27
41 40
25 26
Caution In normal operation mode, directly connect the VPP pin to VSS.
COM0 to COM3: Common Output RESET: Reset
INT: Interrupt from Peripherals S0 to S23: Segment Output
KR00 to KR03: Key Return SCK10: Serial Clock Input/Output
P00 to P03: Port 0 SI10: Serial Data Input
P10, P11: Port 1 SO10: Serial Data Output
P20 to P22: Port 2 VDD: Power Supply
P40 to P43: Port 4 VLC0: Power Supply for LCD
P60, P61: Port 6 VPP: Programming Power Supply
P80 to P85: Port 8 VSS: Ground
TO40: Timer Output X1, X2: Crystal (Main system clock)
XT1, XT2: Crystal (Sabsystem clock)
Preliminary Product Information U14411EJ1V0PM00
8
µ
µµ
µ
PD78F9328
2. BLOCK DIAGRAM
V
DD
V
SS
V
PP
78K/0S
CPU core Flash
memory
8-bit
timer 30 P00 to P03
Port 0
P10, P11
Port 1
P20 to P22
Port 2
P40 to P43
Port 4
P60, P61
Port 6
Watchdog timer
S0 to S23
COM0 to COM3
RAM RAM
space for
LCD data
8-bit
timer 40
Cascaded
16-bit
timer
Serial interface 10
SCK10/P20
SI10/P22
SO10/P21
V
LC0
LCD
controller/driver System control
RESET
X1
X2
XT1
XT2
Interrupt control KR00/P40 to
KR03/P43
INT/P61
P80 to P85
Port 8
Watch timer
TO40/P60
Power-on clear
Preliminary Product Information U14411EJ1V0PM00 9
µ
µµ
µ
PD78F9328
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name I/O Function After Reset Alternat e Function
P00 to P03 I/O Port 0.
This is a 4-bit I/O port.
Input/output can be specif i ed i n 1-bi t units .
When used as an input port, on-chip pull-up res i stors can be
specified for t he whol e port using pull-up resist or option
register 0 (PU0).
Input −
P10, P11 I/O Port 1.
This is a 2-bit I/O port.
Input/output can be specif i ed i n 1-bi t units .
When used as an input port, on-chip pull-up res i stors can be
specified for t he whol e port using pull-up resist or option
register 0 (PU0).
Input −
P20 SCK10
P21 SO10
P22
I/O Port 2.
This is a 3-bit I/O port.
Input/output can be specif i ed i n 1-bi t units .
When used as an input port, on-chip pull-up res i stors can be
specified in 1-bit uni ts usi ng pul l -up resist or option regis t er 2
(PUB2).
Input
SI10
P40 to P43 I/O Port 4.
This is a 4-bit I/O port.
Input/output can be specif i ed i n 1-bi t units .
When used as an input port, on-chip pull-up res i stors can be
specified for t he whol e port using pull-up resist or option
register 0 (PU0), or k ey return mode regi ster 00 (KRM00).
Input KR00 to KR03
P60 TO40
P61
I/O Port 6.
This is a 2-bit I/O port.
Input/output can be specif i ed i n 1-bi t units .
Input
INT
P80 to P85 I/O Port 8.
This is a 6-bit I/O port.
Input/output can be specif i ed i n 1-bi t units .
Low-level
output S22 to S17
Preliminary Product Information U14411EJ1V0PM00
10
µ
µµ
µ
PD78F9328
3.2 Non-Port Pins
Pin Name I/O Function After Reset Alternat e Function
INT Input External i nterrupt input for which t he valid edge (rising edge,
falling edge, or both ris i ng and falling edges) can be s pecified. Input P61
KR00 to KR03 Input Key ret urn signal det ec tion Input P40 to P43
TO40 Output 8-bit t i m er 40 output Input P60
SCK10 I/O Serial c l oc k input/ output of serial interface 10 Input P20
SI10 I nput Seri al dat a i nput of seri al i nterface 10 Input P22
SO10 Output Serial data output of serial interface 10 Input P21
S0 to S16 −
S17 to S22 P85 to P80
S23
Output LCD control l er/driver s egm ent signal out puts Low-level
output
−
COM0 to COM3 Output LCD controller/dri ver comm on s i gnal outputs Low-level
output −
VLC0 −LCD drive vo l tage −−
X1 Input −−
X2 −
Connecting crystal resonat or for main system clock oscillation
−−
XT1 Input −−
XT2 −
Connecting crystal resonat or for subsystem clock oscillation
−−
RESET Input System reset input Input −
VDD −Posit i ve power supply −−
VSS −Ground potential −−
VPP −Flash memory programming mode setting.
High-volt age appl i cation f or program wri te/veri fy.
In normal operat i on m ode, connect direct l y to VSS.
−−
Preliminary Product Information U14411EJ1V0PM00 11
µ
µµ
µ
PD78F9328
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins is shown in Table 3-1.
For the input/output circuit configuration of each type, refer to Figure 3-1.
Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name I/O Circuit Ty pe I/O Recommend Connec tion of Unus ed Pins
P00 to P03
P10, P11
5-A
P20/SCK10 8-A
P21/SO10 5-A
P22/SI10
P40/KR00 t o P43/KR03
8-A
P60/TO40 5
P61/INT 8
P80/S22 to P85/S 17 17-G
I/O Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
S0 to S16, S23 17-D
COM0 to COM3 18-B
Output
VLC0 −
Leave open.
XT1 Input Connect to VSS.
XT2
−
−Leave open.
RESET 2 Input −
VPP −−
Connect directly to VSS.
Figure 3-1. I/O Circuit Type (1/2)
Type 2 Type 5
Schmitt-triggered input with hysteresis characteristics.
IN
P-ch
IN/OUT
Data
Output
disable
Input
enable
V
DD
N-ch
V
SS
Preliminary Product Information U14411EJ1V0PM00
12
µ
µµ
µ
PD78F9328
Figure 3-1. I/O Circuit Type (2/2)
Type 5-A Type 8
Pull-up
enable
V
DD
P-ch
P-ch
IN/OUT
Data
Output
disable
Input
enable
V
DD
N-ch
V
SS
Data
V
DD
P-ch
Output
disable
IN/OUT
N-ch
V
SS
Type 8-A Type 17-D
Pull-up
enable
V
DD
P-ch
Data
V
DD
P-ch
Output
disable
IN/OUT
N-ch
V
SS
P-ch
N-ch
P-ch
N-ch
N-ch
N-ch
data OUT
VLC0
VLC3
SEG
VLC2
P-ch
P-ch
VSS
Type 17-G Type 18-B
P-ch
N-ch
P-ch
N-ch
N-ch
N-ch
data
V
LC0
VLC1
SEG
VLC2
P-ch
P-ch
V
SS
P-ch
IN/OUT
Data
Output
disable
Input
enable
VDD
N-ch
VSS
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch P-ch
N-ch
data
P-ch N-ch
V
LC1
V
LC0
V
LC2
OUT
COM
V
SS
Remark VLC1: VLC0 × 2/3, VLC2: VLC0/3
Preliminary Product Information U14411EJ1V0PM00 13
µ
µµ
µ
PD78F9328
4. CPU ARCHITECTURE
4.1 Memory Space
The
µ
PD78F9328 is provided with 64 Kbytes of accessible memory space. Figure 4-1 shows the memory map.
Figure 4-1. Memory Map
8 0 0 0 H
7 F F F H
Special function registers
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
LCD display RAM
24 × 8 bits
F F F F H
F F 0 0 H
F E F F H
F D 0 0 H
F C F F H
0 0 0 0 H
Program
memory space
Data memory
space
7 F F F H
0 0 0 0 H
Program area
0 0 8 0 H
0 0 7 F H
Program area
0 0 4 0 H
0 0 3 F H
CALLT table area
Reserved
0 0 1 4 H
0 0 1 3 H
Vector table area
Flash memory
32 K × 8 bits
F A 1 8 H
F A 1 7 H
F A 0 0 H
F 9 F F H
Reserved
Preliminary Product Information U14411EJ1V0PM00
14
µ
µµ
µ
PD78F9328
4.2 Data Memory Addressing
The
µ
PD78F9328 is provided with a variety of addressing modes to improve the operability of the memory. In the
area that incorporates data memory (FD00H to FFFFH) in particular, specific addressing modes that correspond to
the particular functions of an area, such as the special function registers (SFRs), are available. Figure 4-2 shows the
data memory addressing modes.
Figure 4-2. Data Memory Addressing Modes
Special function registers (SFRs)
256 × 8 bits
Internal high-speed RAM
512 × 8 bits
LCD display RAM
24 × 8 bits
Flash memory
32 K × 8 bits
F F F F H
8 0 0 0 H
7 F F F H
0 0 0 0 H
Direct addressing
Register indirect
addressing
Based addressing
F F 0 0 H
F E F F H
F F 2 0 H
F F 1 F H
F E 2 0 H
F E 1 F H
SFR addressing
Short direct
addressing
F D 0 0 H
F C F F H
F A 1 8 H
F A 1 7 H
Reserved
F A 0 0 H
F 9 F F H
Reserved
Preliminary Product Information U14411EJ1V0PM00 15
µ
µµ
µ
PD78F9328
4.3 Processor Registers
4.3.1 Control registers
(1) Program counter (PC)
The PC is a 16-bit register that holds the address information of the next program to be executed.
Figure 4-3. Program Counter Configuration
015
PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The PSW is an 8-bit register that indicates the status of the CPU according to the results of instruction execution.
Figure 4-4. Program Status Word Configuration
IE Z 0 AC 0 0 1 CY
70
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgement of the CPU.
(b) Zero flag (Z)
This flag is set (1) if the result of an operation is zero; otherwise it is reset (0).
(c) Auxiliary carry flag (AC)
AC is set (1) if the result of the operation has a carry from bit 3 or a borrow at bit 3; otherwise it is reset (0).
(d) Carry flag (CY)
CY is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or
add instruction.
(3) Stack pointer (SP)
The SP is a 16-bit register that holds the start address of the stack area. Only the internal RAM area (FD00H to
FEFFH) can be specified as the stack area.
Figure 4-5. Stack Pointer Configuration
015
SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Caution RESET input makes the SP contents undefined, so be sure to initialize the SP before instruction
execution.
Preliminary Product Information U14411EJ1V0PM00
16
µ
µµ
µ
PD78F9328
4.3.2 General-purpose registers
The
µ
PD78F9328 has eight 8-bit general-purpose registers (X, A, C, B, E, D, L, and H).
These registers can be used either singly as 8-bit registers or in pairs as 16-bit registers (AX, BC, DE, and HL),
and can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names
(R0 to R7 and RP0 to RP3).
Figure 4-6. General-Purpose Register Configuration
(a) Absolute register names
R7
R6
R5
R4
R3
R2
R1
R0
8-bit processing
70
RP3
RP2
RP1
RP0
16-bit processing
15 0
(b) Functional register names
H
L
D
E
B
C
A
X
8-bit processing
70
HL
DE
BC
AX
16-bit processing
15 0
Preliminary Product Information U14411EJ1V0PM00 17
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PD78F9328
4.3.3 Special function registers (SFRs)
Special function registers are used as peripheral hardware mode registers and control registers, and are mapped
in the 256-byte space from FF00H to FFFFH.
Note that the bit number of a bit name that is a reserved word in the RA78K0S and defined under the header file
“sfrbit.h” in the CC78K0S appears enclosed in a circle in the register formats. Refer to the register formats in 5.
PERIPHERAL HARDWARE FUNCTIONS.
Table 4-1. Special Function Registers (1/2)
Bit Unit for Mani pul at i onAddress Special Func tion Regis t er (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF00H Port 0 P0 √√−
FF01H Port 1 P1 √√−
FF02H Port 2 P2 √√−
FF03H port 4 P4 √√−
FF05H Port 6 P6 √√−
FF08H Port 8 P8 √√−
00H
FF20H Port mode regi ster 0 PM0 √√−
FF21H Port mode regi ster 1 PM1 √√−
FF22H Port mode regi ster 2 PM2 √√−
FF24H Port mode regi ster 4 PM4 √√−
FF26H Port mode regi ster 6 PM6 √√−
FF28H Port mode regi ster 8 PM8 √√−
FFH
FF32H Pull-up res i s tor option regi s ter B2 P UB 2 √√−
FF4AH Watch ti m er m ode control register WTM √√−
FF58H Port func tion regist er 8 PF8
R/W
√√−
00H
FF63H 8-bit com pare regi ster 30 CR30 W −√−
Undefined
FF64H 8-bit tim er c ounter 30 TM30 R −√−
FF65H 8-bit ti m er m ode control register 30 TMC30 R/ W √√−
00H
FF66H 8-bit com pare regi ster 40 CR40 −√−
FF67H 8-bit H wi dth compare regi ster 40 CRH40
W
−√−
Undefined
FF68H 8-bit tim er c ounter 40 TM40 R −√−
FF69H 8-bit ti m er m ode control register 40 TMC40 R/ W √√−
FF6AH Carrier generator output control register 40 TCA40 W √√−
FF72H Serial operat i on m ode regi ster 10 CSIM10 √√−
00H
FF74H Transmis sion/rec eption shi f t regist er 10 SIO10 √√−
Undefined
FFB0H LCD display mode regist er 0 LCDM0 √√−
FFB2H LCD clock c ontrol regis ter 0 LCDC0 √√−
00H
FFDDH Power-on-clear regis ter 1 POCF1
R/W
√√−
00HNote
Note This value is 04H only after a power-on-clear reset.
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
Table 4-1. Special Function Registers (2/2)
Bit Unit for Mani pul at i onAddress Special Func tion Regis t er (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FFE0H Interrupt request flag regis ter 0 IF0 √√−
00H
FFE4H Interrupt mas k flag regis ter 0 MK0 √√−
FFH
FFECH E xternal interrupt mode register 0 INTM0 −√−
FFF0H Subclock os c illation mode register SCKM √√−
FFF2H Subclock control regist er CSS √√−
FFF5H Key return mode regist er 00 KRM00 √√−
FFF7H Pull-up resistor option register 0 PU0 √√−
FFF9H Watchdog timer mode regis ter WDTM √√−
00H
FFFAH Oscillation stabilization time selection register OSTS −√−
04H
FFFBH Processor clock control register PCC
R/W
√√−
02H
Preliminary Product Information U14411EJ1V0PM00 19
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PD78F9328
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 Ports
5.1.1 Port functions
Various kinds of control operations are possible using the ports provided in the
µ
PD78F9328. These ports are
illustrated in Figure 5-1 and their functions are listed in Table 5-1.
A number of alternate functions are also provided, except for those ports functioning as digital I/O ports. Refer to
3. PIN FUNCTIONS for details of the alternate function pins.
Figure 5-1. Ports
P40 P00
P03
Port 0
Port 1
P10
Port 4
P43
P11
Port 2
P20
P22
Port 6 P60
P61
P80
Port 8
P85
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
Table 5-1. Port Functions
Port Name Pin Name Function
Port 0 P00 to P03 Thi s is an I /O port for whi ch input and out put can be specifi ed i n 1-bi t uni ts.
When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up
resistor option register 0 (PU0).
Port 1 P10, P11 This i s an I/O port for whic h i nput and output can be speci fied in 1-bit uni ts.
When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up
resistor option register 0 (PU0).
Port 2 P20 to P22 Thi s is an I /O port for whi ch input and out put can be specifi ed i n 1-bi t uni ts.
When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up
resistor option regi ster B 2 (P UB2).
Port 4 P40 to P43 Thi s is an I /O port for whi ch input and out put can be specifi ed i n 1-bi t uni ts.
When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up
resistor option register 0 (PU0), or key return mode regis t er 00 (KRM00).
Port 6 P60, P61 This i s an I/O port for whic h i nput and output can be speci fied in 1-bit uni ts.
Port 8 P80 to P85 Thi s is an I /O port for whi ch input and out put can be specifi ed i n 1-bi t uni ts.
Preliminary Product Information U14411EJ1V0PM00 21
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PD78F9328
5.1.2 Port configuration
The ports consist of the following hardware.
Table 5-2. Port Configuration
Item Configuration
Control regis t ers Port mode regi s ters (PM m: m = 0 t o 2, 4, 6, 8)
Pull-up resi stor opti on regi sters (P U0, PUB2)
Port function register 8 (PF8)
Ports Total: 21 (CMOS I/O: 21)
Pull-up resi stors Total: 13 (software control: 13)
Figure 5-2. Basic Configuration of CMOS Port
WR
PUm
PU×
WR
PORTm
WR
PORTm
WR
PMm
Output latch
Pmn
PMmn
V
DD
P-ch
Pmn
Internal bus
Selector
Caution Figure 5-2 shows the basic configuration of a CMOS I/O port. This configuration differs
depending on the functions of alternate function pins. Also, an on-chip pull-up resistor can be
connected to port 4 by means of a setting in key return mode register 00 (KRM00).
Remark PU×: Pull-up resistor option register (× = 0, B2)
PMmn: Bit n of port mode register m (m = 0 to 2, 4, 6, 8 n = 0 to 5)
Pmn: Bit n of port m
RD: Port read signal
WR: Port write signal
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
5.1.3 Port function control registers
The ports are controlled by the following three types of registers.
•Port mode registers (PM0 to PM2, PM4, PM6, PM8)
•Pull-up resistor option registers (PU0, PUB2)
•Port function register 8 (PF8)
(1) Port mode registers (PM0 to PM2, PM4, PM6, PM8)
Input and output can be specified in 1-bit units.
These registers can be set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When using the port pins as their alternate functions, set the output latch as shown in Table 5-3.
Caution Because P61 functions alternately as an external interrupt input, when the output level
changes after the output mode of the port function is specified, the interrupt request flag will
be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before
using the port in output mode.
Figure 5-3. Port Mode Register Format
Symbol76543210AddressAfter resetR/W
PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W
PM1111111PM11PM10FF21HFFHR/W
PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R/W
PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W
PM6111111PM61PM60FF26HFFHR/W
PM8 1 1 PM85 PM84 PM83 PM82 PM81 PM80 FF28H FFH R/W
PMmn Pmn pin input/output mode selec tion
(m = 0 to 2, 4, 6, 8 n = 0 to 5)
0 Output mode (output buffer on)
1 Input mode (out put buffer off)
Preliminary Product Information U14411EJ1V0PM00 23
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PD78F9328
Table 5-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions
Alternat e FunctionPin Name
Name I/O
PM×× P××
Input 1 ×
P20 SCK10
Output 0 1
P21 SO10 Output 0 1
P22 SI10 Input 1 ×
P40 to P43 KR00 to KR03 Input 1 ×
P60 TO40 Output 0 0
P61 INT Input 1 ×
P80 to P85 S22 to S17Note Output ××
Note When using P80 to P85 pins as S22 to S17, set port function register 8 (PF8) to 3FH.
Remark ×: don’t care
PM××: Port mode register
P××: Port output latch
(2) Pull-up resistor option register 0 (PU0)
This register sets whether to use on-chip pull-up resistors for ports 0, 1, and 4 on a port by port basis. An on-
chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-
chip pull-up resistor has been specified using PU0.
For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of
PU0. This also applies to alternate-function pins used as output pins.
PU0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-4. Format of Pull-Up Resistor Option Register 0
Symbol 7 6 5 <4> 3 2 <1> <0> Address After reset R/ W
PU0 0 0 0 PU04 0 0 PU01 PU00 FFF7H 00H R/W
PU0m Port m on-c hi p pul l -up resist or selection
(m = 0, 1, 4)
0 An on-chip pul l -up res i stor is not connec t ed
1 An on-chip pul l -up res i stor is connect ed
Caution Always set bits 2, 3, and 5 to 7 to 0.
Preliminary Product Information U14411EJ1V0PM00
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µ
PD78F9328
(3) Pull-up resistor option register B2 (PUB2)
This register sets whether to use on-chip pull-up resistors for P20 to P22 in bit units. An on-chip pull-up
resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up
resistor has been specified using PUB2.
For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of
PUB2. This also applies to alternate-function pins used as output pins.
PUB2 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-5. Format of Pull-Up Resistor Option Register B2
Symbol 7 6 5 4 3 <2> <1> <0> Address Aft er reset R/W
PUB2 0 0 0 0 0 PUB22 PUB21 PUB20 FF32H 00H R/W
PUB2n P2n on-chip pul l -up res i stor sel ection
(n = 0 to 2)
0 An on-chip pul l -up res i stor is not connec t ed
1 An on-chip pul l -up res i stor is connect ed
Caution Always set bits 3 to 7 to 0.
(4) Port function register 8 (PF8)
This register sets the port function of port 8 in 1-bit units.
The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according
to the setting of PF8.
PF8 can be set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-6. Format of Port Function Register 8
Symbol76543210AddressAfter resetR/W
PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W
PF8n P8n port function (n = 0 t o 5)
0 Operates as a general -purpose port
1 Operates as an LCD segment s i gnal output
Preliminary Product Information U14411EJ1V0PM00 25
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PD78F9328
5.2 Clock Generator
5.2.1 Clock generator function
The clock generator generates the clock pulse to be supplied to the CPU and peripheral hardware.
There are two types of system clock oscillators:
•Main system clock oscillator (ceramic/crystal resonator)
This circuit generates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP
instruction or by means of a processor clock control register (PCC) setting.
•Subsystem clock oscillator
This circuit generates a frequency of 32.768 kHz. Oscillation can be stopped using the subclock oscillation
mode register (SCKM).
5.2.2 Clock generator configuration
The clock generator consists of the following hardware.
Table 5-4. Clock Generator Configuration
Item Configuration
Control regis ters Processor clock cont rol regi ster (PCC)
Subclock oscillat i on mode register (SCK M)
Subcloc k cont rol regi s ter (CSS)
Oscillators Main system clock oscillator
Subsystem clock oscillator
Preliminary Product Information U14411EJ1V0PM00
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µ
µµ
µ
PD78F9328
Figure 5-7. Clock Generator Block Diagram
Subsystem
clock
oscillatior
f
XT
X1
X2
XT1
XT2
Main system
clock
oscillator
f
X
f
X
2
2
f
XT
2
1/2
Prescaler
Watch timer
LCD controller/driver
Clock to peripheral hardware
CPU clock
(f
CPU
)
Standby
control
circuit
Wait
control
circuit
Selector
STOP MCC PCC1 CLS CSS0
Internal bus
Subclock oscillation mode
register (SCKM)
FRC SCC
Internal bus
Subclock control
register (CSS)
Processor clock control
register (PCC)
Preliminary Product Information U14411EJ1V0PM00 27
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PD78F9328
5.2.3 Clock generator control registers
The clock generator is controlled by the following three registers.
•Processor clock control register (PCC)
•Subclock oscillation mode register (SCKM)
•Subclock control register (CSS)
(1) Processor clock control register (PCC)
This register is used to select the CPU clock and set the frequency division ratio.
PCC is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 02H.
Figure 5-8. Format of Processor Clock Control Register
Symbol <7> 6 5 4 3 2 1 0 Address After res et R/W
PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R/W
MCC Main system clock oscillator operation c ontrol
0 Operation enabled
1 Operation stopped
CSS0 PCC1 CPU clock (fCPU) selectionNote Minimum i nstruction exec ution time: 2fCPU
00f
X (0.2
µ
s) 0.4
µ
s
01
fX/22 (0.8
µ
s) 1.6
µ
s
1×f
XT/2 (61
µ
s) 122
µ
s
Note The CPU clock is selected by a combination of flag settings in the PCC and CSS registers. (Refer to
5.2.3 (3) Subclock control register (CSS).)
Cautions 1. Always set bits 0 and 2 to 6 to 0.
2. MCC can be set only when the subsystem clock is selected as the CPU clock. Setting
MCC to 1 while the main system clock is operating is invalid.
Remarks 1. f
X: Main system clock oscillation frequency
2. f
XT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
(2) Subclock oscillation mode register (SCKM)
This register is used to select a feedback resistor for the subsystem clock and control the oscillation of the
clock.
SCKM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-9. Format of Subclock Oscillation Mode Register
Symbol 7 6 5 4 3 2 1 <0> Address After reset R/ W
SCKM 0 0 0 0 0 0 FRC SCC FFF0H 00H R/W
FRC Feedback resist or select i on
0 An on-chip f eedback res i s tor is used
1 An on-chip f eedback res i s tor is not used
SCC Control of subsystem clock oscillator operation
0 Operation enabled
1 Operation stopped
Caution Always set bits 2 to 7 to 0.
Preliminary Product Information U14411EJ1V0PM00 29
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PD78F9328
(3) Subclock control register (CSS)
This register is used to specify whether the main system or subsystem clock oscillator is selected and to
indicate the operating status of the CPU clock.
CSS is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-10. Format of Subclock Control Register
Symbol76543210AddressAfter resetR/W
CSS 0 0 CLS CSS0 0 0 0 0 FFF2H 00H R/WNote
CLS CPU cloc k operating s tatus
0 Operating on the output of t he (di vided) main system clock
1 Operating on the output of the subsystem clock
CSS0 Selection of main system clock or subsystem clock oscillator
0 Main system clock oscillator (divided) output
1 Subsystem clock oscillator output
Note Bit 5 is read-only.
Caution Always set bits 0 to 3, 6, and 7 to 0.
Preliminary Product Information U14411EJ1V0PM00
30
µ
µµ
µ
PD78F9328
5.3 8-Bit Timer 30, 40
5.3.1 Functions of 8-bit timer 30, 40
The 8-bit timer in the
µ
PD78F9328 has 2 channels (timer 30 and timer 40). The operation modes in the following
table are possible by means of mode register settings.
Table 5-5. List of Modes
Channel
Mode
Timer 30 Timer 40
8-bit ti m er counter mode
(discret e mode) √√
16-bit ti m er counter mode
(casc ade connecti on m ode) √
Carrier generator mode √
PWM output m ode – √
(1) 8-bit timer counter mode (discrete mode)
The timer can be used for the following functions in this mode.
•8-bit resolution interval timer
•8-bit resolution square wave output (timer 40 only)
(2) 16-bit timer counter mode (cascade connection mode)
These timers can be used for 16-bit timer operations via a cascade connection.
The timer can be used for the following functions in this mode.
•16-bit resolution interval timer
•16-bit resolution square wave output
(3) Carrier generator mode
In this mode the carrier clock generated by timer 40 is output in the cycle set by timer 30.
(4) PWM output mode
In this mode, a pulse with an arbitrary duty ratio, which is set by timer 40, is output.
Preliminary Product Information U14411EJ1V0PM00 31
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PD78F9328
5.3.2 Configuration of 8-bit timer 30, 40
8-bit timers 30 and 40 consist of the following hardware.
Table 5-6. Configuration of 8-Bit Timer 30, 40
Item Configuration
Timer counter 8 bits × 2 (TM30, TM40)
Registers Compare regist ers : 8 bits × 3 (CR30, CR40, CRH40)
Timer outputs 1 (TO40)
Control regis t ers 8-bit ti m er m ode control register 30 (TMC30)
8-bit ti m er m ode control register 40 (TMC40)
Carrier generator output control regi s ter 40 (TCA40)
Port mode regi s ter 6 (PM6)
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
TCE30
TCL300
TMD300
TCL301
8-bit timer mode control registedr 30
(TMC30)
Selector
Decoder
Selector
Selector
8-bit compare register 30
(CR30)
8-bit timer counter 30
(TM30)
Selector
Internal reset signal
Timer 40 match signal
(in cascade connection mode)
Timer 30 match signal
(in cascade connection mode)
From Figure 5-12 (D)
Count operation start signal
(for cascade connection) INTTM30
f
X
/2
6
f
X
/2
8
Timer 40 interrupt request signal
(from Figure 5-12 (B))
Carrier clock (in carrier generator mode)
or timer 40 output signal
(in other than carrier generator mode)
(from Figure 5-12 (C))
Clear
Cascade connection mode
Match
From Figure 5-12 (E)
To Figure 5-12 (F)
To Figure 5-12 (G)
Figure 5-11. Block Diagram of Timer 30
Internal bus
OVF
Timer 30 match signal
(in carrier generator mode)
Bit 7 of TM40
(from Figure
5-12 (A))
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PD78F9328
TCE40
TCL402 TCL401 TCL400
TMD401
TMD400
TOE40
8-bit timer mode control
register 40 (TMC40)
Decoder
8-bit timer counter 40
(TM40)
F/F
TM30 match signal
(in cascade connection mode)
Count operation start signal to timer 30
(in cascade connection mode)
TM40 timer counter match signal
(in cascade connection mode)
Clear
f
X
f
X
/2
2
8-bit compare
register 40 (CR40)
Selector
Output control
circuit
Note
RMC40
NRZB40
NRZ40
Carrier generator output
control register 40 (TCA40)
To Figure 5-11 (D)
count clock input
signal to TM30
Internal reset signal
INTTM40
Bit 7 of TM40
(in cascade connection mode)
To Figure 5-11 (A)
To Figure 5-11 (F)
To Figure 5-11 (E)
Match TO40/P60
To Figure 5-11 (C)
Carrier clock (in carrier generator mode)
or timer 40 output signal
(in other than carrier generator mode)
Reset
Carrier generator mode
PWM mode
Cascade connection mode
Figure 5-12. Block Diagram of Timer 40
Note Refer to Figure 5-13 for details.
8-bit H width compare
register 40 (CRH40)
Internal bus
Selector
OVF
Prescaler
f
X
/2 f
X
/2
2
f
X
/2
3
f
X
/2
4
Timer 40 interrupt request signal
To Figure 5-11 (B)
Timer counter match signal from
timer 30 (in carrier generator mode)
From Figure 5-11 (G)
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
Figure 5-13. Block Diagram of Output Control Circuit (Timer 40)
F/F
RMC40 NRZ40
TOE40
PM60
P60
output latch
Selector
TO40/P60
Carrier generator mode
Carrier clock (in carrier generator mode)
or timer 40 output signal
(in other than carrier generator mode)
(1) 8-bit compare register 30 (CR30)
A value specified in CR30 is compared with the count value in 8-bit timer counter 30 (TM30), and if they
match, an interrupt request (INTTM30) is generated.
CR30 is set using an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution CR30 cannot be used in carrier generator mode or PWM output mode.
(2) 8-bit compare register 40 (CR40)
A value specified in CR40 is compared with the count value in 8-bit timer counter 40 (TM40), and if they
match, an interrupt request (INTTM40) is generated. When operating as a 16-bit timer in cascade
connection with TM30, an interrupt request (INTTM40) is only generated if both CR30 and TM30, and CR40
and TM40 match simultaneously (INTTM30 is not issued).
CR40 is set using an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
(3) 8-bit H width compare register (CRH40)
In carrier generator mode or PWM output mode, a timer output high-level width can be set by writing a value
to CRH40.
CRH40 is set using an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Preliminary Product Information U14411EJ1V0PM00 35
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PD78F9328
(4) 8-bit timer counter 30, 40 (TM30, TM40)
This is an 8-bit register for counting the count pulses.
TM30 and TM40 can be read with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to 00H.
The conditions under which TM30 and TM40 are cleared to 00H are listed below.
(a) Discrete mode
(i) TM30
•Upon a reset
•When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0
•Upon a match between TM30 and CR30
•If the TM30 count value overflows
(ii) TM40
•Upon a reset
•When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0
•Upon a match between TM40 and CR40
•If the TM40 count value overflows
(b) Cascade connection mode (TM30 and TM40 cleared to 00H simultaneously)
•Upon a reset
•When the TCE40 flag is cleared to 0
•Upon a simultaneous match between TM30 and CR30, and TM40 and CR40
•If the TM30 and TM40 count values overflow simultaneously
(c) Carrier generator/PWM output mode (TM40 only)
•Upon a reset
•When the TCE40 flag is cleared to 0
•Upon a match between TM40 and CR40
•Upon a match between TM40 and CRH40
•If the TM40 count value overflows
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PD78F9328
5.3.3 8-bit timer 30, 40 control registers
8-bit timers 30 and 40 are controlled by the following 4 registers.
•8-bit timer mode control register 30 (TMC30)
•8-bit timer mode control register 40 (TMC40)
•Carrier generator output control register 40 (TCA40)
•Port mode register 6 (PM6)
Preliminary Product Information U14411EJ1V0PM00 37
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µ
PD78F9328
(1) 8-bit timer mode control register 30 (TMC30)
This register is used to control the timer 30 count clock and operation mode settings.
TMC30 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-14. Format of 8-Bit Timer Mode Control Register 30
Symbol <7> 6 5 4 3 2 1 0 Address After res et R/W
TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 0 FF65H 00H R/W
TCE30 TM30 count c ont rol operationNote 1
0 TM30 count value cleared and operation st opped
1 Count operation s tarts
TCL301 TCL300 Timer 30 count clock s el ection
00
fX/26 (78.1 kHz)
01
fX/28(19.5 kHz)
1 0 Timer 40 match signal
1 1 Carrier cloc k (i n carrier generator m ode) or t i mer 40 output signal (in ot her than carrier generat or
mode)
TMD300 TMD401 TMD400 Timer 30, ti m er 40 operat i on mode selec tionNote 2
0 0 0 Disc rete mode
1 0 1 Cascade connecti on mode
0 1 1 Carrier generator m ode
0 1 0 PWM out put mode
Other than above Setti ng prohi bi ted
Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is
controlled by TCE40 (bit 7 of TMC40).
2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings.
Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count
clock.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz
Preliminary Product Information U14411EJ1V0PM00
38
µ
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µ
PD78F9328
(2) 8-bit timer mode control register 40 (TMC40)
This register is used to control the timer 40 count clock and operation mode settings.
TMC40 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-15. Format of 8-Bit Timer Mode Control Register 40
Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W
TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF69H 00H R/W
TCE40 TM40 count c ont rol operationNote 1
0 TM40 count value cleared and operation st opped (i n casc ade connecti on m ode, the count value of TM 30 i s
cleared at t he same ti m e)
1 Count operation s tarts (i n casc ade c onnection m ode, the count operation of TM 30 starts at the same tim e)
TCL402 TCL401 TCL400 Timer 40 count clock s el ection
000f
X (5 MHz)
001
fX/22 (1.25 MHz)
010f
X/2 (2.5 MH z)
011
fX/22 (1.25 MHz)
100
fX/23 (625 kHz)
101
fX/24 (313 kHz)
Other than above Setti ng prohi bi ted
TMD300 TMD401 TMD400 Timer 30, ti m er 40 operat i on mode selec tionNote 2
0 0 0 Disc rete mode
1 0 1 Cascade connecti on mode
0 1 1 Carrier generator m ode
0 1 0 PWM out put mode
Other than above Setti ng prohi bi ted
TOE40 Timer output control
0 Output disabled (port m ode)
1 Output enabled
Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is
controlled by TCE40 (bit 7 of TMC40).
2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz
Preliminary Product Information U14411EJ1V0PM00 39
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PD78F9328
(3) Carrier generator output control register 40 (TCA40)
This register is used to set the timer output data in the carrier generator mode.
TCA40 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-16. Format of Carrier Generator Output Control Register 40
Symbol76543<2><1><0>AddressAfter resetR/W
TCA4000000RMC40NRZB40NRZ40FF6AH00HW
RMC40 Remot e controll er out put control
0 When NRZ40 = 1, a carrier pul se is out put to the TO40/P60 pin
1 When NRZ40 = 1, a high lev el i s output to the TO40/P 60 pi n
NRZB40 This bit s t ores the data t hat NRZ40 will output nex t. Data is t ransferred to NRZ40 upon t he generat ion of a
timer 30 match si gnal .
NRZ40 No return, z ero data
0 A low lev el i s output (t he carrier cl ock is stopped)
1 A carrier pul se is out put
(4) Port mode register 6 (PM6)
This register is used to set port 6 to input or output in 1-bit units.
When the TO40/P60 pin is used as a timer output, set the PM60 and P60 output latches to 0.
PM6 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 5-17. Format of Port Mode Register 6
Symbol76543210AddressAfter resetR/W
PM6111111PM61PM60FF26HFFHR/W
PM6n Input/output mode of pi n P6n (n = 0, 1)
0 Output mode (output buffer on)
1 Input mode (output buff er off)
Preliminary Product Information U14411EJ1V0PM00
40
µ
µµ
µ
PD78F9328
5.4 Watch Timer
5.4.1 Watch timer functions
The watch timer has the following functions.
•Watch timer
•Interval timer
The watch and interval timers can be used at the same time.
Figure 5-18 shows a block diagram of the watch timer.
Figure 5-18. Watch Timer Block Diagram
f
X
/2
7
f
XT
Selector
f
W
f
W
2
4
f
W
2
5
f
W
2
6
f
W
2
7
f
W
2
8
f
W
2
9
Clear
9-bit prescaler
Selector
Clear
5-bit counter INTWT
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode control
register (WTM)
Internal bus
Preliminary Product Information U14411EJ1V0PM00 41
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PD78F9328
(1) Watch timer
An interrupt request (INTWT) is generated at 0.5-second intervals using the 4.19-MHz main system clock or
32.768-kHz subsystem clock.
Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-second
interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used
instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWTI) at preset intervals.
Table 5-7. Interval Time of Interval Timer
Interval Time At fX = 5.0 MHz Operat i on At f X = 4.19 MHz Operat i on At fXT = 32. 768 kHz Operati on
24 × 1/fW409.6
µ
s 488
µ
s 488
µ
s
25 × 1/fW819.2
µ
s 977
µ
s 977
µ
s
26 × 1/fW1.64 ms 1.95 ms 1.95 ms
27 × 1/fW3.28 ms 3.91 ms 3.91 ms
28 × 1/fW6.55 ms 7.81 ms 7.81 ms
29 × 1/fW13.1 ms 15.6 ms 15.6 ms
Remarks 1. f
W: Watch timer clock frequency (fX/27 or fXT)
2. f
X: Main system clock oscillation frequency
3. f
XT: Subsystem clock oscillation frequency
5.4.2 Watch timer configuration
The watch timer consists of the following hardware.
Table 5-8. Watch Timer Configuration
Item Configuration
Counter 5 bits × 1
Prescaler 9 bits × 1
Control regis t er Watc h timer mode control register (WTM)
Preliminary Product Information U14411EJ1V0PM00
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µ
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PD78F9328
5.4.3 Watch timer control register
The following register controls the watch timer.
•Watch timer mode control register (WTM)
(1) Watch timer mode control register (WTM)
This register is used to enable/disable the count clock and operation of the watch timer and set the interval
time of the prescaler and operation control of the 5-bit counter.
WTM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-19. Format of Watch Timer Mode Control Register
Symbol 7 6 5 4 3 2 <1> <0> Address Aft er reset R/W
WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R/W
WTM7 Watch tim er count cl ock (f W) selection
0fX/27(39.1 kHz)
1f
XT (32.768 kHz)
WTM6 WTM5 WTM4 Prescaler i nt erval tim e s el ec tion
000
24/fW
001
25/fW
010
26/fW
011
27/fW
100
28/fW
101
29/fW
Other than above Setti ng prohi bi ted
WTM1 5-bit count er operation cont rol
0 Cleared after operation s topped
1Start
WTM0 Watch tim er operat i on enabl e
0 Operati on stopped (both prescaler and t i m er cleared)
1 Operati on enabl ed
Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)
2. fX: Main system clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Preliminary Product Information U14411EJ1V0PM00 43
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PD78F9328
5.5 Watchdog Timer
5.5.1 Watchdog timer functions
The watchdog timer has the following functions.
(1) Watchdog timer
The watchdog timer is used to detect a program runaway. If a runaway is detected, either a non-maskable
interrupt or the RESET signal can be generated.
(2) Interval timer
The interval timer is used to generate interrupts at preset intervals.
5.5.2 Watchdog timer configuration
The watchdog timer consists of the following hardware.
Table 5-9. Watchdog Timer Configuration
Item Configuration
Control regis t er Watc hdog timer mode regi ster (WDTM)
Figure 5-20. Watchdog Timer Block Diagram
Internal bus
Internal bus
7-bit counter
Control circuit
Clear
WDTIF
WDTMK
Watchdog timer mode register
(WDTM)
WDTM4 WDTM3
INTWDT
maskable
interrupt request
RESET
INTWDT
non-maskable
interrupt request
f
X
2
4
RUN
Preliminary Product Information U14411EJ1V0PM00
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µ
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µ
PD78F9328
5.5.3 Watchdog timer control register
The watchdog timer is controlled by the following register.
•Watchdog timer mode register (WDTM)
(1) Watchdog timer mode register (WDTM)
This register is used to set the watchdog timer operation mode and whether to enable or disable counting.
WDTM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-21. Format of Watchdog Timer Mode Register
Symbol <7> 6 5 4 3 2 1 0 Addres s After reset R/W
WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W
RUN Watchdog ti mer operation s el ectionNote 1
0 Counting stopped
1 Counter c l eared and counting s tarts
WDTM4 WDTM3 Watc hdog timer operat i on m ode select i onNote 2
0 0 Operation st opped
01
Interval timer mode (when an overflow oc curs, a m askable interrupt is generated)Note 3
1 0 Watchdog ti m er m ode 1 (when an overflow oc curs, a non-m askable interrupt is generated)
1 1 Watchdog ti m er m ode 2 (when an overflow oc curs, a res et operation i s activated)
Notes 1. Once the RUN bit has been set (1), it is impossible to clear it (0) by software. Consequently, once
counting begins, it cannot be stopped by any means other than RESET input.
2. Once WDTM3 and WDTM4 have been set (1), it is impossible to clear them (0) by software.
3. The interval timer starts operating as soon as the RUN bit is set to 1.
Cautions 1. When the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time
will be up to 0.8% shorter than the time specified by the watchdog timer clock selection
register.
2. To use watchdog timer mode 1 or 2, be sure to set WDTM4 to 1 after confirming that
WDTIF (bit 0 of interrupt request flag 0 (IF0)) has been set to 0. If WDTIF is 1, selecting
watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant
rewriting ends.
Preliminary Product Information U14411EJ1V0PM00 45
µ
µµ
µ
PD78F9328
5.6 Serial Interface 10
5.6.1 Functions of serial interface 10
Serial interface 10 has the following two modes.
•Operation stopped mode
•3-wire serial I/O mode
(1) Operation stopped mode
This mode is used to minimize power consumption when serial transfer is not performed.
(2) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock line (SCK10) and two serial data lines
(SI10 and SO10).
As 3-wire serial I/O mode supports simultaneous transmission and reception, the time required for data
processing can be reduced.
In 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB,
allowing serial interface 10 to be connected to any device regardless of whether that device is designed for
MSB-first or LSB-first transmission.
3-wire serial I/O mode is effective for connecting peripheral I/O circuits and display controllers having
conventional clock synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices.
5.6.2 Configuration of serial interface 10
Serial interface 10 consists of the following hardware.
Table 5-10. Configuration of Serial Interface 10
Item Configuration
Register Transmis sion/rec eption shi f t regist er 10 (SIO10)
Control regis t er Serial operation mode regis ter 10 (CSIM 10)
(1) Transmission/reception shift register 10 (SIO10)
This is an 8-bit register used for parallel/serial data conversion and for serial transmission or reception in
synchronization with the serial clock.
SIO10 is set using an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Preliminary Product Information U14411EJ1V0PM00
46
µ
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µ
PD78F9328
Internal bus
SI10/P22
Serial operation mode register 10
(CSIM10)
CSIE10
TPS101
TPS100
DIR10
CSCK10
Transmission/reception shift
register 10 (SIO10)
SO10/P21
PM21
PM20
SCK10/P20
Serial clock counter Interrupt request
generator
Clock control
circuit
Selector
Selector
INTCSI10
F/F
TPS101 TPS100
f
X
/2
2
f
X
/2
3
Figure 5-22. Block Diagram of Serial Interface 10
Preliminary Product Information U14411EJ1V0PM00 47
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PD78F9328
5.6.3 Control register for serial interface 10
Serial interface 10 is controlled by the following register.
•Serial operation mode register 10 (CSIM10)
Figure 5-23. Format of Serial Operation Mode Register 10
Symbol <7> 6 5 4 3 2 1 0 Addres s After reset R/W
CSIM10 CSIE10 0 TPS101 TPS100 0 DIR10 CSCK10 0 FF72H 00H R/W
CSIE10 3-wire serial I/O mode operat i on control
0 Operation stopped
1 Operation enabled
TPS101 TP S100 Select i on of count clock when internal clock selected
00
fX/22 (1.25 MHz)
01
fX/23 (625 kHz)
Other than above Set t i ng prohi bi ted
DIR10 First-bit specification
0MSB
1LSB
CSCK10 SIO10 clock selection
0 External c l ock puls e i nput to the SCK10 pin
1 Internal clock s el ected wit h TP S100, TPS 101
Cautions 1. Bits 0, 3 and 6 must be fixed to 0.
2. Be sure to switch to operation mode after stopping the serial transmission/reception
operation.
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
Table 5-11. Operation Mode Settings for Serial Interface 10
(1) Operation stopped mode
First
Bit P22/SI10
Pin Function P21/SO10
Pin Function P20/SCK10
Pin Function
P22 P21 P20
CSIE10
0
CSIM10
DIR10
×
CSCK10
×
PM22
×
Note 1
P22
×
Note 1
PM21
×
Note 1
P21
×
Note 1
PM20
×
Note 1
P20
×
Note 1
Shift
Clock
Setting prohibitedOther than above
−−
(2) 3-wire serial I/O mode
First
Bit P22/SI10
Pin Function
P21/SO10
Pin Function P20/SCK10
Pin Function
MSB
LSB
SI10
Note 2
SO10
(CMOS output) SCK10 input
SCK10 output
SCK10 input
SCK10 output
CSIE10
1
CSIM10
DIR10
0
1
CSCK10
0
1
0
1
PM22
1
Note 2
P22
×
Note 2
PM21
0
P21
1
PM20
1
0
1
0
P20
×
1
×
1
Shift
Clock
External
clock
Internal
clock
External
clock
Internal
clock
Setting prohibitedOther than above
Notes 1. Can be used freely as a port
2. Can be used as P22 (CMOS I/O) only when transmitting
Remark ×: don’t care
Preliminary Product Information U14411EJ1V0PM00 49
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µ
PD78F9328
5.7 LCD Controller/Driver
5.7.1 LCD controller/driver functions
The LCD controller/driver incorporated in the
µ
PD78F9328 has the following features.
(1) Segment and common signals based on the automatic reading of the display data memory can be
automatically output
(2) Four types of frame frequencies are selectable
(3) 24 segment signal outputs (S0 to S23), 4 common signal outputs (COM0 to COM3)
(4) Operation with a subsystem clock is possible
The maximum number of displayable pixels is shown in Table 5-12 below.
Table 5-12. Maximum Number of Display Pixels
Bias M et hod Time Div i sion Com m on Signals Used Maximum Number of Display P i xels
1/3 4 COM0 to COM3 96 (24 segments × 4 commons)
Note The LCD panel of the figure consists of 12 rows with 2 segments per row.
5.7.2 LCD controller/driver configuration
The LCD controller/driver consists of the following hardware.
Table 5-13. Configuration of LCD Controller/Driver
Item Configuration
Display outputs Segment signals: 24
Common signal s: 4
Control regis ters LCD display mode regi ster 0 (LCDM0)
LCD clock cont rol regi ster 0 (LCDC0)
Port function register 8 (PF8)
Preliminary Product Information U14411EJ1V0PM00
50
µ
µµ
µ
PD78F9328
The correspondence with the LCD display RAM is shown in Figure 5-24 below.
Figure 5-24. Correspondence with LCD Display RAM
Address Bit Segment
76543210
FA17H 0 0 0 0 → S23
FA16H 0 0 0 0 → S22
FA15H 0 0 0 0 → S21
FA14H 0 0 0 0 → S20
FA13H 0 0 0 0 → S19
FA12H 0 0 0 0 → S18
FA11H 0 0 0 0 → S17
FA10H 0 0 0 0 → S16
FA0FH 0000 → S15
FA0EH 0000 → S14
FA0DH 0000 → S13
FA0CH 0000 → S12
FA0BH 0000 → S11
FA0AH 0000 → S10
FA09H 0 0 0 0 → S9
FA08H 0 0 0 0 → S8
FA07H 0 0 0 0 → S7
FA06H 0 0 0 0 → S6
FA05H 0 0 0 0 → S5
FA04H 0 0 0 0 → S4
FA03H 0 0 0 0 → S3
FA02H 0 0 0 0 → S2
FA01H 0 0 0 0 → S1
FA00H 0 0 0 0 → S0
Common ↑
COM3 ↑
COM2 ↑
COM1 ↑
COM0
Remark Bits 4 to 7 are fixed to 0.
Preliminary Product Information U14411EJ1V0PM00 51
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PD78F9328
Internal bus
LCDC03 LCDC02
LCDC01
LCDC00
2
2
Selector
Prescaker
LCD clock
selection
circuit
Selector
fCLK
26fCLK
27fCLK
28fCLK
29
LCD clock control register 0
(LCDC0)
LCDON0
VAON0
LCD display mode
register 0 (LCDM0)
LCD drive voltage control circuit
VLC0 VLC0
VLC0
Segment
driver
Common driver
COM0 COM1 COM2 COM3
3210
32106574
FA00H
Display data memory
LCDON0
Selector
Segment
driver
3210
32106574
FA16H
LCDON0
S22/P80
Timing
controller
fX/25
fX/26
fX/27
fXT
S0 . . . . .
. . . . . . . . . .
fCLK
1
32
3
VSS
RLCD RLCD RLCD
Selector
Segment
driver
3210
3210654
FA17H
LCDON0
S23
PF85 PF84 PF83 PF82 PF80
PF81
Port function
register 8 (PF8)
PF80
Selector
Segment
driver
3210
32106574
FA11H
LCDON0
S17/P85
PF85
. . .
. . . .
. . . . .
fLCD
LIPS0
Figure 5-25. LCD Controller/Driver Block Diagram
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PD78F9328
5.7.3 LCD controller/driver control registers
The LCD controller/driver is controlled by the following three registers.
•LCD display mode register 0 (LCDM0)
•LCD clock control register 0 (LCDC0)
•Port function register 8 (PF8)
(1) LCD display mode register 0 (LCDM0)
This register is used to enable/disable operation, and set the operation mode and the supply of power for LCD
drive.
LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-26. Format of LCD Display Mode Register 0
Symbol <7> <6> 5 <4> 3 2 1 0 Address After reset R/W
LCDM0 LCDON0 VAON0 0 LIPS0 0 0 0 0 FFB0H 00H R/W
LCDON0 LCD display enabl e/disabl e
0 Dis pl ay off (all segment outputs are unselect ed for signal output)
1 Dis pl ay on
VAON0 LCD controller/driver operation m odeNote
0 No internal booster (for 2.7- to 5.5-V display)
1 Int ernal booster enabled (f or 1.8- to 5.5-V display)
LIPS0 Supply of power f o r LCD dri veNote
0 Power not suppli ed for LCD drive
1 Power supplied f or LCD dri ve
Note To reduce power consumption when the LCD display is not being used, set VAON0 and LIPS0 to 0.
Cautions 1. Always set bits 0 to 3 and 5 to 0.
2. Always manipulate VAON0 after turning off the LCD display by setting LIPS0 and
LCDON0 to 0.
Preliminary Product Information U14411EJ1V0PM00 53
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PD78F9328
(2) L CD clock control register (LCDC0)
This register is used to set the internal and LCD clocks. The frame frequency is determined by the number of
LCD clock time divisions.
LCDC0 is set usi ng a 1-bit or 8-bit memory manipulat ion instruction.
RESET input sets this register to 00H.
Figure 5-27. Format of LCD Clock Control Register 0
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
LCDC0 0 0 0 0 LCDC03 LCDC02 LCDC01 LCDC00 FFB2H 00H R/W
LCDC03 LCDC02 Internal clock (fCLK) selectionNote
00f
XT (32.768 kHz)
01
fX/25(156.3 kHz)
10
fX/26(78.1 kHz)
11
fX/27(39.1 kHz)
LCDC01 LCDC00 LCD cloc k (fLCD) selection
00
fCLK/26
01
fCLK/27
10
fCLK/28
11
fCLK/29
Note Select fX so that a clock of at least 32 kHz is set for the internal clock fCLK.
Remarks 1. f
X: Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz
Caution Always set bits 4 to 7 to 0.
Examples of the frame frequencies when the internal clock is fXT (32.768 kHz) are shown in Table 5-14 below.
Table 5-14. Frame Frequency (Hz)
LCD Clock (fLCD)
Time Division fXT/29
(64 Hz) fXT/28
(128 Hz) fXT/27
(256 Hz) fXT/26
(512 Hz)
4 163264128
Preliminary Product Information U14411EJ1V0PM00
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µ
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µ
PD78F9328
(3) Port function register 8 (PF8)
This register is used to select whether S17/P85 to S22/P80 are used as LCD segment signal outputs or
general-purpose ports.
PF8 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-28. Format of Port Function Register 8
Symbol76543210AddressAfter resetR/W
PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W
PF8n Port f unction of P8n (n = 0 to 5)
0 Operates as a general-purpose port
1 Operates as an LCD segment signal output
Preliminary Product Information U14411EJ1V0PM00 55
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µ
PD78F9328
6. INTERRUPT FUNCTION
6.1 Interrupt Types
Two types of interrupts are supported.
(1) Non-maskable interrupts
Non-maskable interrupt requests are acknowledged unconditionally, i.e. even when interrupts are disabled.
These interrupts take precedence over all other interrupts and are not subject to interrupt priority control.
A non-maskable interrupt causes the generation of the standby release signal
An interrupt from the watchdog timer is the only non-maskable interrupt source supported in the
µ
PD78F9328.
(2) Maskable interrupts
Maskable interrupts are subject to mask control. If two or more maskable interrupts occur simultaneously, the
default priority listed in Table 6-1 applies.
A maskable interrupt causes the generation of the standby release signal.
Maskable interrupts from 2 external and 6 internal sources are supported in the
µ
PD78F9328.
6.2 Interrupt Sources and Configuration
The
µ
PD78F9328 supports a total of 9 maskable and non-maskable interrupt sources (see Table 6-1).
Preliminary Product Information U14411EJ1V0PM00
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µ
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µ
PD78F9328
Table 6-1. Interrupt Sources
Interrupt SourceInterrupt Type Default
PriorityNote 1 Name Trigger
Internal/
External Vector Table
Address Basic
Configuration
TypeNote 2
Non-maskable −INTWDT Watchdog ti m er overflow (with
watchdog ti mer mode 1 selected) (A)
0 I NTWDT Watc hdog timer ov erf l ow (wi th
interval t i mer mode selected)
Internal 0004H
(B)
1 I NTP0 Pin input edge det ection External 0006H (C)
2 I NTCSI10 End of seri al i nterface 10 3-wi re
SIO transfer reception 0008H
3 I NTWT Watch ti m er i nterrupt 000AH
4 I NTTM 30 Generation of 8-bit t i m er 30
matchi ng signal 000CH
5 I NTTM 40 Generation of 8-bit t i m er 40
matchi ng signal
Internal
000EH
(B)
6 I NTKR00 Key ret urn signal det ec tion Ext ernal 0010H (C)
Maskable
7 INTWTI Watch timer interval timer
interrupt Internal 0012H (B)
Notes 1. Default priority is the priority order when more than one maskable interrupt request is generated at the
same time. 0 is the highest priority and 7 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1.
Remark Only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be
selected.
Preliminary Product Information U14411EJ1V0PM00 57
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PD78F9328
Figure 6-1. Basic Configuration of Interrupt Function
(A) Internal non-maskable interrupt
Internal bus
Interrupt request Vector table
address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IF
Interrupt request
IE
Vector table
address generator
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, KRM00 MK
IF
IE
Vector table
address generator
Standby release signal
Edge
detection
circuit
Interrupt request
INTM0: External interrupt mode register 0
KRM00: Key return mode register 00
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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PD78F9328
6.3 Interrupt Function Control Registers
Interrupts are controlled by the following five registers.
•Interrupt request flag register 0 (IF0)
•Interrupt mask flag register 0 (MK0)
•External interrupt mode register 0 (INTM0)
•Program status word (PSW)
•Key return mode register 00 (KRM00)
Table 6-2 lists the interrupt requests and the corresponding interrupt request and interrupt mask flags.
Table 6-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Si gnal Interrupt Request Flag Interrupt Mask Fl ag
INTWDT
INTP0
INTCSI0
INTWT
INTTM30
INTTM40
INTKR00
INTWTI
WDTIF
PIF0
CSIIF0
WTIF
TMIF30
TMIF40
KRIF00
WTIIF
WDTMK
PMK0
CSIMK0
WTMK
TMMK30
TMMK40
KRMK00
WTIMK
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PD78F9328
(1) Interrupt request flag register 0 (IF0)
An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an
instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal
is input, or when an instruction is executed.
IF0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 6-2. Format of Interrupt Request Flag Register 0
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address Af ter reset R/W
IF0 WTIIF KRIF00 TMIF40 TMIF30 WTIF CSIIF0 PIF0 WDTIF FFE0H 00H R/W
××IF× Interrupt reques t flag
0 No interrupt request signal generat ed
1 An i nt errupt request signal is generated and an int errupt request made
Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an
interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer
mode 1 or 2.
2. Because P61 functions alternately as an external interrupt, when the output level
changes after the output mode of the port function is specified, the interrupt request flag
will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0)
before using the port in output mode.
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PD78F9328
(2) Interrupt mask flag register 0 (MK0)
Interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 6-3. Format of Interrupt Mask Flag Register 0
Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address Af ter reset R/W
MK0 WTIMK KRMK00 TMMK40 TMMK30 WTMK CSIMK0 PMK0 WDTMK FFE4H FFH R/W
××MK Interrupt servicing cont rol
0 Int errupt servi cing enabled
1 Int errupt servi cing dis abl ed
Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to
read the WDTMK flag results in an undefined value being detected.
2. Because P61 functions alternately as an external interrupt, when the output level
changes after the output mode of the port function is specified, the interrupt request flag
will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0)
before using the port in output mode.
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PD78F9328
(3) External interrupt mode register 0 (INTM0)
This register is used to specify the valid edge for INTP0.
INTM0 is set using an 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 6-4. Format of External Interrupt Mode Register 0
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
INTM0 0 0 0 0 ES01 ES00 0 0 FFECH 00H R/W
ES01 ES00 INTP0 valid edge sel ection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohi bi ted
1 1 Both rising and f alling edges
Cautions 1. Always set bits 0, 1, and 4 to 7 to 0.
2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts.
To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the interrupt
mask flag (PMK0).
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PD78F9328
(4) Program status word (PSW)
The program status word is used to hold the instruction execution results and the current status of the
interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.
The PSW can be read and written in 8-bit units, as well as in 1-bit units by using bit manipulation instructions
and dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically
saved to the stack, and the IE flag is reset (0).
RESET input sets the PSW to 02H.
Figure 6-5. Program Status Word Configuration
IE Z 0 AC 0 0 1 CYPSW
Symbol After reset
02H
76543210
Used in the execution of ordinary instructions
IE
0
1
Disabled
Enabled
Interrupt acknowledgement enable/disable
Preliminary Product Information U14411EJ1V0PM00 63
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PD78F9328
(5) Ke y return mode register 00 (KRM00)
This register is used to set the pin that is to detect the key return signal (rising edge of port 4).
KRM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 6-6. Format of Key Return Mode Register 00
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
KRM00 0 0 0 0 0 0 0 KRM000 FFF5H 00H R/W
KRM000 Key ret urn signal det ec tion cont rol
0 Key return si gnal not detected
1 Key return si gnal detected (port 4 falling edge detection)
Cautions 1. Always set bits 1 to 7 to 0.
2. Before setting KRM00, set (1) bit 6 (KRMK00) of MK0 to disable interrupts. To enable
interrupts, clear (0) KRMK00 after clearing (0) bit 6 (KRIF00) of IF0.
3. On-chip pull-up resistors are automatically connected in input mode to the pins specified
for key return signal detection (P40 to P43). Although these resistors are disconnected
when the mode changes to output, key return signal detection continues unchanged.
Figure 6-7. Block Diagram of Falling Edge Detection Circuit
Falling edge
detection circuit
KRMK00
KRIF00 setting signal
Standby release signal
Key return mode register 00
(KRM00)
Note
Selector
P40/KR00
P41/KR01
P42/KR02
P43/KR03
Note For selecting the pin to be used as falling edge input.
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PD78F9328
7. STANDBY FUNCTION
7.1 Standby Function
A standby function is incorporated to minimize the system’s power consumption. There are two standby modes:
HALT and STOP.
The HALT and STOP modes are selected using the HALT and STOP instructions.
(1) HALT mode
In this mode, the CPU operating clock is stopped. The average current consumption can be reduced by
intermittent operation combining this mode with the normal operation mode.
(2) STOP mode
In this mode, main system clock oscillation is stopped. All operations performed with the main system clock
are suspended, thus minimizing power consumption.
Caution When shifting to STOP mode, execute the STOP instruction after first stopping the operation
of the hardware.
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PD78F9328
Table 7-1. Operation Statuses in HALT Mode
HALT Mode Operati on S tatus Duri ng M ai n
System Cloc k Operation HALT Mode Operation Stat us During Subsystem
Clock Operation
Item
Subsystem Clock
Operating Subsystem Clock
Stopped Mai n Sys tem Cloc k
Operating Mai n S yst em Clock
Stopped
Main system clock Can be oscillated Oscillation stopped
CPU Operation stopped
Ports (output lat ches) Status before HA LT m ode setti ng retained
8-bit ti m er 30, 40 Operable Operation stopped
Watch ti mer Operable OperableNote 1 Operable OperableNote 2
Watchdog ti mer Operable Operation stopped
Power-on-clear c i rcuit Operabl e
Key return circui t Operable
Serial int erface 10 Operable OperableNote 3
LCD controll e r/ driver OperableNote 4 OperableNotes 1, 4 OperableNote 4 OperableNo t es 2, 4
External i nterrupts OperableNote 5
Notes 1. Operation is enabled when the main system clock is selected
2. Operation is enabled when the subsystem clock is selected
3. Operation is enabled only when an external clock is selected
4. The HALT instruction can be set after display instruction execution
5. Operation is enabled only for a maskable interrupt that is not masked
Table 7-2. Operation Statuses in STOP Mode
STOP Mode Operation St atus During Mai n System Cloc k OperationItem
Subsystem Clock Operating Subsystem Clock Stopped
Main system clock Oscillation stopped
CPU Operation stopped
Ports (output lat ches) Status before S T OP mode set ting retained
8-bit ti m er 30, 40 Operation st opped
Watch ti mer OperableNote 1 Operation stopped
Watchdog ti mer Operati on stopped
Power-on-clear c i rcuit Operabl e
Key return circui t Operable
Serial int erface 10 OperableNote 2
LCD controll e r/ driver OperableNote 1 Operation stopped
External i nterrupts OperableNote 3
Notes 1. Operation is enabled when the subsystem clock is selected.
2. Operation is enabled only when an external clock is selected.
3. Operation is enabled only for a maskable interrupt that is not masked
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PD78F9328
7.2 Standby Function Control Register
The oscillation stabilization time selection register (OSTS) is used to control the wait time from the time STOP
mode is released by an interrupt request until oscillation stabilizes.
OSTS is set using an 8-bit memory manipulation instruction.
RESET input sets this register to 04H. Note that the time required for oscillation to stabilize after RESET input will
be 215/fX, rather than 217/fX.
Figure 7-1. Format of Oscillation Stabilization Time Selection Register
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
000
212/fX(819
µ
s)
010
215/fX(6.55 ms)
100
217/fX(26.2 ms)
Other than above Setti ng prohi bi ted
Caution The wait time required after releasing STOP mode does not include the time (“a” in the following
figure) required for the clock oscillation to restart after STOP mode is released, regardless of
whether STOP mode is released by RESET input or interrupt.
STOP mode release
X1 pin voltage
waveform
V
SS
a
Remarks 1. f
X: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Preliminary Product Information U14411EJ1V0PM00 67
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PD78F9328
8. RESET FUNCTION
8.1 Reset Function
The
µ
PD78F9328 can be reset using the following three signals.
(1) External reset signal input via RESET pin
(2) Internal reset by watchdog timer runaway time detection
(3) Internal reset using power-on-clear circuit (POC)
The external and internal reset signals are functionally equivalent. When RESET is input, program execution
begins from the addresses written at addresses 0000H and 0001H.
If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each
item of the hardware to enter the states listed in Table 8-1. While a reset is being applied, or while the oscillation
frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state.
If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution begins
once the oscillation stabilization time (215/fX) has elapsed. A reset sequence caused by a watchdog timer overflow is
terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time
(215/fX).
Cautions 1. To use an external reset sequence, input a low-level signal to the RESET pin for at least 10
µ
µµ
µ
s.
2. When a reset is used to release STOP mode, the data of when STOP mode was entered is
retained during the reset sequence, except for the port pins, which are in the high-impedance
state.
Figure 8-1. Reset Function Block Diagram
RESET
Count clock
Reset control circuit
Watchdog timer
Stop
Over-
flow
Reset signal
Interrupt function
V
DD
Power-on-clear circuit
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PD78F9328
Table 8-1. Status of Hardware After Reset
Hardware Stat us After Reset
Program counter (PC)Note 1 Contents of reset
vect or t abl e (0000H,
0001H) set
Stack pointer (S P) Undefined
Program st atus word (PSW) 02H
Data memory UndefinedNote 2
RAM
General-purpose regis ters UndefinedNote 2
Ports (P0 to P2, P4, P6, P8) (output l atches) 00H
Port mode regi s ters (PM 0 to PM2, PM4, P M 6, PM8) FFH
Port function register 8 (PF8) 00H
Pull-up resi stor opti on regi sters (P U0, PUB2) 00H
Proces sor clock c ontrol regis ter (PCC) 02H
Subclock oscillat i on mode register (SCK M) 00H
Subcloc k cont rol regi s ter (CSS) 00H
Oscillation stabilization time selection register (OSTS) 04H
Timer counters (TM30, TM40) 00H
Compare registers (CR30, CR40, CRH40) Undefined
Mode control regi sters (TM C30, TMC40) 00H
8-bit ti m er 30, 40
Carrier generator output control regi s ter 00H
Watch ti mer Mode control regi ster (WTM) 00H
Watchdog ti mer Mode register (WDTM) 00H
Serial operati on mode regist er 10 (CS IM10) 00HSerial int erface 10
Transmis sion/rec eption shi f t regist er 10 (SIO10) Undefined
Display mode regis ter 0 (LCDM0) 00HLCD c ontroller/ dri ver
Clock control regi ster 0 (LCDC0) 00H
Power-on-clear c i rcuit P ower-on-clear regis t er 1 (POCF1) 00HNote 3
Request fl ag regi ster 0 (IF0) 00H
Mask f l ag regi s ter 0 (MK0) FFH
External i nterrupt mode regi s ter 0 (INTM0) 00H
Interrupts
Key return m ode regi ster 00 (KRM 00) 00H
Notes 1. While a reset signal is being input, and during the oscillation stabilization period, only the contents of
the PC will be undefined; the remainder of the hardware will be the same state as after reset.
2. In standby mode, RAM enters the hold state after reset.
3. The value is 04H only after a power-on-clear reset.
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PD78F9328
8.2 Power Failure Detection Function
When a reset is generated via the power-on-clear circuit, bit 2 (POCOF1) of the power-on-clear register (POCF1)
is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e. after
program execution has started from address 0000H), a power failure can be detected by detecting POCOF1.
Figure 8-2. Format of Power-on-Clear Register 1
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POCF1 0 0 0 0 0 POCOF1 0 0 FFDDH 00HNote R/W
POCOF1 Power-on-clear generat i on status detection
0 Power-on-clear not generat ed, or cleared by wri te operation
1 Power-on-clear reset generated
Note The value is 04H only after a power-on-clear reset.
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PD78F9328
9. FLASH MEMORY PROGRAMMING
The program memory incorporated in the
µ
PD78F9328 is flash memory.
Writing to flash memory can be performed with the device mounted in the target system (on-board programming).
Writing is performed with a dedicated flash memory programmer (Flashpro III (part number: FL-PR3 and PG-FP3))
connected to the host machine and the target system.
Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.
9.1 Selection of Communication Mode
Writing to flash memory is performed via serial communication using Flashpro III. Select one of the
communication modes from those in Table 9-1. The selection of the communication mode is made by using the
format shown in Figure 9-1. The communication mode is selected by the number of VPP pulses shown in Table 9-1.
Table 9-1. Communication Modes
Communication Mode Pin Used Number of VPP Pulses
3-wire serial I/O SCK10/P20
SO10/P21
SI10/P22
0
Caution Always select the communication mode using the number of pulses shown in Table 9-1.
Figure 9-1. Communication Mode Selection Format
10 V
V
SS
V
DD
V
PP
V
DD
V
SS
RESET
12 n
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PD78F9328
9.2 Flash Memory Programming Functions
Operations such as writing to flash memory are performed by various command/data transmission and reception
operations according to the selected communication mode. Table 9-2 shows the major functions of flash memory
programming.
Table 9-2. Major Functions of Flash Memory Programming
Function Description
Batch erase Deletes t he entire memory contents.
Batch blank check Checks the deletion status of the entire memory.
Data write Writes to flas h m em ory based on the wri te start address and the number of dat a to
be written (num ber of bytes ).
Batch verify Checks the entire memory contents and the input data.
9.3 Flashpro III Connection Example
An example of the connection between the
µ
PD78F9328 and Flashpro III is shown in Figure 9-2.
Figure 9-2. Connection of Flashpro III Using 3-Wire Serial I/O Mode
V
PP
n
Note
V
DD
RESET
SCK
SO
SI
GND
V
PP
V
DD
RESET
SCK10
CLK X1
SI10
SO10
V
SS
Flashpro III PD78F9328
µ
Note n = 1, 2
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PD78F9328
9.4 Setting Example Using Flashpro III (PG-FP3)
When using Flashpro III (PG-FP3) to write to flash memory, set as follows.
<1> Download the parameter file
<2> Select the serial mode and serial clock with the type command
<3> A setting example using the PG-FP3 is shown below
Table 9-3. Setting Example Using PG-FP3
Communication Mode Setti ng Example Using PG-FP 3 Number of V PP
PulsesNote
COMM PORT SIO-c h0
On Target BoardCPU CLK
In Flashpro
On Target Board 4.1943 MHz
SIO CLK 1.0 MHz
In Flashpro 4.0 MHz
3-wire serial I/O mode
SIO CLK 1.0 MHz
0
Note The number of VPP pulses supplied from Flashpro III during the initialization of serial communication. The
pins to be used in communication are determined by this number.
Remark COMM PORT: Selection of the serial port
SIO CLK: Selection of the serial clock frequency
CPU CLK: Selection of the input CPU clock source
Preliminary Product Information U14411EJ1V0PM00 73
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PD78F9328
10. INSTRUCTION SET OVERVIEW
The instruction set for the
µ
PD78F9328 is listed in this section.
10.1 Conventions
10.1.1 Operand formats and descriptions
The description made in the operand field of each instruction conforms to the operand format for the instructions
listed below (the details conform to the assembly specification). If more than one operand format is listed for an
instruction, one is selected. Uppercase letters, #, !, $, and brackets [ ] are used to specify keywords, which must be
written exactly as they appear. The meanings of these special characters are as follows:
•#: Immediate data specification
•$: Relative address specification
•!: Absolute address specification
•[ ]: Indirect address specification
Immediate data should be described using appropriate values or labels. The specification of values and labels
must be accompanied by #, !, $, or [ ].
Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C,
etc.) and absolute names (R0, R1, R2, and other names listed in Table 5-1 below).
Table 10-1. Operand Formats and Descriptions
Format Description
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2 ), HL (RP3)
Special f unction regi s ter sy m bol
saddr
saddrp FE20H to FF1FH Immediat e dat a or l abel
FE20H to FF1FH Immediate data or l abel (even addresses onl y)
addr16
addr5
0000H to FFFFH Immediate data or label
(only even addresses for 16-bit dat a transfer i nstructions)
0040H to 007FH Immediate data or label (even address es only)
word
byte
bit
16-bit imm edi ate data or label
8-bit imm edi ate data or label
3-bit imm edi ate data or label
Remark For details concerning special function register symbols, refer to Table 4-1 Special Function
Registers.
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
10.1.2 Operation field definitions
A: A register (8-bit accumulator)
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair (16-bit accumulator)
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
IE: Interrupt request enable flag
NMIS: Flag to indicate that a non-maskable interrupt is being processed
(): Contents of a memory location indicated by a parenthesized address or register name
XH, XL: Higher and lower 8 bits of a 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
∀: Exclusive OR
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
10.1.3 Flag operation field definitions
(Blank): No change
0: Clear to 0
1: Set to 1
×: Set or clear according to the result
R: Restore to the previous value
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PD78F9328
10.2 Operations
FlagMnemonic Operand Byte Clock Operation
ZACCY
r, #byt e 3 6 r ← byte
saddr , #by t e 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte
A, r Note 1 24A
← r
r, A Note 1 24r
← A
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (s addr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte ×××
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A ×××
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL + byte] 2 6 A ← (HL + byte)
MOV
[HL + byte], A 2 6 (HL + byte) ← A
A, X 1 4 A ↔ X
A, r Note 2 26A
↔ r
A, saddr 2 6 A ↔ (saddr)
A, sfr 2 6 A ↔ (sfr)
A, [DE] 1 8 A ↔ (DE)
A, [HL] 1 8 A ↔ (HL)
XCH
A, [HL + byte] 2 8 A ↔ (HL + byte)
rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rp Note 3 1 4 AX ← rp
MOVW
rp, AX Note 3 14rp
← AX
XCHW AX, rp Note 3 1 8 AX ↔ rp
Notes 1. Except when r = A.
2. Except when r = A or X.
3. Only when rp = BC, DE, or HL.
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control
register (PCC).
Preliminary Product Information U14411EJ1V0PM00
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PD78F9328
FlagMnemonic Operand Byte Clock Operation
ZACCY
A, #byte 2 4 A, CY ← A + byte ×××
saddr, #by te 3 6 (saddr), CY ← (saddr) + byte ×××
A, r 2 4 A, CY ← A + r ×××
A, s addr 2 4 A, CY ← A + (saddr) ×××
A, ! addr16 3 8 A, CY ← A + (addr16) ×××
A, [HL] 1 6 A, CY ← A + (HL) ×××
ADD
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) ×××
A, #byte 2 4 A, CY ← A + byte + CY ×××
saddr, #by te 3 6 (saddr), CY ← (saddr) + byte + CY ×××
A, r 2 4 A, CY ← A + r + CY ×××
A, s addr 2 4 A, CY ← A + (saddr) + CY ×××
A, ! addr16 3 8 A, CY ← A + (addr16) + CY ×××
A, [HL] 1 6 A, CY ← A + (HL) + CY ×××
ADDC
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY ×××
A, #byte 2 4 A, CY ← A − byte ×××
saddr, #by te 3 6 (saddr), CY ← (saddr) − byte ×××
A, r 2 4 A, CY ← A − r ×××
A, s addr 2 4 A, CY ← A − (saddr) ×××
A, ! addr16 3 8 A, CY ← A − (addr16) ×××
A, [HL] 1 6 A, CY ← A − (HL) ×××
SUB
A, [HL + byte] 2 6 A, CY ← A − (HL + byte) ×××
A, #byte 2 4 A, CY ← A − byte − CY ×××
saddr, #by te 3 6 (saddr), CY ← (s addr) − byte − CY ×××
A, r 2 4 A, CY ← A − r − CY ×××
A, s addr 2 4 A, CY ← A − (s addr) − CY ×××
A, ! addr16 3 8 A, CY ← A − (addr16) − CY ×××
A, [HL] 1 6 A, CY ← A − (HL) − CY ×××
SUBC
A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY ×××
A, #byte 2 4 A ← A ∧ byte ×
saddr, #by t e 3 6 (saddr) ← (saddr) ∧ byte ×
A, r 2 4 A ← A ∧ r ×
A, saddr 2 4 A ← A ∧ (saddr) ×
A, !addr16 3 8 A ← A ∧ (addr16) ×
A, [HL] 1 6 A ← A ∧ (HL) ×
AND
A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control
register (PCC).
Preliminary Product Information U14411EJ1V0PM00 77
µ
µµ
µ
PD78F9328
FlagMnemonic Operand Byte Clock Operation
ZACCY
A, #byte 2 4 A ← A ∨ byte ×
saddr, #by t e 3 6 (saddr) ← (saddr) ∨ byte ×
A, r 2 4 A ← A ∨ r×
A, saddr 2 4 A ← A ∨ (saddr) ×
A, !addr16 3 8 A ← A ∨ (addr16) ×
A, [HL] 1 6 A ← A ∨ (HL) ×
OR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×
A, #byte 2 4 A ← A ∀ byte ×
saddr, #by t e 3 6 (saddr) ← (saddr) ∀ byte ×
A, r 2 4 A ← A ∀ r×
A, saddr 2 4 A ← A ∀ (saddr) ×
A, !addr16 3 8 A ← A ∀ (addr16) ×
A, [HL] 1 6 A ← A ∀ (HL) ×
XOR
A, [HL + byte] 2 6 A ← A ∀ (HL + by te) ×
A, #byte 2 4 A − byte ×××
saddr, #by t e 3 6 (saddr) − byte ×××
A, r 2 4 A − r ×××
A, saddr 2 4 A − (s addr) ×××
A, !addr16 3 8 A − (addr16) ×××
A, [HL] 1 6 A − (HL) ×××
CMP
A, [HL + byte] 2 6 A − (HL + byt e) ×××
ADDW AX, #word 3 6 AX, CY ← AX + word ×××
SUBW AX, #word 3 6 AX, CY ← AX − word ×××
CMPW AX, #word 3 6 AX − word ×××
r24r
← r + 1 ××
INC
saddr 2 4 (saddr) ← (s addr) + 1 ××
r24r
← r − 1 ××
DEC
saddr 2 4 (saddr) ← (saddr) − 1 ××
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp − 1
ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 ×
ROL A , 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 ×
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 ×
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 ×
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control
register (PCC).
Preliminary Product Information U14411EJ1V0PM00
78
µ
µµ
µ
PD78F9328
FlagMnemonic Operand Byte Clock Operation
ZACCY
saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW bit ← 1 ×××
SET1
[HL].bit 2 10 (HL).bit ← 1
saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 ×××
CLR1
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 11
CLR1 CY 1 2 CY ← 00
NOT1 CY 1 2 CY ← CY ×
CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
RET 1 6 PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
RRR
PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1PUSH
rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
PSW 1 4 PSW ← (SP), SP ← SP + 1 R R RPOP
rp 1 6 rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, AX 2 8 SP ← AXMOVW
AX, SP 2 6 AX ← SP
!addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
BR
AX 1 6 PCH ← A, PCL ← X
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control
register (PCC).
Preliminary Product Information U14411EJ1V0PM00 79
µ
µµ
µ
PD78F9328
FlagMnemonic Operand Byte Clock Operation
ZACCY
BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
saddr.bit , $addr16 4 10 PC ← PC + 4 + jdisp8
if (saddr. bi t) = 1
sfr. bi t, $addr16 4 10 PC ← P C + 4 + jdi sp8 if s f r.bit = 1
A.bit , $addr16 3 8 P C ← P C + 3 + jdi s p8 i f A.bit = 1
BT
PSW. bi t, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
saddr.bit , $addr16 4 10 PC ← PC + 4 + jdisp8
if (saddr. bi t) = 0
sfr. bi t, $addr16 4 10 PC ← P C + 4 + jdi sp8 if s f r.bit = 0
A.bit , $addr16 3 8 P C ← P C + 3 + jdi s p8 i f A.bit = 0
BF
PSW. bi t, $addr16 4 10 PC ← PC + 4 + dis p8 i f PSW.bi t = 0
B, $addr16 2 6 B ← B − 1, t hen
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C − 1, t hen
PC ← PC + 2 + jdisp8 if C ≠ 0
DBNZ
saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (s addr) ≠ 0
NOP 1 2 No Operat i on
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Dis abl e Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set STOP Mode
Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control
register (PCC).
Preliminary Product Information U14411EJ1V0PM00
80
µ
µµ
µ
PD78F9328
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°
°°
°C)
Parameter Symbol Conditions Ratings Unit
VDD −0.3 to +6.5 V
VPP −0.3 to +10.5 V
Supply v ol tage
VLC0 −0.3 to +6.5 V
Input vol tage VI−0.3 to V DD + 0.3Note V
VO1 P00 to P03, P10, P 11, P20 to P 22,
P40 to P43, P60, P 61 −0.3 to VDD + 0.3Note VOutput vol tage
VO2 COM0 to COM3, S0 to S21,
P80/S22 to P85/S 17 −0.3 to VLC0 + 0.3Note V
Pin P60/TO40 −30 mA
Per pin (exc ept P60/TO40) −10 mA
Output current, high IOH
Total for al l pi ns (except P 60/TO40) −30 mA
Per pin 30 mAOutput current, low IOL
Total for al l pi ns 80 mA
Operating ambient temperat ure TA−40 to +85 °C
Storage tem perature Tstg −65 to +150 °C
Note 6.5 V or lower
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Preliminary Product Information U14411EJ1V0PM00 81
µ
µµ
µ
PD78F9328
Main System Clock Oscillator Characteristics (TA = −
−−
−40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Rec om m ended Ci rcuit Parameter Conditi ons MIN. TY P . MAX. Unit
Oscillati on f requency
(fX)Note 1 1.0 5.0 MHzCeramic
resonator
X1X2V
DD
C1C2
Oscillation
stabilization timeNote 2 After VDD has reached the MIN.
oscillation voltage range 4ms
Oscillati on f requency
(fX)Note 1 1.0 5.0 MHzCrystal
resonator
X1X2IC
C1C2
Oscillation
stabilization timeNote 2 30 ms
X1 input f requency
(fX)Note 1 1.0 5.0 MHzExternal
clock
X2 X1
X1 input high-/low-
level width (tXH, tXL)85 500 ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
•
••
• Keep the wiring length as short as possible.
•
••
• Do not cross the wiring with other signal lines.
•
••
• Do not route the wiring near a signal line through which a high fluctuating current flows.
•
••
• Always make the ground point of the oscillator capacitor the same potential as VSS.
•
••
• Do not ground the capacitor to a ground pattern through which a high current flows.
•
••
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Preliminary Product Information U14411EJ1V0PM00
82
µ
µµ
µ
PD78F9328
Subsystem Clock Oscillator Characteristics (TA = −
−−
−40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator Rec om m ended Ci rcuit Parameter Condit i ons MIN. TYP. MAX . Unit
Oscillati on f requency
(fXT)Note 1 32 32.768 35 kHz
VDD = 4.5 to 5.5 V 1.2 2
Crystal
resonator
XT2XT1IC
C4
C3
R
Oscillation
stabilization timeNote 2 10
s
XT1 input frequency
(fXT)Note 1 32 35 kHzExternal
clock
XT1 XT2
XT1 input hi gh-/low-
level width (tXTH, tXTL)14.3 15.6
µ
s
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a
resonator to stabilize oscillation during the oscillation wait time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
•
••
• Keep the wiring length as short as possible.
•
••
• Do not cross the wiring with the other signal lines.
•
••
• Do not route the wiring near a signal line through which a high fluctuating current flows.
•
••
• Always make the ground point of the oscillator capacitor the same potential as VSS.
•
••
• Do not ground the capacitor to a ground pattern through which a high current flows.
•
••
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Preliminary Product Information U14411EJ1V0PM00 83
µ
µµ
µ
PD78F9328
DC Characteristics (TA = −
−−
−20 to +60°C, VDD = 1.8 to 5.5 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 10 mAOutput current, low IOL
Total for al l pi ns 80 mA
Per pin (exc ept P60/TO40) −1mA
P60/TO40 VDD = 3. 0 V, VOH = 1.0 V −7−15 −24 mA
Output current, high I OH
Total for al l pi ns (except P 60/TO40) −15 mA
VDD = 2.7 to 5.5 V 0.7 VDD VDD VVIH1 P00 to P03, P 10, P11,
P21, P22, P60 0.9 VDD VDD V
VDD = 2.7 to 5.5 V 0.8 VDD VDD VVIH2 RESET, P20, P40 to P43,
P61 0.9 VDD VDD V
VIH3 X1, X2 VDD − 0.1 VDD V
Input vol tage, high
VIH4 XT1, XT2 VDD − 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.3 V DD VVIL1 P00 to P03, P 10, P11,
P21, P22, P60 0 0.1 VDD V
VDD = 2.7 to 5.5 V 0 0.2 V DD VVIL2 RESET, P20, P40 to P43,
P61 0 0.1 VDD V
VIL3 X1, X2 0 0.1 V
Input vol tage, low
VIL4 XT1, XT2 0 0.1 V
VOH11 1.8 ≤ VDD ≤ 5.5 V,
IOH = −100
µ
AVDD − 0.5 V
VOH12
P00 to P03, P10, P 11,
P20 to P22, P40 to P 43,
P61 1.8 ≤ VDD ≤ 5.5 V,
IOH = −500
µ
AVDD − 0.7 V
VOH21 1.8 ≤ VDD ≤ 5.5 V,
IOH = −400
µ
AVDD − 0.5 V
VOH22
P60/TO40
1.8 ≤ VDD ≤ 5.5 V,
IOH = −2 mA VDD − 0. 7 V
VOH31 1.8 ≤ VDD ≤ 5.5 V,
IOH = −100
µ
AVLC0 − 0.5 V
Output vol tage, high
VOH32
P80/S22 to P85/S 17
1.8 ≤ VDD ≤ 5.5 V,
IOH = −500
µ
AVLC0 − 0.7 V
VOL11 1.8 ≤ VDD ≤ 5.5 V,
IOL = 400
µ
A0.5 V
VOL12
P00 to P03, P10, P 11,
P20 to P22, P40 to P 43,
P60, P61 1.8 ≤ VDD ≤ 5. 5 V,
IOL = 2 mA 0.7 V
VOL21 1.8 ≤ VLC0 ≤ 5.5 V,
IOL = 400
µ
A0.5 V
Output vol tage, low
VOL22
P80/S22 to P85/S 17
1.8 ≤ VLC0 ≤ 5.5 V,
IOL = 2 mA 0.7 V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Preliminary Product Information U14411EJ1V0PM00
84
µ
µµ
µ
PD78F9328
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
ILIH1 P00 to P03, P10,
P11, P20 to P22,
P40 to P43, P60,
P61, RESET
3
µ
AInput leak age current,
high
ILIH2
VIN = VDD
X1, X2, XT1, XT2 20
µ
A
ILIL1 P00 to P03, P10,
P11, P20 to P22,
P40 to P43, P60,
P61, RESET
−3
µ
AInput leak age current,
low
ILIL2
VIN = 0 V
X1, X2, XT1, XT2 −20
µ
A
Output leak age current,
high ILOH VOUT = VDD 3
µ
A
Output leak age current,
low ILOL VOUT = 0 V −3
µ
A
Software pul l -up
resistors R1VIN = 0 V P00 to P03, P10,
P11, P20 to P22,
P40 to P43
50 100 200 kΩ
VDD = 5.5 VNote 2 5.0 15.0 mAIDD1 5.0-MHz crystal oscillation
operating mode VDD = 3.3 VNote 3 2.0 5.0 mA
VDD = 5.5 V 1.2 3.6 mAIDD2 5.0-MHz crystal oscillation
HALT mode VDD = 3.3 V 0.5 1.5 mA
VDD = 5.5 V 25 55
µ
AIDD4 32.768-kHz crystal
oscillation HALT modeNote 4 VDD = 3.3 V 5 25
µ
A
VDD = 5.5 V 2 30
µ
A
Supply c urrentNote 1
Ceramic/crystal
oscillation
IDD5 STOP mode
VDD = 3.3 V 1 10
µ
A
Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors) is not
included.
2. High-speed operation (when the processor clock control register (PCC) is set to 00H).
3. Low-speed operation (when PCC is set to 02H)
4. When the main system clock is stopped.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Preliminary Product Information U14411EJ1V0PM00 85
µ
µµ
µ
PD78F9328
AC Characteristics
(1) Basic operation (TA = −
−−
−40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 0.4 8.0
µ
sCycle time
(Min. instruction exec ution ti m e) TCY
1.6 8.0
µ
s
Interrupt i nput
high-/low-l evel widt h tINTH,
tINTL
INT 10
µ
s
Key return pi n
low-level width tKRIL KR00 to KR03 10
µ
s
RESET low-level width tRSL 10
µ
s
TCY vs. VDD (Main System Clock)
Supply voltage V
DD
(V)
123456
0.1
0.4
0.5
1.0
2.0
10
20
60
Cycle time T
CY
[ s]
Guaranteed
operation
range
µ
Preliminary Product Information U14411EJ1V0PM00
86
µ
µµ
µ
PD78F9328
(2) Serial interface 10 (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (Internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 800 nsSCK10 cycle time tKCY1
3,200 ns
VDD = 2.7 to 5.5 V tKCY1/2 − 50 nsSCK10 hi gh-/ l ow-l evel
width tKH1,
tKL1 tKCY1/2 − 150 ns
VDD = 2.7 to 5.5 V 150 nsSI10 setup tim e
(to SCK10 ↑)tSIK1
500 ns
VDD = 2.7 to 5.5 V 400 nsSI10 hold t i m e
(from SCK 10 ↑)tKSI1
800 ns
VDD = 2.7 to 5.5 V 0 250 nsSO10 output del ay time
from SCK 10 ↓tKSO1 R = 1 kΩ, C = 100 pFNote
250 1,000 ns
Note R and C are the load resistance and load capacitance of the SO10 output line.
(b) 3-wire serial I/O mode (External clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 2.7 to 5.5 V 900 nsSCK10 cycle time tKCY2
3,500 ns
VDD = 2.7 to 5.5 V 400 nsSCK10 high-/low-lev el
width tKH2,
tKL2 1,600 ns
VDD = 2.7 to 5.5 V 100 nsSI10 setup ti m e
(to SCK10 ↑)tSIK2
150 ns
VDD = 2.7 to 5.5 V 400 nsSI10 hol d t i me
(from SCK 10 ↑)tKSI2
600 ns
VDD = 2.7 to 5.5 V 0 300 nsSO10 output del ay time
from SCK 10 ↓tKSO2 R = 1 kΩ, C = 100 pFNote
250 1,000 ns
Note R and C are the load resistance and load capacitance of the SO10 output line.
Preliminary Product Information U14411EJ1V0PM00 87
µ
µµ
µ
PD78F9328
AC Timing Measurement Point (excluding X1, XT1 input)
0.8 V
DD
0.2 V
DD
Test points 0.8 V
DD
0.2 V
DD
Clock Timing
1/f
X
t
XL
t
XH
X1 input V
IH3
(MIN.)
V
IL3
(MAX.)
1/f
XT
t
XTL
t
XTH
XT1 input V
IH4
(MIN.)
V
IL4
(MAX.)
Interrupt Input Timing
INT
t
INTL
t
INTH
Key Return Input Timing
KR00 to KR03
t
KRIL
RESET Input Timing
RESET
t
RSL
Preliminary Product Information U14411EJ1V0PM00
88
µ
µµ
µ
PD78F9328
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYn
t
KLn
t
KHn
SCK10
t
SIKn
t
KSIn
t
KSOn
Input data
Output data
SI10
SO10
Remark n = 1, 2
Preliminary Product Information U14411EJ1V0PM00 89
µ
µµ
µ
PD78F9328
LCD Characteristics (TA = −
−−
−40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VAON0Note 1 = 1 1.8 5.5 V
LCD drive vo l tage VLC0
VAON0Note 1 = 0 2.7 5.5 V
RLCD1Note 2 High resis tance 50 100 200 kΩ
LCD division resi stance
RLCD2Note 2 Low resistance 5 10 20 kΩ
LCD output vol tage diff erentialNote 3
(common) VODC IO = ±5
µ
A 1/3 bias 0 ±0.2 V
LCD output vol tage diff erentialNote 3
(segment) VODS IO = ±1
µ
A 1/3 bias 0 ±0.2 V
Notes 1. Bit 6 of LCD display mode register 0 (LCDM0)
2. One or the other can be selected when designing
3. The voltage differential is the difference between the output voltage and the ideal value of the segment
and common signal outputs.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −
−−
−40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retenti on supply voltage V DDDR 1.8 3.6 V
Low voltage det ection (P OC) voltage VPOC Response t i m e: 2 msNote 1 1.8 1.9 2.0 V
Power supply rise time tPth VDD: 0 V → 1.8 V 0.01 100 ms
Release si gnal set ti m e tSREL STOP cancelled by RESET 10
µ
s
Cancelled by RESET 215/fXs
Oscillation stabilization wait timeNote 2 tWAIT
Cancelled by i nterrupt request Note 3 s
Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the
time until operation stabilizes after the shift from the operation stopped state to the operating state.
2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid
unstable operation at the start of oscillation. Program operation does not start until both the oscillation
stabilization time and the time until oscillation starts have elapsed.
3. Selection of 212/fX, 215/fX, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS) (refer to 7.2 Standby Function Control Register).
Remark fX: Main system clock oscillation frequency
Preliminary Product Information U14411EJ1V0PM00
90
µ
µµ
µ
PD78F9328
Data Retention Timing
V
DD
Data retention mode
STOP mode
HALT mode
Internal reset operation
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
RESET
V
DD
Data retention mode
STOP mode
HALT mode
Operating mode
t
SREL
t
WAIT
STOP instruction execution
V
DDDR
Standby release signal
(interrupt request)
Preliminary Product Information U14411EJ1V0PM00 91
µ
µµ
µ
PD78F9328
APPENDIX A. DIFFERENCES BETWEEN
µ
µµ
µ
PD78F9328 AND MASK ROM VERSIONS
The
µ
PD78F9328 is a product provided with flash memory in place of the internal ROM of the mask ROM
versions. Table A-1 shows the differences between the flash memory (
µ
PD78F9328) and the mask ROM versions.
Table A-1. Differences Between
µ
µµ
µ
PD78F9328 and Mask ROM Versions
Flash Memory Version Mask ROM VersionItem
µ
PD78F9328
µ
PD789322
µ
PD789324
µ
PD789326
µ
PD789627
ROM 32 Kbytes
(flash memory) 4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes
High-speed RAM 512 bytes
Internal
memory
LCD display RAM 24 bytes
IC0 pin Not provided P rovided
VPP pin Provided Not provided
Elect ri cal spec i ficat i ons There may be diff erences between m ask ROM and f l ash memory versions .
Caution There are differences in the amount of noise tolerance and noise radiation between flash
memory versions and mask ROM versions. When considering changing from a flash memory
version to a mask ROM version during the process from experimental manufacturing to mass
production, make sure to sufficiently evaluate commercial samples (CS) (not engineering
samples (ES)) of the mask ROM versions.
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APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the
µ
PD78F9328.
Language Processing Software
RA78K0SNotes 1, 2, 3 Assembler pack age common t o 78K /0S Seri es
CC78K0SNo t es 1, 2 ,3 C compil er package c om m on to 78K/0S Series
DF789328Notes 1, 2, 3, 5 Device file for
µ
PD789328 Subseri es
CC78K/0S–LNotes 1, 2, 3 C compil er library source f i l e common to 78K/0S Series
Flash Memory Writing Tools
Flashpro II I
(Part number: FL-PR3Note 4, PG-FP3) Dedicat ed flash memory programm er
FA-52GBNotes 4, 5 Adapter f or wri ting to f l ash memory designed for 52-pin pl astic LQFP (GB-8ET t ype)
Debugging Tools
IE-78K0S-NS
In-circ ui t emulat or In-circuit em ul at or to debug hardware or software when application systems using the
78K/0S S eri es are developed. The IE-78K 0S-NS support s an integrat ed debugger
(ID78K0S-NS ). The IE-78K 0S-NS is used in com bi nat i on wi th an interf ace adapter for
connect i on t o an AC adapter, em ul at i on probe, or host machine.
IE-70000-MC-PS-B
AC adapter AC adapter to supply power f rom a 100- to 240-V AC out l et .
IE-70000-98-IF-C
Interface adapter Interface adapter required when us i ng a PC-9800 Series computer (ex cept notebook type)
as the hos t m achine for t he IE-78K0S -NS (C bus supported).
IE-70000-CD-IF-A
PC card interface PC card and int erface cabl e requi red when a notebook PC i s used as t he hos t machi ne for
the IE -78K 0S-NS (PCM CIA s ocket supported).
IE-70000-PC-IF-C
Interface adapter Interface adapter required when us i ng an IBM P C/ AT™ or compat i bl e as the hos t m achine
for the IE-78K0S-NS (ISA bus supported).
IE-70000-PCI-IF
Interface adapter Interface adapter required when us i ng a PC incorporat i ng a P CI bus as the host m achine
for the IE-78K0S-NS .
IE-789328-NS-EM1Note 5
Emulat i on board Emul at i on board to emulat e t he peri pheral hardware specif i c to the device. The IE-
789328-NS-EM1 is used in combinati on wi th the in-c i rcuit em ul at or.
NP-52GBNo t es 4, 5 Board to connect an i n-circui t em ul ator to the target system. This board is dedicat ed f or a
52-pin plasti c LQFP (GB-8ET type).
SM78K0SNotes 1, 2 S ystem simulator comm on to 78K/0S Series
ID78K0S-NSNotes 1, 2 Integrated debugger common to 78K / 0S Series
DF789328Notes 1, 2, 5 Device file for
µ
PD789328 Subseri es
Notes 1. Based on the PC-9800 series (MS-DOS™ + Windows™)
2. Based on IBM PC/AT or compatibles (Japanese/English Windows)
3. Based on the HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), and NEWS™
(NEWS-OS™)
4. Manufactured by Naito Densei Machida Mfg. Co, Ltd. (+81-44-822-3813). Contact Naito Densei
Machida Mfg. Co, Ltd. regarding the purchase of these products.
5. Under development
Remark The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789328 device file.
Preliminary Product Information U14411EJ1V0PM00 93
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PD78F9328
Real-Time OS
MX78K0SNotes 1, 2 OS for 78K/0S Series
Notes 1. Based on the PC-9800 series (MS-DOS + Windows)
2. Based on IBM PC/AT or compatibles (Japanese/English Windows)
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APPENDIX C. RELATED DOCUMENTS
Documents Related to Devices
Document No.Document Nam e
Japanese English
µ
PD789322, 789324, 789326, 789327 Prelimi nary Product Informat i on To be prepared To be prepared
µ
PD78F9328 Prelim i nary Product Informat i on To be prepared This document
µ
PD789328, 789468 Subs eri es User’s Manual To be prepared To be prepared
78K/0S S eri es User’s Manual Instruc t i ons U11047J U11047E
Documents Related to Development Tools (User’s Manual)
Document No.Document Nam e
Japanese English
Operation U11622J U11622E
Assembly Language U11599J U11599E
RA78K0S Ass em bler Package
Structured Assembly Language U11623J U11623E
Operation U11816J U11816ECC78K0S C Compi l e r
Language U11817J U11817E
SM78K0S S yst em S i m ul ator Windows B ased Referenc e U11489J U11489E
SM78K S eri es System S i m ul ator External Part User Open
Interface Speci ficat i ons U10092J U10092E
ID78K0S-NS Integrated Debugger Wi ndows Based Ref erence U12901J U12901E
IE-78K0S -NS In-ci rcuit E m ul ator U13549J U13549E
IE-789328-NS-E M1 Emulation Board To be prepared To be prepared
Documents Related to Embedded Software (User’s Manual)
Document No.Document Nam e
Japanese English
78K/0S S eri es OS MX 78K0S Fundamental U12938J U12938E
Other Documents
Document No.Document Nam e
English Japanese
SEMI CONDUCT ORS SELECTION GUIDE P roduc ts & Packages (CD-ROM) X13769X
Semic onductor Devi ce Mounting Technology M anual C10535J C10535E
Quality Grades on NEC Sem i c onductor Dev i c es C11531J C11531E
NEC Semiconduc tor Device Reliability/Qualit y Control Sy stem C10983J C10983E
Guide to Prev ent Damage for S em i conductor Devices by El ectrost atic Di s charge (ESD) C11892J C11892E
Guide to Microcontrol l er-Rel ated Product s by Third P arties U11416J −
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
Preliminary Product Information U14411EJ1V0PM00 95
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[MEMO]
Preliminary Product Information U14411EJ1V0PM00
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
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PD78F9328
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
